system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032e17_00000000-6_sum_optimization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
.type _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii, @function
_Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 232
pushq 40(%rsp)
.cfi_def_cfa_offset 240
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sum_optimizationPfiiiiS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii, .-_Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
.globl _Z16sum_optimizationPfiiiiS_iiiiii
.type _Z16sum_optimizationPfiiiiS_iiiiii, @function
_Z16sum_optimizationPfiiiiS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sum_optimizationPfiiiiS_iiiiii, .-_Z16sum_optimizationPfiiiiS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16sum_optimizationPfiiiiS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sum_optimizationPfiiiiS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_optimization.hip"
.globl _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii # -- Begin function _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.p2align 4, 0x90
.type _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii,@function
_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii: # @_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sum_optimizationPfiiiiS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii, .Lfunc_end0-_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sum_optimizationPfiiiiS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sum_optimizationPfiiiiS_iiiiii,@object # @_Z16sum_optimizationPfiiiiS_iiiiii
.section .rodata,"a",@progbits
.globl _Z16sum_optimizationPfiiiiS_iiiiii
.p2align 3, 0x0
_Z16sum_optimizationPfiiiiS_iiiiii:
.quad _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.size _Z16sum_optimizationPfiiiiS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sum_optimizationPfiiiiS_iiiiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sum_optimizationPfiiiiS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} | code for sm_80
Function : _Z19SoftmaxLossBackpropPKfiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ F2I.TRUNC.NTZ R5, R2 ; /* 0x0000000200057305 */
/* 0x004e24000020f100 */
/*00b0*/ IMAD R5, R0, c[0x0][0x168], R5 ; /* 0x00005a0000057a24 */
/* 0x001fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0204 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FADD R7, R0, -1 ; /* 0xbf80000000077421 */
/* 0x004fca0000000000 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} | .file "tmpxft_00052a60_00000000-6_SoftmaxLossBackprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
.type _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf, @function
_Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19SoftmaxLossBackpropPKfiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf, .-_Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
.globl _Z19SoftmaxLossBackpropPKfiiPf
.type _Z19SoftmaxLossBackpropPKfiiPf, @function
_Z19SoftmaxLossBackpropPKfiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19SoftmaxLossBackpropPKfiiPf, .-_Z19SoftmaxLossBackpropPKfiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19SoftmaxLossBackpropPKfiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19SoftmaxLossBackpropPKfiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19SoftmaxLossBackpropPKfiiPf
.globl _Z19SoftmaxLossBackpropPKfiiPf
.p2align 8
.type _Z19SoftmaxLossBackpropPKfiiPf,@function
_Z19SoftmaxLossBackpropPKfiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, -1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19SoftmaxLossBackpropPKfiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19SoftmaxLossBackpropPKfiiPf, .Lfunc_end0-_Z19SoftmaxLossBackpropPKfiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19SoftmaxLossBackpropPKfiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19SoftmaxLossBackpropPKfiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SoftmaxLossBackprop( const float *label, int num_labels, int batch_size, float *diff ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if( idx >= batch_size ) {
return;
}
const int label_value = static_cast<int>(label[ idx ]);
// For each item in the batch, decrease the result of the label's value by 1
diff[ idx * num_labels + label_value ] -= 1.0f;
} | .text
.file "SoftmaxLossBackprop.hip"
.globl _Z34__device_stub__SoftmaxLossBackpropPKfiiPf # -- Begin function _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.p2align 4, 0x90
.type _Z34__device_stub__SoftmaxLossBackpropPKfiiPf,@function
_Z34__device_stub__SoftmaxLossBackpropPKfiiPf: # @_Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19SoftmaxLossBackpropPKfiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__SoftmaxLossBackpropPKfiiPf, .Lfunc_end0-_Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19SoftmaxLossBackpropPKfiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19SoftmaxLossBackpropPKfiiPf,@object # @_Z19SoftmaxLossBackpropPKfiiPf
.section .rodata,"a",@progbits
.globl _Z19SoftmaxLossBackpropPKfiiPf
.p2align 3, 0x0
_Z19SoftmaxLossBackpropPKfiiPf:
.quad _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.size _Z19SoftmaxLossBackpropPKfiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19SoftmaxLossBackpropPKfiiPf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19SoftmaxLossBackpropPKfiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19SoftmaxLossBackpropPKfiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ F2I.TRUNC.NTZ R5, R2 ; /* 0x0000000200057305 */
/* 0x004e24000020f100 */
/*00b0*/ IMAD R5, R0, c[0x0][0x168], R5 ; /* 0x00005a0000057a24 */
/* 0x001fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0204 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FADD R7, R0, -1 ; /* 0xbf80000000077421 */
/* 0x004fca0000000000 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19SoftmaxLossBackpropPKfiiPf
.globl _Z19SoftmaxLossBackpropPKfiiPf
.p2align 8
.type _Z19SoftmaxLossBackpropPKfiiPf,@function
_Z19SoftmaxLossBackpropPKfiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, -1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19SoftmaxLossBackpropPKfiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19SoftmaxLossBackpropPKfiiPf, .Lfunc_end0-_Z19SoftmaxLossBackpropPKfiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19SoftmaxLossBackpropPKfiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19SoftmaxLossBackpropPKfiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00052a60_00000000-6_SoftmaxLossBackprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
.type _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf, @function
_Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19SoftmaxLossBackpropPKfiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf, .-_Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
.globl _Z19SoftmaxLossBackpropPKfiiPf
.type _Z19SoftmaxLossBackpropPKfiiPf, @function
_Z19SoftmaxLossBackpropPKfiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19SoftmaxLossBackpropPKfiiPfPKfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19SoftmaxLossBackpropPKfiiPf, .-_Z19SoftmaxLossBackpropPKfiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19SoftmaxLossBackpropPKfiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19SoftmaxLossBackpropPKfiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SoftmaxLossBackprop.hip"
.globl _Z34__device_stub__SoftmaxLossBackpropPKfiiPf # -- Begin function _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.p2align 4, 0x90
.type _Z34__device_stub__SoftmaxLossBackpropPKfiiPf,@function
_Z34__device_stub__SoftmaxLossBackpropPKfiiPf: # @_Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19SoftmaxLossBackpropPKfiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__SoftmaxLossBackpropPKfiiPf, .Lfunc_end0-_Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19SoftmaxLossBackpropPKfiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19SoftmaxLossBackpropPKfiiPf,@object # @_Z19SoftmaxLossBackpropPKfiiPf
.section .rodata,"a",@progbits
.globl _Z19SoftmaxLossBackpropPKfiiPf
.p2align 3, 0x0
_Z19SoftmaxLossBackpropPKfiiPf:
.quad _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.size _Z19SoftmaxLossBackpropPKfiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19SoftmaxLossBackpropPKfiiPf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__SoftmaxLossBackpropPKfiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19SoftmaxLossBackpropPKfiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
cudaMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
cudaMemcpy(a_h, a_d, sizeof(float)*tam, cudaMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
cudaFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} | code for sm_80
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R12, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff0c7435 */
/* 0x000fe200000001ff */
/*00b0*/ BSSY B0, 0x760 ; /* 0x000006a000007945 */
/* 0x000fe20003800000 */
/*00c0*/ FMUL R5, |R0|.reuse, 16777216 ; /* 0x4b80000000057820 */
/* 0x044fe20000400200 */
/*00d0*/ FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x040fe40003f0e200 */
/*00e0*/ FSETP.NEU.AND P3, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720b */
/* 0x040fe40003f6d000 */
/*00f0*/ FSEL R5, R5, |R0|, !P0 ; /* 0x4000000005057208 */
/* 0x000fe40004000000 */
/*0100*/ FSETP.NEU.AND P2, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fc40003f4d000 */
/*0110*/ IADD3 R4, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05047810 */
/* 0x000fc80007ffe0ff */
/*0120*/ LOP3.LUT R6, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004067812 */
/* 0x000fe400078ec0ff */
/*0130*/ FSEL R4, RZ, -24, P0 ; /* 0xc1c00000ff047808 */
/* 0x000fe40000000000 */
/*0140*/ IADD3 R5, R5, -R6, RZ ; /* 0x8000000605057210 */
/* 0x000fe20007ffe0ff */
/*0150*/ I2F R7, R6 ; /* 0x0000000600077306 */
/* 0x000e280000201400 */
/*0160*/ FADD R8, R5.reuse, 1 ; /* 0x3f80000005087421 */
/* 0x040fe40000000000 */
/*0170*/ FADD R5, R5, -1 ; /* 0xbf80000005057421 */
/* 0x000fc80000000000 */
/*0180*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x000e620000001000 */
/*0190*/ FADD R9, R5, R5 ; /* 0x0000000505097221 */
/* 0x000fe40000000000 */
/*01a0*/ FFMA R4, R7, 1.1920928955078125e-07, R4 ; /* 0x3400000007047823 */
/* 0x001fe40000000004 */
/*01b0*/ FMUL R10, R8, R9 ; /* 0x00000009080a7220 */
/* 0x002fc80000400000 */
/*01c0*/ FADD R9, R5, -R10 ; /* 0x8000000a05097221 */
/* 0x000fe40000000000 */
/*01d0*/ FMUL R7, R10.reuse, R10 ; /* 0x0000000a0a077220 */
/* 0x040fe40000400000 */
/*01e0*/ FFMA R11, R10, 1.4426950216293334961, R4 ; /* 0x3fb8aa3b0a0b7823 */
/* 0x000fe40000000004 */
/*01f0*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe40000000000 */
/*0200*/ FFMA R6, R7, R12, 0.0032181653659790754318 ; /* 0x3b52e7db07067423 */
/* 0x000fe4000000000c */
/*0210*/ FADD R13, R4, -R11 ; /* 0x8000000b040d7221 */
/* 0x000fc40000000000 */
/*0220*/ FFMA R9, R5, -R10, R9 ; /* 0x8000000a05097223 */
/* 0x000fe40000000009 */
/*0230*/ FFMA R6, R7.reuse, R6, 0.018033718690276145935 ; /* 0x3c93bb7307067423 */
/* 0x040fe40000000006 */
/*0240*/ FFMA R4, R10, 1.4426950216293334961, R13 ; /* 0x3fb8aa3b0a047823 */
/* 0x000fe4000000000d */
/*0250*/ FMUL R9, R8, R9 ; /* 0x0000000908097220 */
/* 0x000fe40000400000 */
/*0260*/ FFMA R6, R7, R6, 0.12022458761930465698 ; /* 0x3df6384f07067423 */
/* 0x000fe40000000006 */
/*0270*/ FFMA R5, R9, 1.4426950216293334961, R4 ; /* 0x3fb8aa3b09057823 */
/* 0x000fc40000000004 */
/*0280*/ FMUL R7, R7, R6 ; /* 0x0000000607077220 */
/* 0x000fe40000400000 */
/*0290*/ FFMA R4, R10, 1.9251366722983220825e-08, R5 ; /* 0x32a55e340a047823 */
/* 0x000fe40000000005 */
/*02a0*/ FMUL R5, R7, 3 ; /* 0x4040000007057820 */
/* 0x000fc80000400000 */
/*02b0*/ FFMA R4, R9, R5, R4 ; /* 0x0000000509047223 */
/* 0x000fe20000000004 */
/*02c0*/ MOV R9, 0x391fcb8e ; /* 0x391fcb8e00097802 */
/* 0x000fc60000000f00 */
/*02d0*/ FFMA R4, R10, R7, R4 ; /* 0x000000070a047223 */
/* 0x000fc80000000004 */
/*02e0*/ FADD R6, R11, R4 ; /* 0x000000040b067221 */
/* 0x000fc80000000000 */
/*02f0*/ FMUL R5, R6.reuse, 3 ; /* 0x4040000006057820 */
/* 0x040fe40000400000 */
/*0300*/ FADD R11, -R11, R6 ; /* 0x000000060b0b7221 */
/* 0x000fe40000000100 */
/*0310*/ FRND R8, R5 ; /* 0x0000000500087307 */
/* 0x000e220000201000 */
/*0320*/ FFMA R6, R6, 3, -R5 ; /* 0x4040000006067823 */
/* 0x000fe20000000805 */
/*0330*/ FSETP.GEU.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f2e000 */
/*0340*/ FADD R11, R4, -R11 ; /* 0x8000000b040b7221 */
/* 0x000fc80000000000 */
/*0350*/ FFMA R6, R11, 3, R6 ; /* 0x404000000b067823 */
/* 0x000fe20000000006 */
/*0360*/ F2I.NTZ R4, R5 ; /* 0x0000000500047305 */
/* 0x000e620000203100 */
/*0370*/ FADD R7, R5, -R8 ; /* 0x8000000805077221 */
/* 0x001fe20000000000 */
/*0380*/ FSETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fc60003f04000 */
/*0390*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x000fc80000000000 */
/*03a0*/ FFMA R7, R6.reuse, R9, 0.0013391353422775864601 ; /* 0x3aaf85ed06077423 */
/* 0x040fe20000000009 */
/*03b0*/ SEL R9, RZ, 0x83000000, P0 ; /* 0x83000000ff097807 */
/* 0x000fe40000000000 */
/*03c0*/ FSETP.GT.AND P0, PT, |R5|, 152, PT ; /* 0x431800000500780b */
/* 0x000fe20003f04200 */
/*03d0*/ FFMA R7, R6, R7, 0.0096188392490148544312 ; /* 0x3c1d985606077423 */
/* 0x000fe20000000007 */
/*03e0*/ IADD3 R8, R9, 0x7f000000, RZ ; /* 0x7f00000009087810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ LEA R4, R4, -R9, 0x17 ; /* 0x8000000904047211 */
/* 0x002fe200078eb8ff */
/*0400*/ FFMA R7, R6, R7, 0.055503588169813156128 ; /* 0x3d6357bb06077423 */
/* 0x000fc80000000007 */
/*0410*/ FFMA R7, R6, R7, 0.24022644758224487305 ; /* 0x3e75fdec06077423 */
/* 0x000fc80000000007 */
/*0420*/ FFMA R7, R6, R7, 0.69314718246459960938 ; /* 0x3f31721806077423 */
/* 0x000fc80000000007 */
/*0430*/ FFMA R7, R6, R7, 1 ; /* 0x3f80000006077423 */
/* 0x000fe20000000007 */
/*0440*/ HFMA2.MMA R6, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff067435 */
/* 0x000fc600000001ff */
/*0450*/ FMUL R7, R7, R8 ; /* 0x0000000807077220 */
/* 0x000fc80000400000 */
/*0460*/ FMUL R4, R7, R4 ; /* 0x0000000407047220 */
/* 0x000fe20000400000 */
/*0470*/ @!P3 BRA 0x750 ; /* 0x000002d00000b947 */
/* 0x000fea0003800000 */
/*0480*/ MOV R7, 0x34000000 ; /* 0x3400000000077802 */
/* 0x000fe20000000f00 */
/*0490*/ FFMA R5, RZ, -RZ, RZ ; /* 0x800000ffff057223 */
/* 0x000fe200000000ff */
/*04a0*/ MOV R6, 0x3a2c32e4 ; /* 0x3a2c32e400067802 */
/* 0x000fe40000000f00 */
/*04b0*/ FSETP.GTU.AND P5, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003fac200 */
/*04c0*/ FFMA R7, R7, 8388608, RZ ; /* 0x4b00000007077823 */
/* 0x000fe400000000ff */
/*04d0*/ FFMA R6, RZ, R6, 0.0032181653659790754318 ; /* 0x3b52e7dbff067423 */
/* 0x000fe40000000006 */
/*04e0*/ FFMA R8, RZ, 1.4426950216293334961, R7 ; /* 0x3fb8aa3bff087823 */
/* 0x000fc40000000007 */
/*04f0*/ FFMA R6, RZ, R6, 0.018033718690276145935 ; /* 0x3c93bb73ff067423 */
/* 0x000fe40000000006 */
/*0500*/ FADD R7, R7, -R8 ; /* 0x8000000807077221 */
/* 0x000fe40000000000 */
/*0510*/ FMUL R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000400000 */
/*0520*/ FFMA R6, RZ, R6, 0.12022458761930465698 ; /* 0x3df6384fff067423 */
/* 0x000fe40000000006 */
/*0530*/ FFMA R10, RZ, 1.4426950216293334961, R7 ; /* 0x3fb8aa3bff0a7823 */
/* 0x000fe40000000007 */
/*0540*/ FMUL R6, RZ, R6 ; /* 0x00000006ff067220 */
/* 0x000fc40000400000 */
/*0550*/ FFMA R7, R5, 1.4426950216293334961, R10 ; /* 0x3fb8aa3b05077823 */
/* 0x000fe4000000000a */
/*0560*/ FMUL R10, R6, 3 ; /* 0x40400000060a7820 */
/* 0x000fe40000400000 */
/*0570*/ FFMA R7, RZ, 1.9251366722983220825e-08, R7 ; /* 0x32a55e34ff077823 */
/* 0x000fc80000000007 */
/*0580*/ FFMA R7, R5, R10, R7 ; /* 0x0000000a05077223 */
/* 0x000fe20000000007 */
/*0590*/ MOV R10, 0x391fcb8e ; /* 0x391fcb8e000a7802 */
/* 0x000fc60000000f00 */
/*05a0*/ FFMA R7, RZ, R6, R7 ; /* 0x00000006ff077223 */
/* 0x000fc80000000007 */
/*05b0*/ FADD R5, R8, R7 ; /* 0x0000000708057221 */
/* 0x000fc80000000000 */
/*05c0*/ FMUL R6, R0, R5.reuse ; /* 0x0000000500067220 */
/* 0x080fe40000400000 */
/*05d0*/ FADD R8, -R8, R5 ; /* 0x0000000508087221 */
/* 0x000fe40000000100 */
/*05e0*/ FRND R9, R6 ; /* 0x0000000600097307 */
/* 0x000e220000201000 */
/*05f0*/ FFMA R5, R0, R5, -R6 ; /* 0x0000000500057223 */
/* 0x000fe20000000806 */
/*0600*/ FSETP.GT.AND P3, PT, |R6|, 152, PT ; /* 0x431800000600780b */
/* 0x000fe20003f64200 */
/*0610*/ FADD R8, R7, -R8 ; /* 0x8000000807087221 */
/* 0x000fc80000000000 */
/*0620*/ FFMA R8, R0, R8, R5 ; /* 0x0000000800087223 */
/* 0x000fe40000000005 */
/*0630*/ FADD R5, R6, -R9 ; /* 0x8000000906057221 */
/* 0x001fe20000000000 */
/*0640*/ FSETP.GT.AND P4, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f84000 */
/*0650*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x000fe20000000000 */
/*0660*/ SEL R7, RZ, 0x83000000, P4 ; /* 0x83000000ff077807 */
/* 0x000fe40002000000 */
/*0670*/ FSETP.GEU.AND P4, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe20003f8e000 */
/*0680*/ FFMA R8, R5, R10, 0.0013391353422775864601 ; /* 0x3aaf85ed05087423 */
/* 0x000fe2000000000a */
/*0690*/ IADD3 R9, R7, 0x7f000000, RZ ; /* 0x7f00000007097810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ FFMA R10, R5.reuse, R8, 0.0096188392490148544312 ; /* 0x3c1d9856050a7423 */
/* 0x040fe40000000008 */
/*06b0*/ F2I.NTZ R8, R6 ; /* 0x0000000600087305 */
/* 0x0000640000203100 */
/*06c0*/ FFMA R10, R5, R10, 0.055503588169813156128 ; /* 0x3d6357bb050a7423 */
/* 0x000fc8000000000a */
/*06d0*/ FFMA R10, R5, R10, 0.24022644758224487305 ; /* 0x3e75fdec050a7423 */
/* 0x000fe2000000000a */
/*06e0*/ FSEL R6, RZ, +INF , !P4 ; /* 0x7f800000ff067808 */
/* 0x001fc60006000000 */
/*06f0*/ FFMA R10, R5, R10, 0.69314718246459960938 ; /* 0x3f317218050a7423 */
/* 0x000fc8000000000a */
/*0700*/ FFMA R10, R5, R10, 1 ; /* 0x3f800000050a7423 */
/* 0x000fe2000000000a */
/*0710*/ LEA R8, R8, -R7, 0x17 ; /* 0x8000000708087211 */
/* 0x002fc600078eb8ff */
/*0720*/ FMUL R9, R9, R10 ; /* 0x0000000a09097220 */
/* 0x000fc80000400000 */
/*0730*/ @!P3 FMUL R6, R8, R9 ; /* 0x000000090806b220 */
/* 0x000fe40000400000 */
/*0740*/ @P5 FADD R6, R0, 2 ; /* 0x4000000000065421 */
/* 0x000fe40000000000 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ BSSY B0, 0x880 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0770*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fe40000000f00 */
/*0780*/ @P0 FSEL R4, RZ, +INF , !P1 ; /* 0x7f800000ff040808 */
/* 0x000fe20004800000 */
/*0790*/ @!P2 BRA 0x870 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.GTU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0c200 */
/*07b0*/ @P0 BRA 0x860 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*07c0*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f0d200 */
/*07d0*/ FSETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720b */
/* 0x000fda0004702400 */
/*07e0*/ @P0 BRA 0x840 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*07f0*/ FSETP.GEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fe40003f0e000 */
/*0800*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fd60000000f00 */
/*0810*/ @P0 BRA 0x870 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0820*/ FADD R5, -R4, -RZ ; /* 0x800000ff04057221 */
/* 0x000fe20000000100 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x000fe20000000000 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD R5, R0, 3 ; /* 0x4040000000057421 */
/* 0x000fe40000000000 */
/*0870*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0880*/ FADD R0, R6, R5 ; /* 0x0000000506007221 */
/* 0x000fe20000000000 */
/*0890*/ BSSY B0, 0x970 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*08a0*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x0000620000001400 */
/*08b0*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*08d0*/ @!P0 BRA 0x920 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*08e0*/ MOV R9, 0x900 ; /* 0x0000090000097802 */
/* 0x003fe40000000f00 */
/*08f0*/ CALL.REL.NOINC 0x990 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0900*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*0910*/ BRA 0x960 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0920*/ FMUL.FTZ R5, R0, R7 ; /* 0x0000000700057220 */
/* 0x003fe40000410000 */
/*0930*/ FMUL.FTZ R4, R7, 0.5 ; /* 0x3f00000007047820 */
/* 0x000fe40000410000 */
/*0940*/ FFMA R0, -R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc80000000100 */
/*0950*/ FFMA R5, R0, R4, R5 ; /* 0x0000000400057223 */
/* 0x000fe40000000005 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*09a0*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*09b0*/ @!P0 BRA 0xac0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*09c0*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*09d0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*09e0*/ @!P0 BRA 0xac0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*0a00*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*0a10*/ @P0 BRA 0xac0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0a30*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000050823 */
/* 0x000fc800000000ff */
/*0a40*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0a50*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0a60*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*0a70*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0a80*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*0a90*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0aa0*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0ab0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0ac0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0ad0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*0ae0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fc80000000f00 */
/*0af0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff50004007950 */
/* 0x000fea0003c3ffff */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
cudaMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
cudaMemcpy(a_h, a_d, sizeof(float)*tam, cudaMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
cudaFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} | .file "tmpxft_000687ff_00000000-6_matrix_transformation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nTempo Clock: %f secs"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "tamanho: %d \t tempo decorrido: %f\n"
.section .rodata.str1.1
.LC6:
.string "tempo total decorrido: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10, %r15d
jmp .L16
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rcx
subq 96(%rsp), %rcx
imull $1000, %ecx, %ecx
movq 120(%rsp), %rsi
subq 104(%rsp), %rsi
movabsq $2361183241434822607, %rax
imulq %rsi
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addl %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
subl $1, %r14d
je .L22
.L15:
call clock@PLT
movq %rax, %r15
movl $0, %esi
movq 16(%rsp), %rdi
call gettimeofday@PLT
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L13
.L12:
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 24(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z12square_arrayPfiPfi
jmp .L14
.L22:
movl 28(%rsp), %r15d
divss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r15d
cmpl $19, %r15d
je .L23
.L16:
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,4), %r12
testb $31, %bl
setne %dl
movzbl %dl, %edx
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $5, %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $10, %r14d
movl $0x00000000, 12(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl %r15d, 28(%rsp)
jmp .L15
.L23:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 80(%rsp), %rcx
subq 64(%rsp), %rcx
imull $1000, %ecx, %ecx
movq 88(%rsp), %rsi
subq 72(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
movq %rdx, %rax
sarq $7, %rax
sarq $63, %rsi
subq %rsi, %rax
leal (%rcx,%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
cudaMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
cudaMemcpy(a_h, a_d, sizeof(float)*tam, cudaMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
cudaFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
hipMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
hipMemcpy(a_h, a_d, sizeof(float)*tam, hipMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
hipFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
hipMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
hipMemcpy(a_h, a_d, sizeof(float)*tam, hipMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
hipFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v2
v_frexp_mant_f32_e64 v3, |v2|
v_cndmask_b32_e64 v4, 2.0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v3
v_frexp_mant_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, 1, s0
v_frexp_exp_i32_f32_e32 v4, v4
v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v3, v3, v5
v_cndmask_b32_e64 v5, 0, 1, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v5, v6, v5
v_add_f32_e32 v7, 1.0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v9, -1.0, v3 :: v_dual_add_f32 v12, -1.0, v5
v_add_f32_e32 v8, 1.0, v5
v_rcp_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v15, v12, v10
v_dual_mul_f32 v11, v9, v6 :: v_dual_mul_f32 v16, v8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v7, v11
v_add_f32_e32 v13, -1.0, v7
v_sub_f32_e32 v3, v3, v13
v_add_f32_e32 v13, -1.0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v11, v7, -v14
v_fmac_f32_e32 v7, v11, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v5, v13
v_fma_f32 v5, v15, v8, -v16
v_add_f32_e32 v8, v14, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, v15, v3
v_dual_sub_f32 v3, v9, v8 :: v_dual_sub_f32 v14, v8, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v13, v16, v5
v_sub_f32_e32 v9, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v17, v12, v13 :: v_dual_sub_f32 v8, v9, v8
v_dual_sub_f32 v9, v13, v16 :: v_dual_sub_f32 v12, v12, v17
v_sub_f32_e32 v7, v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v7, v7, v8 :: v_dual_sub_f32 v8, v12, v13
v_sub_f32_e32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v8
v_add_f32_e32 v5, v17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v10, v5
v_add_f32_e32 v8, v15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v7 :: v_dual_mul_f32 v12, v8, v8
v_mul_f32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v11, v3
v_sub_f32_e32 v7, v6, v11
v_mul_f32_e32 v9, v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v7
v_fma_f32 v10, v6, v6, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v3, v3
v_fmac_f32_e32 v10, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v9, v10
v_sub_f32_e32 v9, v13, v9
v_mul_f32_e32 v19, v6, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v9, v10, v9
v_sub_f32_e32 v7, v8, v15
v_fma_f32 v22, v13, v6, -v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v7
v_fma_f32 v7, v8, v8, -v12
v_add_f32_e32 v11, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v11
v_dual_fmaak_f32 v11, s2, v13, 0x3e91f4c4 :: v_dual_add_f32 v14, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v11, v13, v11, 0x3ecccdef :: v_dual_sub_f32 v12, v14, v12
v_dual_mul_f32 v16, v13, v11 :: v_dual_mul_f32 v21, v8, v14
v_fmaak_f32 v15, s2, v14, 0x3e91f4c4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v7, v12
v_fma_f32 v10, v13, v11, -v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v9, v11
v_add_f32_e32 v12, v16, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v16, v12, v16
v_add_f32_e32 v18, 0x3f2aaaaa, v12
v_sub_f32_e32 v10, v10, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v16, 0xbf2aaaaa, v18
v_add_f32_e32 v10, 0x31739010, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v12, v16
v_add_f32_e32 v10, v10, v12
v_fmac_f32_e32 v22, v13, v3
v_fma_f32 v13, v14, v8, -v21
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v12, v18, v10
v_dual_fmaak_f32 v15, v14, v15, 0x3ecccdef :: v_dual_fmac_f32 v22, v9, v6
v_ldexp_f32 v6, v6, 1
v_fmac_f32_e32 v13, v14, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v17, v14, v15
v_fmac_f32_e32 v13, v7, v8
v_ldexp_f32 v8, v8, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v11, v14, v15, -v17
v_add_f32_e32 v14, v19, v22
v_ldexp_f32 v5, v5, 1
v_fmac_f32_e32 v11, v7, v15
v_frexp_exp_i32_f32_e32 v15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v20, v17, v11
v_subrev_co_ci_u32_e64 v15, s0, 0, v15, s0
v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v23, 0x3f2aaaaa, v20
v_cvt_f32_i32_e32 v15, v15
v_sub_f32_e32 v17, v20, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v4, v4
v_cmp_eq_f32_e64 s0, 1.0, v2
v_dual_add_f32 v16, 0xbf2aaaaa, v23 :: v_dual_sub_f32 v11, v11, v17
v_sub_f32_e32 v17, v14, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, 0x31739010, v11
v_sub_f32_e32 v11, v20, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v17, v22, v17
v_add_f32_e32 v7, v9, v11
v_sub_f32_e32 v9, v18, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v11, v14, v12 :: v_dual_add_f32 v18, v23, v7
v_add_f32_e32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, v14, v12, -v11
v_dual_sub_f32 v19, v23, v18 :: v_dual_fmac_f32 v10, v14, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v7, v19 :: v_dual_fmac_f32 v10, v17, v12
v_add_f32_e32 v17, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v17, v11
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v16, v21, v13 :: v_dual_add_f32 v3, v3, v10
v_mul_f32_e32 v9, v16, v18
v_sub_f32_e32 v14, v16, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, v16, v18, -v9
v_dual_sub_f32 v13, v13, v14 :: v_dual_add_f32 v14, v6, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v16, v7
v_sub_f32_e32 v6, v14, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v13, v18
v_sub_f32_e32 v6, v17, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v9, v12
v_dual_add_f32 v3, v3, v6 :: v_dual_add_f32 v10, v8, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v11, v9 :: v_dual_sub_f32 v6, v10, v8
v_sub_f32_e32 v8, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v11, v6 :: v_dual_add_f32 v5, v5, v8
v_add_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v11, v10, v5
v_mul_f32_e32 v7, 0x3f317218, v15
v_dual_mul_f32 v13, 0x3f317218, v4 :: v_dual_sub_f32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, v15, 0x3f317218, -v7
v_fma_f32 v9, v4, 0x3f317218, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v10 :: v_dual_fmac_f32 v16, 0xb102e308, v15
v_fmac_f32_e32 v9, 0xb102e308, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v7, v16
v_dual_add_f32 v6, v13, v9 :: v_dual_sub_f32 v7, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v16, v7
v_add_f32_e32 v16, v6, v11
v_add_f32_e32 v15, v14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v12, v15
v_sub_f32_e32 v14, v15, v14
v_dual_sub_f32 v8, v4, v12 :: v_dual_sub_f32 v3, v3, v14
v_sub_f32_e32 v14, v16, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v17, v4, v8
v_sub_f32_e32 v8, v15, v8
v_add_f32_e32 v15, v7, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_sub_f32 v10, v11, v14 :: v_dual_sub_f32 v13, v6, v13
v_sub_f32_e32 v12, v12, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_sub_f32 v9, v9, v13 :: v_dual_add_f32 v8, v8, v12
v_dual_sub_f32 v12, v16, v14 :: v_dual_sub_f32 v13, v15, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v14, v9, v5
v_add_f32_e32 v8, v15, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v12 :: v_dual_sub_f32 v11, v15, v13
v_dual_sub_f32 v3, v3, v13 :: v_dual_add_f32 v12, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v6, v10, v6 :: v_dual_sub_f32 v7, v7, v11
v_sub_f32_e32 v10, v14, v9
v_sub_f32_e32 v4, v12, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v6, v14, v6 :: v_dual_add_f32 v3, v3, v7
v_dual_sub_f32 v7, v14, v10 :: v_dual_sub_f32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v8, v16, v6 :: v_dual_add_f32 v3, v3, v4
v_sub_f32_e32 v4, v5, v10
v_sub_f32_e32 v5, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v8, v16
v_cndmask_b32_e64 v10, 0x40400000, 1.0, s0
v_add_f32_e32 v9, v12, v3
v_dual_add_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v21, 0.5, v10 :: v_dual_sub_f32 v6, v9, v12
v_mul_f32_e32 v7, v10, v9
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_trunc_f32_e32 v24, v21
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v5, v10, v9, -v7
v_cmp_class_f32_e64 s0, v7, 0x204
v_add_f32_e32 v6, v8, v4
v_cmp_neq_f32_e64 s1, v24, v21
v_fmac_f32_e32 v5, v10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v6, v8
v_dual_mul_f32 v8, v2, v6 :: v_dual_add_f32 v9, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v4, v3
v_fma_f32 v4, v2, v6, -v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v9, v7, s0
v_sub_f32_e32 v7, v9, v7
v_fmac_f32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e64 s0, 0x42b17218, v6
v_sub_f32_e32 v5, v5, v7
v_cmp_neq_f32_e64 s2, 0x7f800000, |v6|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v11, v8, v4
v_cndmask_b32_e64 v3, 0, 0x37000000, s0
v_cmp_class_f32_e64 s0, v8, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, v5, s2
v_sub_f32_e32 v12, v6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, v11, v8, s0
v_sub_f32_e32 v8, v11, v8
v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v14, 0x3fb8aa3b, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_f32_e64 s0, 0x42b17218, v13
v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v12
v_sub_f32_e32 v4, v4, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v16, v12, 0x3fb8aa3b, -v14
v_cndmask_b32_e64 v15, 0, 0x37000000, s0
v_rndne_f32_e32 v17, v14
v_cmp_eq_f32_e64 s0, v2, |v2|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v16, 0x32a5705f, v12
v_sub_f32_e32 v18, v13, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v14, v14, v17
v_cndmask_b32_e64 v20, 0, |v2|, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v19, 0x3fb8aa3b, v18 :: v_dual_add_f32 v14, v14, v16
v_trunc_f32_e32 v16, v10
v_fma_f32 v22, v18, 0x3fb8aa3b, -v19
v_rndne_f32_e32 v23, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_exp_f32_e32 v14, v14
v_cmp_eq_f32_e64 s0, v16, v10
v_cvt_i32_f32_e32 v10, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v22, 0x32a5705f, v18 :: v_dual_sub_f32 v9, v19, v23
v_cvt_i32_f32_e32 v5, v23
s_and_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, 0, v2, s1
v_add_f32_e32 v7, v9, v22
s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v9, v14, v10
v_exp_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0, v9, s2
v_cmp_nlt_f32_e64 s2, 0x42b17218, v12
v_cndmask_b32_e64 v7, 0x7f800000, v7, s2
v_cmp_neq_f32_e64 s2, 0x7f800000, |v13|
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v6, v5
v_cndmask_b32_e64 v6, 1.0, v2, s1
v_fma_f32 v3, v7, v3, v7
v_cndmask_b32_e64 v4, 0, v4, s2
v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v18
v_cmp_class_f32_e64 s1, v2, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v15, v4
v_cndmask_b32_e64 v5, 0, v5, s2
v_cmp_eq_f32_e64 s2, 0x7f800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v7, s2
v_cmp_nlt_f32_e64 s2, 0x42b17218, v18
v_cndmask_b32_e64 v7, 0x7f800000, 0, vcc_lo
v_bfi_b32 v3, 0x7fffffff, v3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0x7f800000, v5, s2
v_bfi_b32 v7, 0x7fffffff, v7, v8
v_cndmask_b32_e64 v6, v20, 1.0, vcc_lo
s_or_b32 vcc_lo, vcc_lo, s1
v_cndmask_b32_e64 v8, 0x7fc00000, v3, s0
v_fma_f32 v4, v5, v4, v5
v_cmp_eq_f32_e64 s0, 0x7f800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_gt_f32_e64 s0, 0, v2
v_cndmask_b32_e64 v4, |v4|, v6, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cmp_u_f32_e32 vcc_lo, v2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v4, 0x7fc00000, vcc_lo
v_cndmask_b32_e64 v3, v3, 0x7fc00000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v2
v_fma_f32 v7, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include<sys/time.h>
#include <time.h>
#include<math.h>
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = sqrtf(powf(2,a[idx]) + powf(a[idx],3));
}
// main routine that executes on the host
int main(void)
{
struct timeval iniciototal, finaltotal;
gettimeofday(&iniciototal, NULL);
int N, exec; // Number of elements in arrays
struct timeval inicio, final;
int tmili,tmilifim;
float media, soma ;
int tam;
for (N = 10; N <= 18; N++)
{
soma=0;
tam = pow(2,N);
for(exec =1; exec <= 10; exec++)
{
clock_t start, end;
double cpu_time_used;
start = clock();
gettimeofday(&inicio, NULL);
float *a_h, *a_d; // Pointer to host & device arrays
size_t size = tam * sizeof(float);
a_h = (float *)malloc(size); // Allocate array on host
hipMalloc((void **) &a_d, size); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i=0; i<tam; i++) a_h[i] = (float)i;
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 32;
int n_blocks = tam/block_size + (tam%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_d, tam);
// Retrieve result from device and store it in host array
hipMemcpy(a_h, a_d, sizeof(float)*tam, hipMemcpyDeviceToHost);
//printf("%d\n", n_blocks);
// Print results
//for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
free(a_h);
hipFree(a_d);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("\nTempo Clock: %f secs", cpu_time_used);
gettimeofday(&final, NULL);
tmili = (int) (1000 * (final.tv_sec - inicio.tv_sec) + (final.tv_usec - inicio.tv_usec) / 1000);
soma+=tmili;
}
media = soma/10;
printf("tamanho: %d \t tempo decorrido: %f\n", tam, media);
}
gettimeofday(&finaltotal, NULL);
tmilifim = (int) (1000 * (finaltotal.tv_sec - iniciototal.tv_sec) + (finaltotal.tv_usec - iniciototal.tv_usec) / 1000);
printf("tempo total decorrido: %d\n", tmilifim);
} | .text
.file "matrix_transformation.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rbx # imm = 0x100000000
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $10, %edi
leaq 32(%rbx), %rax
movq %rax, 56(%rsp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r13d, %esi
movb $1, %al
callq printf
movl 20(%rsp), %edi # 4-byte Reload
incl %edi
cmpl $19, %edi
je .LBB1_9
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_4 Depth 3
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %edi, 20(%rsp) # 4-byte Spill
callq ldexp@PLT
cvttsd2si %xmm0, %r13d
movslq %r13d, %rax
leaq (,%rax,4), %rbx
leal 31(%rax), %r14d
testl %eax, %eax
cmovnsl %r13d, %r14d
sarl $5, %r14d
andl $31, %eax
cmpl $1, %eax
sbbl $-1, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
xorpd %xmm0, %xmm0
movl $1, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbp, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 120(%rsp), %eax
subl 136(%rsp), %eax
imull $1000, %eax, %ecx # imm = 0x3E8
movq 128(%rsp), %rax
subq 144(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
addl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movaps %xmm1, %xmm0
incl %r12d
cmpl $11, %r12d
je .LBB1_8
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
movss %xmm0, 24(%rsp) # 4-byte Spill
callq clock
movq %rax, %r15
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %r13d, %r13d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq 56(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl %r13d, 28(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z12square_arrayPfi, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_9:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 32(%rsp), %eax
subl 152(%rsp), %eax
imull $1000, %eax, %ecx # imm = 0x3E8
movq 40(%rsp), %rax
subq 160(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
shrq $7, %rdx
addl %edx, %esi
addl %ecx, %esi
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTempo Clock: %f secs"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "tamanho: %d \t tempo decorrido: %f\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "tempo total decorrido: %d\n"
.size .L.str.2, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000687ff_00000000-6_matrix_transformation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nTempo Clock: %f secs"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "tamanho: %d \t tempo decorrido: %f\n"
.section .rodata.str1.1
.LC6:
.string "tempo total decorrido: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10, %r15d
jmp .L16
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rcx
subq 96(%rsp), %rcx
imull $1000, %ecx, %ecx
movq 120(%rsp), %rsi
subq 104(%rsp), %rsi
movabsq $2361183241434822607, %rax
imulq %rsi
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addl %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
subl $1, %r14d
je .L22
.L15:
call clock@PLT
movq %rax, %r15
movl $0, %esi
movq 16(%rsp), %rdi
call gettimeofday@PLT
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L13
.L12:
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 24(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z12square_arrayPfiPfi
jmp .L14
.L22:
movl 28(%rsp), %r15d
divss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r15d
cmpl $19, %r15d
je .L23
.L16:
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,4), %r12
testb $31, %bl
setne %dl
movzbl %dl, %edx
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $5, %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $10, %r14d
movl $0x00000000, 12(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl %r15d, 28(%rsp)
jmp .L15
.L23:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 80(%rsp), %rcx
subq 64(%rsp), %rcx
imull $1000, %ecx, %ecx
movq 88(%rsp), %rsi
subq 72(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
movq %rdx, %rax
sarq $7, %rax
sarq $63, %rsi
subq %rsi, %rax
leal (%rcx,%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_transformation.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rbx # imm = 0x100000000
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $10, %edi
leaq 32(%rbx), %rax
movq %rax, 56(%rsp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r13d, %esi
movb $1, %al
callq printf
movl 20(%rsp), %edi # 4-byte Reload
incl %edi
cmpl $19, %edi
je .LBB1_9
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_4 Depth 3
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %edi, 20(%rsp) # 4-byte Spill
callq ldexp@PLT
cvttsd2si %xmm0, %r13d
movslq %r13d, %rax
leaq (,%rax,4), %rbx
leal 31(%rax), %r14d
testl %eax, %eax
cmovnsl %r13d, %r14d
sarl $5, %r14d
andl $31, %eax
cmpl $1, %eax
sbbl $-1, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
xorpd %xmm0, %xmm0
movl $1, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbp, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 120(%rsp), %eax
subl 136(%rsp), %eax
imull $1000, %eax, %ecx # imm = 0x3E8
movq 128(%rsp), %rax
subq 144(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
addl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movaps %xmm1, %xmm0
incl %r12d
cmpl $11, %r12d
je .LBB1_8
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
movss %xmm0, 24(%rsp) # 4-byte Spill
callq clock
movq %rax, %r15
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %r13d, %r13d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq 56(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_2 Depth=2
movq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl %r13d, 28(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z12square_arrayPfi, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_9:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 32(%rsp), %eax
subl 152(%rsp), %eax
imull $1000, %eax, %ecx # imm = 0x3E8
movq 40(%rsp), %rax
subq 160(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
shrq $7, %rdx
addl %edx, %esi
addl %ecx, %esi
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTempo Clock: %f secs"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "tamanho: %d \t tempo decorrido: %f\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "tempo total decorrido: %d\n"
.size .L.str.2, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
cudaDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
cudaFree(array);
} | code for sm_80
Function : _Z3minPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xb40 ; /* 0x00000b0000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R19, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff137424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0xb30 ; /* 0x00000aa000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff117624 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B1, 0xa90 ; /* 0x000009e000017945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff137424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R17, R17, c[0x0][0xc], RZ ; /* 0x0000030011117a24 */
/* 0x000fc800078e02ff */
/*00d0*/ I2F.U32.RP R5, R17 ; /* 0x0000001100057306 */
/* 0x000e220000209000 */
/*00e0*/ IMAD.IADD R2, R0, 0x1, R17.reuse ; /* 0x0000000100027824 */
/* 0x100fe200078e0211 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f45070 */
/*0100*/ IMAD.MOV R7, RZ, RZ, -R17 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a11 */
/*0110*/ LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff047212 */
/* 0x000fe200078e33ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0130*/ IADD3 R4, R4, c[0x0][0x168], R17 ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe011 */
/*0140*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R3, R5, 0xffffffe, RZ ; /* 0x0ffffffe05037810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0170*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*0180*/ IMAD.HI.U32 R7, R3, R7, R2 ; /* 0x0000000703077227 */
/* 0x000fcc00078e0002 */
/*0190*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R2, RZ, RZ, -R7 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a07 */
/*01b0*/ IMAD R4, R17, R2, R4 ; /* 0x0000000211047224 */
/* 0x000fe400078e0204 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0000 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IMAD.IADD R4, R4, 0x1, -R17 ; /* 0x0000000104040824 */
/* 0x000fe200078e0a11 */
/*01f0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R7, RZ, R17, RZ, 0x33, !PT ; /* 0x00000011ff07a212 */
/* 0x000fc800078e33ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x3, PT ; /* 0x000000030700780c */
/* 0x040fe40003f06070 */
/*0240*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0250*/ LOP3.LUT R18, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307127812 */
/* 0x000fce00078ec0ff */
/*0260*/ @!P0 BRA 0xa80 ; /* 0x0000081000008947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.IADD R21, R7, 0x1, -R18 ; /* 0x0000000107157824 */
/* 0x000fe200078e0a12 */
/*0280*/ BSSY B0, 0x960 ; /* 0x000006d000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R19, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff137424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*02b0*/ ISETP.GT.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f04270 */
/*02c0*/ @!P0 BRA 0x950 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*02d0*/ ISETP.GT.AND P1, PT, R21, 0xc, PT ; /* 0x0000000c1500780c */
/* 0x000fe20003f24270 */
/*02e0*/ BSSY B3, 0x6f0 ; /* 0x0000040000037945 */
/* 0x000fe20003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0300*/ @!P1 BRA 0x6e0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0330*/ IMAD.WIDE R10, R2, R5, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x000fe200078e0205 */
/*0340*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fc80007ffe011 */
/*0350*/ IADD3 R4, R17.reuse, R2, R17 ; /* 0x0000000211047210 */
/* 0x040fe20007ffe011 */
/*0360*/ IMAD.WIDE R12, R17.reuse, 0x4, R10 ; /* 0x00000004110c7825 */
/* 0x040fe200078e020a */
/*0370*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0000a6000c1e1900 */
/*0380*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fe200078e0205 */
/*0390*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x0002e6000c1e1900 */
/*03a0*/ IMAD.WIDE R24, R17.reuse, 0x4, R12 ; /* 0x0000000411187825 */
/* 0x040fe200078e020c */
/*03b0*/ IADD3 R4, R17.reuse, R4, R17 ; /* 0x0000000411047210 */
/* 0x040fe20007ffe011 */
/*03c0*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000968000c1e1900 */
/*03d0*/ IMAD.WIDE R28, R17, 0x4, R24 ; /* 0x00000004111c7825 */
/* 0x000fc400078e0218 */
/*03e0*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000164000c1e1900 */
/*03f0*/ IMAD.WIDE R6, R17.reuse, 0x4, R2 ; /* 0x0000000411067825 */
/* 0x040fe400078e0202 */
/*0400*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x000362000c1e1900 */
/*0410*/ IADD3 R4, R17, R4, R17 ; /* 0x0000000411047210 */
/* 0x000fc60007ffe011 */
/*0420*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe200078e0206 */
/*0430*/ LDG.E R25, [R6.64] ; /* 0x0000000406197981 */
/* 0x001166000c1e1900 */
/*0440*/ IMAD.WIDE R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x000fe200078e0205 */
/*0450*/ LDG.E R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000166000c1e1900 */
/*0460*/ IMAD.WIDE R12, R17.reuse, 0x4, R8 ; /* 0x00000004110c7825 */
/* 0x042fe200078e0208 */
/*0470*/ IADD3 R4, R17.reuse, R4, R17 ; /* 0x0000000411047210 */
/* 0x040fe20007ffe011 */
/*0480*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x000364000c1e1900 */
/*0490*/ IMAD.WIDE R10, R17, 0x4, R14 ; /* 0x00000004110a7825 */
/* 0x000fc400078e020e */
/*04a0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000162000c1e1900 */
/*04b0*/ IADD3 R28, R17, R4, R17 ; /* 0x00000004111c7210 */
/* 0x000fc60007ffe011 */
/*04c0*/ IMAD.WIDE R2, R17, 0x4, R10 ; /* 0x0000000411027825 */
/* 0x010fe400078e020a */
/*04d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f24000c1e1900 */
/*04e0*/ IMAD.WIDE R4, R28, R5, c[0x0][0x160] ; /* 0x000058001c047625 */
/* 0x000fc800078e0205 */
/*04f0*/ IMAD.WIDE R6, R17.reuse, 0x4, R2 ; /* 0x0000000411067825 */
/* 0x041fe400078e0202 */
/*0500*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0510*/ IMAD.WIDE R8, R17.reuse, 0x4, R4 ; /* 0x0000000411087825 */
/* 0x040fe400078e0204 */
/*0520*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f22000c1e1900 */
/*0540*/ IMAD.WIDE R12, R17, 0x4, R8 ; /* 0x00000004110c7825 */
/* 0x000fc600078e0208 */
/*0550*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f26000c1e1900 */
/*0560*/ IMAD.WIDE R14, R17, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x002fe400078e020c */
/*0570*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1900 */
/*0580*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1900 */
/*0590*/ IADD3 R21, R21, -0x10, RZ ; /* 0xfffffff015157810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R21, 0xc, PT ; /* 0x0000000c1500780c */
/* 0x000fe40003f24270 */
/*05b0*/ IMNMX R19, R16, R19, PT ; /* 0x0000001310137217 */
/* 0x004fc80003800200 */
/*05c0*/ IMNMX R19, R19, R22, PT ; /* 0x0000001613137217 */
/* 0x008fc80003800200 */
/*05d0*/ IMNMX R24, R19, R24, PT ; /* 0x0000001813187217 */
/* 0x020fc80003800200 */
/*05e0*/ IMNMX R23, R24, R23, PT ; /* 0x0000001718177217 */
/* 0x000fc80003800200 */
/*05f0*/ IMNMX R20, R23, R20, PT ; /* 0x0000001417147217 */
/* 0x000fc80003800200 */
/*0600*/ IMNMX R25, R20, R25, PT ; /* 0x0000001914197217 */
/* 0x000fc80003800200 */
/*0610*/ IMNMX R26, R25, R26, PT ; /* 0x0000001a191a7217 */
/* 0x000fc80003800200 */
/*0620*/ IMNMX R26, R26, R27, PT ; /* 0x0000001b1a1a7217 */
/* 0x000fc80003800200 */
/*0630*/ IMNMX R29, R26, R29, PT ; /* 0x0000001d1a1d7217 */
/* 0x000fc80003800200 */
/*0640*/ IMNMX R29, R29, R10, PT ; /* 0x0000000a1d1d7217 */
/* 0x010fc80003800200 */
/*0650*/ IMNMX R29, R29, R2, PT ; /* 0x000000021d1d7217 */
/* 0x000fc80003800200 */
/*0660*/ IMNMX R29, R29, R6, PT ; /* 0x000000061d1d7217 */
/* 0x000fc80003800200 */
/*0670*/ IMNMX R29, R29, R4, PT ; /* 0x000000041d1d7217 */
/* 0x000fc80003800200 */
/*0680*/ IMNMX R29, R29, R8, PT ; /* 0x000000081d1d7217 */
/* 0x000fe40003800200 */
/*0690*/ IADD3 R2, R17, R28, R17.reuse ; /* 0x0000001c11027210 */
/* 0x100fe40007ffe011 */
/*06a0*/ IMNMX R29, R29, R12, PT ; /* 0x0000000c1d1d7217 */
/* 0x000fe40003800200 */
/*06b0*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fe40007ffe011 */
/*06c0*/ IMNMX R19, R29, R14, PT ; /* 0x0000000e1d137217 */
/* 0x000fe20003800200 */
/*06d0*/ @P1 BRA 0x320 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P1, PT, R21, 0x4, PT ; /* 0x000000041500780c */
/* 0x000fe20003f24270 */
/*0700*/ BSSY B3, 0x920 ; /* 0x0000021000037945 */
/* 0x000fd80003800000 */
/*0710*/ @!P1 BRA 0x910 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE R8, R2, R23, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe200078e0217 */
/*0740*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fc80007ffe011 */
/*0750*/ IADD3 R2, R17.reuse, R2, R17 ; /* 0x0000000211027210 */
/* 0x040fe20007ffe011 */
/*0760*/ IMAD.WIDE R10, R17.reuse, 0x4, R8 ; /* 0x00000004110a7825 */
/* 0x040fe200078e0208 */
/*0770*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x0000aa000c1e1900 */
/*0780*/ IMAD.WIDE R12, R17, 0x4, R10 ; /* 0x00000004110c7825 */
/* 0x000fe400078e020a */
/*0790*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IMAD.WIDE R22, R2, R23, c[0x0][0x160] ; /* 0x0000580002167625 */
/* 0x000fc800078e0217 */
/*07b0*/ IMAD.WIDE R14, R17.reuse, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x040fe400078e020c */
/*07c0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*07d0*/ IMAD.WIDE R4, R17.reuse, 0x4, R22 ; /* 0x0000000411047825 */
/* 0x040fe400078e0216 */
/*07e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*07f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1900 */
/*0800*/ IMAD.WIDE R6, R17, 0x4, R4 ; /* 0x0000000411067825 */
/* 0x000fc600078e0204 */
/*0810*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f66000c1e1900 */
/*0820*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x041fe400078e0206 */
/*0830*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f68000c1e1900 */
/*0840*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1900 */
/*0850*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fc40007ffe011 */
/*0860*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0870*/ IADD3 R21, R21, -0x8, RZ ; /* 0xfffffff815157810 */
/* 0x000fe40007ffe0ff */
/*0880*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fe40007ffe011 */
/*0890*/ IMNMX R16, R19, R16, PT ; /* 0x0000001013107217 */
/* 0x004fc80003800200 */
/*08a0*/ IMNMX R11, R16, R11, PT ; /* 0x0000000b100b7217 */
/* 0x008fc80003800200 */
/*08b0*/ IMNMX R11, R11, R12, PT ; /* 0x0000000c0b0b7217 */
/* 0x010fc80003800200 */
/*08c0*/ IMNMX R11, R11, R14, PT ; /* 0x0000000e0b0b7217 */
/* 0x020fc80003800200 */
/*08d0*/ IMNMX R11, R11, R22, PT ; /* 0x000000160b0b7217 */
/* 0x000fc80003800200 */
/*08e0*/ IMNMX R11, R11, R4, PT ; /* 0x000000040b0b7217 */
/* 0x000fc80003800200 */
/*08f0*/ IMNMX R11, R11, R6, PT ; /* 0x000000060b0b7217 */
/* 0x000fc80003800200 */
/*0900*/ IMNMX R19, R11, R8, PT ; /* 0x000000080b137217 */
/* 0x000fe40003800200 */
/*0910*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.NE.OR P0, PT, R21, RZ, P0 ; /* 0x000000ff1500720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0940*/ @!P0 BRA 0xa80 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0970*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0205 */
/*0980*/ IMAD.WIDE R6, R17.reuse, 0x4, R4 ; /* 0x0000000411067825 */
/* 0x040fe400078e0204 */
/*0990*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe400078e0206 */
/*09b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R17, 0x4, R8 ; /* 0x00000004110a7825 */
/* 0x000fc400078e0208 */
/*09d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1900 */
/*09f0*/ IADD3 R21, R21, -0x4, RZ ; /* 0xfffffffc15157810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ IADD3 R2, R17, R2, R17.reuse ; /* 0x0000000211027210 */
/* 0x100fe40007ffe011 */
/*0a10*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05270 */
/*0a20*/ IADD3 R2, R17, R2, R17 ; /* 0x0000000211027210 */
/* 0x000fc40007ffe011 */
/*0a30*/ IMNMX R19, R4, R19, PT ; /* 0x0000001304137217 */
/* 0x004fc80003800200 */
/*0a40*/ IMNMX R19, R19, R6, PT ; /* 0x0000000613137217 */
/* 0x008fc80003800200 */
/*0a50*/ IMNMX R19, R19, R8, PT ; /* 0x0000000813137217 */
/* 0x010fc80003800200 */
/*0a60*/ IMNMX R19, R19, R10, PT ; /* 0x0000000a13137217 */
/* 0x020fe20003800200 */
/*0a70*/ @P0 BRA 0x960 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0a80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xb30 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0ac0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0ad0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x0000a2000c1e1900 */
/*0ae0*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fc80007ffe0ff */
/*0af0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05270 */
/*0b00*/ IMAD.WIDE R2, R17, 0x4, R2 ; /* 0x0000000411027825 */
/* 0x001fe200078e0202 */
/*0b10*/ IMNMX R19, R4, R19, PT ; /* 0x0000001304137217 */
/* 0x004fd60003800200 */
/*0b20*/ @P0 BRA 0xad0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0b30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b40*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0b50*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b60*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0b70*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9lastDigitPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02c0*/ IMAD.HI R9, R8, 0x66666667, RZ ; /* 0x6666666708097827 */
/* 0x004fca00078e02ff */
/*02d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*02e0*/ LEA.HI.SX32 R9, R9, R10, 0x1e ; /* 0x0000000a09097211 */
/* 0x000fca00078ff2ff */
/*02f0*/ IMAD R9, R9, -0xa, R8 ; /* 0xfffffff609097824 */
/* 0x000fca00078e0208 */
/*0300*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x270 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0360*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fca00078e0208 */
/*0370*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD.HI R6, R2, 0x66666667, RZ ; /* 0x6666666702067827 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.U32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011606 */
/*03a0*/ LEA.HI.SX32 R9, R6, R7, 0x1e ; /* 0x0000000706097211 */
/* 0x000fe200078ff2ff */
/*03b0*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*03c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*03d0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0410*/ IMAD.HI R10, R2, 0x66666667, RZ ; /* 0x66666667020a7827 */
/* 0x004fca00078e02ff */
/*0420*/ SHF.R.U32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fc8000001160a */
/*0430*/ LEA.HI.SX32 R11, R10, R11, 0x1e ; /* 0x0000000b0a0b7211 */
/* 0x000fca00078ff2ff */
/*0440*/ IMAD R15, R11, -0xa, R2 ; /* 0xfffffff60b0f7824 */
/* 0x000fe400078e0202 */
/*0450*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0460*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.HI R12, R2, 0x66666667, RZ ; /* 0x66666667020c7827 */
/* 0x004fca00078e02ff */
/*0490*/ SHF.R.U32.HI R7, RZ, 0x1f, R12 ; /* 0x0000001fff077819 */
/* 0x001fc8000001160c */
/*04a0*/ LEA.HI.SX32 R9, R12, R7, 0x1e ; /* 0x000000070c097211 */
/* 0x000fe200078ff2ff */
/*04b0*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fc800078e0204 */
/*04c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*04d0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x000fc600078e020a */
/*04e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ IMAD.HI R2, R8, 0x66666667, RZ ; /* 0x6666666708027827 */
/* 0x004fca00078e02ff */
/*0540*/ SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x002fc80000011602 */
/*0550*/ LEA.HI.SX32 R11, R2, R5, 0x1e ; /* 0x00000005020b7211 */
/* 0x000fe200078ff2ff */
/*0560*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD R11, R11, -0xa, R8 ; /* 0xfffffff60b0b7824 */
/* 0x000fca00078e0208 */
/*0580*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101904 */
/*0590*/ @!P0 BRA 0x350 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
cudaDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
cudaFree(array);
} | .file "tmpxft_00062b6b_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d, "
.text
.globl _Z11fileToArrayPcPi
.type _Z11fileToArrayPcPi, @function
_Z11fileToArrayPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L4
.L5:
addl $1, %ebx
.L4:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L5
movl %ebx, (%r12)
movslq %ebx, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq %rbp, %rdi
call rewind@PLT
cmpl $0, (%r12)
jle .L6
movl $0, %ebx
leaq .LC1(%rip), %r13
.L7:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %edx
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L7
.L6:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11fileToArrayPcPi, .-_Z11fileToArrayPcPi
.globl _Z31__device_stub__Z9lastDigitPiS_iPiS_i
.type _Z31__device_stub__Z9lastDigitPiS_iPiS_i, @function
_Z31__device_stub__Z9lastDigitPiS_iPiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9lastDigitPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z9lastDigitPiS_iPiS_i, .-_Z31__device_stub__Z9lastDigitPiS_iPiS_i
.globl _Z9lastDigitPiS_i
.type _Z9lastDigitPiS_i, @function
_Z9lastDigitPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9lastDigitPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9lastDigitPiS_i, .-_Z9lastDigitPiS_i
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "q1b.txt"
.LC4:
.string "failed to open file %s\n"
.LC5:
.string "%d"
.LC6:
.string ", %d"
.text
.globl _Z16computeLastDigitPii
.type _Z16computeLastDigitPii, @function
_Z16computeLastDigitPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L29
.L22:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $1, %ebp
jle .L23
movl %ebp, %ebp
salq $2, %rbp
movl $4, %ebx
leaq .LC6(%rip), %r13
.L24:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L23:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z9lastDigitPiS_iPiS_i
jmp .L21
.L29:
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16computeLastDigitPii, .-_Z16computeLastDigitPii
.globl _Z23__device_stub__Z3minPiiPii
.type _Z23__device_stub__Z3minPiiPii, @function
_Z23__device_stub__Z3minPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z23__device_stub__Z3minPiiPii, .-_Z23__device_stub__Z3minPiiPii
.globl _Z3minPii
.type _Z3minPii, @function
_Z3minPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3minPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z3minPii, .-_Z3minPii
.globl _Z10computeMinPii
.type _Z10computeMinPii, @function
_Z10computeMinPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaDeviceSynchronize@PLT
movq %rbx, %rax
leaq 128(%rbx), %rsi
movl $2147483647, %edx
.L41:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovg %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L41
movl %edx, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl %ebp, %esi
movq %rbx, %rdi
call _Z23__device_stub__Z3minPiiPii
jmp .L40
.cfi_endproc
.LFE2058:
.size _Z10computeMinPii, .-_Z10computeMinPii
.section .rodata.str1.1
.LC7:
.string "inp.txt"
.LC8:
.string "q1a.txt"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC7(%rip), %rdi
call _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movl %ebp, %esi
movq %rax, %rdi
call _Z16computeLastDigitPii
movl %ebp, %esi
movq %rbx, %rdi
call _Z10computeMinPii
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L49
.L46:
movl %r12d, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leaq .LC8(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3minPii"
.LC10:
.string "_Z9lastDigitPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9lastDigitPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
cudaDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
cudaFree(array);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
hipDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
hipFree(array);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
hipDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
hipFree(array);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9lastDigitPiS_i
.globl _Z9lastDigitPiS_i
.p2align 8
.type _Z9lastDigitPiS_i,@function
_Z9lastDigitPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_cmp_le_i32_e64 s0, s10, v1
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_mul_hi_i32 v4, v0, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 2, v4
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v4, 10
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_sub_nc_u32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9lastDigitPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9lastDigitPiS_i, .Lfunc_end0-_Z9lastDigitPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3minPii
.globl _Z3minPii
.p2align 8
.type _Z3minPii,@function
_Z3minPii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_bfrev_b32_e32 v0, -2
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_4
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_bfrev_b32_e32 v0, -2
v_mov_b32_e32 v5, v1
s_mov_b32 s1, 0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s0, s4
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 2
.LBB1_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v5, s4, v5
v_add_co_u32 v3, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s8, v5
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v6, v0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s1
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3minPii, .Lfunc_end1-_Z3minPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9lastDigitPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9lastDigitPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3minPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_B "q1b.txt"
#define OUTPUT_FILE_NAME_MIN "q1a.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void lastDigit(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
result[i] = array[i] % 10;
}
}
__global__
void min(int* array, int n){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int currentMin = INT_MAX;
for(int i = index; i < n; i += stride){
if(array[i] < currentMin){
currentMin = array[i];
}
}
array[index] = currentMin;
}
int computeMin(int* array, int n){
min<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, n);
hipDeviceSynchronize();
int minNum = INT_MAX;
for(int i = 0; i < NUM_THREADS_A; i++){
if(array[i] < minNum){
minNum = array[i];
}
}
return minNum;
}
void computeLastDigit(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(n));
lastDigit<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
// for (int i = 0; i < 10; i++) {
// printf("array[%d]: %d, result[%d]: %d\n", i, array[i], i, result[i]);
// }
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < n ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
//printf("Number of elements in array: %d\n", n);
// for (int i = 0; i < n; i++) {
// printf("%d, ", array[i]);
// }
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeLastDigit(array, n);
int min = computeMin(array, n);
FILE *output = fopen(OUTPUT_FILE_NAME_MIN, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_MIN);
fprintf(output, "%d", min);
fclose(output);
hipFree(array);
} | .text
.file "q1.hip"
.globl _Z11fileToArrayPcPi # -- Begin function _Z11fileToArrayPcPi
.p2align 4, 0x90
.type _Z11fileToArrayPcPi,@function
_Z11fileToArrayPcPi: # @_Z11fileToArrayPcPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movq $-4, %r15
movl $-1, %ebp
leaq 4(%rsp), %r12
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
incl %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movl %ebp, (%rbx)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movq %r14, %rdi
callq rewind
cmpl $0, (%rbx)
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
leaq 4(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB0_4
.LBB0_5: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fileToArrayPcPi, .Lfunc_end0-_Z11fileToArrayPcPi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__lastDigitPiS_i # -- Begin function _Z24__device_stub__lastDigitPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__lastDigitPiS_i,@function
_Z24__device_stub__lastDigitPiS_i: # @_Z24__device_stub__lastDigitPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9lastDigitPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__lastDigitPiS_i, .Lfunc_end1-_Z24__device_stub__lastDigitPiS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__minPii # -- Begin function _Z18__device_stub__minPii
.p2align 4, 0x90
.type _Z18__device_stub__minPii,@function
_Z18__device_stub__minPii: # @_Z18__device_stub__minPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z18__device_stub__minPii, .Lfunc_end2-_Z18__device_stub__minPii
.cfi_endproc
# -- End function
.globl _Z10computeMinPii # -- Begin function _Z10computeMinPii
.p2align 4, 0x90
.type _Z10computeMinPii,@function
_Z10computeMinPii: # @_Z10computeMinPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %rbx, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %eax, %edx
cmovll %edx, %eax
incq %rcx
cmpq $32, %rcx
jne .LBB3_3
# %bb.4:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10computeMinPii, .Lfunc_end3-_Z10computeMinPii
.cfi_endproc
# -- End function
.globl _Z16computeLastDigitPii # -- Begin function _Z16computeLastDigitPii
.p2align 4, 0x90
.type _Z16computeLastDigitPii,@function
_Z16computeLastDigitPii: # @_Z16computeLastDigitPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9lastDigitPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB4_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
cmpl $2, %ebx
jl .LBB4_7
# %bb.5: # %.lr.ph.preheader
movl %ebx, %ebx
movl $1, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq %r15, %rbx
jne .LBB4_6
.LBB4_7: # %._crit_edge
movq %r14, %rdi
callq fclose
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16computeLastDigitPii, .Lfunc_end4-_Z16computeLastDigitPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
callq _Z11fileToArrayPcPi
movq %rax, %rbx
movl 12(%rsp), %ebp
movq %rax, %rdi
movl %ebp, %esi
callq _Z16computeLastDigitPii
movq %rbx, %rdi
movl %ebp, %esi
callq _Z10computeMinPii
movl %eax, %ebp
movl $.L.str.8, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB5_2
# %bb.1:
movl $.L.str.4, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
.LBB5_2:
movl $.L.str.5, %esi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9lastDigitPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d, "
.size .L.str.1, 5
.type _Z9lastDigitPiS_i,@object # @_Z9lastDigitPiS_i
.section .rodata,"a",@progbits
.globl _Z9lastDigitPiS_i
.p2align 3, 0x0
_Z9lastDigitPiS_i:
.quad _Z24__device_stub__lastDigitPiS_i
.size _Z9lastDigitPiS_i, 8
.type _Z3minPii,@object # @_Z3minPii
.globl _Z3minPii
.p2align 3, 0x0
_Z3minPii:
.quad _Z18__device_stub__minPii
.size _Z3minPii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "q1b.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "failed to open file %s\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", %d"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "inp.txt"
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "q1a.txt"
.size .L.str.8, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9lastDigitPiS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3minPii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__lastDigitPiS_i
.addrsig_sym _Z18__device_stub__minPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9lastDigitPiS_i
.addrsig_sym _Z3minPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062b6b_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d, "
.text
.globl _Z11fileToArrayPcPi
.type _Z11fileToArrayPcPi, @function
_Z11fileToArrayPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L4
.L5:
addl $1, %ebx
.L4:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L5
movl %ebx, (%r12)
movslq %ebx, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq %rbp, %rdi
call rewind@PLT
cmpl $0, (%r12)
jle .L6
movl $0, %ebx
leaq .LC1(%rip), %r13
.L7:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %edx
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L7
.L6:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11fileToArrayPcPi, .-_Z11fileToArrayPcPi
.globl _Z31__device_stub__Z9lastDigitPiS_iPiS_i
.type _Z31__device_stub__Z9lastDigitPiS_iPiS_i, @function
_Z31__device_stub__Z9lastDigitPiS_iPiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9lastDigitPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z9lastDigitPiS_iPiS_i, .-_Z31__device_stub__Z9lastDigitPiS_iPiS_i
.globl _Z9lastDigitPiS_i
.type _Z9lastDigitPiS_i, @function
_Z9lastDigitPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9lastDigitPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9lastDigitPiS_i, .-_Z9lastDigitPiS_i
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "q1b.txt"
.LC4:
.string "failed to open file %s\n"
.LC5:
.string "%d"
.LC6:
.string ", %d"
.text
.globl _Z16computeLastDigitPii
.type _Z16computeLastDigitPii, @function
_Z16computeLastDigitPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L29
.L22:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $1, %ebp
jle .L23
movl %ebp, %ebp
salq $2, %rbp
movl $4, %ebx
leaq .LC6(%rip), %r13
.L24:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L23:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z9lastDigitPiS_iPiS_i
jmp .L21
.L29:
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16computeLastDigitPii, .-_Z16computeLastDigitPii
.globl _Z23__device_stub__Z3minPiiPii
.type _Z23__device_stub__Z3minPiiPii, @function
_Z23__device_stub__Z3minPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z23__device_stub__Z3minPiiPii, .-_Z23__device_stub__Z3minPiiPii
.globl _Z3minPii
.type _Z3minPii, @function
_Z3minPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3minPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z3minPii, .-_Z3minPii
.globl _Z10computeMinPii
.type _Z10computeMinPii, @function
_Z10computeMinPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaDeviceSynchronize@PLT
movq %rbx, %rax
leaq 128(%rbx), %rsi
movl $2147483647, %edx
.L41:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovg %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L41
movl %edx, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl %ebp, %esi
movq %rbx, %rdi
call _Z23__device_stub__Z3minPiiPii
jmp .L40
.cfi_endproc
.LFE2058:
.size _Z10computeMinPii, .-_Z10computeMinPii
.section .rodata.str1.1
.LC7:
.string "inp.txt"
.LC8:
.string "q1a.txt"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC7(%rip), %rdi
call _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movl %ebp, %esi
movq %rax, %rdi
call _Z16computeLastDigitPii
movl %ebp, %esi
movq %rbx, %rdi
call _Z10computeMinPii
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L49
.L46:
movl %r12d, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leaq .LC8(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3minPii"
.LC10:
.string "_Z9lastDigitPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9lastDigitPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q1.hip"
.globl _Z11fileToArrayPcPi # -- Begin function _Z11fileToArrayPcPi
.p2align 4, 0x90
.type _Z11fileToArrayPcPi,@function
_Z11fileToArrayPcPi: # @_Z11fileToArrayPcPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movq $-4, %r15
movl $-1, %ebp
leaq 4(%rsp), %r12
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
incl %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movl %ebp, (%rbx)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movq %r14, %rdi
callq rewind
cmpl $0, (%rbx)
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
leaq 4(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB0_4
.LBB0_5: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fileToArrayPcPi, .Lfunc_end0-_Z11fileToArrayPcPi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__lastDigitPiS_i # -- Begin function _Z24__device_stub__lastDigitPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__lastDigitPiS_i,@function
_Z24__device_stub__lastDigitPiS_i: # @_Z24__device_stub__lastDigitPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9lastDigitPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__lastDigitPiS_i, .Lfunc_end1-_Z24__device_stub__lastDigitPiS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__minPii # -- Begin function _Z18__device_stub__minPii
.p2align 4, 0x90
.type _Z18__device_stub__minPii,@function
_Z18__device_stub__minPii: # @_Z18__device_stub__minPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z18__device_stub__minPii, .Lfunc_end2-_Z18__device_stub__minPii
.cfi_endproc
# -- End function
.globl _Z10computeMinPii # -- Begin function _Z10computeMinPii
.p2align 4, 0x90
.type _Z10computeMinPii,@function
_Z10computeMinPii: # @_Z10computeMinPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %rbx, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %eax, %edx
cmovll %edx, %eax
incq %rcx
cmpq $32, %rcx
jne .LBB3_3
# %bb.4:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10computeMinPii, .Lfunc_end3-_Z10computeMinPii
.cfi_endproc
# -- End function
.globl _Z16computeLastDigitPii # -- Begin function _Z16computeLastDigitPii
.p2align 4, 0x90
.type _Z16computeLastDigitPii,@function
_Z16computeLastDigitPii: # @_Z16computeLastDigitPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9lastDigitPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB4_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
cmpl $2, %ebx
jl .LBB4_7
# %bb.5: # %.lr.ph.preheader
movl %ebx, %ebx
movl $1, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq %r15, %rbx
jne .LBB4_6
.LBB4_7: # %._crit_edge
movq %r14, %rdi
callq fclose
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16computeLastDigitPii, .Lfunc_end4-_Z16computeLastDigitPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
callq _Z11fileToArrayPcPi
movq %rax, %rbx
movl 12(%rsp), %ebp
movq %rax, %rdi
movl %ebp, %esi
callq _Z16computeLastDigitPii
movq %rbx, %rdi
movl %ebp, %esi
callq _Z10computeMinPii
movl %eax, %ebp
movl $.L.str.8, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB5_2
# %bb.1:
movl $.L.str.4, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
.LBB5_2:
movl $.L.str.5, %esi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9lastDigitPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d, "
.size .L.str.1, 5
.type _Z9lastDigitPiS_i,@object # @_Z9lastDigitPiS_i
.section .rodata,"a",@progbits
.globl _Z9lastDigitPiS_i
.p2align 3, 0x0
_Z9lastDigitPiS_i:
.quad _Z24__device_stub__lastDigitPiS_i
.size _Z9lastDigitPiS_i, 8
.type _Z3minPii,@object # @_Z3minPii
.globl _Z3minPii
.p2align 3, 0x0
_Z3minPii:
.quad _Z18__device_stub__minPii
.size _Z3minPii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "q1b.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "failed to open file %s\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", %d"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "inp.txt"
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "q1a.txt"
.size .L.str.8, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9lastDigitPiS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3minPii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__lastDigitPiS_i
.addrsig_sym _Z18__device_stub__minPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9lastDigitPiS_i
.addrsig_sym _Z3minPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <cuda.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} | code for sm_80
Function : _Z32transitive_closure_stage1_kernelPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R2, R0.reuse, 0x8, R9 ; /* 0x0000000800027824 */
/* 0x041fe400078e0209 */
/*0070*/ IMAD R3, R0, 0x8, R5 ; /* 0x0000000800037824 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R2, R2, 0x40, R3 ; /* 0x0000004002027824 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.SHL.U32 R6, R9, 0x20, RZ ; /* 0x0000002009067824 */
/* 0x000fe200078e00ff */
/*00c0*/ BSSY B0, 0x1c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.SHL.U32 R9, R5, 0x4, RZ ; /* 0x0000000405097824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.IADD R4, R6, 0x1, R9 ; /* 0x0000000106047824 */
/* 0x000fca00078e0209 */
/*00f0*/ STS [R4], R7 ; /* 0x0000000704007388 */
/* 0x004fe80000000800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS R8, [R4] ; /* 0x0000000004087984 */
/* 0x000e240000000800 */
/*0120*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fda0003f05270 */
/*0130*/ @P0 BRA 0x1b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0140*/ LDS R7, [R6] ; /* 0x0000000006077984 */
/* 0x000e240000000800 */
/*0150*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0160*/ @!P0 BRA 0x1b0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0170*/ LDS R7, [R5.X4] ; /* 0x0000000005077984 */
/* 0x000e240000004800 */
/*0180*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0190*/ @P0 LEA R7, R0, 0x2, 0x3 ; /* 0x0000000200070811 */
/* 0x000fca00078e18ff */
/*01a0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ BSSY B0, 0x290 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01e0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*01f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0200*/ @P0 BRA 0x280 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0210*/ LDS R7, [R6+0x4] ; /* 0x0000040006077984 */
/* 0x000e240000000800 */
/*0220*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0230*/ @!P0 BRA 0x280 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R7, [R5.X4+0x20] ; /* 0x0000200005077984 */
/* 0x000e240000004800 */
/*0250*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0260*/ @P0 LEA R7, R0, 0x3, 0x3 ; /* 0x0000000300070811 */
/* 0x000fca00078e18ff */
/*0270*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ BSSY B0, 0x360 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02b0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*02c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*02d0*/ @P0 BRA 0x350 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LDS R7, [R6+0x8] ; /* 0x0000080006077984 */
/* 0x000e240000000800 */
/*02f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0300*/ @!P0 BRA 0x350 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDS R7, [R5.X4+0x40] ; /* 0x0000400005077984 */
/* 0x000e240000004800 */
/*0320*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0330*/ @P0 LEA R7, R0, 0x4, 0x3 ; /* 0x0000000400070811 */
/* 0x000fca00078e18ff */
/*0340*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ BSSY B0, 0x430 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0380*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0390*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03a0*/ @P0 BRA 0x420 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*03b0*/ LDS R7, [R6+0xc] ; /* 0x00000c0006077984 */
/* 0x000e240000000800 */
/*03c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03d0*/ @!P0 BRA 0x420 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS R7, [R5.X4+0x60] ; /* 0x0000600005077984 */
/* 0x000e240000004800 */
/*03f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0400*/ @P0 LEA R7, R0, 0x5, 0x3 ; /* 0x0000000500070811 */
/* 0x000fca00078e18ff */
/*0410*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ BSSY B0, 0x500 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0450*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0460*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0470*/ @P0 BRA 0x4f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDS R7, [R6+0x10] ; /* 0x0000100006077984 */
/* 0x000e240000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*04a0*/ @!P0 BRA 0x4f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04b0*/ LDS R7, [R5.X4+0x80] ; /* 0x0000800005077984 */
/* 0x000e240000004800 */
/*04c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*04d0*/ @P0 LEA R7, R0, 0x6, 0x3 ; /* 0x0000000600070811 */
/* 0x000fca00078e18ff */
/*04e0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ BSSY B0, 0x5d0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0520*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0530*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0540*/ @P0 BRA 0x5c0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0550*/ LDS R7, [R6+0x14] ; /* 0x0000140006077984 */
/* 0x000e240000000800 */
/*0560*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0570*/ @!P0 BRA 0x5c0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDS R7, [R5.X4+0xa0] ; /* 0x0000a00005077984 */
/* 0x000e240000004800 */
/*0590*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*05a0*/ @P0 LEA R7, R0, 0x7, 0x3 ; /* 0x0000000700070811 */
/* 0x000fca00078e18ff */
/*05b0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05e0*/ BSSY B0, 0x6a0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*05f0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0600*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0610*/ @P0 BRA 0x690 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0620*/ LDS R7, [R6+0x18] ; /* 0x0000180006077984 */
/* 0x000e240000000800 */
/*0630*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0640*/ @!P0 BRA 0x690 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R7, [R5.X4+0xc0] ; /* 0x0000c00005077984 */
/* 0x000e240000004800 */
/*0660*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0670*/ @P0 LEA R7, R0, 0x8, 0x3 ; /* 0x0000000800070811 */
/* 0x000fca00078e18ff */
/*0680*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ BSSY B0, 0x770 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*06c0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*06d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*06e0*/ @P0 BRA 0x760 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*06f0*/ LDS R6, [R6+0x1c] ; /* 0x00001c0006067984 */
/* 0x000e240000000800 */
/*0700*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x001fda0003f05270 */
/*0710*/ @!P0 BRA 0x760 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0720*/ LDS R5, [R5.X4+0xe0] ; /* 0x0000e00005057984 */
/* 0x000e240000004800 */
/*0730*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*0740*/ @P0 LEA R7, R0, 0x9, 0x3 ; /* 0x0000000900070811 */
/* 0x000fca00078e18ff */
/*0750*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0760*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0780*/ LDS R5, [R4] ; /* 0x0000000004057984 */
/* 0x000e680000000800 */
/*0790*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <cuda.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} | .file "tmpxft_0013359a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
.type _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji, @function
_Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32transitive_closure_stage1_kernelPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji, .-_Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
.globl _Z32transitive_closure_stage1_kernelPji
.type _Z32transitive_closure_stage1_kernelPji, @function
_Z32transitive_closure_stage1_kernelPji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32transitive_closure_stage1_kernelPji, .-_Z32transitive_closure_stage1_kernelPji
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32transitive_closure_stage1_kernelPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32transitive_closure_stage1_kernelPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <cuda.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32transitive_closure_stage1_kernelPji
.globl _Z32transitive_closure_stage1_kernelPji
.p2align 8
.type _Z32transitive_closure_stage1_kernelPji,@function
_Z32transitive_closure_stage1_kernelPji:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v4, 5, v3
s_waitcnt lgkmcnt(0)
s_lshl_b32 s2, s2, 3
v_add_lshl_u32 v0, s2, v3, 6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v0, s2, v2, v0
v_lshlrev_b32_e32 v2, 2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
s_or_b32 s1, s2, 2
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s0, s0, 4
s_add_i32 s1, s1, 1
s_cmp_eq_u32 s0, 32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_2:
ds_load_b32 v5, v3
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v5, s0, v4
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
v_mov_b32_e32 v5, s1
ds_store_b32 v3, v5
s_branch .LBB0_1
.LBB0_6:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32transitive_closure_stage1_kernelPji
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32transitive_closure_stage1_kernelPji, .Lfunc_end0-_Z32transitive_closure_stage1_kernelPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32transitive_closure_stage1_kernelPji
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z32transitive_closure_stage1_kernelPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=[8,8] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define _2D_ACCESS(A, y, x, X_DIM) A[(y)*(X_DIM)+(x)]
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: TransitiveClosure.cpp
//
// Contains the implementation of algorithms which explores connectivity between
// nodes in a graph and determine shortest path.
// This is based on paper http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
//----------------------------------------------------------------------------
// Defines to help with AMP->OpenCL translation
#define X_DIMENSION 0
#define Y_DIMENSION 1
// Constants - specifies tile size
#define TILE_SIZE (1 << 3)
#define num_vertices (1 << 6)
// State of connection
#define UNCONNECTED 0
#define DIRECTLY_CONNECTED 1
#define INDIRECTLY_CONNECTED 2
//----------------------------------------------------------------------------
// Stage1 - determine connectivity between vertexs' within a TILE - primary
//----------------------------------------------------------------------------
__global__ void transitive_closure_stage1_kernel(unsigned int* graph, int passnum)
{
// Load primary block into shared memory (primary_block_buffer)
__shared__ unsigned int primary_block_buffer[TILE_SIZE][TILE_SIZE];
// TODO: check that in OpenCL the order is 0=x, 1=y, 2=z (in AMP it is reversed)
int idxY = passnum * TILE_SIZE + threadIdx.y;
int idxX = passnum * TILE_SIZE + threadIdx.x;
primary_block_buffer[threadIdx.y][threadIdx.x] = _2D_ACCESS(graph, idxY, idxX, num_vertices);
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Now perform the actual Floyd-Warshall algorithm on this block
for (unsigned int k = 0;
k < TILE_SIZE; ++k)
{
if ( primary_block_buffer[threadIdx.y][threadIdx.x] == UNCONNECTED)
{
if ( (primary_block_buffer[threadIdx.y][k] != UNCONNECTED) && (primary_block_buffer[k][threadIdx.x] != UNCONNECTED) )
{
primary_block_buffer[threadIdx.y][threadIdx.x] = passnum*TILE_SIZE + k + INDIRECTLY_CONNECTED;
}
}
__syncthreads();
}
_2D_ACCESS(graph, idxY, idxX, num_vertices) = primary_block_buffer[threadIdx.y][threadIdx.x];
} | .text
.file "kernel.hip"
.globl _Z47__device_stub__transitive_closure_stage1_kernelPji # -- Begin function _Z47__device_stub__transitive_closure_stage1_kernelPji
.p2align 4, 0x90
.type _Z47__device_stub__transitive_closure_stage1_kernelPji,@function
_Z47__device_stub__transitive_closure_stage1_kernelPji: # @_Z47__device_stub__transitive_closure_stage1_kernelPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z32transitive_closure_stage1_kernelPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z47__device_stub__transitive_closure_stage1_kernelPji, .Lfunc_end0-_Z47__device_stub__transitive_closure_stage1_kernelPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32transitive_closure_stage1_kernelPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32transitive_closure_stage1_kernelPji,@object # @_Z32transitive_closure_stage1_kernelPji
.section .rodata,"a",@progbits
.globl _Z32transitive_closure_stage1_kernelPji
.p2align 3, 0x0
_Z32transitive_closure_stage1_kernelPji:
.quad _Z47__device_stub__transitive_closure_stage1_kernelPji
.size _Z32transitive_closure_stage1_kernelPji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32transitive_closure_stage1_kernelPji"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__transitive_closure_stage1_kernelPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32transitive_closure_stage1_kernelPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32transitive_closure_stage1_kernelPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R2, R0.reuse, 0x8, R9 ; /* 0x0000000800027824 */
/* 0x041fe400078e0209 */
/*0070*/ IMAD R3, R0, 0x8, R5 ; /* 0x0000000800037824 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R2, R2, 0x40, R3 ; /* 0x0000004002027824 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.SHL.U32 R6, R9, 0x20, RZ ; /* 0x0000002009067824 */
/* 0x000fe200078e00ff */
/*00c0*/ BSSY B0, 0x1c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.SHL.U32 R9, R5, 0x4, RZ ; /* 0x0000000405097824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.IADD R4, R6, 0x1, R9 ; /* 0x0000000106047824 */
/* 0x000fca00078e0209 */
/*00f0*/ STS [R4], R7 ; /* 0x0000000704007388 */
/* 0x004fe80000000800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS R8, [R4] ; /* 0x0000000004087984 */
/* 0x000e240000000800 */
/*0120*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fda0003f05270 */
/*0130*/ @P0 BRA 0x1b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0140*/ LDS R7, [R6] ; /* 0x0000000006077984 */
/* 0x000e240000000800 */
/*0150*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0160*/ @!P0 BRA 0x1b0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0170*/ LDS R7, [R5.X4] ; /* 0x0000000005077984 */
/* 0x000e240000004800 */
/*0180*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0190*/ @P0 LEA R7, R0, 0x2, 0x3 ; /* 0x0000000200070811 */
/* 0x000fca00078e18ff */
/*01a0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ BSSY B0, 0x290 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01e0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*01f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0200*/ @P0 BRA 0x280 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0210*/ LDS R7, [R6+0x4] ; /* 0x0000040006077984 */
/* 0x000e240000000800 */
/*0220*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0230*/ @!P0 BRA 0x280 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R7, [R5.X4+0x20] ; /* 0x0000200005077984 */
/* 0x000e240000004800 */
/*0250*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0260*/ @P0 LEA R7, R0, 0x3, 0x3 ; /* 0x0000000300070811 */
/* 0x000fca00078e18ff */
/*0270*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ BSSY B0, 0x360 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02b0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*02c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*02d0*/ @P0 BRA 0x350 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LDS R7, [R6+0x8] ; /* 0x0000080006077984 */
/* 0x000e240000000800 */
/*02f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0300*/ @!P0 BRA 0x350 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDS R7, [R5.X4+0x40] ; /* 0x0000400005077984 */
/* 0x000e240000004800 */
/*0320*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0330*/ @P0 LEA R7, R0, 0x4, 0x3 ; /* 0x0000000400070811 */
/* 0x000fca00078e18ff */
/*0340*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ BSSY B0, 0x430 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0380*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0390*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03a0*/ @P0 BRA 0x420 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*03b0*/ LDS R7, [R6+0xc] ; /* 0x00000c0006077984 */
/* 0x000e240000000800 */
/*03c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03d0*/ @!P0 BRA 0x420 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS R7, [R5.X4+0x60] ; /* 0x0000600005077984 */
/* 0x000e240000004800 */
/*03f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0400*/ @P0 LEA R7, R0, 0x5, 0x3 ; /* 0x0000000500070811 */
/* 0x000fca00078e18ff */
/*0410*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ BSSY B0, 0x500 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0450*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0460*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0470*/ @P0 BRA 0x4f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDS R7, [R6+0x10] ; /* 0x0000100006077984 */
/* 0x000e240000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*04a0*/ @!P0 BRA 0x4f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04b0*/ LDS R7, [R5.X4+0x80] ; /* 0x0000800005077984 */
/* 0x000e240000004800 */
/*04c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*04d0*/ @P0 LEA R7, R0, 0x6, 0x3 ; /* 0x0000000600070811 */
/* 0x000fca00078e18ff */
/*04e0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ BSSY B0, 0x5d0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0520*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0530*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0540*/ @P0 BRA 0x5c0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0550*/ LDS R7, [R6+0x14] ; /* 0x0000140006077984 */
/* 0x000e240000000800 */
/*0560*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0570*/ @!P0 BRA 0x5c0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDS R7, [R5.X4+0xa0] ; /* 0x0000a00005077984 */
/* 0x000e240000004800 */
/*0590*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*05a0*/ @P0 LEA R7, R0, 0x7, 0x3 ; /* 0x0000000700070811 */
/* 0x000fca00078e18ff */
/*05b0*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05e0*/ BSSY B0, 0x6a0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*05f0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*0600*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0610*/ @P0 BRA 0x690 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0620*/ LDS R7, [R6+0x18] ; /* 0x0000180006077984 */
/* 0x000e240000000800 */
/*0630*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0640*/ @!P0 BRA 0x690 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R7, [R5.X4+0xc0] ; /* 0x0000c00005077984 */
/* 0x000e240000004800 */
/*0660*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0670*/ @P0 LEA R7, R0, 0x8, 0x3 ; /* 0x0000000800070811 */
/* 0x000fca00078e18ff */
/*0680*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ BSSY B0, 0x770 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*06c0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x001e240000000800 */
/*06d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*06e0*/ @P0 BRA 0x760 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*06f0*/ LDS R6, [R6+0x1c] ; /* 0x00001c0006067984 */
/* 0x000e240000000800 */
/*0700*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x001fda0003f05270 */
/*0710*/ @!P0 BRA 0x760 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0720*/ LDS R5, [R5.X4+0xe0] ; /* 0x0000e00005057984 */
/* 0x000e240000004800 */
/*0730*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*0740*/ @P0 LEA R7, R0, 0x9, 0x3 ; /* 0x0000000900070811 */
/* 0x000fca00078e18ff */
/*0750*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*0760*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0780*/ LDS R5, [R4] ; /* 0x0000000004057984 */
/* 0x000e680000000800 */
/*0790*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32transitive_closure_stage1_kernelPji
.globl _Z32transitive_closure_stage1_kernelPji
.p2align 8
.type _Z32transitive_closure_stage1_kernelPji,@function
_Z32transitive_closure_stage1_kernelPji:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v4, 5, v3
s_waitcnt lgkmcnt(0)
s_lshl_b32 s2, s2, 3
v_add_lshl_u32 v0, s2, v3, 6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v0, s2, v2, v0
v_lshlrev_b32_e32 v2, 2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
s_or_b32 s1, s2, 2
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s0, s0, 4
s_add_i32 s1, s1, 1
s_cmp_eq_u32 s0, 32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_2:
ds_load_b32 v5, v3
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v5, s0, v4
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
v_mov_b32_e32 v5, s1
ds_store_b32 v3, v5
s_branch .LBB0_1
.LBB0_6:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32transitive_closure_stage1_kernelPji
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32transitive_closure_stage1_kernelPji, .Lfunc_end0-_Z32transitive_closure_stage1_kernelPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32transitive_closure_stage1_kernelPji
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z32transitive_closure_stage1_kernelPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013359a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
.type _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji, @function
_Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32transitive_closure_stage1_kernelPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji, .-_Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
.globl _Z32transitive_closure_stage1_kernelPji
.type _Z32transitive_closure_stage1_kernelPji, @function
_Z32transitive_closure_stage1_kernelPji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z32transitive_closure_stage1_kernelPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32transitive_closure_stage1_kernelPji, .-_Z32transitive_closure_stage1_kernelPji
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32transitive_closure_stage1_kernelPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32transitive_closure_stage1_kernelPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z47__device_stub__transitive_closure_stage1_kernelPji # -- Begin function _Z47__device_stub__transitive_closure_stage1_kernelPji
.p2align 4, 0x90
.type _Z47__device_stub__transitive_closure_stage1_kernelPji,@function
_Z47__device_stub__transitive_closure_stage1_kernelPji: # @_Z47__device_stub__transitive_closure_stage1_kernelPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z32transitive_closure_stage1_kernelPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z47__device_stub__transitive_closure_stage1_kernelPji, .Lfunc_end0-_Z47__device_stub__transitive_closure_stage1_kernelPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32transitive_closure_stage1_kernelPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32transitive_closure_stage1_kernelPji,@object # @_Z32transitive_closure_stage1_kernelPji
.section .rodata,"a",@progbits
.globl _Z32transitive_closure_stage1_kernelPji
.p2align 3, 0x0
_Z32transitive_closure_stage1_kernelPji:
.quad _Z47__device_stub__transitive_closure_stage1_kernelPji
.size _Z32transitive_closure_stage1_kernelPji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32transitive_closure_stage1_kernelPji"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__transitive_closure_stage1_kernelPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32transitive_closure_stage1_kernelPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Author: Polizois Siois 8535
*/
/*
Faculty of Electrical and Computer Engineering AUTH
3rd assignment at Parallel and Distributed Systems (7th semester)
*/
/*
Parallel implementation of mean shift algorithm for running on nvidia GPUs using cuda.
Give N number of points in a D-dimendional space, the program repeatedly makes NxN
parallel calculations.In every step it finds vectors(mean shifts) that move the points to
new positions which tend to be closer to the maxima of a predefined kernel function,
the Gaussian.The repetitions stop when each point has moved close enough(depends on
EPSILON) to the maxima.
*/
/*
This iteration of mean shift uses the GPU's SHARED MEMORY to perfom reduction and
speed up the process of calculating a sum of N doubles.
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda.h>
//set VAR=1 for the demo dataset (600x2)
//set VAR=0.1 for the dataset from the knn search exercise (60000x30) or the products of it
#define VAR 1 // σ^2
#define EPSILON 0.0001 // ε
#define THREADSPERBLOCK 128 // the number of threads in every block
//Used in main
double** alloc2d(int rows, int cols);
void loadFile(char name[65], double **x, int rows, int cols);
void showResults(double **x, int start, int end, int rows, int cols);
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters);
double timeCalc(struct timeval start, struct timeval end);
void free2d(double **matrix);
int blockNum(int N, int thPerBlock);
int errors(double **y, int rows, int cols);
//Used inside kernels
__device__ double d_k_func(double x);
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid);
//Kernels
__global__ void tableCopy(double *from, double *to, int rows, int cols);
__global__ void colsToRow(double *from, double *to, int rows, int cols);
__global__ void rowToCols(double *from, double *to, int rows, int cols);
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY);
struct timeval startwtime, endwtime; // Timer start and end value
int main(int argc, char *argv[])
{
if(argc!=5) { printf("Wrong number of args\n"); return -1; }
int ROWS = atoi(argv[1]);
int COLS = atoi(argv[2]);
char *FILENAME = argv[3];
int EXPORT = atoi(argv[4]);
int size2d = ROWS*COLS*sizeof(double);
int bNum = blockNum(ROWS, THREADSPERBLOCK); // the number of blocks needed to store <<ROWS>>
int tempRows = ROWS * bNum; // The number of blocks needed for ROWS*ROWS parallel calculations
int i, j, k, con = 1, iters=0;
double denom, dist=0;
double nb1 = sqrt(tempRows);
int nb = (int)nb1;
if(nb1 > (double)(int)nb1) nb = (int)(nb1+1);
//printf("Blocks per grid dimenson : %d\n", nb);
double **x, // The points at their original positions
**y; // The points after they have moved towards the maxima
double **temp; // stores the result of the reduction of every block
double *num = (double*) malloc(COLS * sizeof(double));
// Memory allocation in Host memory
x = alloc2d(ROWS, COLS);
y = alloc2d(ROWS, COLS);
temp = alloc2d((COLS+1), tempRows);
// Loading data from file to table
loadFile(FILENAME, x, ROWS, COLS);
// Memory allocation in Device memory
double *dx;
cudaMalloc(&dx, size2d);
double *dy;
cudaMalloc(&dy, size2d);
double *dtemp;
cudaMalloc(&dtemp, tempRows*(COLS+1)*sizeof(double));
int *dcon;
cudaMalloc(&dcon, 1*sizeof(int));
// Copy points from host memory to device memory
cudaMemcpy(dx, x[0], size2d, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1); // Defining number of threads in a block (1d)
dim3 numBlocks(blockNum(ROWS, threadsPerBlock.x), blockNum(ROWS, threadsPerBlock.x), 1); // Defining number of blocks in a grid (2d)
//rearrange table data so that we have coalesced memory access
colsToRow<<<numBlocks, threadsPerBlock>>>(dx, dy, ROWS, COLS); // Stores the transpose of dx to dy
cudaThreadSynchronize(); // wait all threads to finish
tableCopy<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS); // Copies dy to dx
cudaThreadSynchronize(); // wait all threads to finish
// Timer start
gettimeofday( &startwtime, NULL ); // Starts timing the process (memory copies between device and host will be included)
// Repeat until all mean shifts converge
do
{
iters++;
//printf("Iteration: %d\n", iters);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1);
dim3 numBlocks(nb , nb, 1);
//Reducing the sum parts for each new y from <<ROWS>> to <<bNum>> and storing them to dtemp
yNext<<<numBlocks, threadsPerBlock, THREADSPERBLOCK*sizeof(double)>>>(dx, dy, dtemp, ROWS, COLS, blockNum(ROWS, THREADSPERBLOCK));
cudaThreadSynchronize();
con=1;
cudaMemcpy(temp[0], dtemp, tempRows*(COLS+1)*sizeof(double), cudaMemcpyDeviceToHost);
//Calculating every new y (using dtemp) and checking if the corresponding mean shift converges
//printf("checking convergence\n");
for(i=0;i<ROWS;i++)
{
dist=0;
denom = 0; for(k=0;k<COLS;k++) num[k] = 0;
for(j=0;j<bNum;j++)
{
for(k=0;k<COLS;k++) num[k] += temp[0][k*tempRows+i*bNum+j];
denom += temp[0][COLS*tempRows+i*bNum+j];
}
for(k=0;k<COLS;k++) num[k] = num[k]/denom;
for(k=0;k<COLS;k++) dist+=pow(y[0][k*ROWS+i]-num[k],2);
dist = sqrt(dist);
if (dist >= EPSILON) con=0;
for(k=0;k<COLS;k++) y[0][k*ROWS+i] = num[k];
}
cudaMemcpy(dy, y[0], size2d, cudaMemcpyHostToDevice);
//printf("done checking\n");
}while(!con && iters <15);
// Timer stop
gettimeofday( &endwtime, NULL );
// Test prints
printf("Final positions\n");
cudaMemcpy(y[0], dy, size2d, cudaMemcpyDeviceToHost);
printf("first 5\n");
showResults(y, 0, 5, ROWS, COLS);
printf("last 5\n");
showResults(y, ROWS-5, ROWS, ROWS, COLS);
// Completion time show
double duration = timeCalc(startwtime, endwtime);
printf("Completed in %.3f sec !\n", duration);
printf("Iteration num: %d\n", iters);
// Exporting results
if(EXPORT)
{
numBlocks.x = bNum; numBlocks.y = bNum; numBlocks.z = 1;
rowToCols<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS);
cudaMemcpy(x[0], dx, size2d, cudaMemcpyDeviceToHost);
exportResults(x, ROWS, COLS, THREADSPERBLOCK, duration, iters);
}
// Checking for errors
int errs = errors(y, ROWS, COLS);
if(errs != -1) printf("Errors = %d\n", errs);
// Freeing the allocated memory
free2d(x); free2d(y); free2d(temp);
cudaFree(dx); cudaFree(dy); cudaFree(dtemp);
}
// Calculates (and reduces to bNum) all parts of the sum of the new position of every point based on its former
// position and the inititial position of all the points.
// Reduction results stored in "out"
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY)
{
extern __shared__ double shared[]; //will be used for reuduction
double *denom = (double*)shared;
double *numer = (double*)shared;
int bid = blockIdx.y*gridDim.x + blockIdx.x;
int blockOfY = bid % blocksForY;
int id = blockOfY*blockDim.x +threadIdx.x; // 0-ROWS
int yRow = bid / blocksForY; // 0-ROWS
double dist=0;
int i, tempRows = rows*blocksForY;
double inRows=0, inVar=0, gaus;
int tid1d = threadIdx.x;
if(id < rows && bid < tempRows) inRows=1;
//Distance calculation and check
for(i=0;i<cols;i++) dist+=pow(y[i*rows+yRow]-x[i*rows+id],2);
dist = sqrt(dist);
if(dist <= VAR) inVar=1;
gaus = d_k_func(pow(dist, 2));
// Every thread in a block(if in limits) fills the accornding place of denom[]
if(bid < tempRows)
denom[tid1d] = inRows * inVar * gaus;
// When all threads are done filling, denom gets reduced to one sum and stored to the according place of out[][]
__syncthreads();
if(bid < tempRows)
d_reduce(denom, &out[cols*tempRows+bid], blockDim.x, tid1d);
// The exact same thing done here for every dimention(colum)
for(i=0;i<cols;i++)
{
__syncthreads();
if(bid < tempRows)
numer[tid1d] = inRows * inVar * gaus * x[i*rows+id]; // rows x 1
__syncthreads();
if(bid < tempRows)
d_reduce(numer, &out[i*tempRows+bid], blockDim.x, tid1d);
}
}
//Gaussian kernel
__device__ double d_k_func(double x)
{
return exp(-x/(2*VAR));
}
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid)
{
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) *out = sdata[0];
}
__global__ void tableCopy(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int current = i*cols + j;
if (i < rows && j < cols)
to[current] = from[current];
}
__global__ void colsToRow(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int before = i*cols + j;
int after = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
__global__ void rowToCols(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; // row
int j = blockIdx.y * blockDim.y + threadIdx.y; // col
int after = i*cols + j;
int before = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
int blockNum(int N, int thPerBlock)
{
int num = N / thPerBlock,
mod = N % thPerBlock;
if(N <= thPerBlock) num = 1;
else if(mod) num += 1;
return num;
}
// Allocates continuous memory for a 2d array of doubles
double** alloc2d(int rows, int cols)
{
int i;
double **matrix= (double**)malloc(rows * sizeof(*matrix));
if(!matrix)
{
printf("Out of memory\n");
exit(-1);
}
matrix[0] = (double*)malloc(rows * (cols) * sizeof(**matrix));
if(!matrix[0])
{
printf("Out of memory\n");
exit(-1);
}
for(i = 1; i < rows; i++)
matrix[i] = matrix[0] + i * (cols);
return matrix;
}
void free2d(double **matrix)
{
free(matrix[0]);
free(matrix);
}
void loadFile(char name[65], double **x, int rows, int cols)
{
FILE *pointFile;
int i;
pointFile=fopen(name,"rb");
if (!pointFile){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fread(&(x[i][0]),sizeof(double),cols,pointFile))
{ printf("Unable to read from file!"); exit(1); }
fclose(pointFile);
}
void showResults(double **x, int start, int end, int rows, int cols)
{
int i,j;
for(i=start;i<end;i++)
{
printf("%d:",i);
for(j=0;j<cols;j++) printf(" %f ", x[0][j*rows+i]);
printf("\n");
}
}
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters)
{
FILE *out;
int i;
char name[65];
//Generating the file name
sprintf(name, "./results/y_(%d_%d)_(%d_%.3f_%d).bin", rows, cols, threads, dur, iters);
out=fopen(name,"wb");
if (!out){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fwrite(&(x[i][0]),sizeof(double),cols,out))
{ printf("Unable to read from file!"); exit(1); }
printf("Exported !\n");
fclose(out);
}
double timeCalc(struct timeval start, struct timeval end)
{
return (double)( ( end.tv_usec - start.tv_usec ) / 1.0e6 + end.tv_sec - start.tv_sec );
}
// Opens a binary file that has the results of a serial execution of mean shift for the same data
// Checks the points stored in y for errors, counts the errors and returns them
// The binary files used for comparisson should be stored in a folder called "compare" in the same
// directory with proggram
// For example if we want to test our result for the data set of 600 2-dimentional points we
// refer to the ./compare/600_2.bin file
int errors(double **y, int rows, int cols)
{
FILE *data;
double *tempLine;
char fileName[650];
int i,j, er=0;
//Generating the file name
sprintf(fileName, "./compare/%d_%d.bin", rows, cols);
// Allocating space for the reading line
tempLine = (double *) malloc(cols * sizeof(double));
//Opening the label results binary file for reading
data=fopen(fileName,"rb");
if (!data){ printf("Unable to open file in order to compare results!\n"); return -1; }
// Finding the correct place to start loadng
//fseek(data, 0, SEEK_SET);
// reading every line and checking if theres a difference between my results and those from matlab
for (i=0; i < rows; i++)
{
//Loading a label
if(!fread(tempLine, sizeof(double), cols, data))
{ printf("Unable to read from file!\n"); return -1; }
for(j=0;j<cols;j++)
// comparing with 10 decimal percision
if((int)(10000000000*tempLine[j]) != (int)(10000000000*y[0][j*rows+i])) { er++; break; }
}
//Closing the binary files
fclose(data);
return er;
} | .file "tmpxft_0016ec24_00000000-6_mShift_cuda_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8d_k_funcd
.type _Z8d_k_funcd, @function
_Z8d_k_funcd:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8d_k_funcd, .-_Z8d_k_funcd
.globl _Z8d_reducePdS_ii
.type _Z8d_reducePdS_ii, @function
_Z8d_reducePdS_ii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8d_reducePdS_ii, .-_Z8d_reducePdS_ii
.globl _Z8blockNumii
.type _Z8blockNumii, @function
_Z8blockNumii:
.LFB2060:
.cfi_startproc
endbr64
movl %edi, %eax
movl $1, %edx
cmpl %esi, %edi
jle .L7
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %edx
.L7:
movl %edx, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z8blockNumii, .-_Z8blockNumii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Out of memory\n"
.text
.globl _Z7alloc2dii
.type _Z7alloc2dii, @function
_Z7alloc2dii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movl %esi, %ebx
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
testq %rax, %rax
je .L18
movq %rax, %rbp
movl %r12d, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 0(%rbp)
testq %rax, %rax
je .L12
cmpl $1, %r12d
jle .L10
movslq %ebx, %rsi
salq $3, %rsi
leaq 8(%rbp), %rax
leal -2(%r12), %edx
leaq 16(%rbp,%rdx,8), %rdi
movq %rsi, %rdx
.L15:
movq %rdx, %rcx
addq 0(%rbp), %rcx
movq %rcx, (%rax)
addq %rsi, %rdx
addq $8, %rax
cmpq %rdi, %rax
jne .L15
.L10:
movq %rbp, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z7alloc2dii, .-_Z7alloc2dii
.globl _Z6free2dPPd
.type _Z6free2dPPd, @function
_Z6free2dPPd:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z6free2dPPd, .-_Z6free2dPPd
.section .rodata.str1.1
.LC1:
.string "rb"
.LC2:
.string "Unable to open file!\n"
.LC3:
.string "Unable to read from file!"
.text
.globl _Z8loadFilePcPPdii
.type _Z8loadFilePcPPdii, @function
_Z8loadFilePcPPdii:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r14
movl %edx, %r13d
movl %ecx, %r12d
leaq .LC1(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L22
movq %rax, %rbp
testl %r13d, %r13d
jle .L24
movq %r14, %rbx
movslq %r13d, %r13
leaq (%r14,%r13,8), %r13
movslq %r12d, %r12
.L26:
movq (%rbx), %rdi
movq %rbp, %r8
movq %r12, %rcx
movl $8, %edx
movq $-1, %rsi
call __fread_chk@PLT
testq %rax, %rax
je .L29
addq $8, %rbx
cmpq %r13, %rbx
jne .L26
.L24:
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z8loadFilePcPPdii, .-_Z8loadFilePcPPdii
.section .rodata.str1.1
.LC4:
.string "%d:"
.LC5:
.string " %f "
.LC6:
.string "\n"
.text
.globl _Z11showResultsPPdiiii
.type _Z11showResultsPPdiiii, @function
_Z11showResultsPPdiiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
cmpl %edx, %esi
jge .L30
movq %rdi, %r14
movl %r8d, %r12d
movslq %esi, %rax
salq $3, %rax
movq %rax, (%rsp)
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r13
leaq .LC5(%rip), %r15
.L34:
movl 8(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L32
movq (%rsp), %rbp
movl $0, %ebx
.L33:
movq (%r14), %rax
movsd (%rax,%rbp), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
addq %r13, %rbp
cmpl %ebx, %r12d
jne .L33
.L32:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addq $8, (%rsp)
cmpl %eax, 12(%rsp)
jne .L34
.L30:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11showResultsPPdiiii, .-_Z11showResultsPPdiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "./results/y_(%d_%d)_(%d_%.3f_%d).bin"
.section .rodata.str1.1
.LC8:
.string "wb"
.LC9:
.string "Exported !\n"
.text
.globl _Z13exportResultsPPdiiidi
.type _Z13exportResultsPPdiiidi, @function
_Z13exportResultsPPdiiidi:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %r13d
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
pushq %r8
.cfi_def_cfa_offset 136
pushq %rcx
.cfi_def_cfa_offset 144
movl %edx, %r9d
movl %esi, %r8d
leaq .LC7(%rip), %rcx
movl $65, %edx
movl $2, %esi
movq %rbx, %rdi
movl $1, %eax
call __sprintf_chk@PLT
movq %rbx, %rsp
.cfi_def_cfa_offset 128
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
testq %rax, %rax
je .L39
movq %rax, %r12
testl %r13d, %r13d
jle .L41
movq %r14, %rbx
movslq %r13d, %r13
leaq (%r14,%r13,8), %r13
movslq %ebp, %rbp
.L43:
movq (%rbx), %rdi
movq %r12, %rcx
movq %rbp, %rdx
movl $8, %esi
call fwrite@PLT
testq %rax, %rax
je .L47
addq $8, %rbx
cmpq %r13, %rbx
jne .L43
.L41:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z13exportResultsPPdiiidi, .-_Z13exportResultsPPdiiidi
.globl _Z8timeCalc7timevalS_
.type _Z8timeCalc7timevalS_, @function
_Z8timeCalc7timevalS_:
.LFB2066:
.cfi_startproc
endbr64
subq %rsi, %rcx
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
divsd .LC10(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rdi, %xmm1
subsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2066:
.size _Z8timeCalc7timevalS_, .-_Z8timeCalc7timevalS_
.section .rodata.str1.1
.LC11:
.string "./compare/%d_%d.bin"
.section .rodata.str1.8
.align 8
.LC12:
.string "Unable to open file in order to compare results!\n"
.section .rodata.str1.1
.LC13:
.string "Unable to read from file!\n"
.text
.globl _Z6errorsPPdii
.type _Z6errorsPPdii, @function
_Z6errorsPPdii:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $712, %rsp
.cfi_def_cfa_offset 768
movq %rdi, %r15
movl %esi, %ebx
movl %edx, %r14d
movl %edx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 696(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
movl %edx, %r9d
movl %esi, %r8d
leaq .LC11(%rip), %rcx
movl $650, %edx
movl $2, %esi
movq %rbp, %rdi
call __sprintf_chk@PLT
movslq %r14d, %rax
movq %rax, 8(%rsp)
leaq 0(,%rax,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq .LC1(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
testq %rax, %rax
je .L51
movq %rax, %rdi
testl %ebx, %ebx
jle .L65
movslq %ebx, %r9
leaq 0(,%r9,8), %rbp
leaq (%r14,%r13), %rbx
movl $0, %r12d
movl $0, 28(%rsp)
movq %r14, 16(%rsp)
movq %rax, (%rsp)
movq %r9, %r14
jmp .L60
.L65:
movl $0, 28(%rsp)
jmp .L53
.L51:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, 28(%rsp)
jmp .L50
.L55:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, 28(%rsp)
jmp .L50
.L67:
addl $1, 28(%rsp)
.L57:
addq $1, %r12
cmpq %r14, %r12
je .L66
.L60:
movq (%rsp), %r8
movq 8(%rsp), %rcx
movl $8, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call __fread_chk@PLT
testq %rax, %rax
je .L55
cmpl $0, 24(%rsp)
jle .L57
movq (%r15), %rax
leaq (%rax,%r12,8), %rdx
movq %r13, %rax
.L59:
movsd (%rax), %xmm0
mulsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %esi
movsd (%rdx), %xmm0
mulsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %ecx
cmpl %ecx, %esi
jne .L67
addq $8, %rax
addq %rbp, %rdx
cmpq %rbx, %rax
jne .L59
jmp .L57
.L66:
movq (%rsp), %rdi
.L53:
call fclose@PLT
.L50:
movq 696(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl 28(%rsp), %eax
addq $712, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z6errorsPPdii, .-_Z6errorsPPdii
.globl _Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii
.type _Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii, @function
_Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii:
.LFB2092:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5yNextPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii, .-_Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii
.globl _Z5yNextPdS_S_iii
.type _Z5yNextPdS_S_iii, @function
_Z5yNextPdS_S_iii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z5yNextPdS_S_iii, .-_Z5yNextPdS_S_iii
.globl _Z32__device_stub__Z9tableCopyPdS_iiPdS_ii
.type _Z32__device_stub__Z9tableCopyPdS_iiPdS_ii, @function
_Z32__device_stub__Z9tableCopyPdS_iiPdS_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9tableCopyPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z32__device_stub__Z9tableCopyPdS_iiPdS_ii, .-_Z32__device_stub__Z9tableCopyPdS_iiPdS_ii
.globl _Z9tableCopyPdS_ii
.type _Z9tableCopyPdS_ii, @function
_Z9tableCopyPdS_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9tableCopyPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z9tableCopyPdS_ii, .-_Z9tableCopyPdS_ii
.globl _Z32__device_stub__Z9colsToRowPdS_iiPdS_ii
.type _Z32__device_stub__Z9colsToRowPdS_iiPdS_ii, @function
_Z32__device_stub__Z9colsToRowPdS_iiPdS_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L89
.L85:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9colsToRowPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L85
.L90:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z32__device_stub__Z9colsToRowPdS_iiPdS_ii, .-_Z32__device_stub__Z9colsToRowPdS_iiPdS_ii
.globl _Z9colsToRowPdS_ii
.type _Z9colsToRowPdS_ii, @function
_Z9colsToRowPdS_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9colsToRowPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z9colsToRowPdS_ii, .-_Z9colsToRowPdS_ii
.globl _Z32__device_stub__Z9rowToColsPdS_iiPdS_ii
.type _Z32__device_stub__Z9rowToColsPdS_iiPdS_ii, @function
_Z32__device_stub__Z9rowToColsPdS_iiPdS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L97
.L93:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L98
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9rowToColsPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L93
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z32__device_stub__Z9rowToColsPdS_iiPdS_ii, .-_Z32__device_stub__Z9rowToColsPdS_iiPdS_ii
.globl _Z9rowToColsPdS_ii
.type _Z9rowToColsPdS_ii, @function
_Z9rowToColsPdS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9rowToColsPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z9rowToColsPdS_ii, .-_Z9rowToColsPdS_ii
.section .rodata.str1.1
.LC16:
.string "Wrong number of args\n"
.LC19:
.string "Final positions\n"
.LC20:
.string "first 5\n"
.LC21:
.string "last 5\n"
.LC22:
.string "Completed in %.3f sec !\n"
.LC23:
.string "Iteration num: %d\n"
.LC24:
.string "Errors = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L161
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 80(%rsp)
movl %eax, 52(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq %rax, 72(%rsp)
movl %eax, %r14d
movq 24(%rbp), %rbx
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 104(%rsp)
movl %r15d, %eax
imull %r12d, %eax
sall $3, %eax
movl %eax, 16(%rsp)
movl $128, %esi
movl %r15d, %edi
call _Z8blockNumii
movl %eax, %r12d
movl %r15d, %ebp
imull %eax, %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L154
sqrtsd %xmm0, %xmm0
.L106:
cvttsd2sil %xmm0, %eax
movl %eax, 92(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
comisd %xmm1, %xmm0
jbe .L107
addsd .LC17(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 92(%rsp)
.L107:
movq 72(%rsp), %r13
movslq %r13d, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl %r14d, %esi
movl 52(%rsp), %r15d
movl %r15d, %edi
call _Z7alloc2dii
movq %rax, 64(%rsp)
movl %r14d, %esi
movl %r15d, 52(%rsp)
movl %r15d, %edi
call _Z7alloc2dii
movq %rax, %r15
leal 1(%r13), %r13d
movl %ebp, %esi
movl %r13d, %edi
call _Z7alloc2dii
movq %rax, 32(%rsp)
movl %r14d, %ecx
movl 52(%rsp), %edx
movq 64(%rsp), %rsi
movq %rbx, %rdi
call _Z8loadFilePcPPdii
movslq 16(%rsp), %rbx
movq %rbx, 56(%rsp)
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
imull %ebp, %r13d
movl %r13d, %eax
cltq
leaq 0(,%rax,8), %rdi
movq %rdi, %rsi
movq %rdi, 96(%rsp)
leaq 136(%rsp), %rdi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq 64(%rsp), %rax
movq (%rax), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl %r12d, 164(%rsp)
movl %r12d, 168(%rsp)
movl $1, 172(%rsp)
movl $128, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movl $1, %ecx
movq 164(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L162
.L109:
call cudaThreadSynchronize@PLT
movl 160(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movq 164(%rsp), %rdi
movl 172(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L163
.L110:
call cudaThreadSynchronize@PLT
movl $0, %esi
leaq startwtime(%rip), %rdi
call gettimeofday@PLT
movq 72(%rsp), %rdi
movl %edi, %eax
imull %ebp, %eax
movl %eax, 48(%rsp)
leal -1(%rdi), %eax
movq 8(%rsp), %rdi
leaq 8(%rdi,%rax,8), %rbx
movslq %ebp, %rbp
salq $3, %rbp
movslq 80(%rsp), %rax
leaq 0(,%rax,8), %r13
movl $0, 88(%rsp)
jmp .L132
.L161:
leaq .LC16(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L101
.L154:
call sqrt@PLT
jmp .L106
.L162:
movl %r14d, %ecx
movl 52(%rsp), %edx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z32__device_stub__Z9colsToRowPdS_iiPdS_ii
jmp .L109
.L163:
movl %r14d, %ecx
movl 52(%rsp), %edx
movq 120(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z32__device_stub__Z9tableCopyPdS_iiPdS_ii
jmp .L110
.L165:
movl %r12d, %r9d
movl %r14d, %r8d
movl 52(%rsp), %ecx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z31__device_stub__Z5yNextPdS_S_iiiPdS_S_iii
jmp .L111
.L117:
movsd (%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
addq %rbp, %rdx
cmpq %rbx, %rax
jne .L117
.L119:
addsd (%r8,%rcx), %xmm1
addl $1, %esi
addq $8, %rcx
cmpl %esi, %r12d
je .L115
.L116:
leaq (%rdi,%rcx), %rdx
movq %r9, %rax
testl %r14d, %r14d
jg .L117
jmp .L119
.L139:
pxor %xmm1, %xmm1
.L115:
testl %r14d, %r14d
jle .L140
movq 8(%rsp), %rax
.L121:
movsd (%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L121
movq (%r15), %rax
movq 16(%rsp), %rdi
leaq (%rax,%rdi,8), %rdx
movq 8(%rsp), %rax
pxor %xmm1, %xmm1
.L122:
movsd (%rdx), %xmm0
subsd (%rax), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq %r13, %rdx
addq $8, %rax
cmpq %rbx, %rax
jne .L122
pxor %xmm0, %xmm0
ucomisd %xmm1, %xmm0
ja .L164
.L120:
sqrtsd %xmm1, %xmm1
ucomisd .LC18(%rip), %xmm1
movl $0, %eax
cmovb 24(%rsp), %eax
movl %eax, 24(%rsp)
.L125:
testl %r14d, %r14d
jle .L128
.L127:
movq 16(%rsp), %rax
leaq 0(,%rax,8), %rdx
movq 8(%rsp), %rax
.L129:
movq (%r15), %rcx
movsd (%rax), %xmm0
movsd %xmm0, (%rcx,%rdx)
addq %r13, %rdx
addq $8, %rax
cmpq %rbx, %rax
jne .L129
.L128:
movq 16(%rsp), %rdi
leaq 1(%rdi), %rax
addl %r12d, 28(%rsp)
movq 40(%rsp), %rsi
cmpq %rsi, %rdi
je .L130
movq %rax, 16(%rsp)
.L113:
movq 8(%rsp), %rax
testl %r14d, %r14d
jle .L131
.L114:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L114
.L131:
testl %r12d, %r12d
jle .L139
movq 32(%rsp), %rax
movq (%rax), %rdi
movl 28(%rsp), %eax
movslq %eax, %rdx
leaq 0(,%rdx,8), %rcx
movl 48(%rsp), %esi
addl %esi, %eax
cltq
subq %rdx, %rax
leaq (%rdi,%rax,8), %r8
pxor %xmm1, %xmm1
movl $0, %esi
movq 8(%rsp), %r9
jmp .L116
.L140:
pxor %xmm1, %xmm1
jmp .L120
.L164:
movapd %xmm1, %xmm0
call sqrt@PLT
comisd .LC18(%rip), %xmm0
jb .L125
movl $0, 24(%rsp)
jmp .L127
.L130:
movq (%r15), %rsi
movl $1, %ecx
movq 56(%rsp), %rdx
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 24(%rsp)
jne .L137
cmpl $14, 88(%rsp)
jg .L137
.L132:
addl $1, 88(%rsp)
movl $128, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl 92(%rsp), %eax
movl %eax, 188(%rsp)
movl %eax, 192(%rsp)
movl $1, 196(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 176(%rsp), %rdx
movl $1, %ecx
movq 188(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L165
.L111:
call cudaThreadSynchronize@PLT
movq 32(%rsp), %rax
movq (%rax), %rdi
movl $2, %ecx
movq 96(%rsp), %rdx
movq 136(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 52(%rsp)
jle .L112
movq 80(%rsp), %rax
leal -1(%rax), %eax
movq %rax, 40(%rsp)
movl $0, 28(%rsp)
movq $0, 16(%rsp)
movl $1, 24(%rsp)
jmp .L113
.L167:
movl 160(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movq 164(%rsp), %rdi
movl 172(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L166
.L135:
movl $2, %ecx
movq 56(%rsp), %rdx
movq 120(%rsp), %rsi
movq 64(%rsp), %rbx
movq (%rbx), %rdi
call cudaMemcpy@PLT
movl 88(%rsp), %r8d
movsd 8(%rsp), %xmm0
movl $128, %ecx
movl %r14d, %edx
movl 52(%rsp), %esi
movq %rbx, %rdi
call _Z13exportResultsPPdiiidi
jmp .L134
.L166:
movl %r14d, %ecx
movl 52(%rsp), %edx
movq 120(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z32__device_stub__Z9rowToColsPdS_iiPdS_ii
jmp .L135
.L168:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L136
.L112:
movq (%r15), %rsi
movl $1, %ecx
movq 56(%rsp), %rdx
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
.L137:
movl $0, %esi
leaq endwtime(%rip), %rdi
call gettimeofday@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%r15), %rdi
movl $2, %ecx
movq 56(%rsp), %rdx
movq 128(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rbp
movl %ebp, %r8d
movl 52(%rsp), %ebx
movl %ebx, %ecx
movl $5, %edx
movl $0, %esi
movq %r15, %rdi
call _Z11showResultsPPdiiii
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 80(%rsp), %esi
subl $5, %esi
movl %ebp, %r8d
movl %ebx, %ecx
movl %ebx, %edx
movq %r15, %rdi
call _Z11showResultsPPdiiii
movq endwtime(%rip), %rdx
movq 8+endwtime(%rip), %rcx
movq startwtime(%rip), %rdi
movq 8+startwtime(%rip), %rsi
call _Z8timeCalc7timevalS_
movsd %xmm0, 8(%rsp)
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 88(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 104(%rsp)
jne .L167
.L134:
movl %r14d, %edx
movl 52(%rsp), %esi
movq %r15, %rdi
call _Z6errorsPPdii
movl %eax, %edx
cmpl $-1, %eax
jne .L168
.L136:
movq 64(%rsp), %rdi
call _Z6free2dPPd
movq %r15, %rdi
call _Z6free2dPPd
movq 32(%rsp), %rdi
call _Z6free2dPPd
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L101:
movq 200(%rsp), %rdx
subq %fs:40, %rdx
jne .L169
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L169:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z9rowToColsPdS_ii"
.LC26:
.string "_Z9colsToRowPdS_ii"
.LC27:
.string "_Z9tableCopyPdS_ii"
.LC28:
.string "_Z5yNextPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z9rowToColsPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z9colsToRowPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z9tableCopyPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z5yNextPdS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl endwtime
.bss
.align 16
.type endwtime, @object
.size endwtime, 16
endwtime:
.zero 16
.globl startwtime
.align 16
.type startwtime, @object
.size startwtime, 16
startwtime:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1093567616
.align 8
.LC14:
.long 536870912
.long 1107468383
.align 8
.LC17:
.long 0
.long 1072693248
.align 8
.LC18:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Author: Polizois Siois 8535
*/
/*
Faculty of Electrical and Computer Engineering AUTH
3rd assignment at Parallel and Distributed Systems (7th semester)
*/
/*
Parallel implementation of mean shift algorithm for running on nvidia GPUs using cuda.
Give N number of points in a D-dimendional space, the program repeatedly makes NxN
parallel calculations.In every step it finds vectors(mean shifts) that move the points to
new positions which tend to be closer to the maxima of a predefined kernel function,
the Gaussian.The repetitions stop when each point has moved close enough(depends on
EPSILON) to the maxima.
*/
/*
This iteration of mean shift uses the GPU's SHARED MEMORY to perfom reduction and
speed up the process of calculating a sum of N doubles.
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda.h>
//set VAR=1 for the demo dataset (600x2)
//set VAR=0.1 for the dataset from the knn search exercise (60000x30) or the products of it
#define VAR 1 // σ^2
#define EPSILON 0.0001 // ε
#define THREADSPERBLOCK 128 // the number of threads in every block
//Used in main
double** alloc2d(int rows, int cols);
void loadFile(char name[65], double **x, int rows, int cols);
void showResults(double **x, int start, int end, int rows, int cols);
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters);
double timeCalc(struct timeval start, struct timeval end);
void free2d(double **matrix);
int blockNum(int N, int thPerBlock);
int errors(double **y, int rows, int cols);
//Used inside kernels
__device__ double d_k_func(double x);
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid);
//Kernels
__global__ void tableCopy(double *from, double *to, int rows, int cols);
__global__ void colsToRow(double *from, double *to, int rows, int cols);
__global__ void rowToCols(double *from, double *to, int rows, int cols);
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY);
struct timeval startwtime, endwtime; // Timer start and end value
int main(int argc, char *argv[])
{
if(argc!=5) { printf("Wrong number of args\n"); return -1; }
int ROWS = atoi(argv[1]);
int COLS = atoi(argv[2]);
char *FILENAME = argv[3];
int EXPORT = atoi(argv[4]);
int size2d = ROWS*COLS*sizeof(double);
int bNum = blockNum(ROWS, THREADSPERBLOCK); // the number of blocks needed to store <<ROWS>>
int tempRows = ROWS * bNum; // The number of blocks needed for ROWS*ROWS parallel calculations
int i, j, k, con = 1, iters=0;
double denom, dist=0;
double nb1 = sqrt(tempRows);
int nb = (int)nb1;
if(nb1 > (double)(int)nb1) nb = (int)(nb1+1);
//printf("Blocks per grid dimenson : %d\n", nb);
double **x, // The points at their original positions
**y; // The points after they have moved towards the maxima
double **temp; // stores the result of the reduction of every block
double *num = (double*) malloc(COLS * sizeof(double));
// Memory allocation in Host memory
x = alloc2d(ROWS, COLS);
y = alloc2d(ROWS, COLS);
temp = alloc2d((COLS+1), tempRows);
// Loading data from file to table
loadFile(FILENAME, x, ROWS, COLS);
// Memory allocation in Device memory
double *dx;
cudaMalloc(&dx, size2d);
double *dy;
cudaMalloc(&dy, size2d);
double *dtemp;
cudaMalloc(&dtemp, tempRows*(COLS+1)*sizeof(double));
int *dcon;
cudaMalloc(&dcon, 1*sizeof(int));
// Copy points from host memory to device memory
cudaMemcpy(dx, x[0], size2d, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1); // Defining number of threads in a block (1d)
dim3 numBlocks(blockNum(ROWS, threadsPerBlock.x), blockNum(ROWS, threadsPerBlock.x), 1); // Defining number of blocks in a grid (2d)
//rearrange table data so that we have coalesced memory access
colsToRow<<<numBlocks, threadsPerBlock>>>(dx, dy, ROWS, COLS); // Stores the transpose of dx to dy
cudaThreadSynchronize(); // wait all threads to finish
tableCopy<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS); // Copies dy to dx
cudaThreadSynchronize(); // wait all threads to finish
// Timer start
gettimeofday( &startwtime, NULL ); // Starts timing the process (memory copies between device and host will be included)
// Repeat until all mean shifts converge
do
{
iters++;
//printf("Iteration: %d\n", iters);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1);
dim3 numBlocks(nb , nb, 1);
//Reducing the sum parts for each new y from <<ROWS>> to <<bNum>> and storing them to dtemp
yNext<<<numBlocks, threadsPerBlock, THREADSPERBLOCK*sizeof(double)>>>(dx, dy, dtemp, ROWS, COLS, blockNum(ROWS, THREADSPERBLOCK));
cudaThreadSynchronize();
con=1;
cudaMemcpy(temp[0], dtemp, tempRows*(COLS+1)*sizeof(double), cudaMemcpyDeviceToHost);
//Calculating every new y (using dtemp) and checking if the corresponding mean shift converges
//printf("checking convergence\n");
for(i=0;i<ROWS;i++)
{
dist=0;
denom = 0; for(k=0;k<COLS;k++) num[k] = 0;
for(j=0;j<bNum;j++)
{
for(k=0;k<COLS;k++) num[k] += temp[0][k*tempRows+i*bNum+j];
denom += temp[0][COLS*tempRows+i*bNum+j];
}
for(k=0;k<COLS;k++) num[k] = num[k]/denom;
for(k=0;k<COLS;k++) dist+=pow(y[0][k*ROWS+i]-num[k],2);
dist = sqrt(dist);
if (dist >= EPSILON) con=0;
for(k=0;k<COLS;k++) y[0][k*ROWS+i] = num[k];
}
cudaMemcpy(dy, y[0], size2d, cudaMemcpyHostToDevice);
//printf("done checking\n");
}while(!con && iters <15);
// Timer stop
gettimeofday( &endwtime, NULL );
// Test prints
printf("Final positions\n");
cudaMemcpy(y[0], dy, size2d, cudaMemcpyDeviceToHost);
printf("first 5\n");
showResults(y, 0, 5, ROWS, COLS);
printf("last 5\n");
showResults(y, ROWS-5, ROWS, ROWS, COLS);
// Completion time show
double duration = timeCalc(startwtime, endwtime);
printf("Completed in %.3f sec !\n", duration);
printf("Iteration num: %d\n", iters);
// Exporting results
if(EXPORT)
{
numBlocks.x = bNum; numBlocks.y = bNum; numBlocks.z = 1;
rowToCols<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS);
cudaMemcpy(x[0], dx, size2d, cudaMemcpyDeviceToHost);
exportResults(x, ROWS, COLS, THREADSPERBLOCK, duration, iters);
}
// Checking for errors
int errs = errors(y, ROWS, COLS);
if(errs != -1) printf("Errors = %d\n", errs);
// Freeing the allocated memory
free2d(x); free2d(y); free2d(temp);
cudaFree(dx); cudaFree(dy); cudaFree(dtemp);
}
// Calculates (and reduces to bNum) all parts of the sum of the new position of every point based on its former
// position and the inititial position of all the points.
// Reduction results stored in "out"
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY)
{
extern __shared__ double shared[]; //will be used for reuduction
double *denom = (double*)shared;
double *numer = (double*)shared;
int bid = blockIdx.y*gridDim.x + blockIdx.x;
int blockOfY = bid % blocksForY;
int id = blockOfY*blockDim.x +threadIdx.x; // 0-ROWS
int yRow = bid / blocksForY; // 0-ROWS
double dist=0;
int i, tempRows = rows*blocksForY;
double inRows=0, inVar=0, gaus;
int tid1d = threadIdx.x;
if(id < rows && bid < tempRows) inRows=1;
//Distance calculation and check
for(i=0;i<cols;i++) dist+=pow(y[i*rows+yRow]-x[i*rows+id],2);
dist = sqrt(dist);
if(dist <= VAR) inVar=1;
gaus = d_k_func(pow(dist, 2));
// Every thread in a block(if in limits) fills the accornding place of denom[]
if(bid < tempRows)
denom[tid1d] = inRows * inVar * gaus;
// When all threads are done filling, denom gets reduced to one sum and stored to the according place of out[][]
__syncthreads();
if(bid < tempRows)
d_reduce(denom, &out[cols*tempRows+bid], blockDim.x, tid1d);
// The exact same thing done here for every dimention(colum)
for(i=0;i<cols;i++)
{
__syncthreads();
if(bid < tempRows)
numer[tid1d] = inRows * inVar * gaus * x[i*rows+id]; // rows x 1
__syncthreads();
if(bid < tempRows)
d_reduce(numer, &out[i*tempRows+bid], blockDim.x, tid1d);
}
}
//Gaussian kernel
__device__ double d_k_func(double x)
{
return exp(-x/(2*VAR));
}
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid)
{
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) *out = sdata[0];
}
__global__ void tableCopy(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int current = i*cols + j;
if (i < rows && j < cols)
to[current] = from[current];
}
__global__ void colsToRow(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int before = i*cols + j;
int after = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
__global__ void rowToCols(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; // row
int j = blockIdx.y * blockDim.y + threadIdx.y; // col
int after = i*cols + j;
int before = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
int blockNum(int N, int thPerBlock)
{
int num = N / thPerBlock,
mod = N % thPerBlock;
if(N <= thPerBlock) num = 1;
else if(mod) num += 1;
return num;
}
// Allocates continuous memory for a 2d array of doubles
double** alloc2d(int rows, int cols)
{
int i;
double **matrix= (double**)malloc(rows * sizeof(*matrix));
if(!matrix)
{
printf("Out of memory\n");
exit(-1);
}
matrix[0] = (double*)malloc(rows * (cols) * sizeof(**matrix));
if(!matrix[0])
{
printf("Out of memory\n");
exit(-1);
}
for(i = 1; i < rows; i++)
matrix[i] = matrix[0] + i * (cols);
return matrix;
}
void free2d(double **matrix)
{
free(matrix[0]);
free(matrix);
}
void loadFile(char name[65], double **x, int rows, int cols)
{
FILE *pointFile;
int i;
pointFile=fopen(name,"rb");
if (!pointFile){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fread(&(x[i][0]),sizeof(double),cols,pointFile))
{ printf("Unable to read from file!"); exit(1); }
fclose(pointFile);
}
void showResults(double **x, int start, int end, int rows, int cols)
{
int i,j;
for(i=start;i<end;i++)
{
printf("%d:",i);
for(j=0;j<cols;j++) printf(" %f ", x[0][j*rows+i]);
printf("\n");
}
}
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters)
{
FILE *out;
int i;
char name[65];
//Generating the file name
sprintf(name, "./results/y_(%d_%d)_(%d_%.3f_%d).bin", rows, cols, threads, dur, iters);
out=fopen(name,"wb");
if (!out){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fwrite(&(x[i][0]),sizeof(double),cols,out))
{ printf("Unable to read from file!"); exit(1); }
printf("Exported !\n");
fclose(out);
}
double timeCalc(struct timeval start, struct timeval end)
{
return (double)( ( end.tv_usec - start.tv_usec ) / 1.0e6 + end.tv_sec - start.tv_sec );
}
// Opens a binary file that has the results of a serial execution of mean shift for the same data
// Checks the points stored in y for errors, counts the errors and returns them
// The binary files used for comparisson should be stored in a folder called "compare" in the same
// directory with proggram
// For example if we want to test our result for the data set of 600 2-dimentional points we
// refer to the ./compare/600_2.bin file
int errors(double **y, int rows, int cols)
{
FILE *data;
double *tempLine;
char fileName[650];
int i,j, er=0;
//Generating the file name
sprintf(fileName, "./compare/%d_%d.bin", rows, cols);
// Allocating space for the reading line
tempLine = (double *) malloc(cols * sizeof(double));
//Opening the label results binary file for reading
data=fopen(fileName,"rb");
if (!data){ printf("Unable to open file in order to compare results!\n"); return -1; }
// Finding the correct place to start loadng
//fseek(data, 0, SEEK_SET);
// reading every line and checking if theres a difference between my results and those from matlab
for (i=0; i < rows; i++)
{
//Loading a label
if(!fread(tempLine, sizeof(double), cols, data))
{ printf("Unable to read from file!\n"); return -1; }
for(j=0;j<cols;j++)
// comparing with 10 decimal percision
if((int)(10000000000*tempLine[j]) != (int)(10000000000*y[0][j*rows+i])) { er++; break; }
}
//Closing the binary files
fclose(data);
return er;
} | /*
Author: Polizois Siois 8535
*/
/*
Faculty of Electrical and Computer Engineering AUTH
3rd assignment at Parallel and Distributed Systems (7th semester)
*/
/*
Parallel implementation of mean shift algorithm for running on nvidia GPUs using cuda.
Give N number of points in a D-dimendional space, the program repeatedly makes NxN
parallel calculations.In every step it finds vectors(mean shifts) that move the points to
new positions which tend to be closer to the maxima of a predefined kernel function,
the Gaussian.The repetitions stop when each point has moved close enough(depends on
EPSILON) to the maxima.
*/
/*
This iteration of mean shift uses the GPU's SHARED MEMORY to perfom reduction and
speed up the process of calculating a sum of N doubles.
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
//set VAR=1 for the demo dataset (600x2)
//set VAR=0.1 for the dataset from the knn search exercise (60000x30) or the products of it
#define VAR 1 // σ^2
#define EPSILON 0.0001 // ε
#define THREADSPERBLOCK 128 // the number of threads in every block
//Used in main
double** alloc2d(int rows, int cols);
void loadFile(char name[65], double **x, int rows, int cols);
void showResults(double **x, int start, int end, int rows, int cols);
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters);
double timeCalc(struct timeval start, struct timeval end);
void free2d(double **matrix);
int blockNum(int N, int thPerBlock);
int errors(double **y, int rows, int cols);
//Used inside kernels
__device__ double d_k_func(double x);
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid);
//Kernels
__global__ void tableCopy(double *from, double *to, int rows, int cols);
__global__ void colsToRow(double *from, double *to, int rows, int cols);
__global__ void rowToCols(double *from, double *to, int rows, int cols);
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY);
struct timeval startwtime, endwtime; // Timer start and end value
int main(int argc, char *argv[])
{
if(argc!=5) { printf("Wrong number of args\n"); return -1; }
int ROWS = atoi(argv[1]);
int COLS = atoi(argv[2]);
char *FILENAME = argv[3];
int EXPORT = atoi(argv[4]);
int size2d = ROWS*COLS*sizeof(double);
int bNum = blockNum(ROWS, THREADSPERBLOCK); // the number of blocks needed to store <<ROWS>>
int tempRows = ROWS * bNum; // The number of blocks needed for ROWS*ROWS parallel calculations
int i, j, k, con = 1, iters=0;
double denom, dist=0;
double nb1 = sqrt(tempRows);
int nb = (int)nb1;
if(nb1 > (double)(int)nb1) nb = (int)(nb1+1);
//printf("Blocks per grid dimenson : %d\n", nb);
double **x, // The points at their original positions
**y; // The points after they have moved towards the maxima
double **temp; // stores the result of the reduction of every block
double *num = (double*) malloc(COLS * sizeof(double));
// Memory allocation in Host memory
x = alloc2d(ROWS, COLS);
y = alloc2d(ROWS, COLS);
temp = alloc2d((COLS+1), tempRows);
// Loading data from file to table
loadFile(FILENAME, x, ROWS, COLS);
// Memory allocation in Device memory
double *dx;
hipMalloc(&dx, size2d);
double *dy;
hipMalloc(&dy, size2d);
double *dtemp;
hipMalloc(&dtemp, tempRows*(COLS+1)*sizeof(double));
int *dcon;
hipMalloc(&dcon, 1*sizeof(int));
// Copy points from host memory to device memory
hipMemcpy(dx, x[0], size2d, hipMemcpyHostToDevice);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1); // Defining number of threads in a block (1d)
dim3 numBlocks(blockNum(ROWS, threadsPerBlock.x), blockNum(ROWS, threadsPerBlock.x), 1); // Defining number of blocks in a grid (2d)
//rearrange table data so that we have coalesced memory access
colsToRow<<<numBlocks, threadsPerBlock>>>(dx, dy, ROWS, COLS); // Stores the transpose of dx to dy
hipDeviceSynchronize(); // wait all threads to finish
tableCopy<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS); // Copies dy to dx
hipDeviceSynchronize(); // wait all threads to finish
// Timer start
gettimeofday( &startwtime, NULL ); // Starts timing the process (memory copies between device and host will be included)
// Repeat until all mean shifts converge
do
{
iters++;
//printf("Iteration: %d\n", iters);
dim3 threadsPerBlock(THREADSPERBLOCK, 1, 1);
dim3 numBlocks(nb , nb, 1);
//Reducing the sum parts for each new y from <<ROWS>> to <<bNum>> and storing them to dtemp
yNext<<<numBlocks, threadsPerBlock, THREADSPERBLOCK*sizeof(double)>>>(dx, dy, dtemp, ROWS, COLS, blockNum(ROWS, THREADSPERBLOCK));
hipDeviceSynchronize();
con=1;
hipMemcpy(temp[0], dtemp, tempRows*(COLS+1)*sizeof(double), hipMemcpyDeviceToHost);
//Calculating every new y (using dtemp) and checking if the corresponding mean shift converges
//printf("checking convergence\n");
for(i=0;i<ROWS;i++)
{
dist=0;
denom = 0; for(k=0;k<COLS;k++) num[k] = 0;
for(j=0;j<bNum;j++)
{
for(k=0;k<COLS;k++) num[k] += temp[0][k*tempRows+i*bNum+j];
denom += temp[0][COLS*tempRows+i*bNum+j];
}
for(k=0;k<COLS;k++) num[k] = num[k]/denom;
for(k=0;k<COLS;k++) dist+=pow(y[0][k*ROWS+i]-num[k],2);
dist = sqrt(dist);
if (dist >= EPSILON) con=0;
for(k=0;k<COLS;k++) y[0][k*ROWS+i] = num[k];
}
hipMemcpy(dy, y[0], size2d, hipMemcpyHostToDevice);
//printf("done checking\n");
}while(!con && iters <15);
// Timer stop
gettimeofday( &endwtime, NULL );
// Test prints
printf("Final positions\n");
hipMemcpy(y[0], dy, size2d, hipMemcpyDeviceToHost);
printf("first 5\n");
showResults(y, 0, 5, ROWS, COLS);
printf("last 5\n");
showResults(y, ROWS-5, ROWS, ROWS, COLS);
// Completion time show
double duration = timeCalc(startwtime, endwtime);
printf("Completed in %.3f sec !\n", duration);
printf("Iteration num: %d\n", iters);
// Exporting results
if(EXPORT)
{
numBlocks.x = bNum; numBlocks.y = bNum; numBlocks.z = 1;
rowToCols<<<numBlocks, threadsPerBlock>>>(dy, dx, ROWS, COLS);
hipMemcpy(x[0], dx, size2d, hipMemcpyDeviceToHost);
exportResults(x, ROWS, COLS, THREADSPERBLOCK, duration, iters);
}
// Checking for errors
int errs = errors(y, ROWS, COLS);
if(errs != -1) printf("Errors = %d\n", errs);
// Freeing the allocated memory
free2d(x); free2d(y); free2d(temp);
hipFree(dx); hipFree(dy); hipFree(dtemp);
}
// Calculates (and reduces to bNum) all parts of the sum of the new position of every point based on its former
// position and the inititial position of all the points.
// Reduction results stored in "out"
__global__ void yNext(double *x, double *y, double *out, int rows, int cols, int blocksForY)
{
extern __shared__ double shared[]; //will be used for reuduction
double *denom = (double*)shared;
double *numer = (double*)shared;
int bid = blockIdx.y*gridDim.x + blockIdx.x;
int blockOfY = bid % blocksForY;
int id = blockOfY*blockDim.x +threadIdx.x; // 0-ROWS
int yRow = bid / blocksForY; // 0-ROWS
double dist=0;
int i, tempRows = rows*blocksForY;
double inRows=0, inVar=0, gaus;
int tid1d = threadIdx.x;
if(id < rows && bid < tempRows) inRows=1;
//Distance calculation and check
for(i=0;i<cols;i++) dist+=pow(y[i*rows+yRow]-x[i*rows+id],2);
dist = sqrt(dist);
if(dist <= VAR) inVar=1;
gaus = d_k_func(pow(dist, 2));
// Every thread in a block(if in limits) fills the accornding place of denom[]
if(bid < tempRows)
denom[tid1d] = inRows * inVar * gaus;
// When all threads are done filling, denom gets reduced to one sum and stored to the according place of out[][]
__syncthreads();
if(bid < tempRows)
d_reduce(denom, &out[cols*tempRows+bid], blockDim.x, tid1d);
// The exact same thing done here for every dimention(colum)
for(i=0;i<cols;i++)
{
__syncthreads();
if(bid < tempRows)
numer[tid1d] = inRows * inVar * gaus * x[i*rows+id]; // rows x 1
__syncthreads();
if(bid < tempRows)
d_reduce(numer, &out[i*tempRows+bid], blockDim.x, tid1d);
}
}
//Gaussian kernel
__device__ double d_k_func(double x)
{
return exp(-x/(2*VAR));
}
__device__ void d_reduce(double *sdata, double *out, int blockSize, int tid)
{
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) *out = sdata[0];
}
__global__ void tableCopy(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int current = i*cols + j;
if (i < rows && j < cols)
to[current] = from[current];
}
__global__ void colsToRow(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int before = i*cols + j;
int after = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
__global__ void rowToCols(double *from, double *to, int rows, int cols)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; // row
int j = blockIdx.y * blockDim.y + threadIdx.y; // col
int after = i*cols + j;
int before = j*rows + i;
if (i < rows && j < cols)
to[after] = from[before];
}
int blockNum(int N, int thPerBlock)
{
int num = N / thPerBlock,
mod = N % thPerBlock;
if(N <= thPerBlock) num = 1;
else if(mod) num += 1;
return num;
}
// Allocates continuous memory for a 2d array of doubles
double** alloc2d(int rows, int cols)
{
int i;
double **matrix= (double**)malloc(rows * sizeof(*matrix));
if(!matrix)
{
printf("Out of memory\n");
exit(-1);
}
matrix[0] = (double*)malloc(rows * (cols) * sizeof(**matrix));
if(!matrix[0])
{
printf("Out of memory\n");
exit(-1);
}
for(i = 1; i < rows; i++)
matrix[i] = matrix[0] + i * (cols);
return matrix;
}
void free2d(double **matrix)
{
free(matrix[0]);
free(matrix);
}
void loadFile(char name[65], double **x, int rows, int cols)
{
FILE *pointFile;
int i;
pointFile=fopen(name,"rb");
if (!pointFile){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fread(&(x[i][0]),sizeof(double),cols,pointFile))
{ printf("Unable to read from file!"); exit(1); }
fclose(pointFile);
}
void showResults(double **x, int start, int end, int rows, int cols)
{
int i,j;
for(i=start;i<end;i++)
{
printf("%d:",i);
for(j=0;j<cols;j++) printf(" %f ", x[0][j*rows+i]);
printf("\n");
}
}
void exportResults(double **x, int rows, int cols, int threads, double dur, int iters)
{
FILE *out;
int i;
char name[65];
//Generating the file name
sprintf(name, "./results/y_(%d_%d)_(%d_%.3f_%d).bin", rows, cols, threads, dur, iters);
out=fopen(name,"wb");
if (!out){ printf("Unable to open file!\n"); exit(1); }
for (i=0; i < rows; i++)
//Writing a row of coordinates
if (!fwrite(&(x[i][0]),sizeof(double),cols,out))
{ printf("Unable to read from file!"); exit(1); }
printf("Exported !\n");
fclose(out);
}
double timeCalc(struct timeval start, struct timeval end)
{
return (double)( ( end.tv_usec - start.tv_usec ) / 1.0e6 + end.tv_sec - start.tv_sec );
}
// Opens a binary file that has the results of a serial execution of mean shift for the same data
// Checks the points stored in y for errors, counts the errors and returns them
// The binary files used for comparisson should be stored in a folder called "compare" in the same
// directory with proggram
// For example if we want to test our result for the data set of 600 2-dimentional points we
// refer to the ./compare/600_2.bin file
int errors(double **y, int rows, int cols)
{
FILE *data;
double *tempLine;
char fileName[650];
int i,j, er=0;
//Generating the file name
sprintf(fileName, "./compare/%d_%d.bin", rows, cols);
// Allocating space for the reading line
tempLine = (double *) malloc(cols * sizeof(double));
//Opening the label results binary file for reading
data=fopen(fileName,"rb");
if (!data){ printf("Unable to open file in order to compare results!\n"); return -1; }
// Finding the correct place to start loadng
//fseek(data, 0, SEEK_SET);
// reading every line and checking if theres a difference between my results and those from matlab
for (i=0; i < rows; i++)
{
//Loading a label
if(!fread(tempLine, sizeof(double), cols, data))
{ printf("Unable to read from file!\n"); return -1; }
for(j=0;j<cols;j++)
// comparing with 10 decimal percision
if((int)(10000000000*tempLine[j]) != (int)(10000000000*y[0][j*rows+i])) { er++; break; }
}
//Closing the binary files
fclose(data);
return er;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} | code for sm_80
Function : _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R5, c[0x0][0x164] ; /* 0x0000590000057a13 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0003 */
/*0220*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*0230*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0aaa12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R3, RZ, RZ, -R10 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a0a */
/*0250*/ IMAD.WIDE R18, R10, R9, c[0x0][0x190] ; /* 0x000064000a127625 */
/* 0x000fc800078e0209 */
/*0260*/ IMAD R12, R3, c[0x0][0x164], R0 ; /* 0x00005900030c7a24 */
/* 0x000fe200078e0200 */
/*0270*/ LDG.E R2, [R18.64] ; /* 0x0000000412027981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.WIDE R4, R10, R9, c[0x0][0x188] ; /* 0x000062000a047625 */
/* 0x000fc800078e0209 */
/*0290*/ IMAD.WIDE R14, R12, R9.reuse, c[0x0][0x178] ; /* 0x00005e000c0e7625 */
/* 0x080fe200078e0209 */
/*02a0*/ IADD3 R6, R10, c[0x0][0x160], RZ ; /* 0x000058000a067a10 */
/* 0x000fe20007ffe0ff */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0004e4000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R12.reuse, R9.reuse, c[0x0][0x180] ; /* 0x000060000c107625 */
/* 0x0c0fe400078e0209 */
/*02d0*/ LDG.E R3, [R14.64] ; /* 0x000000040e037981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R8, R12, c[0x0][0x164], RZ ; /* 0x000059000c087a10 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.WIDE R10, R10, R9.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe400078e0209 */
/*0300*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0310*/ IMAD.WIDE R12, R12, R9, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fc400078e0209 */
/*0320*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f24000c1e1900 */
/*0330*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe400078e0209 */
/*0340*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*0350*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe400078e0209 */
/*0360*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1900 */
/*0380*/ BSSY B0, 0x4e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0390*/ FMUL R5, R3, R2 ; /* 0x0000000203057220 */
/* 0x004fc80000400000 */
/*03a0*/ FFMA R5, R16, R4, -R5 ; /* 0x0000000410057223 */
/* 0x008fc80000000805 */
/*03b0*/ MUFU.RCP R18, R5 ; /* 0x0000000500127308 */
/* 0x000e220000001000 */
/*03c0*/ FADD R15, -R12, R11 ; /* 0x0000000b0c0f7221 */
/* 0x010fc80000000100 */
/*03d0*/ FMUL R16, R15, R16 ; /* 0x000000100f107220 */
/* 0x000fe40000400000 */
/*03e0*/ FADD R14, -R8, R7 ; /* 0x00000007080e7221 */
/* 0x020fc80000000100 */
/*03f0*/ FFMA R16, R14, R3, -R16 ; /* 0x000000030e107223 */
/* 0x000fe40000000810 */
/*0400*/ FFMA R17, -R5, R18, 1 ; /* 0x3f80000005117423 */
/* 0x001fe40000000112 */
/*0410*/ FCHK P0, R16, R5 ; /* 0x0000000510007302 */
/* 0x000e240000000000 */
/*0420*/ FFMA R17, R18, R17, R18 ; /* 0x0000001112117223 */
/* 0x000fc80000000012 */
/*0430*/ FFMA R6, R16, R17, RZ ; /* 0x0000001110067223 */
/* 0x000fe400000000ff */
/*0440*/ FMUL R15, R15, R2 ; /* 0x000000020f0f7220 */
/* 0x000fe40000400000 */
/*0450*/ FFMA R2, -R5, R6, R16 ; /* 0x0000000605027223 */
/* 0x000fe40000000110 */
/*0460*/ FFMA R4, R14, R4, -R15 ; /* 0x000000040e047223 */
/* 0x000fe4000000080f */
/*0470*/ FFMA R2, R17, R2, R6 ; /* 0x0000000211027223 */
/* 0x000fe20000000006 */
/*0480*/ @!P0 BRA 0x4d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0010 */
/*04a0*/ MOV R6, 0x4c0 ; /* 0x000004c000067802 */
/* 0x000fc40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x640 ; /* 0x0000018000007944 */
/* 0x000fea0003c00000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0003 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e220000001000 */
/*04f0*/ BSSY B0, 0x5b0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0500*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*0510*/ FFMA R3, -R5, R6, 1 ; /* 0x3f80000005037423 */
/* 0x001fc80000000106 */
/*0520*/ FFMA R7, R6, R3, R6 ; /* 0x0000000306077223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R3, R4, R7, RZ ; /* 0x0000000704037223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R6, -R5, R3, R4 ; /* 0x0000000305067223 */
/* 0x000fc80000000104 */
/*0550*/ FFMA R3, R7, R6, R3 ; /* 0x0000000607037223 */
/* 0x000fe20000000003 */
/*0560*/ @!P0 BRA 0x5a0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0580*/ MOV R6, 0x5a0 ; /* 0x000005a000067802 */
/* 0x000fe40000000f00 */
/*0590*/ CALL.REL.NOINC 0x640 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.GTU.AND P0, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fe20003f0c000 */
/*05c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*05d0*/ FSETP.GE.AND P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720b */
/* 0x000fc80004706000 */
/*05e0*/ FSETP.GE.AND P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720b */
/* 0x001fc80000706000 */
/*05f0*/ FSETP.LE.AND P0, PT, R3, 1, P0 ; /* 0x3f8000000300780b */
/* 0x000fe20000703000 */
/*0600*/ IMAD.WIDE R2, R0, R5, c[0x0][0x198] ; /* 0x0000660000027625 */
/* 0x000fc600078e0205 */
/*0610*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0620*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fe20000011605 */
/*0650*/ BSSY B1, 0xca0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0660*/ SHF.R.U32.HI R3, RZ, 0x17, R9 ; /* 0x00000017ff037819 */
/* 0x000fe20000011609 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0680*/ LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070d7812 */
/* 0x000fe400078ec0ff */
/*0690*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*06b0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*06e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*06f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0700*/ @!P0 BRA 0x880 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0720*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0740*/ @P0 BRA 0xc80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c803 */
/*0760*/ @!P0 BRA 0xc60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0770*/ FSETP.NEU.FTZ.AND P2, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f5d200 */
/*0780*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0790*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07a0*/ @!P1 BRA !P2, 0xc60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07b0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*07c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07d0*/ @P1 BRA 0xc40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*07f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0800*/ @P0 BRA 0xc10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0820*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0830*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0840*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0850*/ @!P0 FFMA R3, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009038823 */
/* 0x000fe400000000ff */
/*0860*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0870*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*0890*/ BSSY B2, 0xc00 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*08a0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe200078e0a09 */
/*08b0*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*08c0*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x000e220000001000 */
/*08d0*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fe40000010100 */
/*08e0*/ IMAD R3, R8, -0x800000, R3 ; /* 0xff80000008037824 */
/* 0x000fe400078e0203 */
/*08f0*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0900*/ FFMA R14, R10, R11, R10 ; /* 0x0000000b0a0e7223 */
/* 0x000fc8000000000a */
/*0910*/ FFMA R10, R3, R14, RZ ; /* 0x0000000e030a7223 */
/* 0x000fc800000000ff */
/*0920*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0930*/ FFMA R11, R14, R11, R10 ; /* 0x0000000b0e0b7223 */
/* 0x000fe2000000000a */
/*0940*/ IADD3 R10, R8, 0x7f, -R13 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe80d */
/*0950*/ FFMA R12, R12, R11, R3 ; /* 0x0000000b0c0c7223 */
/* 0x000fe40000000003 */
/*0960*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0207 */
/*0970*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fca000000000b */
/*0980*/ SHF.R.U32.HI R8, RZ, 0x17, R3 ; /* 0x00000017ff087819 */
/* 0x000fc80000011603 */
/*0990*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*09a0*/ IMAD.IADD R13, R8, 0x1, R10 ; /* 0x00000001080d7824 */
/* 0x000fca00078e020a */
/*09b0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*09d0*/ @!P0 BRA 0xbe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*09f0*/ @P0 BRA 0xbb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0a10*/ @P0 BRA 0xbf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0a40*/ @!P0 BRA 0xbf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a50*/ FFMA.RZ R7, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00b */
/*0a60*/ IADD3 R10, R13.reuse, 0x20, RZ ; /* 0x000000200d0a7810 */
/* 0x040fe20007ffe0ff */
/*0a70*/ FFMA.RM R8, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400b */
/*0a80*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0a90*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0aa0*/ FFMA.RP R7, R14, R12, R11 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800b */
/*0ab0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0ac0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0d */
/*0ad0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0ae0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0af0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0b00*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0b10*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0b20*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b40*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0b50*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0b60*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0b70*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0b80*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*0b90*/ LOP3.LUT R3, R10, R3, RZ, 0xfc, !PT ; /* 0x000000030a037212 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0bc0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xbf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*0bf0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4803 */
/*0c20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4803 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0c70*/ BRA 0xc90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FADD.FTZ R3, R9, R5 ; /* 0x0000000509037221 */
/* 0x000fe40000010000 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0cb0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff34006007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} | .file "tmpxft_000d54e2_00000000-6_pathAdjacencyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
.type _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi, @function
_Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi, .-_Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, @function
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .-_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 8
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@function
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x40
s_load_b32 s5, s[0:1], 0x4c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s4, s3, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s3, s4
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x38
s_xor_b32 s5, s5, s4
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b256 s[4:11], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_mul_lo_u32 v0, v2, s3
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v5, 31, v4
v_sub_nc_u32_e32 v6, v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v2
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v12, s3, v6
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v10, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s14, v2
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v0, v[8:9], off
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v14, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v12, v[12:13], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[14:15], off
global_load_b32 v5, v[8:9], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
s_waitcnt vmcnt(6)
v_sub_f32_e32 v0, v0, v12
s_waitcnt vmcnt(2)
v_dual_mul_f32 v8, v4, v2 :: v_dual_sub_f32 v3, v3, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f32_e32 v5, v0, v6
v_mul_f32_e32 v0, v0, v2
s_waitcnt vmcnt(0)
v_fma_f32 v2, v6, v7, -v8
v_fma_f32 v4, v3, v4, -v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v0, v3, v7, -v0
v_div_scale_f32 v3, null, v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v5, null, v2, v2, v0
v_div_scale_f32 v10, vcc_lo, v4, v2, v4
v_rcp_f32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v3, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, v2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v7, v9, v7
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v3, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v3, -v3, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v3, v3, v6, v9
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
v_div_fixup_f32 v3, v3, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v0, v5, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_le_f32_e32 vcc_lo, 0, v3
v_cmp_ge_f32_e64 s1, 1.0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_le_f32_e64 s0, 0, v0
v_cmp_ge_f32_e64 s2, 1.0, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s0, s0, s1
v_add_co_u32 v0, vcc_lo, s16, v0
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, 1, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .Lfunc_end0-_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void pathAdjacencyKernel(int noTransitions, int noSegments, float* XY1, float* XY2, float* X4_X3, float* Y4_Y3, float* X2_X1, float* Y2_Y1, int* adjacency) {
int blockId = blockIdx.y * gridDim.x + blockIdx.x;
int idx = blockId * blockDim.x + threadIdx.x;
if (idx < noTransitions*noSegments) {
int seg1 = idx/noSegments;
int seg2 = idx - seg1*noSegments;
float Y1_Y3 = XY1[seg1 + noTransitions] - XY2[seg2 + noSegments];
float X1_X3 = XY1[seg1] - XY2[seg2];
float numa = X4_X3[seg2]*Y1_Y3 - Y4_Y3[seg2]*X1_X3;
float numb = X2_X1[seg1]*Y1_Y3 - Y2_Y1[seg1]*X1_X3;
float deno = Y4_Y3[seg2]*X2_X1[seg1] - X4_X3[seg2]*Y2_Y1[seg1];
float u_a = numa/deno;
float u_b = numb/deno;
adjacency[idx] = (int)((u_a >= 0.0) && (u_a <= 1.0) && (u_b >= 0.0)
&& (u_b <= 1.0));
}
} | .text
.file "pathAdjacencyKernel.hip"
.globl _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi # -- Begin function _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 4, 0x90
.type _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@function
_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi: # @_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .Lfunc_end0-_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@object # @_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .rodata,"a",@progbits
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 3, 0x0
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
.quad _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R5, c[0x0][0x164] ; /* 0x0000590000057a13 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0003 */
/*0220*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*0230*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0aaa12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R3, RZ, RZ, -R10 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a0a */
/*0250*/ IMAD.WIDE R18, R10, R9, c[0x0][0x190] ; /* 0x000064000a127625 */
/* 0x000fc800078e0209 */
/*0260*/ IMAD R12, R3, c[0x0][0x164], R0 ; /* 0x00005900030c7a24 */
/* 0x000fe200078e0200 */
/*0270*/ LDG.E R2, [R18.64] ; /* 0x0000000412027981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.WIDE R4, R10, R9, c[0x0][0x188] ; /* 0x000062000a047625 */
/* 0x000fc800078e0209 */
/*0290*/ IMAD.WIDE R14, R12, R9.reuse, c[0x0][0x178] ; /* 0x00005e000c0e7625 */
/* 0x080fe200078e0209 */
/*02a0*/ IADD3 R6, R10, c[0x0][0x160], RZ ; /* 0x000058000a067a10 */
/* 0x000fe20007ffe0ff */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0004e4000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R12.reuse, R9.reuse, c[0x0][0x180] ; /* 0x000060000c107625 */
/* 0x0c0fe400078e0209 */
/*02d0*/ LDG.E R3, [R14.64] ; /* 0x000000040e037981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R8, R12, c[0x0][0x164], RZ ; /* 0x000059000c087a10 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.WIDE R10, R10, R9.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe400078e0209 */
/*0300*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0310*/ IMAD.WIDE R12, R12, R9, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fc400078e0209 */
/*0320*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f24000c1e1900 */
/*0330*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe400078e0209 */
/*0340*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*0350*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe400078e0209 */
/*0360*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1900 */
/*0380*/ BSSY B0, 0x4e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0390*/ FMUL R5, R3, R2 ; /* 0x0000000203057220 */
/* 0x004fc80000400000 */
/*03a0*/ FFMA R5, R16, R4, -R5 ; /* 0x0000000410057223 */
/* 0x008fc80000000805 */
/*03b0*/ MUFU.RCP R18, R5 ; /* 0x0000000500127308 */
/* 0x000e220000001000 */
/*03c0*/ FADD R15, -R12, R11 ; /* 0x0000000b0c0f7221 */
/* 0x010fc80000000100 */
/*03d0*/ FMUL R16, R15, R16 ; /* 0x000000100f107220 */
/* 0x000fe40000400000 */
/*03e0*/ FADD R14, -R8, R7 ; /* 0x00000007080e7221 */
/* 0x020fc80000000100 */
/*03f0*/ FFMA R16, R14, R3, -R16 ; /* 0x000000030e107223 */
/* 0x000fe40000000810 */
/*0400*/ FFMA R17, -R5, R18, 1 ; /* 0x3f80000005117423 */
/* 0x001fe40000000112 */
/*0410*/ FCHK P0, R16, R5 ; /* 0x0000000510007302 */
/* 0x000e240000000000 */
/*0420*/ FFMA R17, R18, R17, R18 ; /* 0x0000001112117223 */
/* 0x000fc80000000012 */
/*0430*/ FFMA R6, R16, R17, RZ ; /* 0x0000001110067223 */
/* 0x000fe400000000ff */
/*0440*/ FMUL R15, R15, R2 ; /* 0x000000020f0f7220 */
/* 0x000fe40000400000 */
/*0450*/ FFMA R2, -R5, R6, R16 ; /* 0x0000000605027223 */
/* 0x000fe40000000110 */
/*0460*/ FFMA R4, R14, R4, -R15 ; /* 0x000000040e047223 */
/* 0x000fe4000000080f */
/*0470*/ FFMA R2, R17, R2, R6 ; /* 0x0000000211027223 */
/* 0x000fe20000000006 */
/*0480*/ @!P0 BRA 0x4d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0010 */
/*04a0*/ MOV R6, 0x4c0 ; /* 0x000004c000067802 */
/* 0x000fc40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x640 ; /* 0x0000018000007944 */
/* 0x000fea0003c00000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0003 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e220000001000 */
/*04f0*/ BSSY B0, 0x5b0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0500*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*0510*/ FFMA R3, -R5, R6, 1 ; /* 0x3f80000005037423 */
/* 0x001fc80000000106 */
/*0520*/ FFMA R7, R6, R3, R6 ; /* 0x0000000306077223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R3, R4, R7, RZ ; /* 0x0000000704037223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R6, -R5, R3, R4 ; /* 0x0000000305067223 */
/* 0x000fc80000000104 */
/*0550*/ FFMA R3, R7, R6, R3 ; /* 0x0000000607037223 */
/* 0x000fe20000000003 */
/*0560*/ @!P0 BRA 0x5a0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0580*/ MOV R6, 0x5a0 ; /* 0x000005a000067802 */
/* 0x000fe40000000f00 */
/*0590*/ CALL.REL.NOINC 0x640 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.GTU.AND P0, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fe20003f0c000 */
/*05c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*05d0*/ FSETP.GE.AND P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720b */
/* 0x000fc80004706000 */
/*05e0*/ FSETP.GE.AND P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720b */
/* 0x001fc80000706000 */
/*05f0*/ FSETP.LE.AND P0, PT, R3, 1, P0 ; /* 0x3f8000000300780b */
/* 0x000fe20000703000 */
/*0600*/ IMAD.WIDE R2, R0, R5, c[0x0][0x198] ; /* 0x0000660000027625 */
/* 0x000fc600078e0205 */
/*0610*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0620*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fe20000011605 */
/*0650*/ BSSY B1, 0xca0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0660*/ SHF.R.U32.HI R3, RZ, 0x17, R9 ; /* 0x00000017ff037819 */
/* 0x000fe20000011609 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0680*/ LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070d7812 */
/* 0x000fe400078ec0ff */
/*0690*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*06b0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*06e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*06f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0700*/ @!P0 BRA 0x880 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0720*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0740*/ @P0 BRA 0xc80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c803 */
/*0760*/ @!P0 BRA 0xc60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0770*/ FSETP.NEU.FTZ.AND P2, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f5d200 */
/*0780*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0790*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07a0*/ @!P1 BRA !P2, 0xc60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07b0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*07c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07d0*/ @P1 BRA 0xc40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*07f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0800*/ @P0 BRA 0xc10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0820*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0830*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0840*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0850*/ @!P0 FFMA R3, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009038823 */
/* 0x000fe400000000ff */
/*0860*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0870*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*0890*/ BSSY B2, 0xc00 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*08a0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe200078e0a09 */
/*08b0*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*08c0*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x000e220000001000 */
/*08d0*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fe40000010100 */
/*08e0*/ IMAD R3, R8, -0x800000, R3 ; /* 0xff80000008037824 */
/* 0x000fe400078e0203 */
/*08f0*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0900*/ FFMA R14, R10, R11, R10 ; /* 0x0000000b0a0e7223 */
/* 0x000fc8000000000a */
/*0910*/ FFMA R10, R3, R14, RZ ; /* 0x0000000e030a7223 */
/* 0x000fc800000000ff */
/*0920*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0930*/ FFMA R11, R14, R11, R10 ; /* 0x0000000b0e0b7223 */
/* 0x000fe2000000000a */
/*0940*/ IADD3 R10, R8, 0x7f, -R13 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe80d */
/*0950*/ FFMA R12, R12, R11, R3 ; /* 0x0000000b0c0c7223 */
/* 0x000fe40000000003 */
/*0960*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0207 */
/*0970*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fca000000000b */
/*0980*/ SHF.R.U32.HI R8, RZ, 0x17, R3 ; /* 0x00000017ff087819 */
/* 0x000fc80000011603 */
/*0990*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*09a0*/ IMAD.IADD R13, R8, 0x1, R10 ; /* 0x00000001080d7824 */
/* 0x000fca00078e020a */
/*09b0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*09d0*/ @!P0 BRA 0xbe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*09f0*/ @P0 BRA 0xbb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0a10*/ @P0 BRA 0xbf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0a40*/ @!P0 BRA 0xbf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a50*/ FFMA.RZ R7, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00b */
/*0a60*/ IADD3 R10, R13.reuse, 0x20, RZ ; /* 0x000000200d0a7810 */
/* 0x040fe20007ffe0ff */
/*0a70*/ FFMA.RM R8, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400b */
/*0a80*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0a90*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0aa0*/ FFMA.RP R7, R14, R12, R11 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800b */
/*0ab0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0ac0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0d */
/*0ad0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0ae0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0af0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0b00*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0b10*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0b20*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b40*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0b50*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0b60*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0b70*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0b80*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*0b90*/ LOP3.LUT R3, R10, R3, RZ, 0xfc, !PT ; /* 0x000000030a037212 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0bc0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xbf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*0bf0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4803 */
/*0c20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4803 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0c70*/ BRA 0xc90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FADD.FTZ R3, R9, R5 ; /* 0x0000000509037221 */
/* 0x000fe40000010000 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0cb0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff34006007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 8
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@function
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x40
s_load_b32 s5, s[0:1], 0x4c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s4, s3, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s3, s4
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x38
s_xor_b32 s5, s5, s4
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b256 s[4:11], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_mul_lo_u32 v0, v2, s3
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v5, 31, v4
v_sub_nc_u32_e32 v6, v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v2
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v12, s3, v6
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v10, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s14, v2
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v0, v[8:9], off
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v14, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v12, v[12:13], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[14:15], off
global_load_b32 v5, v[8:9], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
s_waitcnt vmcnt(6)
v_sub_f32_e32 v0, v0, v12
s_waitcnt vmcnt(2)
v_dual_mul_f32 v8, v4, v2 :: v_dual_sub_f32 v3, v3, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f32_e32 v5, v0, v6
v_mul_f32_e32 v0, v0, v2
s_waitcnt vmcnt(0)
v_fma_f32 v2, v6, v7, -v8
v_fma_f32 v4, v3, v4, -v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v0, v3, v7, -v0
v_div_scale_f32 v3, null, v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v5, null, v2, v2, v0
v_div_scale_f32 v10, vcc_lo, v4, v2, v4
v_rcp_f32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v3, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, v2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v7, v9, v7
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v3, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v3, -v3, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v3, v3, v6, v9
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
v_div_fixup_f32 v3, v3, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v0, v5, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_le_f32_e32 vcc_lo, 0, v3
v_cmp_ge_f32_e64 s1, 1.0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_le_f32_e64 s0, 0, v0
v_cmp_ge_f32_e64 s2, 1.0, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s0, s0, s1
v_add_co_u32 v0, vcc_lo, s16, v0
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, 1, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .Lfunc_end0-_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d54e2_00000000-6_pathAdjacencyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
.type _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi, @function
_Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi, .-_Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, @function
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z19pathAdjacencyKerneliiPfS_S_S_S_S_PiiiPfS_S_S_S_S_Pi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .-_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pathAdjacencyKernel.hip"
.globl _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi # -- Begin function _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 4, 0x90
.type _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@function
_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi: # @_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi, .Lfunc_end0-_Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi,@object # @_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.section .rodata,"a",@progbits
.globl _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.p2align 3, 0x0
_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi:
.quad _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.size _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19pathAdjacencyKerneliiPfS_S_S_S_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
cudaMalloc((void**) &d_M, mMatSize);
cudaMalloc((void**) &d_N, nMatSize);
cudaMalloc((void**) &d_P, pMatSize);
cudaMemcpy(d_M, M, mMatSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N, nMatSize, cudaMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
cudaMemcpy(P, d_P, pMatSize, cudaMemcpyDeviceToHost);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0080*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R14, R3, 0x4, R0 ; /* 0x00000004030e7824 */
/* 0x001fc400078e0200 */
/*00a0*/ IMAD R17, R4, 0x4, R15 ; /* 0x0000000404117824 */
/* 0x002fc800078e020f */
/*00b0*/ @!P0 BRA 0x790 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R5.reuse, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ ISETP.GE.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0110*/ SHF.L.U32 R16, R0, 0x4, RZ ; /* 0x0000000400107819 */
/* 0x000fe400000006ff */
/*0120*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fc600078f10ff */
/*0130*/ IMAD R16, R15, 0x4, R16 ; /* 0x000000040f107824 */
/* 0x000fe200078e0210 */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fc80000011403 */
/*0150*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fc80007800200 */
/*0160*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc80007ffe0ff */
/*0170*/ LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078ec0ff */
/*0180*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0190*/ @!P0 BRA 0x5b0 ; /* 0x0000041000008947 */
/* 0x000fd80003800000 */
/*01a0*/ IADD3 R18, R0.reuse, 0x4, RZ ; /* 0x0000000400127810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD R20, R0, c[0x0][0x180], R15.reuse ; /* 0x0000600000147a24 */
/* 0x100fe200078e020f */
/*01c0*/ ISETP.GE.AND P2, PT, R14.reuse, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x040fe20003f46270 */
/*01d0*/ IMAD R27, R14, c[0x0][0x17c], R15.reuse ; /* 0x00005f000e1b7a24 */
/* 0x100fe200078e020f */
/*01e0*/ IADD3 R22, -R3, -0x1, R2 ; /* 0xffffffff03167810 */
/* 0x000fe20007ffe102 */
/*01f0*/ IMAD R19, R18, c[0x0][0x180], R15 ; /* 0x0000600012137a24 */
/* 0x000fe200078e020f */
/*0200*/ LEA R20, R4.reuse, R20, 0x2 ; /* 0x0000001404147211 */
/* 0x040fe200078e10ff */
/*0210*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R25, R15, 0x4, RZ ; /* 0x000000040f197810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD R19, R4, 0x4, R19 ; /* 0x0000000404137824 */
/* 0x000fe200078e0213 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0250*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fe20003f06270 */
/*0260*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x000fe2000fffe0ff */
/*0280*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R12, R27, UR4, RZ ; /* 0x000000041b0c7c10 */
/* 0x000fe2000fffe0ff */
/*02a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*02b0*/ ISETP.GE.OR P4, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fc40000786670 */
/*02c0*/ IADD3 R2, R15, UR4, RZ ; /* 0x000000040f027c10 */
/* 0x000fc6000fffe0ff */
/*02d0*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0203 */
/*02e0*/ ISETP.GE.OR P3, PT, R2, c[0x0][0x17c], P2 ; /* 0x00005f0002007a0c */
/* 0x000fce0001766670 */
/*02f0*/ @!P4 IMAD.WIDE R4, R20, R3, c[0x0][0x168] ; /* 0x00005a001404c625 */
/* 0x000fca00078e0203 */
/*0300*/ @!P4 LDG.E R29, [R4.64] ; /* 0x00000006041dc981 */
/* 0x000ea8000c1e1900 */
/*0310*/ @!P3 LDG.E R9, [R12.64] ; /* 0x000000060c09b981 */
/* 0x000ee2000c1e1900 */
/*0320*/ ISETP.GE.OR P0, PT, R18, c[0x0][0x17c], P0 ; /* 0x00005f0012007a0c */
/* 0x000fe20000706670 */
/*0330*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.GE.OR P3, PT, R25, c[0x0][0x17c], P2 ; /* 0x00005f0019007a0c */
/* 0x000fd60001766670 */
/*0350*/ @!P0 IMAD.WIDE R2, R19, R3, c[0x0][0x168] ; /* 0x00005a0013028625 */
/* 0x000fe200078e0203 */
/*0360*/ STS [R16+0x40], R29 ; /* 0x0000401d10007388 */
/* 0x004fe80000000800 */
/*0370*/ STS [R16], R9 ; /* 0x0000000910007388 */
/* 0x008fe80000000800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDS R28, [R15.X4+0x40] ; /* 0x000040000f1c7984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R26, [R15.X4+0x50] ; /* 0x000050000f1a7984 */
/* 0x000fe80000004800 */
/*03b0*/ LDS R23, [R15.X4+0x60] ; /* 0x000060000f177984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R24, [R15.X4+0x70] ; /* 0x000070000f187984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS.128 R4, [R0.X16] ; /* 0x0000000000047984 */
/* 0x000e28000000cc00 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ @!P3 LDG.E R11, [R12.64+0x10] ; /* 0x000010060c0bb981 */
/* 0x000ea8000c1e1900 */
/*0400*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000602088981 */
/* 0x0000e2000c1e1900 */
/*0410*/ IADD3 R22, R22, 0x2, RZ ; /* 0x0000000216167810 */
/* 0x000fe20007ffe0ff */
/*0420*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0430*/ IADD3 R25, R25, 0x8, RZ ; /* 0x0000000819197810 */
/* 0x000fc40007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*0450*/ IADD3 R18, R18, 0x8, RZ ; /* 0x0000000812127810 */
/* 0x000fe20007ffe0ff */
/*0460*/ FFMA R2, R28, R4, R21 ; /* 0x000000041c027223 */
/* 0x001fc80000000015 */
/*0470*/ FFMA R5, R26, R5, R2 ; /* 0x000000051a057223 */
/* 0x000fe20000000002 */
/*0480*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fc60000000f00 */
/*0490*/ FFMA R5, R23, R6, R5 ; /* 0x0000000617057223 */
/* 0x000fe40000000005 */
/*04a0*/ IMAD R19, R2, c[0x0][0x180], R19 ; /* 0x0000600002137a24 */
/* 0x000fe400078e0213 */
/*04b0*/ FFMA R5, R24, R7, R5 ; /* 0x0000000718057223 */
/* 0x000fe40000000005 */
/*04c0*/ IMAD R20, R2, c[0x0][0x180], R20 ; /* 0x0000600002147a24 */
/* 0x000fe200078e0214 */
/*04d0*/ STS [R16], R11 ; /* 0x0000000b10007388 */
/* 0x004fe80000000800 */
/*04e0*/ STS [R16+0x40], R8 ; /* 0x0000400810007388 */
/* 0x008fe80000000800 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ LDS R29, [R15.X4+0x40] ; /* 0x000040000f1d7984 */
/* 0x000fe80000004800 */
/*0510*/ LDS.128 R8, [R0.X16] ; /* 0x0000000000087984 */
/* 0x000e28000000cc00 */
/*0520*/ LDS R28, [R15.X4+0x50] ; /* 0x000050000f1c7984 */
/* 0x000e680000004800 */
/*0530*/ LDS R21, [R15.X4+0x60] ; /* 0x000060000f157984 */
/* 0x000ea80000004800 */
/*0540*/ LDS R4, [R15.X4+0x70] ; /* 0x000070000f047984 */
/* 0x000ee20000004800 */
/*0550*/ FFMA R8, R29, R8, R5 ; /* 0x000000081d087223 */
/* 0x001fc80000000005 */
/*0560*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0570*/ FFMA R21, R21, R10, R8 ; /* 0x0000000a15157223 */
/* 0x004fc80000000008 */
/*0580*/ FFMA R21, R4, R11, R21 ; /* 0x0000000b04157223 */
/* 0x008fe20000000015 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @P0 BRA 0x250 ; /* 0xfffffca000000947 */
/* 0x000fea000383ffff */
/*05b0*/ @!P1 BRA 0x790 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R3, R15, UR4, RZ ; /* 0x000000040f037c10 */
/* 0x000fe2000fffe0ff */
/*05d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*05e0*/ IADD3 R8, R0, UR4, RZ ; /* 0x0000000400087c10 */
/* 0x000fe2000fffe0ff */
/*05f0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0600*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fc40003f06270 */
/*0610*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe40003f26270 */
/*0620*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fe40000706670 */
/*0630*/ ISETP.GE.OR P1, PT, R17, c[0x0][0x180], P1 ; /* 0x0000600011007a0c */
/* 0x000fd60000f26670 */
/*0640*/ @!P0 IMAD R2, R14, c[0x0][0x17c], R3 ; /* 0x00005f000e028a24 */
/* 0x000fe400078e0203 */
/*0650*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe400078e00ff */
/*0660*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff099424 */
/* 0x000fe400078e00ff */
/*0670*/ @!P1 IMAD R8, R8, c[0x0][0x180], R17 ; /* 0x0000600008089a24 */
/* 0x000fe400078e0211 */
/*0680*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fc800078e0203 */
/*0690*/ @!P1 IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008089625 */
/* 0x000fe200078e0209 */
/*06a0*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000006020d8981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ @!P1 LDG.E R11, [R8.64] ; /* 0x00000006080b9981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ STS [R16], R13 ; /* 0x0000000d10007388 */
/* 0x004fe80000000800 */
/*06d0*/ STS [R16+0x40], R11 ; /* 0x0000400b10007388 */
/* 0x008fe80000000800 */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ LDS R10, [R15.X4+0x40] ; /* 0x000040000f0a7984 */
/* 0x000fe80000004800 */
/*0700*/ LDS.128 R4, [R0.X16] ; /* 0x0000000000047984 */
/* 0x000e28000000cc00 */
/*0710*/ LDS R12, [R15.X4+0x50] ; /* 0x000050000f0c7984 */
/* 0x000e680000004800 */
/*0720*/ LDS R18, [R15.X4+0x60] ; /* 0x000060000f127984 */
/* 0x000ea80000004800 */
/*0730*/ LDS R19, [R15.X4+0x70] ; /* 0x000070000f137984 */
/* 0x000ee20000004800 */
/*0740*/ FFMA R4, R10, R4, R21 ; /* 0x000000040a047223 */
/* 0x001fc80000000015 */
/*0750*/ FFMA R5, R12, R5, R4 ; /* 0x000000050c057223 */
/* 0x002fc80000000004 */
/*0760*/ FFMA R6, R18, R6, R5 ; /* 0x0000000612067223 */
/* 0x004fc80000000005 */
/*0770*/ FFMA R21, R19, R7, R6 ; /* 0x0000000713157223 */
/* 0x008fe20000000006 */
/*0780*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0790*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fc80003f06270 */
/*07a0*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fda0000706670 */
/*07b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD R2, R14, c[0x0][0x180], R17 ; /* 0x000060000e027a24 */
/* 0x000fc800078e0211 */
/*07e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*07f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
cudaMalloc((void**) &d_M, mMatSize);
cudaMalloc((void**) &d_N, nMatSize);
cudaMalloc((void**) &d_P, pMatSize);
cudaMemcpy(d_M, M, mMatSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N, nMatSize, cudaMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
cudaMemcpy(P, d_P, pMatSize, cudaMemcpyDeviceToHost);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} | .file "tmpxft_00078569_00000000-6_RecMatMulTiled.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s:\n"
.LC1:
.string "\n"
.LC2:
.string " %10.2f"
.text
.globl _Z5printPfiiPKc
.type _Z5printPfiiPKc, @function
_Z5printPfiiPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
movq %rcx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L4
movslq %r12d, %r12
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
jmp .L6
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
je .L4
.L6:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPfiiPKc, .-_Z5printPfiiPKc
.globl _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.type _Z15MatrixMulKernelPfS_S_iii, @function
_Z15MatrixMulKernelPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15MatrixMulKernelPfS_S_iii, .-_Z15MatrixMulKernelPfS_S_iii
.globl _Z20MatrixMultiplicationPfS_S_iii
.type _Z20MatrixMultiplicationPfS_S_iii, @function
_Z20MatrixMultiplicationPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %ebx
movl %r8d, %r15d
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %ecx, %r14d
imull %r8d, %r14d
sall $2, %r14d
movslq %r14d, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r15d, %r13d
imull %ebp, %r13d
sall $2, %r13d
movslq %r13d, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %ebx, %r12d
imull %ebp, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal 3(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $2, %eax
addl $1, %eax
movl %eax, 64(%rsp)
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
addl $1, %eax
movl %eax, 68(%rsp)
movl $4, 76(%rsp)
movl $4, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebp, %r9d
movl %r15d, %r8d
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z20MatrixMultiplicationPfS_S_iii, .-_Z20MatrixMultiplicationPfS_S_iii
.section .rodata.str1.1
.LC3:
.string "Enter rows(j) for matrix m: "
.LC4:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Enter columns(k) for matrix m and rows(k) for matrix n: "
.align 8
.LC6:
.string "Enter columns(l) for matrix n: "
.section .rodata.str1.1
.LC8:
.string "M"
.LC9:
.string "N"
.LC10:
.string "P"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 44(%rsp), %rsi
leaq .LC4(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 52(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %ecx
movl %ecx, 20(%rsp)
movl 48(%rsp), %r14d
movl %ecx, %eax
imull %r14d, %eax
movl 52(%rsp), %r15d
movl %r14d, %ebx
imull %r15d, %ebx
movl %ebx, 16(%rsp)
imull %r15d, %ecx
movl %ecx, 8(%rsp)
movl %eax, 12(%rsp)
movslq %eax, %r13
leaq 0(,%r13,4), %rdi
call malloc@PLT
movq %rax, %rbp
movslq %ebx, %r12
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %rbx
movslq 8(%rsp), %rax
leaq 0(,%rax,4), %rdi
movq %rdi, 24(%rsp)
call malloc@PLT
movq %rax, %rdi
cmpl $0, 12(%rsp)
jle .L24
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L25
.L24:
cmpl $0, 16(%rsp)
jle .L26
movl $1, %eax
.L27:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %r12
jne .L27
.L26:
cmpl $0, 8(%rsp)
jle .L28
movq %rdi, %rax
movq 24(%rsp), %rdx
addq %rdi, %rdx
.L29:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L29
.L28:
movl %r15d, %r9d
movl %r14d, %r8d
movl 20(%rsp), %ecx
movq %rdi, %r14
movq %rdi, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z20MatrixMultiplicationPfS_S_iii
leaq .LC8(%rip), %rcx
movl 48(%rsp), %edx
movl 12(%rsp), %esi
movq %rbp, %rdi
call _Z5printPfiiPKc
leaq .LC9(%rip), %rcx
movl 52(%rsp), %edx
movl 16(%rsp), %esi
movq %rbx, %rdi
call _Z5printPfiiPKc
leaq .LC10(%rip), %rcx
movl 52(%rsp), %edx
movl 8(%rsp), %esi
movq %r14, %rdi
call _Z5printPfiiPKc
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z15MatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
cudaMalloc((void**) &d_M, mMatSize);
cudaMalloc((void**) &d_N, nMatSize);
cudaMalloc((void**) &d_P, pMatSize);
cudaMemcpy(d_M, M, mMatSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N, nMatSize, cudaMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
cudaMemcpy(P, d_P, pMatSize, cudaMemcpyDeviceToHost);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
hipMalloc((void**) &d_M, mMatSize);
hipMalloc((void**) &d_N, nMatSize);
hipMalloc((void**) &d_P, pMatSize);
hipMemcpy(d_M, M, mMatSize, hipMemcpyHostToDevice);
hipMemcpy(d_N, N, nMatSize, hipMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
hipMemcpy(P, d_P, pMatSize, hipMemcpyDeviceToHost);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
hipMalloc((void**) &d_M, mMatSize);
hipMalloc((void**) &d_N, nMatSize);
hipMalloc((void**) &d_P, pMatSize);
hipMemcpy(d_M, M, mMatSize, hipMemcpyHostToDevice);
hipMemcpy(d_N, N, nMatSize, hipMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
hipMemcpy(P, d_P, pMatSize, hipMemcpyDeviceToHost);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPfS_S_iii,@function
_Z15MatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 2, v2
v_lshl_add_u32 v0, s14, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s9, -2
s_cbranch_scc1 .LBB0_16
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v3
s_add_i32 s10, s9, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v5, 4, v2
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v6, 64, v4
s_lshr_b32 s11, s11, 30
v_mul_lo_u32 v8, v1, s9
s_add_i32 s10, s10, s11
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v5, v4
s_ashr_i32 s11, s10, 2
v_cmp_le_i32_e64 s10, s8, v1
v_add_nc_u32_e32 v9, v6, v5
s_mov_b32 s13, 0
s_max_i32 s11, s11, 0
s_xor_b32 s12, s2, -1
.LBB0_2:
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
v_lshl_add_u32 v11, s13, 2, v3
s_and_not1_b32 s16, s10, exec_lo
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s9, v11
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_6
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v12, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s15
v_lshl_add_u32 v12, s13, 2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s9, v12
s_or_b32 s2, s2, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_10
ds_store_b32 v9, v10
.LBB0_10:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v12, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, v6
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_add_nc_u32_e32 v13, s2, v5
s_add_i32 s2, s2, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 16, v12
s_cmp_eq_u32 s2, 16
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v13, v14
s_cbranch_scc0 .LBB0_13
s_add_i32 s2, s13, 1
s_cmp_eq_u32 s13, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_16
s_mov_b32 s13, s2
s_branch .LBB0_2
.LBB0_16:
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************************
* Eric Blasko
* 6/02/19
* Homework #3
* RecMatMulTiled.cu
* This program performs rectangle matrix multiplication, which uses shared mem
* of size TILE_WIDTH x TILE_WIDTH. Values of Matrix M and N are chosen by the
* user such that M is of size JxK and N is of size KxL. The kernal function
* produces the results of the matrix multiplication between M and N, storing
* it in matrix P which is of size JxL.
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define TILE_WIDTH 4
//kernal to compute C = A * B. Uses shared memory/tile execution
__global__ void MatrixMulKernel(float *d_M, float *d_N, float *d_P, int JSIZE, int KSIZE, int LSIZE)
{
//tile size to store element in shared memory
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
//generate ids of threads and blocks
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify row, col of d_P elem to work on
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
float Pvalue = 0.0;
// loop over d_M and dN tiles required to compute d_P elem
for (int ph = 0; ph < ((KSIZE - 1)/TILE_WIDTH) + 1; ph++) {
//collaborative loading of d_M and d_N tiles into shared memory
if((Row < JSIZE) && (ph*TILE_WIDTH + tx) < KSIZE)
Mds[ty][tx] = d_M[Row*KSIZE + ((ph*TILE_WIDTH) + tx)];
else
Mds[ty][tx] = 0.0;
if((ph*TILE_WIDTH + ty) < KSIZE && Col < LSIZE)
Nds[ty][tx] = d_N[(ph*TILE_WIDTH + ty) * LSIZE + Col];
else
Nds[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH;k++)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Store final results into C
if(Row < JSIZE && Col < LSIZE)
d_P[Row*LSIZE+Col] = Pvalue;
}
//Set up and launch of kernal function
void MatrixMultiplication(float *M, float *N, float *P, int j, int k, int l)
{
int mMatSize = (j*k)*sizeof(float);
int nMatSize = (k*l)*sizeof(float);
int pMatSize = (j*l)*sizeof(float);
float *d_M;
float *d_N;
float *d_P;
hipMalloc((void**) &d_M, mMatSize);
hipMalloc((void**) &d_N, nMatSize);
hipMalloc((void**) &d_P, pMatSize);
hipMemcpy(d_M, M, mMatSize, hipMemcpyHostToDevice);
hipMemcpy(d_N, N, nMatSize, hipMemcpyHostToDevice);
// execution configuration
dim3 dimGrid((l/TILE_WIDTH) + 1, (j/TILE_WIDTH) + 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// launch the kernels
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, j, k, l);
hipMemcpy(P, d_P, pMatSize, hipMemcpyDeviceToHost);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
}
//Print the values in a matrix
void print(float * matrix, int size, int col, const char * name)
{
printf("%s:\n", name);
for (int i = 0; i < size; i++)
{
if((i % col) == 0)
printf("\n");
printf(" %10.2f", matrix[i]);
}
printf("\n");
}
//main function to get users input and to launch kernal
int main(int argc, char** argv)
{
int j,k,l;
int mSize, nSize, pSize;
float *M;
float *N;
float *P;
printf("Enter rows(j) for matrix m: ");
scanf("%d", &j);
printf("Enter columns(k) for matrix m and rows(k) for matrix n: ");
scanf("%d", &k);
printf("Enter columns(l) for matrix n: ");
scanf("%d", &l);
//get size of each matrix
mSize = j * k;
nSize = k * l;
pSize = j * l;
//allocate in memory
M = (float *) malloc(mSize*sizeof(float));
N = (float *) malloc(nSize*sizeof(float));
P = (float *) malloc(pSize*sizeof(float));
//assign values to each matrix
for (int i = 0; i < mSize; i++)
M[i] = i;
for (int i = 0; i < nSize; i++)
N[i] = i+1;
for (int i = 0; i < pSize; i++)
P[i] = 0;
MatrixMultiplication(M, N, P, j, k, l);
print(M, mSize,k, "M");
print(N, nSize,l, "N");
print(P, pSize,l, "P");
free(M);
free(N);
free(P);
} | .text
.file "RecMatMulTiled.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPfS_S_iii: # @_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z20MatrixMultiplicationPfS_S_iii # -- Begin function _Z20MatrixMultiplicationPfS_S_iii
.p2align 4, 0x90
.type _Z20MatrixMultiplicationPfS_S_iii,@function
_Z20MatrixMultiplicationPfS_S_iii: # @_Z20MatrixMultiplicationPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movl %ecx, %r12d
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdi, %rbx
leal (,%r12,4), %r13d
movl %r13d, %eax
imull %r8d, %eax
movl %r8d, 24(%rsp) # 4-byte Spill
movl %r8d, %ebp
imull %r9d, %ebp
shll $2, %ebp
imull %r9d, %r13d
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %ebp, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r13d, %r13
movq %rsp, %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leal 3(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $2, %eax
incl %eax
leal 3(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $2, %edi
incl %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 36(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movl %r15d, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20MatrixMultiplicationPfS_S_iii, .Lfunc_end1-_Z20MatrixMultiplicationPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z5printPfiiPKc # -- Begin function _Z5printPfiiPKc
.p2align 4, 0x90
.type _Z5printPfiiPKc,@function
_Z5printPfiiPKc: # @_Z5printPfiiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movq %rcx, %rsi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r15d, %eax
cltd
idivl %ebx
testl %edx, %edx
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z5printPfiiPKc, .Lfunc_end2-_Z5printPfiiPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 36(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 36(%rsp), %eax
movl 8(%rsp), %ecx
movl %ecx, %r15d
imull %eax, %r15d
movl 4(%rsp), %ebp
movl %ebp, %r12d
movl %ecx, 16(%rsp) # 4-byte Spill
imull %ecx, %r12d
movl %ebp, 12(%rsp) # 4-byte Spill
movl %eax, 20(%rsp) # 4-byte Spill
imull %eax, %ebp
movslq %r15d, %r13
leaq (,%r13,4), %rdi
callq malloc
movq %rax, %rbx
movslq %r12d, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movslq %ebp, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movl %r15d, 24(%rsp) # 4-byte Spill
movl %r15d, %r15d
testl %r13d, %r13d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_2
.LBB3_3: # %.preheader55
movl %r12d, %r13d
movl %r12d, 28(%rsp) # 4-byte Spill
testl %r12d, %r12d
jle .LBB3_6
# %bb.4: # %.lr.ph58.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_5: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq %rcx, %r13
jne .LBB3_5
.LBB3_6: # %.preheader
movl %ebp, %r12d
movl %ebp, 32(%rsp) # 4-byte Spill
testl %ebp, %ebp
movq 40(%rsp), %rbp # 8-byte Reload
jle .LBB3_8
# %bb.7: # %.lr.ph60.preheader
leaq (,%r12,4), %rdx
movq %rbp, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB3_8: # %._crit_edge
movq %r12, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl 20(%rsp), %ecx # 4-byte Reload
movl 16(%rsp), %r8d # 4-byte Reload
movl 12(%rsp), %r9d # 4-byte Reload
callq _Z20MatrixMultiplicationPfS_S_iii
movl 8(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
cmpl $0, 24(%rsp) # 4-byte Folded Reload
jle .LBB3_13
# %bb.9: # %.lr.ph.preheader.i
xorl %r12d, %r12d
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_10 Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r15
je .LBB3_13
.LBB3_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_12
.LBB3_13: # %_Z5printPfiiPKc.exit
movl $10, %edi
callq putchar@PLT
movl 4(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
cmpl $0, 28(%rsp) # 4-byte Folded Reload
movq 40(%rsp), %r15 # 8-byte Reload
jle .LBB3_18
# %bb.14: # %.lr.ph.preheader.i38
xorl %r12d, %r12d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
je .LBB3_18
.LBB3_15: # %.lr.ph.i40
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_17
.LBB3_18: # %_Z5printPfiiPKc.exit45
movl $10, %edi
callq putchar@PLT
movl 4(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
cmpl $0, 32(%rsp) # 4-byte Folded Reload
movq 48(%rsp), %r13 # 8-byte Reload
jle .LBB3_23
# %bb.19: # %.lr.ph.preheader.i47
xorl %r12d, %r12d
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_20 Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
je .LBB3_23
.LBB3_20: # %.lr.ph.i49
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_22
# %bb.21: # in Loop: Header=BB3_20 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_22
.LBB3_23: # %_Z5printPfiiPKc.exit54
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_iii,@object # @_Z15MatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_iii
.size _Z15MatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s:\n"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %10.2f"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter rows(j) for matrix m: "
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter columns(k) for matrix m and rows(k) for matrix n: "
.size .L.str.5, 57
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter columns(l) for matrix n: "
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "M"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "N"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P"
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0080*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R14, R3, 0x4, R0 ; /* 0x00000004030e7824 */
/* 0x001fc400078e0200 */
/*00a0*/ IMAD R17, R4, 0x4, R15 ; /* 0x0000000404117824 */
/* 0x002fc800078e020f */
/*00b0*/ @!P0 BRA 0x790 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R5.reuse, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ ISETP.GE.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0110*/ SHF.L.U32 R16, R0, 0x4, RZ ; /* 0x0000000400107819 */
/* 0x000fe400000006ff */
/*0120*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fc600078f10ff */
/*0130*/ IMAD R16, R15, 0x4, R16 ; /* 0x000000040f107824 */
/* 0x000fe200078e0210 */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fc80000011403 */
/*0150*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fc80007800200 */
/*0160*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc80007ffe0ff */
/*0170*/ LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078ec0ff */
/*0180*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0190*/ @!P0 BRA 0x5b0 ; /* 0x0000041000008947 */
/* 0x000fd80003800000 */
/*01a0*/ IADD3 R18, R0.reuse, 0x4, RZ ; /* 0x0000000400127810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD R20, R0, c[0x0][0x180], R15.reuse ; /* 0x0000600000147a24 */
/* 0x100fe200078e020f */
/*01c0*/ ISETP.GE.AND P2, PT, R14.reuse, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x040fe20003f46270 */
/*01d0*/ IMAD R27, R14, c[0x0][0x17c], R15.reuse ; /* 0x00005f000e1b7a24 */
/* 0x100fe200078e020f */
/*01e0*/ IADD3 R22, -R3, -0x1, R2 ; /* 0xffffffff03167810 */
/* 0x000fe20007ffe102 */
/*01f0*/ IMAD R19, R18, c[0x0][0x180], R15 ; /* 0x0000600012137a24 */
/* 0x000fe200078e020f */
/*0200*/ LEA R20, R4.reuse, R20, 0x2 ; /* 0x0000001404147211 */
/* 0x040fe200078e10ff */
/*0210*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R25, R15, 0x4, RZ ; /* 0x000000040f197810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD R19, R4, 0x4, R19 ; /* 0x0000000404137824 */
/* 0x000fe200078e0213 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0250*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fe20003f06270 */
/*0260*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x000fe2000fffe0ff */
/*0280*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R12, R27, UR4, RZ ; /* 0x000000041b0c7c10 */
/* 0x000fe2000fffe0ff */
/*02a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*02b0*/ ISETP.GE.OR P4, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fc40000786670 */
/*02c0*/ IADD3 R2, R15, UR4, RZ ; /* 0x000000040f027c10 */
/* 0x000fc6000fffe0ff */
/*02d0*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0203 */
/*02e0*/ ISETP.GE.OR P3, PT, R2, c[0x0][0x17c], P2 ; /* 0x00005f0002007a0c */
/* 0x000fce0001766670 */
/*02f0*/ @!P4 IMAD.WIDE R4, R20, R3, c[0x0][0x168] ; /* 0x00005a001404c625 */
/* 0x000fca00078e0203 */
/*0300*/ @!P4 LDG.E R29, [R4.64] ; /* 0x00000006041dc981 */
/* 0x000ea8000c1e1900 */
/*0310*/ @!P3 LDG.E R9, [R12.64] ; /* 0x000000060c09b981 */
/* 0x000ee2000c1e1900 */
/*0320*/ ISETP.GE.OR P0, PT, R18, c[0x0][0x17c], P0 ; /* 0x00005f0012007a0c */
/* 0x000fe20000706670 */
/*0330*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.GE.OR P3, PT, R25, c[0x0][0x17c], P2 ; /* 0x00005f0019007a0c */
/* 0x000fd60001766670 */
/*0350*/ @!P0 IMAD.WIDE R2, R19, R3, c[0x0][0x168] ; /* 0x00005a0013028625 */
/* 0x000fe200078e0203 */
/*0360*/ STS [R16+0x40], R29 ; /* 0x0000401d10007388 */
/* 0x004fe80000000800 */
/*0370*/ STS [R16], R9 ; /* 0x0000000910007388 */
/* 0x008fe80000000800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDS R28, [R15.X4+0x40] ; /* 0x000040000f1c7984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R26, [R15.X4+0x50] ; /* 0x000050000f1a7984 */
/* 0x000fe80000004800 */
/*03b0*/ LDS R23, [R15.X4+0x60] ; /* 0x000060000f177984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R24, [R15.X4+0x70] ; /* 0x000070000f187984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS.128 R4, [R0.X16] ; /* 0x0000000000047984 */
/* 0x000e28000000cc00 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ @!P3 LDG.E R11, [R12.64+0x10] ; /* 0x000010060c0bb981 */
/* 0x000ea8000c1e1900 */
/*0400*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000602088981 */
/* 0x0000e2000c1e1900 */
/*0410*/ IADD3 R22, R22, 0x2, RZ ; /* 0x0000000216167810 */
/* 0x000fe20007ffe0ff */
/*0420*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0430*/ IADD3 R25, R25, 0x8, RZ ; /* 0x0000000819197810 */
/* 0x000fc40007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*0450*/ IADD3 R18, R18, 0x8, RZ ; /* 0x0000000812127810 */
/* 0x000fe20007ffe0ff */
/*0460*/ FFMA R2, R28, R4, R21 ; /* 0x000000041c027223 */
/* 0x001fc80000000015 */
/*0470*/ FFMA R5, R26, R5, R2 ; /* 0x000000051a057223 */
/* 0x000fe20000000002 */
/*0480*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fc60000000f00 */
/*0490*/ FFMA R5, R23, R6, R5 ; /* 0x0000000617057223 */
/* 0x000fe40000000005 */
/*04a0*/ IMAD R19, R2, c[0x0][0x180], R19 ; /* 0x0000600002137a24 */
/* 0x000fe400078e0213 */
/*04b0*/ FFMA R5, R24, R7, R5 ; /* 0x0000000718057223 */
/* 0x000fe40000000005 */
/*04c0*/ IMAD R20, R2, c[0x0][0x180], R20 ; /* 0x0000600002147a24 */
/* 0x000fe200078e0214 */
/*04d0*/ STS [R16], R11 ; /* 0x0000000b10007388 */
/* 0x004fe80000000800 */
/*04e0*/ STS [R16+0x40], R8 ; /* 0x0000400810007388 */
/* 0x008fe80000000800 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ LDS R29, [R15.X4+0x40] ; /* 0x000040000f1d7984 */
/* 0x000fe80000004800 */
/*0510*/ LDS.128 R8, [R0.X16] ; /* 0x0000000000087984 */
/* 0x000e28000000cc00 */
/*0520*/ LDS R28, [R15.X4+0x50] ; /* 0x000050000f1c7984 */
/* 0x000e680000004800 */
/*0530*/ LDS R21, [R15.X4+0x60] ; /* 0x000060000f157984 */
/* 0x000ea80000004800 */
/*0540*/ LDS R4, [R15.X4+0x70] ; /* 0x000070000f047984 */
/* 0x000ee20000004800 */
/*0550*/ FFMA R8, R29, R8, R5 ; /* 0x000000081d087223 */
/* 0x001fc80000000005 */
/*0560*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0570*/ FFMA R21, R21, R10, R8 ; /* 0x0000000a15157223 */
/* 0x004fc80000000008 */
/*0580*/ FFMA R21, R4, R11, R21 ; /* 0x0000000b04157223 */
/* 0x008fe20000000015 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @P0 BRA 0x250 ; /* 0xfffffca000000947 */
/* 0x000fea000383ffff */
/*05b0*/ @!P1 BRA 0x790 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R3, R15, UR4, RZ ; /* 0x000000040f037c10 */
/* 0x000fe2000fffe0ff */
/*05d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*05e0*/ IADD3 R8, R0, UR4, RZ ; /* 0x0000000400087c10 */
/* 0x000fe2000fffe0ff */
/*05f0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0600*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fc40003f06270 */
/*0610*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe40003f26270 */
/*0620*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fe40000706670 */
/*0630*/ ISETP.GE.OR P1, PT, R17, c[0x0][0x180], P1 ; /* 0x0000600011007a0c */
/* 0x000fd60000f26670 */
/*0640*/ @!P0 IMAD R2, R14, c[0x0][0x17c], R3 ; /* 0x00005f000e028a24 */
/* 0x000fe400078e0203 */
/*0650*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe400078e00ff */
/*0660*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff099424 */
/* 0x000fe400078e00ff */
/*0670*/ @!P1 IMAD R8, R8, c[0x0][0x180], R17 ; /* 0x0000600008089a24 */
/* 0x000fe400078e0211 */
/*0680*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fc800078e0203 */
/*0690*/ @!P1 IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008089625 */
/* 0x000fe200078e0209 */
/*06a0*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000006020d8981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ @!P1 LDG.E R11, [R8.64] ; /* 0x00000006080b9981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ STS [R16], R13 ; /* 0x0000000d10007388 */
/* 0x004fe80000000800 */
/*06d0*/ STS [R16+0x40], R11 ; /* 0x0000400b10007388 */
/* 0x008fe80000000800 */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ LDS R10, [R15.X4+0x40] ; /* 0x000040000f0a7984 */
/* 0x000fe80000004800 */
/*0700*/ LDS.128 R4, [R0.X16] ; /* 0x0000000000047984 */
/* 0x000e28000000cc00 */
/*0710*/ LDS R12, [R15.X4+0x50] ; /* 0x000050000f0c7984 */
/* 0x000e680000004800 */
/*0720*/ LDS R18, [R15.X4+0x60] ; /* 0x000060000f127984 */
/* 0x000ea80000004800 */
/*0730*/ LDS R19, [R15.X4+0x70] ; /* 0x000070000f137984 */
/* 0x000ee20000004800 */
/*0740*/ FFMA R4, R10, R4, R21 ; /* 0x000000040a047223 */
/* 0x001fc80000000015 */
/*0750*/ FFMA R5, R12, R5, R4 ; /* 0x000000050c057223 */
/* 0x002fc80000000004 */
/*0760*/ FFMA R6, R18, R6, R5 ; /* 0x0000000612067223 */
/* 0x004fc80000000005 */
/*0770*/ FFMA R21, R19, R7, R6 ; /* 0x0000000713157223 */
/* 0x008fe20000000006 */
/*0780*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0790*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fc80003f06270 */
/*07a0*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fda0000706670 */
/*07b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD R2, R14, c[0x0][0x180], R17 ; /* 0x000060000e027a24 */
/* 0x000fc800078e0211 */
/*07e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*07f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPfS_S_iii,@function
_Z15MatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 2, v2
v_lshl_add_u32 v0, s14, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s9, -2
s_cbranch_scc1 .LBB0_16
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v3
s_add_i32 s10, s9, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v5, 4, v2
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v6, 64, v4
s_lshr_b32 s11, s11, 30
v_mul_lo_u32 v8, v1, s9
s_add_i32 s10, s10, s11
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v5, v4
s_ashr_i32 s11, s10, 2
v_cmp_le_i32_e64 s10, s8, v1
v_add_nc_u32_e32 v9, v6, v5
s_mov_b32 s13, 0
s_max_i32 s11, s11, 0
s_xor_b32 s12, s2, -1
.LBB0_2:
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
v_lshl_add_u32 v11, s13, 2, v3
s_and_not1_b32 s16, s10, exec_lo
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s9, v11
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_6
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v12, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s15
v_lshl_add_u32 v12, s13, 2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s9, v12
s_or_b32 s2, s2, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_10
ds_store_b32 v9, v10
.LBB0_10:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v12, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, v6
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_add_nc_u32_e32 v13, s2, v5
s_add_i32 s2, s2, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 16, v12
s_cmp_eq_u32 s2, 16
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v13, v14
s_cbranch_scc0 .LBB0_13
s_add_i32 s2, s13, 1
s_cmp_eq_u32 s13, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_16
s_mov_b32 s13, s2
s_branch .LBB0_2
.LBB0_16:
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00078569_00000000-6_RecMatMulTiled.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s:\n"
.LC1:
.string "\n"
.LC2:
.string " %10.2f"
.text
.globl _Z5printPfiiPKc
.type _Z5printPfiiPKc, @function
_Z5printPfiiPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
movq %rcx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L4
movslq %r12d, %r12
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
jmp .L6
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
je .L4
.L6:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPfiiPKc, .-_Z5printPfiiPKc
.globl _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.type _Z15MatrixMulKernelPfS_S_iii, @function
_Z15MatrixMulKernelPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15MatrixMulKernelPfS_S_iii, .-_Z15MatrixMulKernelPfS_S_iii
.globl _Z20MatrixMultiplicationPfS_S_iii
.type _Z20MatrixMultiplicationPfS_S_iii, @function
_Z20MatrixMultiplicationPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %ebx
movl %r8d, %r15d
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %ecx, %r14d
imull %r8d, %r14d
sall $2, %r14d
movslq %r14d, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r15d, %r13d
imull %ebp, %r13d
sall $2, %r13d
movslq %r13d, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %ebx, %r12d
imull %ebp, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal 3(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $2, %eax
addl $1, %eax
movl %eax, 64(%rsp)
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
addl $1, %eax
movl %eax, 68(%rsp)
movl $4, 76(%rsp)
movl $4, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebp, %r9d
movl %r15d, %r8d
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z20MatrixMultiplicationPfS_S_iii, .-_Z20MatrixMultiplicationPfS_S_iii
.section .rodata.str1.1
.LC3:
.string "Enter rows(j) for matrix m: "
.LC4:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Enter columns(k) for matrix m and rows(k) for matrix n: "
.align 8
.LC6:
.string "Enter columns(l) for matrix n: "
.section .rodata.str1.1
.LC8:
.string "M"
.LC9:
.string "N"
.LC10:
.string "P"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 44(%rsp), %rsi
leaq .LC4(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 52(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %ecx
movl %ecx, 20(%rsp)
movl 48(%rsp), %r14d
movl %ecx, %eax
imull %r14d, %eax
movl 52(%rsp), %r15d
movl %r14d, %ebx
imull %r15d, %ebx
movl %ebx, 16(%rsp)
imull %r15d, %ecx
movl %ecx, 8(%rsp)
movl %eax, 12(%rsp)
movslq %eax, %r13
leaq 0(,%r13,4), %rdi
call malloc@PLT
movq %rax, %rbp
movslq %ebx, %r12
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %rbx
movslq 8(%rsp), %rax
leaq 0(,%rax,4), %rdi
movq %rdi, 24(%rsp)
call malloc@PLT
movq %rax, %rdi
cmpl $0, 12(%rsp)
jle .L24
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L25
.L24:
cmpl $0, 16(%rsp)
jle .L26
movl $1, %eax
.L27:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %r12
jne .L27
.L26:
cmpl $0, 8(%rsp)
jle .L28
movq %rdi, %rax
movq 24(%rsp), %rdx
addq %rdi, %rdx
.L29:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L29
.L28:
movl %r15d, %r9d
movl %r14d, %r8d
movl 20(%rsp), %ecx
movq %rdi, %r14
movq %rdi, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z20MatrixMultiplicationPfS_S_iii
leaq .LC8(%rip), %rcx
movl 48(%rsp), %edx
movl 12(%rsp), %esi
movq %rbp, %rdi
call _Z5printPfiiPKc
leaq .LC9(%rip), %rcx
movl 52(%rsp), %edx
movl 16(%rsp), %esi
movq %rbx, %rdi
call _Z5printPfiiPKc
leaq .LC10(%rip), %rcx
movl 52(%rsp), %edx
movl 8(%rsp), %esi
movq %r14, %rdi
call _Z5printPfiiPKc
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z15MatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "RecMatMulTiled.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPfS_S_iii: # @_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z20MatrixMultiplicationPfS_S_iii # -- Begin function _Z20MatrixMultiplicationPfS_S_iii
.p2align 4, 0x90
.type _Z20MatrixMultiplicationPfS_S_iii,@function
_Z20MatrixMultiplicationPfS_S_iii: # @_Z20MatrixMultiplicationPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movl %ecx, %r12d
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdi, %rbx
leal (,%r12,4), %r13d
movl %r13d, %eax
imull %r8d, %eax
movl %r8d, 24(%rsp) # 4-byte Spill
movl %r8d, %ebp
imull %r9d, %ebp
shll $2, %ebp
imull %r9d, %r13d
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %ebp, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r13d, %r13
movq %rsp, %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leal 3(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $2, %eax
incl %eax
leal 3(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $2, %edi
incl %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 36(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movl %r15d, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20MatrixMultiplicationPfS_S_iii, .Lfunc_end1-_Z20MatrixMultiplicationPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z5printPfiiPKc # -- Begin function _Z5printPfiiPKc
.p2align 4, 0x90
.type _Z5printPfiiPKc,@function
_Z5printPfiiPKc: # @_Z5printPfiiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movq %rcx, %rsi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r15d, %eax
cltd
idivl %ebx
testl %edx, %edx
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z5printPfiiPKc, .Lfunc_end2-_Z5printPfiiPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 36(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 36(%rsp), %eax
movl 8(%rsp), %ecx
movl %ecx, %r15d
imull %eax, %r15d
movl 4(%rsp), %ebp
movl %ebp, %r12d
movl %ecx, 16(%rsp) # 4-byte Spill
imull %ecx, %r12d
movl %ebp, 12(%rsp) # 4-byte Spill
movl %eax, 20(%rsp) # 4-byte Spill
imull %eax, %ebp
movslq %r15d, %r13
leaq (,%r13,4), %rdi
callq malloc
movq %rax, %rbx
movslq %r12d, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movslq %ebp, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movl %r15d, 24(%rsp) # 4-byte Spill
movl %r15d, %r15d
testl %r13d, %r13d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_2
.LBB3_3: # %.preheader55
movl %r12d, %r13d
movl %r12d, 28(%rsp) # 4-byte Spill
testl %r12d, %r12d
jle .LBB3_6
# %bb.4: # %.lr.ph58.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_5: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq %rcx, %r13
jne .LBB3_5
.LBB3_6: # %.preheader
movl %ebp, %r12d
movl %ebp, 32(%rsp) # 4-byte Spill
testl %ebp, %ebp
movq 40(%rsp), %rbp # 8-byte Reload
jle .LBB3_8
# %bb.7: # %.lr.ph60.preheader
leaq (,%r12,4), %rdx
movq %rbp, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB3_8: # %._crit_edge
movq %r12, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl 20(%rsp), %ecx # 4-byte Reload
movl 16(%rsp), %r8d # 4-byte Reload
movl 12(%rsp), %r9d # 4-byte Reload
callq _Z20MatrixMultiplicationPfS_S_iii
movl 8(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
cmpl $0, 24(%rsp) # 4-byte Folded Reload
jle .LBB3_13
# %bb.9: # %.lr.ph.preheader.i
xorl %r12d, %r12d
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_10 Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r15
je .LBB3_13
.LBB3_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_12
.LBB3_13: # %_Z5printPfiiPKc.exit
movl $10, %edi
callq putchar@PLT
movl 4(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
cmpl $0, 28(%rsp) # 4-byte Folded Reload
movq 40(%rsp), %r15 # 8-byte Reload
jle .LBB3_18
# %bb.14: # %.lr.ph.preheader.i38
xorl %r12d, %r12d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
je .LBB3_18
.LBB3_15: # %.lr.ph.i40
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_17
.LBB3_18: # %_Z5printPfiiPKc.exit45
movl $10, %edi
callq putchar@PLT
movl 4(%rsp), %ebp
movl $.L.str, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
cmpl $0, 32(%rsp) # 4-byte Folded Reload
movq 48(%rsp), %r13 # 8-byte Reload
jle .LBB3_23
# %bb.19: # %.lr.ph.preheader.i47
xorl %r12d, %r12d
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_20 Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
je .LBB3_23
.LBB3_20: # %.lr.ph.i49
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB3_22
# %bb.21: # in Loop: Header=BB3_20 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_22
.LBB3_23: # %_Z5printPfiiPKc.exit54
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_iii,@object # @_Z15MatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_iii
.size _Z15MatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s:\n"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %10.2f"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter rows(j) for matrix m: "
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter columns(k) for matrix m and rows(k) for matrix n: "
.size .L.str.5, 57
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter columns(l) for matrix n: "
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "M"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "N"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P"
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} | code for sm_80
Function : _Z14kernel_computePiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xc00 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0100*/ @!P0 BRA 0xab0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R9, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006097a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD R2, R0, 0x310, RZ ; /* 0x0000031000027824 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007f3e0ff */
/*01a0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*01b0*/ @!P0 BRA 0x930 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x680 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c04040f7981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R17, [R4.64+0x10] ; /* 0x0000100404117981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R19, [R4.64+0x18] ; /* 0x0000180404137981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0404087981 */
/* 0x000f62000c1e1900 */
/*0300*/ IADD3 R13, -R13, R20, RZ ; /* 0x000000140d0d7210 */
/* 0x004fca0007ffe1ff */
/*0310*/ IMAD R20, R13, R13, R10 ; /* 0x0000000d0d147224 */
/* 0x000fe400078e020a */
/*0320*/ LDG.E R13, [R2.64+0x18] ; /* 0x00001804020d7981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.IADD R23, R23, 0x1, -R22 ; /* 0x0000000117177824 */
/* 0x008fc600078e0a16 */
/*0340*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x0002a2000c1e1900 */
/*0350*/ IMAD R20, R23, R23, R20 ; /* 0x0000001717147224 */
/* 0x000fe200078e0214 */
/*0360*/ IADD3 R25, -R24, R25, RZ ; /* 0x0000001918197210 */
/* 0x010fca0007ffe1ff */
/*0370*/ IMAD R20, R25, R25, R20 ; /* 0x0000001919147224 */
/* 0x000fe400078e0214 */
/*0380*/ IMAD.IADD R23, R15, 0x1, -R12 ; /* 0x000000010f177824 */
/* 0x020fe400078e0a0c */
/*0390*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x0000e8000c1e1900 */
/*03a0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ IADD3 R25, -R14, R17, RZ ; /* 0x000000110e197210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD R20, R23, R23, R20 ; /* 0x0000001717147224 */
/* 0x000fc400078e0214 */
/*03d0*/ LDG.E R17, [R2.64+0x20] ; /* 0x0000200402117981 */
/* 0x000128000c1e1900 */
/*03e0*/ LDG.E R14, [R4.64+0x28] ; /* 0x00002804040e7981 */
/* 0x000322000c1e1900 */
/*03f0*/ IMAD R25, R25, R25, R20 ; /* 0x0000001919197224 */
/* 0x000fe400078e0214 */
/*0400*/ IMAD.IADD R22, R21, 0x1, -R18 ; /* 0x0000000115167824 */
/* 0x000fe200078e0a12 */
/*0410*/ LDG.E R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x000362000c1e1900 */
/*0440*/ IMAD R25, R22, R22, R25 ; /* 0x0000001616197224 */
/* 0x000fe200078e0219 */
/*0450*/ IADD3 R22, -R16, R19, RZ ; /* 0x0000001310167210 */
/* 0x000fc40007ffe1ff */
/*0460*/ LDG.E R23, [R4.64+0x30] ; /* 0x0000300404177981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.IADD R27, R8, 0x1, -R11 ; /* 0x00000001081b7824 */
/* 0x000fc600078e0a0b */
/*0480*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0402137981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD R24, R22, R22, R25 ; /* 0x0000001616187224 */
/* 0x000fc600078e0219 */
/*04a0*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R22, [R2.64+0x30] ; /* 0x0000300402167981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R25, [R2.64+0x34] ; /* 0x0000340402197981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0404087981 */
/* 0x000362000c1e1900 */
/*04f0*/ IMAD R24, R27, R27, R24 ; /* 0x0000001b1b187224 */
/* 0x000fe200078e0218 */
/*0500*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0520*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f5e0ff */
/*0530*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x002fe40007f7e0ff */
/*0540*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0550*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0570*/ IADD3 R13, -R13, R10, RZ ; /* 0x0000000a0d0d7210 */
/* 0x004fca0007ffe1ff */
/*0580*/ IMAD R24, R13, R13, R24 ; /* 0x0000000d0d187224 */
/* 0x000fe400078e0218 */
/*0590*/ IMAD.IADD R15, R12, 0x1, -R15 ; /* 0x000000010c0f7824 */
/* 0x008fc800078e0a0f */
/*05a0*/ IMAD R24, R15, R15, R24 ; /* 0x0000000f0f187224 */
/* 0x000fe200078e0218 */
/*05b0*/ IADD3 R17, -R17, R14, RZ ; /* 0x0000000e11117210 */
/* 0x010fca0007ffe1ff */
/*05c0*/ IMAD R24, R17, R17, R24 ; /* 0x0000001111187224 */
/* 0x000fe400078e0218 */
/*05d0*/ IMAD.IADD R21, R21, 0x1, -R18 ; /* 0x0000000115157824 */
/* 0x020fe200078e0a12 */
/*05e0*/ IADD3 R23, -R20, R23, RZ ; /* 0x0000001714177210 */
/* 0x000fc60007ffe1ff */
/*05f0*/ IMAD R24, R21, R21, R24 ; /* 0x0000001515187224 */
/* 0x000fc800078e0218 */
/*0600*/ IMAD R24, R23, R23, R24 ; /* 0x0000001717187224 */
/* 0x000fe400078e0218 */
/*0610*/ IMAD.IADD R19, R16, 0x1, -R19 ; /* 0x0000000110137824 */
/* 0x000fc800078e0a13 */
/*0620*/ IMAD R24, R19, R19, R24 ; /* 0x0000001313187224 */
/* 0x000fe200078e0218 */
/*0630*/ IADD3 R11, -R22, R11, RZ ; /* 0x0000000b160b7210 */
/* 0x000fca0007ffe1ff */
/*0640*/ IMAD R24, R11, R11, R24 ; /* 0x0000000b0b187224 */
/* 0x000fe400078e0218 */
/*0650*/ IMAD.IADD R25, R8, 0x1, -R25 ; /* 0x0000000108197824 */
/* 0x000fc800078e0a19 */
/*0660*/ IMAD R10, R25, R25, R24 ; /* 0x00000019190a7224 */
/* 0x000fe200078e0218 */
/*0670*/ @P1 BRA 0x200 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x910 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06a0*/ LDG.E R20, [R2.64+-0x8] ; /* 0xfffff80402147981 */
/* 0x0000a8000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x0002a8000c1e1900 */
/*06c0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */
/* 0x0000e8000c1e1900 */
/*06d0*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x0002e8000c1e1900 */
/*06e0*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000128000c1e1900 */
/*06f0*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000328000c1e1900 */
/*0700*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000168000c1e1900 */
/*0710*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000368000c1e1900 */
/*0720*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000168000c1e1900 */
/*0730*/ LDG.E R14, [R4.64+0x10] ; /* 0x00001004040e7981 */
/* 0x000368000c1e1900 */
/*0740*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000168000c1e1900 */
/*0750*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x000368000c1e1900 */
/*0760*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*0770*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000168000c1e1900 */
/*0790*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c04040b7981 */
/* 0x000362000c1e1900 */
/*07a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*07b0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe40007f3e0ff */
/*07e0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x002fe40007f5e0ff */
/*07f0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0800*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0810*/ IADD3 R21, -R20, R21, RZ ; /* 0x0000001514157210 */
/* 0x004fca0007ffe1ff */
/*0820*/ IMAD R10, R21, R21, R10 ; /* 0x00000015150a7224 */
/* 0x000fe400078e020a */
/*0830*/ IMAD.IADD R23, R23, 0x1, -R22 ; /* 0x0000000117177824 */
/* 0x008fc800078e0a16 */
/*0840*/ IMAD R10, R23, R23, R10 ; /* 0x00000017170a7224 */
/* 0x000fe200078e020a */
/*0850*/ IADD3 R25, -R24, R25, RZ ; /* 0x0000001918197210 */
/* 0x010fca0007ffe1ff */
/*0860*/ IMAD R10, R25, R25, R10 ; /* 0x00000019190a7224 */
/* 0x000fe400078e020a */
/*0870*/ IMAD.IADD R17, R17, 0x1, -R18 ; /* 0x0000000111117824 */
/* 0x020fc800078e0a12 */
/*0880*/ IMAD R10, R17, R17, R10 ; /* 0x00000011110a7224 */
/* 0x000fe200078e020a */
/*0890*/ IADD3 R19, -R19, R14, RZ ; /* 0x0000000e13137210 */
/* 0x000fca0007ffe1ff */
/*08a0*/ IMAD R10, R19, R19, R10 ; /* 0x00000013130a7224 */
/* 0x000fe400078e020a */
/*08b0*/ IMAD.IADD R13, R13, 0x1, -R16 ; /* 0x000000010d0d7824 */
/* 0x000fc800078e0a10 */
/*08c0*/ IMAD R10, R13, R13, R10 ; /* 0x0000000d0d0a7224 */
/* 0x000fe200078e020a */
/*08d0*/ IADD3 R15, -R15, R8, RZ ; /* 0x000000080f0f7210 */
/* 0x000fca0007ffe1ff */
/*08e0*/ IMAD R10, R15, R15, R10 ; /* 0x0000000f0f0a7224 */
/* 0x000fe400078e020a */
/*08f0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x000fc800078e0a0c */
/*0900*/ IMAD R10, R11, R11, R10 ; /* 0x0000000b0b0a7224 */
/* 0x000fe400078e020a */
/*0910*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xab0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x0000a8000c1e1900 */
/*0940*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x0002a8000c1e1900 */
/*0950*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x0000e8000c1e1900 */
/*0960*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0002e8000c1e1900 */
/*0970*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*0980*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000328000c1e1900 */
/*0990*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000168000c1e1900 */
/*09a0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000362000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc40007ffe0ff */
/*09c0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fe40007f3e0ff */
/*09f0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x002fe40007f5e0ff */
/*0a00*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0a10*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0a20*/ IADD3 R11, -R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x004fca0007ffe1ff */
/*0a30*/ IMAD R10, R11, R11, R10 ; /* 0x0000000b0b0a7224 */
/* 0x000fe400078e020a */
/*0a40*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x008fc800078e0a0c */
/*0a50*/ IMAD R10, R13, R13, R10 ; /* 0x0000000d0d0a7224 */
/* 0x000fe200078e020a */
/*0a60*/ IADD3 R15, -R14, R15, RZ ; /* 0x0000000f0e0f7210 */
/* 0x010fca0007ffe1ff */
/*0a70*/ IMAD R10, R15, R15, R10 ; /* 0x0000000f0f0a7224 */
/* 0x000fe400078e020a */
/*0a80*/ IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x0000000111117824 */
/* 0x020fc800078e0a10 */
/*0a90*/ IMAD R10, R17, R17, R10 ; /* 0x00000011110a7224 */
/* 0x000fe200078e020a */
/*0aa0*/ @P0 BRA 0x930 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0ac0*/ @!P0 BRA 0xc00 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0ae0*/ IMAD R2, R0, 0x310, R7 ; /* 0x0000031000027824 */
/* 0x000fd200078e0207 */
/*0af0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0204 */
/*0b00*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0204 */
/*0b10*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0b20*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc60000000f00 */
/*0b30*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0b40*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fca0000000f00 */
/*0b50*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0b60*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0ba0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe200008e0603 */
/*0bb0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fc80007f5e0ff */
/*0bc0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0bd0*/ IADD3 R7, -R2, R5, RZ ; /* 0x0000000502077210 */
/* 0x004fca0007ffe1ff */
/*0be0*/ IMAD R10, R7, R7, R10 ; /* 0x00000007070a7224 */
/* 0x000fe200078e020a */
/*0bf0*/ @P0 BRA 0xb30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} | .file "tmpxft_000d0681_00000000-6_kernel_compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
.type _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii, @function
_Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernel_computePiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii, .-_Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
.globl _Z14kernel_computePiS_S_ii
.type _Z14kernel_computePiS_S_ii, @function
_Z14kernel_computePiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kernel_computePiS_S_ii, .-_Z14kernel_computePiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernel_computePiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_computePiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_computePiS_S_ii
.globl _Z14kernel_computePiS_S_ii
.p2align 8
.type _Z14kernel_computePiS_S_ii,@function
_Z14kernel_computePiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, 0x310
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s3, s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v6, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, v6, v[0:1]
v_mov_b32_e32 v0, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_computePiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_computePiS_S_ii, .Lfunc_end0-_Z14kernel_computePiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_computePiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_computePiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void kernel_compute(int* trainingSet, int* data, int* res, int setSize, int dataSize){
int diff, toAdd, computeId;
computeId = blockIdx.x * blockDim.x + threadIdx.x;
//__shared__ int set[784];
if(computeId < setSize){
diff = 0;
for(int i = 0; i < dataSize; i++){
toAdd = data[i] - trainingSet[computeId*784 + i];
diff += toAdd * toAdd;
}
res[computeId] = diff;
}
} | .text
.file "kernel_compute.hip"
.globl _Z29__device_stub__kernel_computePiS_S_ii # -- Begin function _Z29__device_stub__kernel_computePiS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__kernel_computePiS_S_ii,@function
_Z29__device_stub__kernel_computePiS_S_ii: # @_Z29__device_stub__kernel_computePiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernel_computePiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_computePiS_S_ii, .Lfunc_end0-_Z29__device_stub__kernel_computePiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_computePiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_computePiS_S_ii,@object # @_Z14kernel_computePiS_S_ii
.section .rodata,"a",@progbits
.globl _Z14kernel_computePiS_S_ii
.p2align 3, 0x0
_Z14kernel_computePiS_S_ii:
.quad _Z29__device_stub__kernel_computePiS_S_ii
.size _Z14kernel_computePiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14kernel_computePiS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_computePiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_computePiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14kernel_computePiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xc00 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0100*/ @!P0 BRA 0xab0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R9, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006097a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD R2, R0, 0x310, RZ ; /* 0x0000031000027824 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007f3e0ff */
/*01a0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*01b0*/ @!P0 BRA 0x930 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x680 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c04040f7981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R17, [R4.64+0x10] ; /* 0x0000100404117981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R19, [R4.64+0x18] ; /* 0x0000180404137981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0404087981 */
/* 0x000f62000c1e1900 */
/*0300*/ IADD3 R13, -R13, R20, RZ ; /* 0x000000140d0d7210 */
/* 0x004fca0007ffe1ff */
/*0310*/ IMAD R20, R13, R13, R10 ; /* 0x0000000d0d147224 */
/* 0x000fe400078e020a */
/*0320*/ LDG.E R13, [R2.64+0x18] ; /* 0x00001804020d7981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.IADD R23, R23, 0x1, -R22 ; /* 0x0000000117177824 */
/* 0x008fc600078e0a16 */
/*0340*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x0002a2000c1e1900 */
/*0350*/ IMAD R20, R23, R23, R20 ; /* 0x0000001717147224 */
/* 0x000fe200078e0214 */
/*0360*/ IADD3 R25, -R24, R25, RZ ; /* 0x0000001918197210 */
/* 0x010fca0007ffe1ff */
/*0370*/ IMAD R20, R25, R25, R20 ; /* 0x0000001919147224 */
/* 0x000fe400078e0214 */
/*0380*/ IMAD.IADD R23, R15, 0x1, -R12 ; /* 0x000000010f177824 */
/* 0x020fe400078e0a0c */
/*0390*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x0000e8000c1e1900 */
/*03a0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ IADD3 R25, -R14, R17, RZ ; /* 0x000000110e197210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD R20, R23, R23, R20 ; /* 0x0000001717147224 */
/* 0x000fc400078e0214 */
/*03d0*/ LDG.E R17, [R2.64+0x20] ; /* 0x0000200402117981 */
/* 0x000128000c1e1900 */
/*03e0*/ LDG.E R14, [R4.64+0x28] ; /* 0x00002804040e7981 */
/* 0x000322000c1e1900 */
/*03f0*/ IMAD R25, R25, R25, R20 ; /* 0x0000001919197224 */
/* 0x000fe400078e0214 */
/*0400*/ IMAD.IADD R22, R21, 0x1, -R18 ; /* 0x0000000115167824 */
/* 0x000fe200078e0a12 */
/*0410*/ LDG.E R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x000362000c1e1900 */
/*0440*/ IMAD R25, R22, R22, R25 ; /* 0x0000001616197224 */
/* 0x000fe200078e0219 */
/*0450*/ IADD3 R22, -R16, R19, RZ ; /* 0x0000001310167210 */
/* 0x000fc40007ffe1ff */
/*0460*/ LDG.E R23, [R4.64+0x30] ; /* 0x0000300404177981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.IADD R27, R8, 0x1, -R11 ; /* 0x00000001081b7824 */
/* 0x000fc600078e0a0b */
/*0480*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0402137981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD R24, R22, R22, R25 ; /* 0x0000001616187224 */
/* 0x000fc600078e0219 */
/*04a0*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R22, [R2.64+0x30] ; /* 0x0000300402167981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R25, [R2.64+0x34] ; /* 0x0000340402197981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0404087981 */
/* 0x000362000c1e1900 */
/*04f0*/ IMAD R24, R27, R27, R24 ; /* 0x0000001b1b187224 */
/* 0x000fe200078e0218 */
/*0500*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0520*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f5e0ff */
/*0530*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x002fe40007f7e0ff */
/*0540*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0550*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0570*/ IADD3 R13, -R13, R10, RZ ; /* 0x0000000a0d0d7210 */
/* 0x004fca0007ffe1ff */
/*0580*/ IMAD R24, R13, R13, R24 ; /* 0x0000000d0d187224 */
/* 0x000fe400078e0218 */
/*0590*/ IMAD.IADD R15, R12, 0x1, -R15 ; /* 0x000000010c0f7824 */
/* 0x008fc800078e0a0f */
/*05a0*/ IMAD R24, R15, R15, R24 ; /* 0x0000000f0f187224 */
/* 0x000fe200078e0218 */
/*05b0*/ IADD3 R17, -R17, R14, RZ ; /* 0x0000000e11117210 */
/* 0x010fca0007ffe1ff */
/*05c0*/ IMAD R24, R17, R17, R24 ; /* 0x0000001111187224 */
/* 0x000fe400078e0218 */
/*05d0*/ IMAD.IADD R21, R21, 0x1, -R18 ; /* 0x0000000115157824 */
/* 0x020fe200078e0a12 */
/*05e0*/ IADD3 R23, -R20, R23, RZ ; /* 0x0000001714177210 */
/* 0x000fc60007ffe1ff */
/*05f0*/ IMAD R24, R21, R21, R24 ; /* 0x0000001515187224 */
/* 0x000fc800078e0218 */
/*0600*/ IMAD R24, R23, R23, R24 ; /* 0x0000001717187224 */
/* 0x000fe400078e0218 */
/*0610*/ IMAD.IADD R19, R16, 0x1, -R19 ; /* 0x0000000110137824 */
/* 0x000fc800078e0a13 */
/*0620*/ IMAD R24, R19, R19, R24 ; /* 0x0000001313187224 */
/* 0x000fe200078e0218 */
/*0630*/ IADD3 R11, -R22, R11, RZ ; /* 0x0000000b160b7210 */
/* 0x000fca0007ffe1ff */
/*0640*/ IMAD R24, R11, R11, R24 ; /* 0x0000000b0b187224 */
/* 0x000fe400078e0218 */
/*0650*/ IMAD.IADD R25, R8, 0x1, -R25 ; /* 0x0000000108197824 */
/* 0x000fc800078e0a19 */
/*0660*/ IMAD R10, R25, R25, R24 ; /* 0x00000019190a7224 */
/* 0x000fe200078e0218 */
/*0670*/ @P1 BRA 0x200 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x910 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06a0*/ LDG.E R20, [R2.64+-0x8] ; /* 0xfffff80402147981 */
/* 0x0000a8000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x0002a8000c1e1900 */
/*06c0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */
/* 0x0000e8000c1e1900 */
/*06d0*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x0002e8000c1e1900 */
/*06e0*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000128000c1e1900 */
/*06f0*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000328000c1e1900 */
/*0700*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000168000c1e1900 */
/*0710*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000368000c1e1900 */
/*0720*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000168000c1e1900 */
/*0730*/ LDG.E R14, [R4.64+0x10] ; /* 0x00001004040e7981 */
/* 0x000368000c1e1900 */
/*0740*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000168000c1e1900 */
/*0750*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x000368000c1e1900 */
/*0760*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*0770*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000168000c1e1900 */
/*0790*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c04040b7981 */
/* 0x000362000c1e1900 */
/*07a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*07b0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe40007f3e0ff */
/*07e0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x002fe40007f5e0ff */
/*07f0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0800*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0810*/ IADD3 R21, -R20, R21, RZ ; /* 0x0000001514157210 */
/* 0x004fca0007ffe1ff */
/*0820*/ IMAD R10, R21, R21, R10 ; /* 0x00000015150a7224 */
/* 0x000fe400078e020a */
/*0830*/ IMAD.IADD R23, R23, 0x1, -R22 ; /* 0x0000000117177824 */
/* 0x008fc800078e0a16 */
/*0840*/ IMAD R10, R23, R23, R10 ; /* 0x00000017170a7224 */
/* 0x000fe200078e020a */
/*0850*/ IADD3 R25, -R24, R25, RZ ; /* 0x0000001918197210 */
/* 0x010fca0007ffe1ff */
/*0860*/ IMAD R10, R25, R25, R10 ; /* 0x00000019190a7224 */
/* 0x000fe400078e020a */
/*0870*/ IMAD.IADD R17, R17, 0x1, -R18 ; /* 0x0000000111117824 */
/* 0x020fc800078e0a12 */
/*0880*/ IMAD R10, R17, R17, R10 ; /* 0x00000011110a7224 */
/* 0x000fe200078e020a */
/*0890*/ IADD3 R19, -R19, R14, RZ ; /* 0x0000000e13137210 */
/* 0x000fca0007ffe1ff */
/*08a0*/ IMAD R10, R19, R19, R10 ; /* 0x00000013130a7224 */
/* 0x000fe400078e020a */
/*08b0*/ IMAD.IADD R13, R13, 0x1, -R16 ; /* 0x000000010d0d7824 */
/* 0x000fc800078e0a10 */
/*08c0*/ IMAD R10, R13, R13, R10 ; /* 0x0000000d0d0a7224 */
/* 0x000fe200078e020a */
/*08d0*/ IADD3 R15, -R15, R8, RZ ; /* 0x000000080f0f7210 */
/* 0x000fca0007ffe1ff */
/*08e0*/ IMAD R10, R15, R15, R10 ; /* 0x0000000f0f0a7224 */
/* 0x000fe400078e020a */
/*08f0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x000fc800078e0a0c */
/*0900*/ IMAD R10, R11, R11, R10 ; /* 0x0000000b0b0a7224 */
/* 0x000fe400078e020a */
/*0910*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xab0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x0000a8000c1e1900 */
/*0940*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x0002a8000c1e1900 */
/*0950*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x0000e8000c1e1900 */
/*0960*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0002e8000c1e1900 */
/*0970*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*0980*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000328000c1e1900 */
/*0990*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000168000c1e1900 */
/*09a0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000362000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc40007ffe0ff */
/*09c0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fe40007f3e0ff */
/*09f0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x002fe40007f5e0ff */
/*0a00*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0a10*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0a20*/ IADD3 R11, -R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x004fca0007ffe1ff */
/*0a30*/ IMAD R10, R11, R11, R10 ; /* 0x0000000b0b0a7224 */
/* 0x000fe400078e020a */
/*0a40*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x008fc800078e0a0c */
/*0a50*/ IMAD R10, R13, R13, R10 ; /* 0x0000000d0d0a7224 */
/* 0x000fe200078e020a */
/*0a60*/ IADD3 R15, -R14, R15, RZ ; /* 0x0000000f0e0f7210 */
/* 0x010fca0007ffe1ff */
/*0a70*/ IMAD R10, R15, R15, R10 ; /* 0x0000000f0f0a7224 */
/* 0x000fe400078e020a */
/*0a80*/ IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x0000000111117824 */
/* 0x020fc800078e0a10 */
/*0a90*/ IMAD R10, R17, R17, R10 ; /* 0x00000011110a7224 */
/* 0x000fe200078e020a */
/*0aa0*/ @P0 BRA 0x930 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0ac0*/ @!P0 BRA 0xc00 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0ae0*/ IMAD R2, R0, 0x310, R7 ; /* 0x0000031000027824 */
/* 0x000fd200078e0207 */
/*0af0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0204 */
/*0b00*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0204 */
/*0b10*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0b20*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc60000000f00 */
/*0b30*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0b40*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fca0000000f00 */
/*0b50*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0b60*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0ba0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe200008e0603 */
/*0bb0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fc80007f5e0ff */
/*0bc0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0bd0*/ IADD3 R7, -R2, R5, RZ ; /* 0x0000000502077210 */
/* 0x004fca0007ffe1ff */
/*0be0*/ IMAD R10, R7, R7, R10 ; /* 0x00000007070a7224 */
/* 0x000fe200078e020a */
/*0bf0*/ @P0 BRA 0xb30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_computePiS_S_ii
.globl _Z14kernel_computePiS_S_ii
.p2align 8
.type _Z14kernel_computePiS_S_ii,@function
_Z14kernel_computePiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, 0x310
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s3, s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v6, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, v6, v[0:1]
v_mov_b32_e32 v0, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_computePiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_computePiS_S_ii, .Lfunc_end0-_Z14kernel_computePiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_computePiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_computePiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d0681_00000000-6_kernel_compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
.type _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii, @function
_Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernel_computePiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii, .-_Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
.globl _Z14kernel_computePiS_S_ii
.type _Z14kernel_computePiS_S_ii, @function
_Z14kernel_computePiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14kernel_computePiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kernel_computePiS_S_ii, .-_Z14kernel_computePiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernel_computePiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_computePiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_compute.hip"
.globl _Z29__device_stub__kernel_computePiS_S_ii # -- Begin function _Z29__device_stub__kernel_computePiS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__kernel_computePiS_S_ii,@function
_Z29__device_stub__kernel_computePiS_S_ii: # @_Z29__device_stub__kernel_computePiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernel_computePiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_computePiS_S_ii, .Lfunc_end0-_Z29__device_stub__kernel_computePiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_computePiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_computePiS_S_ii,@object # @_Z14kernel_computePiS_S_ii
.section .rodata,"a",@progbits
.globl _Z14kernel_computePiS_S_ii
.p2align 3, 0x0
_Z14kernel_computePiS_S_ii:
.quad _Z29__device_stub__kernel_computePiS_S_ii
.size _Z14kernel_computePiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14kernel_computePiS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_computePiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_computePiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} | .file "tmpxft_000f5539_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C,int nums)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
//C[i] = A[i] + B[i];
if(i<nums){
//C[i]=A[i]+B[i];
C[i]=static_cast<float>(i);
}
} | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5539_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
cudaDeviceProp dev_prop;
cudaGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
cudaMalloc((void**)&d_A, size*sizeof(float));
cudaMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), cudaMemcpyHostToDevice);
float* d_B;
cudaMalloc((void**)&d_B, size*sizeof(float));
cudaMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), cudaMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
cudaMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
cudaMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), cudaMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} | code for sm_80
Function : _Z11matMulTiledPfPKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e220000201400 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe400000001ff */
/*0050*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e680000002100 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000ea20000002200 */
/*0080*/ FMUL R2, R0, 0.0625 ; /* 0x3d80000000027820 */
/* 0x001fcc0000400000 */
/*0090*/ FRND.CEIL R2, R2 ; /* 0x0000000200027307 */
/* 0x000e220000209000 */
/*00a0*/ LEA R3, R4, R17, 0x4 ; /* 0x0000001104037211 */
/* 0x002fc800078e20ff */
/*00b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*00c0*/ LEA R0, R5, R16, 0x4 ; /* 0x0000001005007211 */
/* 0x004fe400078e20ff */
/*00d0*/ FSETP.GT.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x001fe40003f24000 */
/*00e0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fd60000706670 */
/*00f0*/ @!P1 BRA 0x4f0 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R18, R16, 0x6, RZ ; /* 0x0000000610127819 */
/* 0x000fe400000006ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0130*/ LEA R20, R17, R18, 0x2 ; /* 0x0000001211147211 */
/* 0x000fe400078e10ff */
/*0140*/ LEA R7, R19.reuse, R17, 0x4 ; /* 0x0000001113077211 */
/* 0x040fe400078e20ff */
/*0150*/ LEA R6, R19, R16, 0x4 ; /* 0x0000001013067211 */
/* 0x000fe400078e20ff */
/*0160*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc40003f26270 */
/*0170*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f46270 */
/*0180*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; /* 0x00005e0000007a0c */
/* 0x000fe40000f26670 */
/*0190*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*01a0*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe20000000f00 */
/*01b0*/ @!P1 IMAD R4, R0, c[0x0][0x178], R7 ; /* 0x00005e0000049a24 */
/* 0x000fe200078e0207 */
/*01c0*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fe20000000f00 */
/*01d0*/ @!P2 IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e000606aa24 */
/* 0x000fe400078e0203 */
/*01e0*/ @!P1 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004049625 */
/* 0x000fc800078e0205 */
/*01f0*/ @!P2 IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c000606a625 */
/* 0x000fe200078e0207 */
/*0200*/ @!P1 LDG.E R11, [R4.64] ; /* 0x00000004040b9981 */
/* 0x000ea8000c1e1900 */
/*0210*/ @!P2 LDG.E R21, [R6.64] ; /* 0x000000040615a981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fc60007ffe0ff */
/*0230*/ @!P1 STS [R20], R11 ; /* 0x0000000b14009388 */
/* 0x0041e40000000800 */
/*0240*/ @!P2 LEA R20, R17, R18, 0x2 ; /* 0x000000121114a211 */
/* 0x001fca00078e10ff */
/*0250*/ @!P2 STS [R20+0x400], R21 ; /* 0x000400151400a388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R8, [R17.X4+0x400] ; /* 0x0004000011087984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R12, [R18] ; /* 0x00000000120c7984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R10, [R17.X4+0x440] ; /* 0x00044000110a7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R27, [R17.X4+0x480] ; /* 0x00048000111b7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R24, [R17.X4+0x4c0] ; /* 0x0004c00011187984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R25, [R17.X4+0x500] ; /* 0x0005000011197984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R4, [R18+0x10] ; /* 0x0000100012047984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R26, [R17.X4+0x540] ; /* 0x00054000111a7984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R23, [R17.X4+0x580] ; /* 0x0005800011177984 */
/* 0x000f680000004800 */
/*0300*/ LDS R22, [R17.X4+0x5c0] ; /* 0x0005c00011167984 */
/* 0x000f680000004800 */
/*0310*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000fe20000004800 */
/*0320*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*0330*/ FFMA R13, R10, R13, R8 ; /* 0x0000000d0a0d7223 */
/* 0x002fe40000000008 */
/*0340*/ LDS.128 R8, [R18+0x20] ; /* 0x0000200012087984 */
/* 0x000e240000000c00 */
/*0350*/ FFMA R13, R27, R14, R13 ; /* 0x0000000e1b0d7223 */
/* 0x004fc8000000000d */
/*0360*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x008fe4000000000d */
/*0370*/ LDS R24, [R17.X4+0x640] ; /* 0x0006400011187984 */
/* 0x000e640000004800 */
/*0380*/ FFMA R4, R25, R4, R13 ; /* 0x0000000419047223 */
/* 0x010fe4000000000d */
/*0390*/ LDS R25, [R17.X4+0x680] ; /* 0x0006800011197984 */
/* 0x000ea40000004800 */
/*03a0*/ FFMA R5, R26, R5, R4 ; /* 0x000000051a057223 */
/* 0x020fe40000000004 */
/*03b0*/ LDS R4, [R17.X4+0x6c0] ; /* 0x0006c00011047984 */
/* 0x000ee40000004800 */
/*03c0*/ FFMA R23, R23, R6, R5 ; /* 0x0000000617177223 */
/* 0x000fc40000000005 */
/*03d0*/ LDS R5, [R17.X4+0x700] ; /* 0x0007000011057984 */
/* 0x000fe40000004800 */
/*03e0*/ FFMA R23, R22, R7, R23 ; /* 0x0000000716177223 */
/* 0x000fe40000000017 */
/*03f0*/ LDS.128 R12, [R18+0x30] ; /* 0x00003000120c7984 */
/* 0x000f280000000c00 */
/*0400*/ LDS R6, [R17.X4+0x740] ; /* 0x0007400011067984 */
/* 0x000f680000004800 */
/*0410*/ LDS R7, [R17.X4+0x780] ; /* 0x0007800011077984 */
/* 0x000f680000004800 */
/*0420*/ LDS R22, [R17.X4+0x7c0] ; /* 0x0007c00011167984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R8, R21, R8, R23 ; /* 0x0000000815087223 */
/* 0x001fc80000000017 */
/*0440*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fe40000000008 */
/*0450*/ I2F R9, R19 ; /* 0x0000001300097306 */
/* 0x000e240000201400 */
/*0460*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x004fc80000000008 */
/*0470*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fe20000000008 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0490*/ FSETP.GT.AND P1, PT, R2, R9, PT ; /* 0x000000090200720b */
/* 0x001fe40003f24000 */
/*04a0*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fc80000000004 */
/*04b0*/ FFMA R4, R6, R13, R4 ; /* 0x0000000d06047223 */
/* 0x020fc80000000004 */
/*04c0*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*04d0*/ FFMA R9, R22, R15, R4 ; /* 0x0000000f16097223 */
/* 0x000fe20000000004 */
/*04e0*/ @P1 BRA 0x140 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*04f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0510*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fd200078e0203 */
/*0520*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0530*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6matMulPfPKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x170] ; /* 0x00005c0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
cudaDeviceProp dev_prop;
cudaGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
cudaMalloc((void**)&d_A, size*sizeof(float));
cudaMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), cudaMemcpyHostToDevice);
float* d_B;
cudaMalloc((void**)&d_B, size*sizeof(float));
cudaMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), cudaMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
cudaMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
cudaMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), cudaMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} | .file "tmpxft_0001b0f3_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i
.type _Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i, @function
_Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matMulPfPKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i, .-_Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i
.globl _Z6matMulPfPKfS1_i
.type _Z6matMulPfPKfS1_i, @function
_Z6matMulPfPKfS1_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matMulPfPKfS1_i, .-_Z6matMulPfPKfS1_i
.globl _Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i
.type _Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i, @function
_Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matMulTiledPfPKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i, .-_Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i
.globl _Z11matMulTiledPfPKfS1_i
.type _Z11matMulTiledPfPKfS1_i, @function
_Z11matMulTiledPfPKfS1_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z11matMulTiledPfPKfS1_i, .-_Z11matMulTiledPfPKfS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---------------------------------------------"
.align 8
.LC1:
.string " GPU PROPERTIES "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Device Name: "
.LC3:
.string "Memory Clock Rate: "
.LC5:
.string " GHz"
.LC6:
.string "Memory Bandwidth: "
.LC7:
.string " GB/s"
.LC8:
.string "Number of SM: "
.LC9:
.string "Max Threads per SM: "
.LC10:
.string "Registers per Block: "
.LC11:
.string "Shared Memory per Block: "
.LC12:
.string " B"
.section .rodata.str1.8
.align 8
.LC13:
.string "Total Global Memory per Block: "
.section .rodata.str1.1
.LC15:
.string " GB"
.LC16:
.string "shared memory per block: "
.LC18:
.string "can run at most "
.LC20:
.string " blocks"
.LC25:
.string "invalid argument!"
.section .rodata.str1.8
.align 8
.LC28:
.string "ERROR: something is not right."
.section .rodata.str1.1
.LC29:
.string "Closing..."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC0(%rip), %r12
movq %r12, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 672(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 672(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 676(%rsp), %eax
leal 7(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $3, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
mulsd %xmm1, %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 452(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 688(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 368(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 360(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 352(%rsp), %rdx
testq %rdx, %rdx
js .L20
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L21:
divsd .LC14(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
movl %eax, %r13d
imull %eax, %r13d
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd .LC17(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 360(%rsp), %rdx
testq %rdx, %rdx
js .L22
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L23:
mulss .LC19(%rip), %xmm0
cvttss2sil %xmm0, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq %r13d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r12
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %rbp
testl %r13d, %r13d
jle .L24
movl $0, %eax
movss .LC21(%rip), %xmm0
.L25:
movss %xmm0, (%r12,%rax)
movl $0x00000000, 0(%rbp,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L25
movslq %r14d, %rax
leaq 4(,%rax,4), %rsi
movq %rbp, %rdx
movl $0, %eax
movss .LC23(%rip), %xmm0
movl 12(%rsp), %ecx
addl $1, %ecx
.L26:
movss %xmm0, (%rdx)
addl %ecx, %eax
addq %rsi, %rdx
cmpl %eax, %r13d
jg .L26
.L24:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1, %eax
je .L43
cmpl $2, %eax
je .L44
leaq .LC25(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L29:
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r14
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L32
movq %r14, %rax
addq %r14, %rbx
movss .LC21(%rip), %xmm2
movss .LC26(%rip), %xmm1
.L35:
movss (%rax), %xmm0
subss %xmm2, %xmm0
andps %xmm1, %xmm0
comiss .LC27(%rip), %xmm0
ja .L45
addq $4, %rax
cmpq %rbx, %rax
jne .L35
jmp .L32
.L20:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L21
.L22:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L23
.L43:
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC24(%rip), %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %rax
movl %eax, 40(%rsp)
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 52(%rsp)
movl $16, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 12(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z6matMulPfPKfS1_iPfPKfS1_i
jmp .L29
.L44:
movl $1, 48(%rsp)
shrl $4, %r14d
movl %r14d, 52(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 12(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z11matMulTiledPfPKfS1_iPfPKfS1_i
jmp .L29
.L45:
leaq .LC28(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L32:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
leaq .LC29(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC30:
.string "_Z11matMulTiledPfPKfS1_i"
.LC31:
.string "_Z6matMulPfPKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matMulTiledPfPKfS1_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPfPKfS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC14:
.long 0
.long 1104006501
.align 8
.LC17:
.long 0
.long 1084227584
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC19:
.long 973078528
.align 4
.LC21:
.long 1077936128
.align 4
.LC23:
.long 1065353216
.align 4
.LC24:
.long 1031798784
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC26:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC27:
.long 953267991
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
cudaDeviceProp dev_prop;
cudaGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
cudaMalloc((void**)&d_A, size*sizeof(float));
cudaMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), cudaMemcpyHostToDevice);
float* d_B;
cudaMalloc((void**)&d_B, size*sizeof(float));
cudaMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), cudaMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
cudaMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
cudaMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), cudaMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
hipMalloc((void**)&d_A, size*sizeof(float));
hipMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), hipMemcpyHostToDevice);
float* d_B;
hipMalloc((void**)&d_B, size*sizeof(float));
hipMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), hipMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
hipMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
hipMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), hipMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
hipMalloc((void**)&d_A, size*sizeof(float));
hipMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), hipMemcpyHostToDevice);
float* d_B;
hipMalloc((void**)&d_B, size*sizeof(float));
hipMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), hipMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
hipMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
hipMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), hipMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPfPKfS1_i
.globl _Z6matMulPfPKfS1_i
.p2align 8
.type _Z6matMulPfPKfS1_i,@function
_Z6matMulPfPKfS1_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPfPKfS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPfPKfS1_i, .Lfunc_end0-_Z6matMulPfPKfS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11matMulTiledPfPKfS1_i
.globl _Z11matMulTiledPfPKfS1_i
.p2align 8
.type _Z11matMulTiledPfPKfS1_i,@function
_Z11matMulTiledPfPKfS1_i:
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, s15, 4, v6
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v1, s8
v_mul_f32_e32 v1, 0x3d800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ceil_f32_e32 v5, v1
v_and_b32_e32 v1, 0x3ff, v0
v_cmp_nlt_f32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 4, v1
s_cbranch_vccnz .LBB1_9
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v9, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
v_mad_u64_u32 v[2:3], null, v4, s8, v[1:2]
v_cmp_gt_i32_e64 s2, s8, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v8, 0x400, v9
v_add_nc_u32_e32 v9, v7, v9
v_cmp_gt_i32_e64 s3, s8, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v10, v8, v7
.LBB1_2:
s_lshl_b32 s11, s9, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, s11, v1
v_cmp_gt_i32_e32 vcc_lo, s8, v11
s_and_b32 s12, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s12
s_cbranch_execz .LBB1_4
v_add_nc_u32_e32 v11, s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s10
v_lshl_add_u32 v11, s9, 4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s8, v11
s_and_b32 s11, vcc_lo, s3
s_and_saveexec_b32 s10, s11
s_cbranch_execz .LBB1_6
v_mad_u64_u32 v[12:13], null, v11, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v11, v8
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_7:
v_add_nc_u32_e32 v12, s10, v7
s_add_i32 s10, s10, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s10, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v12, v13
s_cbranch_scc0 .LBB1_7
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v11, s9
s_barrier
buffer_gl0_inv
v_cmp_ngt_f32_e32 vcc_lo, v5, v11
s_cbranch_vccz .LBB1_2
.LBB1_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v4, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v4, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matMulTiledPfPKfS1_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11matMulTiledPfPKfS1_i, .Lfunc_end1-_Z11matMulTiledPfPKfS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPfPKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPfPKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matMulTiledPfPKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matMulTiledPfPKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define TILE_WIDTH 16
/**
* C = A * B
*/
__global__
void matMul(float* C, const float* A, const float* B, int dim)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(col < dim && row < dim) {
float prod = 0.0f;
for(int i = 0; i < dim; i++)
prod += A[row*dim+i]*B[i*dim+col];
C[row*dim+col] = prod;
}
}
/**
* C = A * B (tiled)
*/
__global__
void matMulTiled(float* C, const float* A, const float* B, int dim)
{
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bs[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int tx = threadIdx.x;
int by = blockIdx.y; int ty = threadIdx.y;
int row = by*TILE_WIDTH + ty;
int col = bx*TILE_WIDTH + tx;
// Loop over the tiles required to compute the element
float prod = 0.0f;
for(int ph = 0; ph < ceil(dim/(float)TILE_WIDTH); ++ph) {
// 1. Load the tiles into shared memory
if((row < dim) && (ph*TILE_WIDTH + tx < dim))
As[ty][tx] = A[row*dim + ph*TILE_WIDTH + tx];
if((ph*TILE_WIDTH + ty < dim) && (col < dim))
Bs[ty][tx] = B[(ph*TILE_WIDTH + ty)*dim + col];
__syncthreads();
// 2. Dot product
for(int i = 0; i < TILE_WIDTH; ++i)
prod += As[ty][i]*Bs[i][tx];
__syncthreads();
}
// 3. Write result
if((row < dim) && (col < dim)) C[row*dim+col] = prod;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int dim = atoi(argv[1]);
int size = dim*dim;
float sharedMemPerBlock = 2*TILE_WIDTH*TILE_WIDTH*4;
cout << "shared memory per block: " << sharedMemPerBlock << " B" << endl;
cout << "can run at most " << int(dev_prop.sharedMemPerBlock/sharedMemPerBlock) << " blocks" << endl;
// creating matrices on host side
float* h_A = new float[size];
float* h_B = new float[size];
for (int i = 0; i < size; ++i) {
h_A[i] = 3.0f;
h_B[i] = 0.0f;
}
for (int i = 0; i < size; i+=dim+1)
h_B[i] = 1.0f;
// Copy matrices on device side
float* d_A;
hipMalloc((void**)&d_A, size*sizeof(float));
hipMemcpy((void*)d_A, (void*)h_A, size*sizeof(float), hipMemcpyHostToDevice);
float* d_B;
hipMalloc((void**)&d_B, size*sizeof(float));
hipMemcpy((void*)d_B, (void*)h_B, size*sizeof(float), hipMemcpyHostToDevice);
// Allocate C matrix on device
float* d_C;
hipMalloc((void**)&d_C, size*sizeof(float));
// call Kernel
int type = atoi(argv[2]);
if (type == 1) { // "regular" matrix multiplication
dim3 dimGrid(ceil(dim/16.0f), ceil(dim/16.0f), 1);
dim3 dimBlock(16, 16, 1);
matMul<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else if (type == 2) { // "tiled" matrix multiplication
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
dim3 dimGrid(ceil(dim/dimBlock.x), dim/dimBlock.y, 1);
matMulTiled<<<dimGrid, dimBlock>>> (d_C, d_A, d_B, dim);
}
else
cout << "invalid argument!" << endl;
// Recover C matrix from device to host
float* h_C = new float[size];
hipMemcpy((void*)h_C, (void*)d_C, size*sizeof(float), hipMemcpyDeviceToHost);
// Check results
for (int i = 0; i < size; ++i) {
if (fabs(h_C[i] - 3.0f) > 0.0001f) {
cout << "ERROR: something is not right." << endl;
break;
}
}
// Finalize storage
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
delete [] h_A;
delete [] h_B;
delete [] h_C;
cout << "Closing..." << endl;
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matMulPfPKfS1_i # -- Begin function _Z21__device_stub__matMulPfPKfS1_i
.p2align 4, 0x90
.type _Z21__device_stub__matMulPfPKfS1_i,@function
_Z21__device_stub__matMulPfPKfS1_i: # @_Z21__device_stub__matMulPfPKfS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matMulPfPKfS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPfPKfS1_i, .Lfunc_end0-_Z21__device_stub__matMulPfPKfS1_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__matMulTiledPfPKfS1_i # -- Begin function _Z26__device_stub__matMulTiledPfPKfS1_i
.p2align 4, 0x90
.type _Z26__device_stub__matMulTiledPfPKfS1_i,@function
_Z26__device_stub__matMulTiledPfPKfS1_i: # @_Z26__device_stub__matMulTiledPfPKfS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matMulTiledPfPKfS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub__matMulTiledPfPKfS1_i, .Lfunc_end1-_Z26__device_stub__matMulTiledPfPKfS1_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_4:
.quad 0x40a0000000000000 # double 2048
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.LCPI2_8:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_5:
.long 0x3a000000 # float 4.8828125E-4
.LCPI2_6:
.long 0x3d800000 # float 0.0625
.LCPI2_7:
.long 0xc0400000 # float -3
.LCPI2_9:
.long 0x38d1b717 # float 9.99999974E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1696
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB2_4
.LBB2_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit76
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB2_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB2_12
.LBB2_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 168(%rsp), %r14
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r14)
je .LBB2_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB2_16
.LBB2_15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 776(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_90
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r15)
je .LBB2_19
# %bb.18:
movzbl 67(%r15), %eax
jmp .LBB2_20
.LBB2_19:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 776(%rsp), %xmm1
movl 780(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_90
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r15)
je .LBB2_23
# %bb.22:
movzbl 67(%r15), %eax
jmp .LBB2_24
.LBB2_23:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 556(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_90
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%r14)
je .LBB2_27
# %bb.26:
movzbl 67(%r14), %ecx
jmp .LBB2_28
.LBB2_27:
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 792(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_90
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r14)
je .LBB2_31
# %bb.30:
movzbl 67(%r14), %ecx
jmp .LBB2_32
.LBB2_31:
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 472(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_90
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i108
cmpb $0, 56(%r14)
je .LBB2_35
# %bb.34:
movzbl 67(%r14), %ecx
jmp .LBB2_36
.LBB2_35:
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit111
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 464(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.11, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_90
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i113
cmpb $0, 56(%r15)
je .LBB2_39
# %bb.38:
movzbl 67(%r15), %eax
jmp .LBB2_40
.LBB2_39:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit116
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 456(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI2_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI2_3(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.13, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_90
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i118
cmpb $0, 56(%r15)
je .LBB2_43
# %bb.42:
movzbl 67(%r15), %eax
jmp .LBB2_44
.LBB2_43:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit121
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i123
cmpb $0, 56(%r14)
je .LBB2_47
# %bb.46:
movzbl 67(%r14), %eax
jmp .LBB2_48
.LBB2_47:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit126
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI2_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.11, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i128
cmpb $0, 56(%r12)
je .LBB2_51
# %bb.50:
movzbl 67(%r12), %eax
jmp .LBB2_52
.LBB2_51:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 464(%rsp), %rax
testq %rax, %rax
js .LBB2_53
# %bb.54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
jmp .LBB2_55
.LBB2_53:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB2_55: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
mulss .LCPI2_5(%rip), %xmm0
cvttss2si %xmm0, %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.16, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.56: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i133
movl %ebx, %r14d
imull %r14d, %r14d
cmpb $0, 56(%r12)
je .LBB2_58
# %bb.57:
movzbl 67(%r12), %eax
jmp .LBB2_59
.LBB2_58:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_59: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit136
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %r14d, %r13d
shlq $2, %r13
movq %r13, %rdi
callq _Znam
movq %rax, %r15
movq %r13, %rdi
callq _Znam
movq %rax, %r12
testl %ebx, %ebx
je .LBB2_64
# %bb.60: # %.lr.ph.preheader
movq %rbx, 152(%rsp) # 8-byte Spill
movq %rbp, 160(%rsp) # 8-byte Spill
cmpl $1, %r14d
movl %r14d, %ebp
adcl $0, %ebp
leaq (,%rbp,4), %rdx
xorl %ebx, %ebx
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_61: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1077936128, (%r15,%rbx,4) # imm = 0x40400000
incq %rbx
cmpq %rbx, %rbp
jne .LBB2_61
# %bb.62: # %.lr.ph160
movq 152(%rsp), %rbx # 8-byte Reload
movl %ebx, %eax
incl %eax
cltq
movslq %r14d, %rcx
xorl %edx, %edx
movq 160(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB2_63: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r12,%rdx,4) # imm = 0x3F800000
addq %rax, %rdx
cmpq %rcx, %rdx
jl .LBB2_63
.LBB2_64: # %._crit_edge
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
je .LBB2_68
# %bb.65: # %._crit_edge
cmpl $2, %eax
jne .LBB2_71
# %bb.66:
movl %ebx, %eax
shrl $4, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_76
# %bb.67:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11matMulTiledPfPKfS1_i, %edi
jmp .LBB2_70
.LBB2_68:
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
mulss .LCPI2_6(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq $1, %rdi
imulq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_76
# %bb.69:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matMulPfPKfS1_i, %edi
.LBB2_70:
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_76
.LBB2_71:
movq %rbx, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_90
# %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
cmpb $0, 56(%rbx)
je .LBB2_74
# %bb.73:
movzbl 67(%rbx), %eax
jmp .LBB2_75
.LBB2_74:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_75: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit141
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rbx
.LBB2_76:
movq %r13, %rdi
callq _Znam
movq %rbx, %rbp
movq %rax, %rbx
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebp, %ebp
je .LBB2_85
# %bb.77: # %.lr.ph163.preheader
cmpl $1, %r14d
adcl $0, %r14d
xorl %eax, %eax
movss .LCPI2_7(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_8(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movss .LCPI2_9(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_79: # %.lr.ph163
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
ucomiss %xmm2, %xmm3
ja .LBB2_80
# %bb.78: # in Loop: Header=BB2_79 Depth=1
incq %rax
cmpq %rax, %r14
jne .LBB2_79
jmp .LBB2_85
.LBB2_80:
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_90
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i143
cmpb $0, 56(%r14)
je .LBB2_83
# %bb.82:
movzbl 67(%r14), %eax
jmp .LBB2_84
.LBB2_83:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_84: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit146
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB2_85: # %.loopexit
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_90
# %bb.86: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i148
cmpb $0, 56(%rbx)
je .LBB2_88
# %bb.87:
movzbl 67(%rbx), %eax
jmp .LBB2_89
.LBB2_88:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_89: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit151
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_90:
.cfi_def_cfa_offset 1696
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPfPKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matMulTiledPfPKfS1_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPfPKfS1_i,@object # @_Z6matMulPfPKfS1_i
.section .rodata,"a",@progbits
.globl _Z6matMulPfPKfS1_i
.p2align 3, 0x0
_Z6matMulPfPKfS1_i:
.quad _Z21__device_stub__matMulPfPKfS1_i
.size _Z6matMulPfPKfS1_i, 8
.type _Z11matMulTiledPfPKfS1_i,@object # @_Z11matMulTiledPfPKfS1_i
.globl _Z11matMulTiledPfPKfS1_i
.p2align 3, 0x0
_Z11matMulTiledPfPKfS1_i:
.quad _Z26__device_stub__matMulTiledPfPKfS1_i
.size _Z11matMulTiledPfPKfS1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "---------------------------------------------"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " GPU PROPERTIES "
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Name: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Memory Clock Rate: "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " GHz"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Memory Bandwidth: "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " GB/s"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Number of SM: "
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Max Threads per SM: "
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Registers per Block: "
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Shared Memory per Block: "
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " B"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Global Memory per Block: "
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " GB"
.size .L.str.13, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "shared memory per block: "
.size .L.str.14, 26
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "can run at most "
.size .L.str.15, 17
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " blocks"
.size .L.str.16, 8
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "invalid argument!"
.size .L.str.17, 18
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "ERROR: something is not right."
.size .L.str.18, 31
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Closing..."
.size .L.str.19, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPfPKfS1_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11matMulTiledPfPKfS1_i"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPfPKfS1_i
.addrsig_sym _Z26__device_stub__matMulTiledPfPKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPfPKfS1_i
.addrsig_sym _Z11matMulTiledPfPKfS1_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
cudaDeviceProp devp;
cudaGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
cudaDeviceProp devp;
cudaGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} | .file "tmpxft_0001edb4_00000000-6_device_query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.LC2:
.string "Major revision number: %d\n"
.LC3:
.string "Minor revision number: %d\n"
.LC4:
.string "Name: %s\n"
.LC5:
.string "Total global memory: %lu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Total shared memory per block: %lu\n"
.align 8
.LC7:
.string "Total Registers per block: %d\n"
.section .rodata.str1.1
.LC8:
.string "Warp Size: %d\n"
.LC9:
.string "Maximum Memory pitch: %lu\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Maximum Threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension of block %d: %d\n"
.align 8
.LC12:
.string "Maximum dimension of grid %d: %d\n"
.section .rodata.str1.1
.LC13:
.string "Clock rate: %d\n"
.LC14:
.string "Total Constant Memory: %lu\n"
.LC15:
.string "Texture alignment: %lu\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L12
movl $0, %ebx
leaq 16(%rsp), %rbp
.L13:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L13
.L12:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
cudaDeviceProp devp;
cudaGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
hipDeviceProp_t devp;
hipGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
hipDeviceProp_t devp;
hipGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp Size: %d\n", devProp.warpSize);
printf("Maximum Memory pitch: %lu\n", devProp.memPitch);
printf("Maximum Threads per block: %d\n", devProp.maxThreadsPerBlock);
for(int i = 0; i<3; i++)
printf("Maximum dimension of block %d: %d\n", i, devProp.maxThreadsDim[i]);
for(int i = 0; i<3; i++)
printf("Maximum dimension of grid %d: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total Constant Memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
for(int i=0; i<devCount; i++)
{
hipDeviceProp_t devp;
hipGetDeviceProperties(&devp, i);
printDevProp(devp);
}
return 0;
} | .text
.file "device_query.hip"
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %eax
movl $.L.str.15, %esi
cmoveq %rax, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end0-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %lu\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %lu\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total Registers per block: %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp Size: %d\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum Memory pitch: %lu\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum Threads per block: %d\n"
.size .L.str.8, 31
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension of block %d: %d\n"
.size .L.str.9, 35
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension of grid %d: %d\n"
.size .L.str.10, 34
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 16
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Constant Memory: %lu\n"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %lu\n"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 31
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001edb4_00000000-6_device_query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.LC2:
.string "Major revision number: %d\n"
.LC3:
.string "Minor revision number: %d\n"
.LC4:
.string "Name: %s\n"
.LC5:
.string "Total global memory: %lu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Total shared memory per block: %lu\n"
.align 8
.LC7:
.string "Total Registers per block: %d\n"
.section .rodata.str1.1
.LC8:
.string "Warp Size: %d\n"
.LC9:
.string "Maximum Memory pitch: %lu\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Maximum Threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension of block %d: %d\n"
.align 8
.LC12:
.string "Maximum dimension of grid %d: %d\n"
.section .rodata.str1.1
.LC13:
.string "Clock rate: %d\n"
.LC14:
.string "Total Constant Memory: %lu\n"
.LC15:
.string "Texture alignment: %lu\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L12
movl $0, %ebx
leaq 16(%rsp), %rbp
.L13:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L13
.L12:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device_query.hip"
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %eax
movl $.L.str.15, %esi
cmoveq %rax, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end0-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %lu\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %lu\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total Registers per block: %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp Size: %d\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum Memory pitch: %lu\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum Threads per block: %d\n"
.size .L.str.8, 31
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension of block %d: %d\n"
.size .L.str.9, 35
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension of grid %d: %d\n"
.size .L.str.10, 34
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 16
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Constant Memory: %lu\n"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %lu\n"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 31
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
cudaMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
cudaMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
cudaMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
cudaThreadSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
cudaMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
return time/float(MANY);
} | code for sm_80
Function : _Z7kernaddPfS_S_iim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD R5, R4, c[0x0][0x180], RZ ; /* 0x0000600004057a24 */
/* 0x000fc600078e02ff */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R5, R2.reuse, c[0x0][0x184], R5 ; /* 0x0000610002057a24 */
/* 0x040fe400078e0205 */
/*00c0*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x180], RZ ; /* 0x0000600002027a25 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R3, R3, R5, RZ ; /* 0x0000000503037210 */
/* 0x000fc80007ffe0ff */
/*00e0*/ SHF.R.U64 R3, R2, 0x2, R3 ; /* 0x0000000202037819 */
/* 0x000fe20000001203 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0100*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0110*/ IADD3 R0, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0130*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*0140*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
cudaMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
cudaMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
cudaMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
cudaThreadSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
cudaMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
return time/float(MANY);
} | .file "tmpxft_001944c3_00000000-6_addongpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
.type _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim, @function
_Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernaddPfS_S_iim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim, .-_Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
.globl _Z7kernaddPfS_S_iim
.type _Z7kernaddPfS_S_iim, @function
_Z7kernaddPfS_S_iim:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7kernaddPfS_S_iim, .-_Z7kernaddPfS_S_iim
.globl AddOnGpu
.type AddOnGpu, @function
AddOnGpu:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, %r14
movq %rdx, 8(%rsp)
movl %ecx, %ebx
movl %r8d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %r8d, %r13
movslq %ecx, %r12
salq $2, %r12
leaq 32(%rsp), %r15
leaq 40(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
leaq 48(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
leaq 56(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r13, %r9
movq %r12, %r8
movq %r12, %rcx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $2, (%rsp)
movq %r13, %r9
movq %r12, %r8
movq %r12, %rcx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $32, 80(%rsp)
movl $16, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%rbx), %eax
addq $16, %rsp
.cfi_def_cfa_offset 160
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 76(%rsp)
leal 30(%rbx), %eax
movl %ebx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
leaq 28(%rsp), %rsi
movl $1, %edi
call chrono@PLT
movl $200, %r14d
jmp .L13
.L12:
call cudaThreadSynchronize@PLT
subl $1, %r14d
je .L17
.L13:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 32(%rsp), %r9
movl %ebp, %r8d
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
jmp .L12
.L17:
leaq 28(%rsp), %rsi
movl $0, %edi
call chrono@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r13, %r9
movq %r12, %r8
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movss 28(%rsp), %xmm0
divss .LC0(%rip), %xmm0
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size AddOnGpu, .-AddOnGpu
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7kernaddPfS_S_iim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernaddPfS_S_iim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1128792064
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
cudaMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
cudaMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
cudaMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
cudaMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
cudaThreadSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
cudaMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
return time/float(MANY);
} | #include <hip/hip_runtime.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
hipMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
hipMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
hipMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
hipDeviceSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
hipMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
return time/float(MANY);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
hipMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
hipMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
hipMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
hipDeviceSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
hipMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
return time/float(MANY);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernaddPfS_S_iim
.globl _Z7kernaddPfS_S_iim
.p2align 8
.type _Z7kernaddPfS_S_iim,@function
_Z7kernaddPfS_S_iim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s3
v_mul_lo_u32 v5, v2, s2
v_mad_u64_u32 v[2:3], null, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v3, v4, v5
v_alignbit_b32 v1, v1, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernaddPfS_S_iim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernaddPfS_S_iim, .Lfunc_end0-_Z7kernaddPfS_S_iim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernaddPfS_S_iim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernaddPfS_S_iim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
/* Size of a block */
#define BLOCK_X 32
#define BLOCK_Y 16
#define MANY 200
#define STOP 0
#define START 1
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny, size_t pitch)
{
int i, j, index;
/* UP TO YOU edit line below so that the index is correctly evaluated */
i = blockDim.x * blockIdx.x + threadIdx.x;
j = blockDim.y * blockIdx.y + threadIdx.y;
index = i + j * pitch / sizeof(float);
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/* extern "C" below is because this file follows C++ linking conventions */
/* whereas the companion C file (addition.c) follows C linking conventions */
/* which are different */
extern "C" void chrono (int kind, float *time);
extern "C" float AddOnGpu(float* mat_out, float *mat_in1, float *mat_in2,int nx, int ny) {
size_t pitch; /* Same pitch for all matrices, since
they all have same size */
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* UP TO YOU : do the allocation below, using cudaMallocPitch ()*/
hipMallocPitch (&mat_out_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in1_gpu, &pitch, sizeof(float) * nx, ny);
hipMallocPitch (&mat_in2_gpu, &pitch, sizeof(float) * nx, ny);
/* The arguments mat_in1 and mat_in2 passed above are on the host. */
/* UP TO YOU : write below the instructions to copy it to the device */
/* You'll need to google the function cudaMemcpy2D () */
hipMemcpy2D(mat_in1_gpu,pitch,mat_in1,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
hipMemcpy2D(mat_in2_gpu,pitch,mat_in2,nx*sizeof(float),nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* Grid topology below */
/* A block is BLOCK_X threads wide by BLOCK_Y threads high */
dim3 block (BLOCK_X, BLOCK_Y);
/* UP TO YOU : complete the number of blocks below */
int n1 = (nx+BLOCK_X-1)/BLOCK_X;
int n2 = (nx+BLOCK_Y-1)/BLOCK_Y;;
dim3 grid (n1,n2);
int count;
float time;
chrono (START, &time);
/* UP TO YOU : kernel invocation */
for (count = 0;count < MANY; count++){
kernadd <<< grid,block >>> (mat_out_gpu, mat_in1_gpu,mat_in2_gpu,nx,ny,pitch);
hipDeviceSynchronize();
}
chrono (STOP, &time);
/* We now transfer back the matrix from the device to the host */
/* UP TO YOU : write cudaMemcpy2D () instruction below */
hipMemcpy2D (mat_out,sizeof(float)*nx,mat_out_gpu,pitch,nx*sizeof(float),ny,hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
return time/float(MANY);
} | .text
.file "addongpu.hip"
.globl _Z22__device_stub__kernaddPfS_S_iim # -- Begin function _Z22__device_stub__kernaddPfS_S_iim
.p2align 4, 0x90
.type _Z22__device_stub__kernaddPfS_S_iim,@function
_Z22__device_stub__kernaddPfS_S_iim: # @_Z22__device_stub__kernaddPfS_S_iim
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernaddPfS_S_iim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernaddPfS_S_iim, .Lfunc_end0-_Z22__device_stub__kernaddPfS_S_iim
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function AddOnGpu
.LCPI1_0:
.long 0x43480000 # float 200
.text
.globl AddOnGpu
.p2align 4, 0x90
.type AddOnGpu,@function
AddOnGpu: # @AddOnGpu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r12d
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdi, 88(%rsp) # 8-byte Spill
movslq %ecx, %r13
leaq (,%r13,4), %rbx
movslq %r8d, %r14
leaq 72(%rsp), %rdi
leaq 32(%rsp), %r15
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
leaq 64(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
leaq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
movq 64(%rsp), %rdi
movq 32(%rsp), %rsi
movl $2, (%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movq %rbx, %rcx
movq %rbx, %r8
movq %r14, %r9
callq hipMemcpy2D
movq 56(%rsp), %rdi
movq 32(%rsp), %rsi
movl $2, (%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rbx, %rcx
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %r8
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %r9
callq hipMemcpy2D
leal 31(%r13), %eax
leal 62(%r13), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 15(%r13), %eax
addl $30, %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $4, %r13d
shlq $32, %r13
orq %rcx, %r13
leaq 28(%rsp), %rsi
movl $1, %edi
callq chrono
movl $200, %ebx
movabsq $68719476768, %r15 # imm = 0x1000000020
leaq 176(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
decl %ebx
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r12d, 84(%rsp)
movl %ebp, 80(%rsp)
movq %rsi, 144(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 84(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 144(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rax
movq 96(%rsp), %rdi
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
movl $_Z7kernaddPfS_S_iim, %edi
movq %r14, %r9
callq hipLaunchKernel
jmp .LBB1_3
.LBB1_4:
leaq 28(%rsp), %rsi
xorl %edi, %edi
callq chrono
movq 72(%rsp), %rdx
movq 32(%rsp), %rcx
movl $2, (%rsp)
movq 88(%rsp), %rdi # 8-byte Reload
movq 48(%rsp), %rsi # 8-byte Reload
movq %rsi, %r8
movq 40(%rsp), %r9 # 8-byte Reload
callq hipMemcpy2D
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size AddOnGpu, .Lfunc_end1-AddOnGpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernaddPfS_S_iim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernaddPfS_S_iim,@object # @_Z7kernaddPfS_S_iim
.section .rodata,"a",@progbits
.globl _Z7kernaddPfS_S_iim
.p2align 3, 0x0
_Z7kernaddPfS_S_iim:
.quad _Z22__device_stub__kernaddPfS_S_iim
.size _Z7kernaddPfS_S_iim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernaddPfS_S_iim"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernaddPfS_S_iim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernaddPfS_S_iim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernaddPfS_S_iim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD R5, R4, c[0x0][0x180], RZ ; /* 0x0000600004057a24 */
/* 0x000fc600078e02ff */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R5, R2.reuse, c[0x0][0x184], R5 ; /* 0x0000610002057a24 */
/* 0x040fe400078e0205 */
/*00c0*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x180], RZ ; /* 0x0000600002027a25 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R3, R3, R5, RZ ; /* 0x0000000503037210 */
/* 0x000fc80007ffe0ff */
/*00e0*/ SHF.R.U64 R3, R2, 0x2, R3 ; /* 0x0000000202037819 */
/* 0x000fe20000001203 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0100*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0110*/ IADD3 R0, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0130*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*0140*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernaddPfS_S_iim
.globl _Z7kernaddPfS_S_iim
.p2align 8
.type _Z7kernaddPfS_S_iim,@function
_Z7kernaddPfS_S_iim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s3
v_mul_lo_u32 v5, v2, s2
v_mad_u64_u32 v[2:3], null, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v3, v4, v5
v_alignbit_b32 v1, v1, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernaddPfS_S_iim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernaddPfS_S_iim, .Lfunc_end0-_Z7kernaddPfS_S_iim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernaddPfS_S_iim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernaddPfS_S_iim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001944c3_00000000-6_addongpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
.type _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim, @function
_Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernaddPfS_S_iim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim, .-_Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
.globl _Z7kernaddPfS_S_iim
.type _Z7kernaddPfS_S_iim, @function
_Z7kernaddPfS_S_iim:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7kernaddPfS_S_iim, .-_Z7kernaddPfS_S_iim
.globl AddOnGpu
.type AddOnGpu, @function
AddOnGpu:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, %r14
movq %rdx, 8(%rsp)
movl %ecx, %ebx
movl %r8d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %r8d, %r13
movslq %ecx, %r12
salq $2, %r12
leaq 32(%rsp), %r15
leaq 40(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
leaq 48(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
leaq 56(%rsp), %rdi
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r13, %r9
movq %r12, %r8
movq %r12, %rcx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $2, (%rsp)
movq %r13, %r9
movq %r12, %r8
movq %r12, %rcx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $32, 80(%rsp)
movl $16, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%rbx), %eax
addq $16, %rsp
.cfi_def_cfa_offset 160
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 76(%rsp)
leal 30(%rbx), %eax
movl %ebx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
leaq 28(%rsp), %rsi
movl $1, %edi
call chrono@PLT
movl $200, %r14d
jmp .L13
.L12:
call cudaThreadSynchronize@PLT
subl $1, %r14d
je .L17
.L13:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 32(%rsp), %r9
movl %ebp, %r8d
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z7kernaddPfS_S_iimPfS_S_iim
jmp .L12
.L17:
leaq 28(%rsp), %rsi
movl $0, %edi
call chrono@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r13, %r9
movq %r12, %r8
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movss 28(%rsp), %xmm0
divss .LC0(%rip), %xmm0
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size AddOnGpu, .-AddOnGpu
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7kernaddPfS_S_iim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernaddPfS_S_iim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1128792064
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addongpu.hip"
.globl _Z22__device_stub__kernaddPfS_S_iim # -- Begin function _Z22__device_stub__kernaddPfS_S_iim
.p2align 4, 0x90
.type _Z22__device_stub__kernaddPfS_S_iim,@function
_Z22__device_stub__kernaddPfS_S_iim: # @_Z22__device_stub__kernaddPfS_S_iim
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernaddPfS_S_iim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernaddPfS_S_iim, .Lfunc_end0-_Z22__device_stub__kernaddPfS_S_iim
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function AddOnGpu
.LCPI1_0:
.long 0x43480000 # float 200
.text
.globl AddOnGpu
.p2align 4, 0x90
.type AddOnGpu,@function
AddOnGpu: # @AddOnGpu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r12d
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdi, 88(%rsp) # 8-byte Spill
movslq %ecx, %r13
leaq (,%r13,4), %rbx
movslq %r8d, %r14
leaq 72(%rsp), %rdi
leaq 32(%rsp), %r15
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
leaq 64(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
leaq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq hipMallocPitch
movq 64(%rsp), %rdi
movq 32(%rsp), %rsi
movl $2, (%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movq %rbx, %rcx
movq %rbx, %r8
movq %r14, %r9
callq hipMemcpy2D
movq 56(%rsp), %rdi
movq 32(%rsp), %rsi
movl $2, (%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rbx, %rcx
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %r8
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %r9
callq hipMemcpy2D
leal 31(%r13), %eax
leal 62(%r13), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 15(%r13), %eax
addl $30, %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $4, %r13d
shlq $32, %r13
orq %rcx, %r13
leaq 28(%rsp), %rsi
movl $1, %edi
callq chrono
movl $200, %ebx
movabsq $68719476768, %r15 # imm = 0x1000000020
leaq 176(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
decl %ebx
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r12d, 84(%rsp)
movl %ebp, 80(%rsp)
movq %rsi, 144(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 84(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 144(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rax
movq 96(%rsp), %rdi
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
movl $_Z7kernaddPfS_S_iim, %edi
movq %r14, %r9
callq hipLaunchKernel
jmp .LBB1_3
.LBB1_4:
leaq 28(%rsp), %rsi
xorl %edi, %edi
callq chrono
movq 72(%rsp), %rdx
movq 32(%rsp), %rcx
movl $2, (%rsp)
movq 88(%rsp), %rdi # 8-byte Reload
movq 48(%rsp), %rsi # 8-byte Reload
movq %rsi, %r8
movq 40(%rsp), %r9 # 8-byte Reload
callq hipMemcpy2D
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size AddOnGpu, .Lfunc_end1-AddOnGpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernaddPfS_S_iim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernaddPfS_S_iim,@object # @_Z7kernaddPfS_S_iim
.section .rodata,"a",@progbits
.globl _Z7kernaddPfS_S_iim
.p2align 3, 0x0
_Z7kernaddPfS_S_iim:
.quad _Z22__device_stub__kernaddPfS_S_iim
.size _Z7kernaddPfS_S_iim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernaddPfS_S_iim"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernaddPfS_S_iim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernaddPfS_S_iim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} | .file "tmpxft_00122306_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10nextPower2i
.type _Z10nextPower2i, @function
_Z10nextPower2i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10nextPower2i, .-_Z10nextPower2i
.globl _Z4swapPfS_
.type _Z4swapPfS_, @function
_Z4swapPfS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z4swapPfS_, .-_Z4swapPfS_
.globl _Z11bitonicSortPfi
.type _Z11bitonicSortPfi, @function
_Z11bitonicSortPfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11bitonicSortPfi, .-_Z11bitonicSortPfi
.globl _Z13bitonicSortFFiPfS_
.type _Z13bitonicSortFFiPfS_, @function
_Z13bitonicSortFFiPfS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z13bitonicSortFFiPfS_, .-_Z13bitonicSortFFiPfS_
.globl _Z11computeRankPfi
.type _Z11computeRankPfi, @function
_Z11computeRankPfi:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z11computeRankPfi, .-_Z11computeRankPfi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} | #include <hip/hip_runtime.h>
/*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*!
* Compute the next power of 2 which occurs after a number.
*
* @param n
*/
__device__
int nextPower2(int n)
{
int pow2 = 2;
while ( pow2 < n )
{
pow2 *= 2;
}
return pow2;
}
/*!
* Swap two values
*
* @param a
* @param b
*/
__device__
void swap(float *a, float *b)
{
float c = *a;
*a = *b;
*b = c;
}
/*!
* Sort an array using bitonic sort. The array should have a size which is a
* power of two.
*
* @param array
* @param size
*/
__device__
void bitonicSort(float *array, int size)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
}
}
}
}
}
/*!
* Sort an array using bitonic sort, while also applying the same swap operations
* to a second array of the same size. The arrays should have a size which is a
* power of two.
*
* @param size
* @param array
* @param extra
*/
__device__
void bitonicSortFF(int size, float *array, float *extra)
{
int bsize = size / 2;
int dir, a, b, t;
for ( int ob = 2; ob <= size; ob *= 2 )
{
for ( int ib = ob; ib >= 2; ib /= 2 )
{
t = ib/2;
for ( int i = 0; i < bsize; ++i )
{
dir = -((i/(ob/2)) & 0x1);
a = (i/t) * ib + (i%t);
b = a + t;
if ( (!dir && (array[a] > array[b])) || (dir && (array[a] < array[b])) )
{
swap(&array[a], &array[b]);
swap(&extra[a], &extra[b]);
}
}
}
}
}
/*!
* Compute the rank of a sorted vector in place. In the event of ties,
* the ranks are corrected using fractional ranking.
*
* @param array
* @param n
*/
__device__
void computeRank(float *array, int n)
{
int i = 0;
while ( i < n - 1 )
{
float a_i = array[i];
if ( a_i == array[i + 1] )
{
int j = i + 2;
int k;
float rank = 0;
// we have detected a tie, find number of equal elements
while ( j < n && a_i == array[j] )
{
++j;
}
// compute rank
for ( k = i; k < j; ++k )
{
rank += k;
}
// divide by number of ties
rank /= (float) (j - i);
for ( k = i; k < j; ++k )
{
array[k] = rank;
}
i = j;
}
else
{
// no tie - set rank to natural ordered position
array[i] = i;
++i;
}
}
if ( i == n - 1 )
{
array[n - 1] = (float) (n - 1);
}
} | .text
.file "sort.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122306_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10nextPower2i
.type _Z10nextPower2i, @function
_Z10nextPower2i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10nextPower2i, .-_Z10nextPower2i
.globl _Z4swapPfS_
.type _Z4swapPfS_, @function
_Z4swapPfS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z4swapPfS_, .-_Z4swapPfS_
.globl _Z11bitonicSortPfi
.type _Z11bitonicSortPfi, @function
_Z11bitonicSortPfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11bitonicSortPfi, .-_Z11bitonicSortPfi
.globl _Z13bitonicSortFFiPfS_
.type _Z13bitonicSortFFiPfS_, @function
_Z13bitonicSortFFiPfS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z13bitonicSortFFiPfS_, .-_Z13bitonicSortFFiPfS_
.globl _Z11computeRankPfi
.type _Z11computeRankPfi, @function
_Z11computeRankPfi:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z11computeRankPfi, .-_Z11computeRankPfi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sort.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "./test_utilities.cuh"
std::string get_env_var(std::string const &key) {
char *val = getenv(key.c_str());
if (val == nullptr) {
throw TestException(key + " is not defined.");
}
return std::string(val);
}
Probe probe_from_env() {
auto n_channels = std::stoi(get_env_var("TEST_NCHANNELS"));
auto n_active = std::stoi(get_env_var("TEST_NACTIVE"));
auto n_groups = std::stoi(get_env_var("TEST_NGROUPS"));
auto srate_hz = std::stod(get_env_var("TEST_SRATE_HZ"));
return make_probe(n_channels, n_active, n_groups, srate_hz);
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "./test_utilities.cuh"
std::string get_env_var(std::string const &key) {
char *val = getenv(key.c_str());
if (val == nullptr) {
throw TestException(key + " is not defined.");
}
return std::string(val);
}
Probe probe_from_env() {
auto n_channels = std::stoi(get_env_var("TEST_NCHANNELS"));
auto n_active = std::stoi(get_env_var("TEST_NACTIVE"));
auto n_groups = std::stoi(get_env_var("TEST_NGROUPS"));
auto srate_hz = std::stod(get_env_var("TEST_SRATE_HZ"));
return make_probe(n_channels, n_active, n_groups, srate_hz);
} | #include <hip/hip_runtime.h>
#include "./test_utilities.cuh"
std::string get_env_var(std::string const &key) {
char *val = getenv(key.c_str());
if (val == nullptr) {
throw TestException(key + " is not defined.");
}
return std::string(val);
}
Probe probe_from_env() {
auto n_channels = std::stoi(get_env_var("TEST_NCHANNELS"));
auto n_active = std::stoi(get_env_var("TEST_NACTIVE"));
auto n_groups = std::stoi(get_env_var("TEST_NGROUPS"));
auto srate_hz = std::stod(get_env_var("TEST_SRATE_HZ"));
return make_probe(n_channels, n_active, n_groups, srate_hz);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "./test_utilities.cuh"
std::string get_env_var(std::string const &key) {
char *val = getenv(key.c_str());
if (val == nullptr) {
throw TestException(key + " is not defined.");
}
return std::string(val);
}
Probe probe_from_env() {
auto n_channels = std::stoi(get_env_var("TEST_NCHANNELS"));
auto n_active = std::stoi(get_env_var("TEST_NACTIVE"));
auto n_groups = std::stoi(get_env_var("TEST_NGROUPS"));
auto srate_hz = std::stod(get_env_var("TEST_SRATE_HZ"));
return make_probe(n_channels, n_active, n_groups, srate_hz);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "./test_utilities.cuh"
std::string get_env_var(std::string const &key) {
char *val = getenv(key.c_str());
if (val == nullptr) {
throw TestException(key + " is not defined.");
}
return std::string(val);
}
Probe probe_from_env() {
auto n_channels = std::stoi(get_env_var("TEST_NCHANNELS"));
auto n_active = std::stoi(get_env_var("TEST_NACTIVE"));
auto n_groups = std::stoi(get_env_var("TEST_NGROUPS"));
auto srate_hz = std::stod(get_env_var("TEST_SRATE_HZ"));
return make_probe(n_channels, n_active, n_groups, srate_hz);
} | .text
.file "test_utilities.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
movq (%rsi), %rdi
callq getenv
testq %rax, %rax
je .LBB0_1
# %bb.10:
movq %rax, %r14
leaq 16(%rbx), %rax
movq %rax, (%rbx)
movq %r14, %rdi
callq strlen
movq %rax, %r15
cmpq $16, %rax
jb .LBB0_14
# %bb.11:
testq %r15, %r15
js .LBB0_20
# %bb.12:
movq %r15, %rdi
incq %rdi
js .LBB0_21
# %bb.13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, (%rbx)
movq %r15, 16(%rbx)
.LBB0_14:
testq %r15, %r15
je .LBB0_18
# %bb.15:
movq (%rbx), %rdi
cmpq $1, %r15
jne .LBB0_17
# %bb.16:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB0_18
.LBB0_17:
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_21: # %.noexc11.i
.cfi_def_cfa_offset 80
callq _ZSt17__throw_bad_allocv
.LBB0_1:
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %rbx
.Ltmp0:
leaq 8(%rsp), %rdi
movl $.L.str, %edx
movq %r15, %rsi
callq _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.Ltmp1:
# %bb.2:
movb $1, %bpl
.Ltmp3:
leaq 8(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSt13runtime_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp4:
# %bb.3: # %_ZN13TestExceptionC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.exit
movq $_ZTV13TestException+16, (%rbx)
xorl %ebp, %ebp
.Ltmp5:
movl $_ZTI13TestException, %esi
movl $_ZNSt13runtime_errorD2Ev, %edx
movq %rbx, %rdi
callq __cxa_throw
.Ltmp6:
# %bb.19:
.LBB0_20: # %.noexc.i
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.LBB0_5:
.Ltmp7:
movq %rax, %r14
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
jne .LBB0_6
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
testb %bpl, %bpl
jne .LBB0_8
.LBB0_9:
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB0_6: # %.critedge.i.i
callq _ZdlPv
testb %bpl, %bpl
je .LBB0_9
jmp .LBB0_8
.LBB0_4:
.Ltmp2:
movq %rax, %r14
movb $1, %bpl
testb %bpl, %bpl
je .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq __cxa_free_exception
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end0-_Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,comdat
.weak _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_ # -- Begin function _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.p2align 4, 0x90
.type _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,@function
_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_: # @_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r14
movq (%rsi), %r15
movq 8(%rsi), %r12
movq %rdx, %rdi
callq strlen
leaq 7(%rsp), %r9
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %rbx, %rcx
movq %rax, %r8
callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_, .Lfunc_end1-_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.cfi_endproc
# -- End function
.text
.globl _Z14probe_from_envv # -- Begin function _Z14probe_from_envv
.p2align 4, 0x90
.type _Z14probe_from_envv,@function
_Z14probe_from_envv: # @_Z14probe_from_envv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r15
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movabsq $5207091765514028372, %rax # imm = 0x48434E5F54534554
movq %rax, 24(%rsp)
movabsq $6002248606000695363, %rax # imm = 0x534C454E4E414843
movq %rax, 30(%rsp)
movq $14, 16(%rsp)
movb $0, 38(%rsp)
.Ltmp8:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp9:
# %bb.1:
movq 48(%rsp), %r12
callq __errno_location
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
leaq 40(%rsp), %rsi
movq %r12, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r12, 40(%rsp)
je .LBB2_42
# %bb.2:
movslq %eax, %rcx
cmpq %rax, %rcx
jne .LBB2_44
# %bb.3:
movl (%rbx), %ecx
cmpl $34, %ecx
je .LBB2_44
# %bb.4:
movq %rax, 96(%rsp) # 8-byte Spill
testl %ecx, %ecx
jne .LBB2_6
# %bb.5:
movl %ebp, (%rbx)
.LBB2_6: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_8
# %bb.7: # %.critedge.i.i32
callq _ZdlPv
.LBB2_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_10
# %bb.9: # %.critedge.i.i33
callq _ZdlPv
.LBB2_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit35
movq %r14, 8(%rsp)
movabsq $4846240845370967380, %rax # imm = 0x43414E5F54534554
movq %rax, 24(%rsp)
movl $1163282772, 32(%rsp) # imm = 0x45564954
movq $12, 16(%rsp)
movb $0, 36(%rsp)
.Ltmp11:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp12:
# %bb.11:
movq 48(%rsp), %r13
movl (%rbx), %ebp
movl $0, (%rbx)
leaq 40(%rsp), %rsi
movq %r13, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r13, 40(%rsp)
je .LBB2_46
# %bb.12:
movq %rax, %r12
movq %r15, 88(%rsp) # 8-byte Spill
movabsq $-4294967296, %r14 # imm = 0xFFFFFFFF00000000
addq $-2147483648, %rax # imm = 0x80000000
cmpq %r14, %rax
jb .LBB2_48
# %bb.13:
movl (%rbx), %eax
cmpl $34, %eax
je .LBB2_48
# %bb.14:
testl %eax, %eax
leaq 24(%rsp), %r15
jne .LBB2_16
# %bb.15:
movl %ebp, (%rbx)
.LBB2_16: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit48
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_18
# %bb.17: # %.critedge.i.i49
callq _ZdlPv
.LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit51
movq 8(%rsp), %rdi
cmpq %r15, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i52
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit54
movq %r15, 8(%rsp)
movabsq $5928793605800150356, %rax # imm = 0x52474E5F54534554
movq %rax, 24(%rsp)
movl $1397773647, 32(%rsp) # imm = 0x5350554F
movq $12, 16(%rsp)
movb $0, 36(%rsp)
.Ltmp14:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp15:
# %bb.21:
movq 48(%rsp), %rbp
movl (%rbx), %r15d
movl $0, (%rbx)
leaq 40(%rsp), %rsi
movq %rbp, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %rbp, 40(%rsp)
je .LBB2_50
# %bb.22:
movq %rax, %r13
addq $-2147483648, %rax # imm = 0x80000000
cmpq %r14, %rax
jb .LBB2_52
# %bb.23:
movl (%rbx), %eax
cmpl $34, %eax
je .LBB2_52
# %bb.24:
testl %eax, %eax
jne .LBB2_26
# %bb.25:
movl %r15d, (%rbx)
.LBB2_26: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit67
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_28
# %bb.27: # %.critedge.i.i68
callq _ZdlPv
.LBB2_28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit70
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_30
# %bb.29: # %.critedge.i.i71
callq _ZdlPv
.LBB2_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit73
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
movabsq $4706916229457331540, %rax # imm = 0x4152535F54534554
movq %rax, 24(%rsp)
movabsq $6505554413107630675, %rax # imm = 0x5A485F4554415253
movq %rax, 29(%rsp)
movq $13, 16(%rsp)
movb $0, 37(%rsp)
.Ltmp17:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z11get_env_varRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp18:
# %bb.31:
movq 48(%rsp), %rbp
movl (%rbx), %r15d
movl $0, (%rbx)
leaq 40(%rsp), %rsi
movq %rbp, %rdi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
cmpq %rbp, 40(%rsp)
je .LBB2_54
# %bb.32:
movl (%rbx), %eax
testl %eax, %eax
je .LBB2_36
# %bb.33:
cmpl $34, %eax
jne .LBB2_37
# %bb.34: # %.critedge.i.i81
.Ltmp20:
movl $.L.str.9, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp21:
# %bb.35:
.LBB2_36:
movl %r15d, (%rbx)
.LBB2_37: # %_ZNSt7__cxx114stodERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_39
# %bb.38: # %.critedge.i.i84
callq _ZdlPv
.LBB2_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit86
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
movq 88(%rsp), %rbx # 8-byte Reload
je .LBB2_41
# %bb.40: # %.critedge.i.i87
callq _ZdlPv
.LBB2_41: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit89
movq %rbx, %rdi
movq 96(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl %r12d, %edx
movl %r13d, %ecx
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _Z10make_probejjjd
movq %rbx, %rax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_42:
.cfi_def_cfa_offset 160
.Ltmp37:
movq %r14, %r15
movl $.L.str.8, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp38:
# %bb.43:
.LBB2_44: # %.critedge.i.i
.Ltmp35:
movq %r14, %r15
movl $.L.str.8, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp36:
# %bb.45:
.LBB2_46:
.Ltmp32:
movl $.L.str.8, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp33:
# %bb.47:
.LBB2_48: # %.critedge.i.i44
.Ltmp30:
movl $.L.str.8, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp31:
# %bb.49:
.LBB2_50:
.Ltmp27:
movl $.L.str.8, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp28:
# %bb.51:
.LBB2_52: # %.critedge.i.i63
.Ltmp25:
movl $.L.str.8, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp26:
# %bb.53:
.LBB2_54:
.Ltmp22:
movl $.L.str.9, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp23:
# %bb.55:
.LBB2_56:
.Ltmp19:
jmp .LBB2_59
.LBB2_57:
.Ltmp16:
jmp .LBB2_59
.LBB2_58:
.Ltmp13:
.LBB2_59: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit110
movq %rax, %r14
jmp .LBB2_69
.LBB2_60:
.Ltmp10:
movq %r14, %r15
movq %rax, %r14
jmp .LBB2_76
.LBB2_61:
.Ltmp24:
jmp .LBB2_62
.LBB2_64:
.Ltmp29:
.LBB2_62:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB2_67
# %bb.63:
movl %r15d, (%rbx)
jmp .LBB2_67
.LBB2_65:
.Ltmp34:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB2_67
# %bb.66:
movl %ebp, (%rbx)
.LBB2_67: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i45
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_69
# %bb.68: # %.critedge.i.i96
callq _ZdlPv
.LBB2_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit110
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_71
.LBB2_70: # %.critedge.i.i111
callq _ZdlPv
.LBB2_71:
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB2_72:
.Ltmp39:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB2_74
# %bb.73:
movl %ebp, (%rbx)
.LBB2_74: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_76
# %bb.75: # %.critedge.i.i90
callq _ZdlPv
.LBB2_76: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit92
movq 8(%rsp), %rdi
cmpq %r15, %rdi
jne .LBB2_70
jmp .LBB2_71
.Lfunc_end2:
.size _Z14probe_from_envv, .Lfunc_end2-_Z14probe_from_envv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp8-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin1 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin1 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin1 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin1 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp24-.Lfunc_begin1 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp37-.Ltmp21 # Call between .Ltmp21 and .Ltmp37
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp36-.Ltmp37 # Call between .Ltmp37 and .Ltmp36
.uleb128 .Ltmp39-.Lfunc_begin1 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp31-.Ltmp32 # Call between .Ltmp32 and .Ltmp31
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp26-.Ltmp27 # Call between .Ltmp27 and .Ltmp26
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin1 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Lfunc_end2-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"axG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.weak _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE # -- Begin function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.p2align 4, 0x90
.type _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,@function
_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE: # @_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 16(%rdi), %rbp
movq %rbp, (%rdi)
movq $0, 8(%rdi)
movb $0, 16(%rdi)
leaq (%r8,%rdx), %rsi
.Ltmp40:
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp41:
# %bb.1:
movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
movq 8(%rbx), %rsi
movq %r15, %rax
subq %rsi, %rax
cmpq %r12, %rax
jb .LBB3_11
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
leaq (%rsi,%r12), %r13
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB3_4
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq (%rbp), %rax
.LBB3_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
cmpq %rax, %r13
jbe .LBB3_5
# %bb.9:
.Ltmp42:
movq %rbx, %rdi
xorl %edx, %edx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r12, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp43:
jmp .LBB3_10
.LBB3_5:
testq %r12, %r12
je .LBB3_10
# %bb.6:
addq %rsi, %rdi
cmpq $1, %r12
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB3_10
.LBB3_8:
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq memcpy@PLT
.LBB3_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit
movq %r13, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r13)
movq 8(%rbx), %rsi
subq %rsi, %r15
cmpq %r14, %r15
jb .LBB3_11
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
leaq (%rsi,%r14), %r15
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB3_15
# %bb.14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
movq (%rbp), %rax
.LBB3_15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
cmpq %rax, %r15
jbe .LBB3_16
# %bb.20:
.Ltmp44:
movq %rbx, %rdi
xorl %edx, %edx
movq 8(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp45:
jmp .LBB3_21
.LBB3_16:
testq %r14, %r14
je .LBB3_21
# %bb.17:
addq %rsi, %rdi
cmpq $1, %r14
jne .LBB3_19
# %bb.18:
movq 8(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB3_21
.LBB3_19:
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
.LBB3_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit17
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_11: # %.invoke
.cfi_def_cfa_offset 80
.Ltmp46:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp47:
# %bb.12: # %.cont
.LBB3_22:
.Ltmp48:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %rbp, %rdi
je .LBB3_24
# %bb.23: # %.critedge.i.i
callq _ZdlPv
.LBB3_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE, .Lfunc_end3-_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.cfi_endproc
.section .gcc_except_table._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"aG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp43-.Ltmp40 # Call between .Ltmp40 and .Ltmp43
.uleb128 .Ltmp48-.Lfunc_begin2 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp48-.Lfunc_begin2 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin2 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Lfunc_end3-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq (%rdi), %r14
leaq 16(%rdi), %r12
movl $15, %eax
cmpq %r12, %r14
je .LBB4_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB4_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
cmpq %rsi, %rax
jae .LBB4_12
# %bb.3:
testq %rsi, %rsi
js .LBB4_13
# %bb.4:
addq %rax, %rax
movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF
cmpq %r13, %rax
cmovbq %rax, %r13
cmpq %rsi, %rax
cmovbeq %rsi, %r13
movq %r13, %rdi
incq %rdi
js .LBB4_14
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
callq _Znwm
movq %rax, %r15
movq 8(%rbx), %rdx
cmpq $-1, %rdx
je .LBB4_9
# %bb.6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
testq %rdx, %rdx
jne .LBB4_8
# %bb.7:
movzbl (%r14), %eax
movb %al, (%r15)
.LBB4_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
cmpq %r12, %r14
je .LBB4_11
.LBB4_10: # %.critedge.i
movq %r14, %rdi
callq _ZdlPv
.LBB4_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r15, (%rbx)
movq %r13, 16(%rbx)
.LBB4_12:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 48
incq %rdx
movq %r15, %rdi
movq %r14, %rsi
callq memcpy@PLT
cmpq %r12, %r14
jne .LBB4_10
jmp .LBB4_11
.LBB4_14:
callq _ZSt17__throw_bad_allocv
.LBB4_13:
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB5_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB5_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB5_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB5_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB5_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB5_6:
movq %rbp, %rdi
incq %rdi
js .LBB5_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB5_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB5_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB5_11
.LBB5_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB5_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB5_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB5_18
# %bb.13:
je .LBB5_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB5_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB5_17
.LBB5_16:
callq memcpy@PLT
.LBB5_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB5_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB5_23
# %bb.19:
subq %r14, %r12
je .LBB5_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB5_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB5_23
.LBB5_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB5_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB5_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB5_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB5_26:
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end5:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end5-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZN13TestExceptionD0Ev,"axG",@progbits,_ZN13TestExceptionD0Ev,comdat
.weak _ZN13TestExceptionD0Ev # -- Begin function _ZN13TestExceptionD0Ev
.p2align 4, 0x90
.type _ZN13TestExceptionD0Ev,@function
_ZN13TestExceptionD0Ev: # @_ZN13TestExceptionD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZNSt13runtime_errorD2Ev
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end6:
.size _ZN13TestExceptionD0Ev, .Lfunc_end6-_ZN13TestExceptionD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " is not defined."
.size .L.str, 17
.type _ZTS13TestException,@object # @_ZTS13TestException
.section .rodata._ZTS13TestException,"aG",@progbits,_ZTS13TestException,comdat
.weak _ZTS13TestException
_ZTS13TestException:
.asciz "13TestException"
.size _ZTS13TestException, 16
.type _ZTI13TestException,@object # @_ZTI13TestException
.section .rodata._ZTI13TestException,"aG",@progbits,_ZTI13TestException,comdat
.weak _ZTI13TestException
.p2align 3, 0x0
_ZTI13TestException:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTS13TestException
.quad _ZTISt13runtime_error
.size _ZTI13TestException, 24
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "TEST_NCHANNELS"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "TEST_NACTIVE"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "TEST_NGROUPS"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "TEST_SRATE_HZ"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "basic_string::_M_create"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "basic_string::append"
.size .L.str.6, 21
.type _ZTV13TestException,@object # @_ZTV13TestException
.section .rodata._ZTV13TestException,"aG",@progbits,_ZTV13TestException,comdat
.weak _ZTV13TestException
.p2align 3, 0x0
_ZTV13TestException:
.quad 0
.quad _ZTI13TestException
.quad _ZNSt13runtime_errorD2Ev
.quad _ZN13TestExceptionD0Ev
.quad _ZNKSt13runtime_error4whatEv
.size _ZTV13TestException, 40
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "stoi"
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "stod"
.size .L.str.9, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTS13TestException
.addrsig_sym _ZTISt13runtime_error
.addrsig_sym _ZTI13TestException
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z11Final_Hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_0008dd67_00000000-6_final_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11Final_Hellovv
.type _Z30__device_stub__Z11Final_Hellovv, @function
_Z30__device_stub__Z11Final_Hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11Final_Hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11Final_Hellovv, .-_Z30__device_stub__Z11Final_Hellovv
.globl _Z11Final_Hellov
.type _Z11Final_Hellov, @function
_Z11Final_Hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11Final_Hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11Final_Hellov, .-_Z11Final_Hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11Final_Hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Final_Hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Final_Hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
hipDeviceSynchronize();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Final_Hellov
.globl _Z11Final_Hellov
.p2align 8
.type _Z11Final_Hellov,@function
_Z11Final_Hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 12
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Final_Hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Final_Hellov, .Lfunc_end0-_Z11Final_Hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Final_Hello"
.size .str, 12
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Final_Hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11Final_Hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void Final_Hello()
{printf("Final_Hello");}
int main()
{
Final_Hello<<<1,1>>>();
hipDeviceSynchronize();
} | .text
.file "final_hello.hip"
.globl _Z26__device_stub__Final_Hellov # -- Begin function _Z26__device_stub__Final_Hellov
.p2align 4, 0x90
.type _Z26__device_stub__Final_Hellov,@function
_Z26__device_stub__Final_Hellov: # @_Z26__device_stub__Final_Hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11Final_Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__Final_Hellov, .Lfunc_end0-_Z26__device_stub__Final_Hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11Final_Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Final_Hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Final_Hellov,@object # @_Z11Final_Hellov
.section .rodata,"a",@progbits
.globl _Z11Final_Hellov
.p2align 3, 0x0
_Z11Final_Hellov:
.quad _Z26__device_stub__Final_Hellov
.size _Z11Final_Hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Final_Hellov"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Final_Hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Final_Hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Final_Hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Final_Hellov
.globl _Z11Final_Hellov
.p2align 8
.type _Z11Final_Hellov,@function
_Z11Final_Hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 12
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Final_Hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Final_Hellov, .Lfunc_end0-_Z11Final_Hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Final_Hello"
.size .str, 12
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Final_Hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11Final_Hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008dd67_00000000-6_final_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11Final_Hellovv
.type _Z30__device_stub__Z11Final_Hellovv, @function
_Z30__device_stub__Z11Final_Hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11Final_Hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11Final_Hellovv, .-_Z30__device_stub__Z11Final_Hellovv
.globl _Z11Final_Hellov
.type _Z11Final_Hellov, @function
_Z11Final_Hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11Final_Hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11Final_Hellov, .-_Z11Final_Hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11Final_Hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Final_Hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Final_Hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "final_hello.hip"
.globl _Z26__device_stub__Final_Hellov # -- Begin function _Z26__device_stub__Final_Hellov
.p2align 4, 0x90
.type _Z26__device_stub__Final_Hellov,@function
_Z26__device_stub__Final_Hellov: # @_Z26__device_stub__Final_Hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11Final_Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__Final_Hellov, .Lfunc_end0-_Z26__device_stub__Final_Hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11Final_Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Final_Hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Final_Hellov,@object # @_Z11Final_Hellov
.section .rodata,"a",@progbits
.globl _Z11Final_Hellov
.p2align 3, 0x0
_Z11Final_Hellov:
.quad _Z26__device_stub__Final_Hellov
.size _Z11Final_Hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Final_Hellov"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Final_Hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Final_Hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} | code for sm_80
Function : _Z7x_dot_wPfS_S_jjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002500 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0xa, PT ; /* 0x0000000a0300780c */
/* 0x040fe20003f06070 */
/*00a0*/ IMAD.WIDE.U32 R4, R3, -0x33333333, RZ ; /* 0xcccccccd03047825 */
/* 0x000fc400078e00ff */
/*00b0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ea60000002100 */
/*00c0*/ LEA.HI R10, R5, 0x1, RZ, 0x1d ; /* 0x00000001050a7811 */
/* 0x000fe200078fe8ff */
/*00d0*/ IMAD R5, R0, 0x28, RZ ; /* 0x0000002800057824 */
/* 0x001fe400078e02ff */
/*00e0*/ IMAD R3, R9, c[0x0][0x4], R0 ; /* 0x0000010009037a24 */
/* 0x002fe200078e0200 */
/*00f0*/ LOP3.LUT R9, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010a097812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD R4, R7, c[0x0][0x0], R2.reuse ; /* 0x0000000007047a24 */
/* 0x104fe200078e0202 */
/*0110*/ LEA R8, R2, R5, 0x2 ; /* 0x0000000502087211 */
/* 0x000fe200078e10ff */
/*0120*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe200078e0202 */
/*0130*/ @!P0 BRA 0x760 ; /* 0x0000062000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f26070 */
/*0150*/ IADD3 R10, R10, -R9, RZ ; /* 0x800000090a0a7210 */
/* 0x000fc40007ffe0ff */
/*0160*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD R11, R7.reuse, 0xa, R0 ; /* 0x0000000a070b7824 */
/* 0x040fe200078e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f06070 */
/*01a0*/ IMAD R12, R7, 0xa, R2 ; /* 0x0000000a070c7824 */
/* 0x000fe200078e0202 */
/*01b0*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe40000000f00 */
/*01c0*/ ISETP.GE.U32.OR P3, PT, R11, c[0x0][0x17c], P0 ; /* 0x00005f000b007a0c */
/* 0x000fe40000766470 */
/*01d0*/ ISETP.GE.U32.OR P2, PT, R12, c[0x0][0x17c], P1 ; /* 0x00005f000c007a0c */
/* 0x000fd60000f46470 */
/*01e0*/ @!P3 IMAD R20, R11, c[0x0][0x180], R4 ; /* 0x000060000b14ba24 */
/* 0x000fe200078e0204 */
/*01f0*/ @!P3 MOV R21, 0x4 ; /* 0x000000040015b802 */
/* 0x000fe20000000f00 */
/*0200*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0210*/ @!P2 MOV R15, 0x4 ; /* 0x00000004000fa802 */
/* 0x000fe20000000f00 */
/*0220*/ @!P2 IMAD R14, R7, 0xa, R6 ; /* 0x0000000a070ea824 */
/* 0x000fe400078e0206 */
/*0230*/ @!P3 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fc800078e0015 */
/*0240*/ @!P2 IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0ea625 */
/* 0x000fe200078e000f */
/*0250*/ @!P3 LDG.E R25, [R20.64] ; /* 0x000000041419b981 */
/* 0x0000a8000c1e1900 */
/*0260*/ @!P2 LDG.E R11, [R14.64] ; /* 0x000000040e0ba981 */
/* 0x000ee2000c1e1900 */
/*0270*/ HFMA2.MMA R20, -RZ, RZ, 0, 5.9604644775390625e-07 ; /* 0x0000000aff147435 */
/* 0x001fe400000001ff */
/*0280*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0290*/ STS [R8+0x190], R25 ; /* 0x0001901908007388 */
/* 0x004fe80000000800 */
/*02a0*/ STS [R8], R11 ; /* 0x0000000b08007388 */
/* 0x0081e80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R18, [R2.X4+0x190] ; /* 0x0001900002127984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.64 R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000e680000000a00 */
/*02e0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R24, [R2.X4+0x1e0] ; /* 0x0001e00002187984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.64 R16, [R5+0x8] ; /* 0x0000080005107984 */
/* 0x000ee80000000a00 */
/*0310*/ LDS R26, [R2.X4+0x208] ; /* 0x00020800021a7984 */
/* 0x000f280000004800 */
/*0320*/ LDS R23, [R2.X4+0x230] ; /* 0x0002300002177984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R14, [R5+0x10] ; /* 0x00001000050e7984 */
/* 0x000f620000000a00 */
/*0340*/ IMAD R11, R7, R20, 0xa ; /* 0x0000000a070b7424 */
/* 0x001fc600078e0214 */
/*0350*/ LDS R28, [R2.X4+0x258] ; /* 0x00025800021c7984 */
/* 0x000e240000004800 */
/*0360*/ IADD3 R20, R11, R2, RZ ; /* 0x000000020b147210 */
/* 0x000fe40007ffe0ff */
/*0370*/ LDS R29, [R2.X4+0x280] ; /* 0x00028000021d7984 */
/* 0x000fe40000004800 */
/*0380*/ ISETP.GE.U32.OR P2, PT, R20, c[0x0][0x17c], P1 ; /* 0x00005f0014007a0c */
/* 0x000fe40000f46470 */
/*0390*/ LDS R25, [R2.X4+0x2d0] ; /* 0x0002d00002197984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R12, R18, R12, R19 ; /* 0x0000000c120c7223 */
/* 0x002fc60000000013 */
/*03b0*/ LDS.64 R18, [R5+0x18] ; /* 0x0000180005127984 */
/* 0x000e620000000a00 */
/*03c0*/ FFMA R13, R22, R13, R12 ; /* 0x0000000d160d7223 */
/* 0x004fcc000000000c */
/*03d0*/ @!P2 IADD3 R22, R6, R11, RZ ; /* 0x0000000b0616a210 */
/* 0x000fe20007ffe0ff */
/*03e0*/ FFMA R16, R24, R16, R13 ; /* 0x0000001018107223 */
/* 0x008fe2000000000d */
/*03f0*/ @!P2 MOV R13, 0x4 ; /* 0x00000004000da802 */
/* 0x000fe20000000f00 */
/*0400*/ LDS R24, [R2.X4+0x2f8] ; /* 0x0002f80002187984 */
/* 0x000fe40000004800 */
/*0410*/ FFMA R16, R26, R17, R16 ; /* 0x000000111a107223 */
/* 0x010fe20000000010 */
/*0420*/ IADD3 R17, R11, R0, RZ ; /* 0x000000000b117210 */
/* 0x000fe20007ffe0ff */
/*0430*/ LDS R26, [R2.X4+0x2a8] ; /* 0x0002a800021a7984 */
/* 0x000ea60000004800 */
/*0440*/ ISETP.GE.U32.OR P0, PT, R17, c[0x0][0x17c], P0 ; /* 0x00005f0011007a0c */
/* 0x000fe20000706470 */
/*0450*/ FFMA R14, R23, R14, R16 ; /* 0x0000000e170e7223 */
/* 0x020fc40000000010 */
/*0460*/ @!P2 IMAD.WIDE.U32 R22, R22, R13, c[0x0][0x160] ; /* 0x000058001616a625 */
/* 0x000fe400078e000d */
/*0470*/ LDS.64 R12, [R5+0x20] ; /* 0x00002000050c7984 */
/* 0x000ee80000000a00 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0490*/ @!P0 IMAD R20, R17, c[0x0][0x180], R4 ; /* 0x0000600011148a24 */
/* 0x000fe200078e0204 */
/*04a0*/ @!P0 MOV R21, 0x4 ; /* 0x0000000400158802 */
/* 0x000fe20000000f00 */
/*04b0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fc800000001ff */
/*04c0*/ @!P0 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x168] ; /* 0x00005a0014148625 */
/* 0x000fe200078e0015 */
/*04d0*/ @!P2 LDG.E R27, [R22.64] ; /* 0x00000004161ba981 */
/* 0x000f2a000c1e1900 */
/*04e0*/ @!P0 LDG.E R17, [R20.64] ; /* 0x0000000414118981 */
/* 0x000f62000c1e1900 */
/*04f0*/ FFMA R14, R28, R15, R14 ; /* 0x0000000f1c0e7223 */
/* 0x001fc8000000000e */
/*0500*/ FFMA R18, R29, R18, R14 ; /* 0x000000121d127223 */
/* 0x002fc8000000000e */
/*0510*/ FFMA R18, R26, R19, R18 ; /* 0x000000131a127223 */
/* 0x004fc80000000012 */
/*0520*/ FFMA R12, R25, R12, R18 ; /* 0x0000000c190c7223 */
/* 0x008fc80000000012 */
/*0530*/ FFMA R12, R24, R13, R12 ; /* 0x0000000d180c7223 */
/* 0x000fe2000000000c */
/*0540*/ IADD3 R10, R10, -0x2, RZ ; /* 0xfffffffe0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0560*/ IADD3 R7, R7, 0x2, RZ ; /* 0x0000000207077810 */
/* 0x000fe20007ffe0ff */
/*0570*/ STS [R8], R27 ; /* 0x0000001b08007388 */
/* 0x010fe80000000800 */
/*0580*/ STS [R8+0x190], R17 ; /* 0x0001901108007388 */
/* 0x020fe80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ LDS R27, [R2.X4+0x190] ; /* 0x00019000021b7984 */
/* 0x000fe80000004800 */
/*05b0*/ LDS.64 R16, [R5] ; /* 0x0000000005107984 */
/* 0x000e280000000a00 */
/*05c0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000e680000004800 */
/*05d0*/ LDS R23, [R2.X4+0x1e0] ; /* 0x0001e00002177984 */
/* 0x000fe80000004800 */
/*05e0*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000ea80000000a00 */
/*05f0*/ LDS R20, [R2.X4+0x208] ; /* 0x0002080002147984 */
/* 0x000ee80000004800 */
/*0600*/ LDS R21, [R2.X4+0x230] ; /* 0x0002300002157984 */
/* 0x000fe80000004800 */
/*0610*/ LDS.64 R18, [R5+0x10] ; /* 0x0000100005127984 */
/* 0x000f280000000a00 */
/*0620*/ LDS R24, [R2.X4+0x258] ; /* 0x0002580002187984 */
/* 0x000f680000004800 */
/*0630*/ LDS R25, [R2.X4+0x280] ; /* 0x0002800002197984 */
/* 0x000fe20000004800 */
/*0640*/ FFMA R16, R27, R16, R12 ; /* 0x000000101b107223 */
/* 0x001fc6000000000c */
/*0650*/ LDS.64 R12, [R5+0x18] ; /* 0x00001800050c7984 */
/* 0x000e220000000a00 */
/*0660*/ FFMA R16, R22, R17, R16 ; /* 0x0000001116107223 */
/* 0x002fc60000000010 */
/*0670*/ LDS R22, [R2.X4+0x2a8] ; /* 0x0002a80002167984 */
/* 0x000e620000004800 */
/*0680*/ FFMA R26, R23, R14, R16 ; /* 0x0000000e171a7223 */
/* 0x004fc60000000010 */
/*0690*/ LDS R23, [R2.X4+0x2d0] ; /* 0x0002d00002177984 */
/* 0x000fe80000004800 */
/*06a0*/ LDS.64 R16, [R5+0x20] ; /* 0x0000200005107984 */
/* 0x000ea80000000a00 */
/*06b0*/ LDS R14, [R2.X4+0x2f8] ; /* 0x0002f800020e7984 */
/* 0x000ea20000004800 */
/*06c0*/ FFMA R15, R20, R15, R26 ; /* 0x0000000f140f7223 */
/* 0x008fc8000000001a */
/*06d0*/ FFMA R15, R21, R18, R15 ; /* 0x00000012150f7223 */
/* 0x010fc8000000000f */
/*06e0*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x020fc8000000000f */
/*06f0*/ FFMA R12, R25, R12, R15 ; /* 0x0000000c190c7223 */
/* 0x001fc8000000000f */
/*0700*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x002fc8000000000c */
/*0710*/ FFMA R12, R23, R16, R12 ; /* 0x00000010170c7223 */
/* 0x004fc8000000000c */
/*0720*/ FFMA R19, R14, R17, R12 ; /* 0x000000110e137223 */
/* 0x000fe2000000000c */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 BRA 0x180 ; /* 0xfffffa3000000947 */
/* 0x000fea000383ffff */
/*0750*/ IADD3 R11, R11, 0xa, RZ ; /* 0x0000000a0b0b7810 */
/* 0x000fe40007ffe0ff */
/*0760*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*0780*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fce0000706470 */
/*0790*/ @!P1 BRA 0xa70 ; /* 0x000002d000009947 */
/* 0x000fec0003800000 */
/*07a0*/ IADD3 R9, R2, R11.reuse, RZ ; /* 0x0000000b02097210 */
/* 0x080fe20007ffe0ff */
/*07b0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fe200000001ff */
/*07c0*/ IADD3 R7, R0, R11, RZ ; /* 0x0000000b00077210 */
/* 0x000fe40007ffe0ff */
/*07d0*/ ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fe40003f26070 */
/*07e0*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe40003f46070 */
/*07f0*/ ISETP.GE.U32.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe40000f26470 */
/*0800*/ ISETP.GE.U32.OR P2, PT, R4, c[0x0][0x180], P2 ; /* 0x0000600004007a0c */
/* 0x000fc40001746470 */
/*0810*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fd20000000f00 */
/*0820*/ @!P1 IADD3 R6, R6, R11, RZ ; /* 0x0000000b06069210 */
/* 0x000fe40007ffe0ff */
/*0830*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fe20000000f00 */
/*0840*/ @!P2 IMAD R10, R7, c[0x0][0x180], R4 ; /* 0x00006000070aaa24 */
/* 0x000fe200078e0204 */
/*0850*/ @!P2 MOV R13, 0x4 ; /* 0x00000004000da802 */
/* 0x000fc60000000f00 */
/*0860*/ @!P1 IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006069625 */
/* 0x000fc800078e000b */
/*0870*/ @!P2 IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x168] ; /* 0x00005a000a0aa625 */
/* 0x000fe200078e000d */
/*0880*/ @!P1 LDG.E R17, [R6.64] ; /* 0x0000000406119981 */
/* 0x000ea8000c1e1900 */
/*0890*/ @!P2 LDG.E R9, [R10.64] ; /* 0x000000040a09a981 */
/* 0x000ee8000c1e1900 */
/*08a0*/ STS [R8], R17 ; /* 0x0000001108007388 */
/* 0x004fe80000000800 */
/*08b0*/ STS [R8+0x190], R9 ; /* 0x0001900908007388 */
/* 0x008fe80000000800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ LDS R20, [R2.X4+0x190] ; /* 0x0001900002147984 */
/* 0x000fe80000004800 */
/*08e0*/ LDS.64 R14, [R5] ; /* 0x00000000050e7984 */
/* 0x000e280000000a00 */
/*08f0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000e680000004800 */
/*0900*/ LDS R23, [R2.X4+0x1e0] ; /* 0x0001e00002177984 */
/* 0x000fe80000004800 */
/*0910*/ LDS.64 R12, [R5+0x8] ; /* 0x00000800050c7984 */
/* 0x000ea80000000a00 */
/*0920*/ LDS R24, [R2.X4+0x208] ; /* 0x0002080002187984 */
/* 0x000ee80000004800 */
/*0930*/ LDS R25, [R2.X4+0x230] ; /* 0x0002300002197984 */
/* 0x000fe80000004800 */
/*0940*/ LDS.64 R10, [R5+0x10] ; /* 0x00001000050a7984 */
/* 0x000f280000000a00 */
/*0950*/ LDS R16, [R2.X4+0x258] ; /* 0x0002580002107984 */
/* 0x000f680000004800 */
/*0960*/ LDS R21, [R2.X4+0x280] ; /* 0x0002800002157984 */
/* 0x000fe80000004800 */
/*0970*/ LDS.64 R6, [R5+0x18] ; /* 0x0000180005067984 */
/* 0x000f680000000a00 */
/*0980*/ LDS R0, [R2.X4+0x2a8] ; /* 0x0002a80002007984 */
/* 0x000f620000004800 */
/*0990*/ FFMA R14, R20, R14, R19 ; /* 0x0000000e140e7223 */
/* 0x001fc60000000013 */
/*09a0*/ LDS R17, [R2.X4+0x2d0] ; /* 0x0002d00002117984 */
/* 0x000fe20000004800 */
/*09b0*/ FFMA R15, R22, R15, R14 ; /* 0x0000000f160f7223 */
/* 0x002fc6000000000e */
/*09c0*/ LDS.64 R8, [R5+0x20] ; /* 0x0000200005087984 */
/* 0x000e280000000a00 */
/*09d0*/ LDS R18, [R2.X4+0x2f8] ; /* 0x0002f80002127984 */
/* 0x000e620000004800 */
/*09e0*/ FFMA R12, R23, R12, R15 ; /* 0x0000000c170c7223 */
/* 0x004fc8000000000f */
/*09f0*/ FFMA R13, R24, R13, R12 ; /* 0x0000000d180d7223 */
/* 0x008fc8000000000c */
/*0a00*/ FFMA R10, R25, R10, R13 ; /* 0x0000000a190a7223 */
/* 0x010fc8000000000d */
/*0a10*/ FFMA R10, R16, R11, R10 ; /* 0x0000000b100a7223 */
/* 0x020fc8000000000a */
/*0a20*/ FFMA R6, R21, R6, R10 ; /* 0x0000000615067223 */
/* 0x000fc8000000000a */
/*0a30*/ FFMA R0, R0, R7, R6 ; /* 0x0000000700007223 */
/* 0x000fc80000000006 */
/*0a40*/ FFMA R0, R17, R8, R0 ; /* 0x0000000811007223 */
/* 0x001fc80000000000 */
/*0a50*/ FFMA R19, R18, R9, R0 ; /* 0x0000000912137223 */
/* 0x002fe20000000000 */
/*0a60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R3, R3, c[0x0][0x180], R4 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0204 */
/*0aa0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*0ab0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} | .file "tmpxft_0003e1ff_00000000-6_x_dot_w_tile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
.type _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj, @function
_Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7x_dot_wPfS_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj, .-_Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
.globl _Z7x_dot_wPfS_S_jjj
.type _Z7x_dot_wPfS_S_jjj, @function
_Z7x_dot_wPfS_S_jjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7x_dot_wPfS_S_jjj, .-_Z7x_dot_wPfS_S_jjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7x_dot_wPfS_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7x_dot_wPfS_S_jjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} | #include <hip/hip_runtime.h>
#define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7x_dot_wPfS_S_jjj
.globl _Z7x_dot_wPfS_S_jjj
.p2align 8
.type _Z7x_dot_wPfS_S_jjj,@function
_Z7x_dot_wPfS_S_jjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 2, v1
v_mov_b32_e32 v9, 0
v_mul_u32_u24_e32 v10, 40, v0
v_add_nc_u32_e32 v12, 0x190, v5
v_mad_u32_u24 v11, v0, 40, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v13, v0, 40, v12
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s9, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s2, 0xcccccccd
s_lshr_b32 s11, s11, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, s14, s10, v[1:2]
v_mad_u64_u32 v[4:5], null, v2, s9, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s8, v2
v_cmp_le_u32_e64 s10, s8, v2
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s12, s2, -1
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2)
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
s_mul_i32 s16, s13, 10
s_mov_b32 s14, exec_lo
v_dual_mov_b32 v14, s16 :: v_dual_add_nc_u32 v5, s16, v1
s_and_not1_b32 s16, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s9, v5
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_5
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v11, v6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v5, v4, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_add_co_u32 v7, s2, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s5, v8, s2
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s15
v_mad_u64_u32 v[7:8], null, s13, 10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s9, v7
s_or_b32 s2, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_9
ds_store_b32 v13, v6
.LBB0_9:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[15:16], null, v7, s3, v[3:4]
v_mov_b32_e32 v16, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[15:16]
v_add_co_u32 v7, s2, s6, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v13, v5
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v5, v12
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_12:
v_add_nc_u32_e32 v7, s2, v10
s_add_i32 s2, s2, 4
ds_load_b32 v8, v5
ds_load_b32 v7, v7
v_add_nc_u32_e32 v5, 40, v5
s_cmp_eq_u32 s2, 40
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v7, v8
s_cbranch_scc0 .LBB0_12
s_add_i32 s2, s13, 1
s_cmp_eq_u32 s13, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_15
s_mov_b32 s13, s2
s_branch .LBB0_1
.LBB0_15:
v_cmp_gt_u32_e32 vcc_lo, s8, v2
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_17
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v9, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7x_dot_wPfS_S_jjj
.amdhsa_group_segment_fixed_size 800
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7x_dot_wPfS_S_jjj, .Lfunc_end0-_Z7x_dot_wPfS_S_jjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 800
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7x_dot_wPfS_S_jjj
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z7x_dot_wPfS_S_jjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define TW 10
__global__ void x_dot_w(float *a, float *b, float *c, const unsigned int X, const unsigned int Y, const unsigned int Z)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float temp = 0;
__shared__ float S_X [10][TW];
__shared__ float S_Y [10][TW];
for (int t = 0; t < (Y-1)/TW + 1; t++) {
if(row < X && (t* TW +tx) < Y )
S_X[ty][tx] = a[row * Y + t*TW + tx];
else
S_X[ty][tx] = 0.0;
if ( (t* TW + ty) < Y && col < Z )
S_Y[ty][tx] = b[(t*TW + ty)* Z + col];
else
S_Y[ty][tx] = 0.0;
__syncthreads();
for (int k = 0; k < TW; k++) {
temp+= S_X[ty][k] * S_Y[k][tx];
}
__syncthreads();
}
if(row < X && col <Z) {
c[row * Z + col] = temp;
}
} | .text
.file "x_dot_w_tile.hip"
.globl _Z22__device_stub__x_dot_wPfS_S_jjj # -- Begin function _Z22__device_stub__x_dot_wPfS_S_jjj
.p2align 4, 0x90
.type _Z22__device_stub__x_dot_wPfS_S_jjj,@function
_Z22__device_stub__x_dot_wPfS_S_jjj: # @_Z22__device_stub__x_dot_wPfS_S_jjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7x_dot_wPfS_S_jjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__x_dot_wPfS_S_jjj, .Lfunc_end0-_Z22__device_stub__x_dot_wPfS_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7x_dot_wPfS_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7x_dot_wPfS_S_jjj,@object # @_Z7x_dot_wPfS_S_jjj
.section .rodata,"a",@progbits
.globl _Z7x_dot_wPfS_S_jjj
.p2align 3, 0x0
_Z7x_dot_wPfS_S_jjj:
.quad _Z22__device_stub__x_dot_wPfS_S_jjj
.size _Z7x_dot_wPfS_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7x_dot_wPfS_S_jjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__x_dot_wPfS_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7x_dot_wPfS_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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