system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
hipfftReal *hostInputData = (hipfftReal*)malloc(N*BATCH*sizeof(hipfftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
hipfftReal *deviceInputData;
gpuErrchk(hipMalloc((void**)&deviceInputData, N * BATCH * sizeof(hipfftReal)));
hipMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(hipfftReal), hipMemcpyHostToDevice);
// --- Host side output data allocation
hipfftComplex *hostOutputData = (hipfftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex));
// --- Device side output data allocation
hipfftComplex *deviceOutputData; gpuErrchk(hipMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex)));
// --- Batched 1D FFTs
hipfftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
hipfftPlan1d(&handle, FFTSIZE, HIPFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
hipfftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, HIPFFT_R2C, batch);
}
hipfftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(hipMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex), hipMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
hipfftDestroy(handle);
gpuErrchk(hipFree(deviceOutputData));
gpuErrchk(hipFree(deviceInputData));
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
hipfftReal *hostInputData = (hipfftReal*)malloc(N*BATCH*sizeof(hipfftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
hipfftReal *deviceInputData;
gpuErrchk(hipMalloc((void**)&deviceInputData, N * BATCH * sizeof(hipfftReal)));
hipMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(hipfftReal), hipMemcpyHostToDevice);
// --- Host side output data allocation
hipfftComplex *hostOutputData = (hipfftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex));
// --- Device side output data allocation
hipfftComplex *deviceOutputData; gpuErrchk(hipMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex)));
// --- Batched 1D FFTs
hipfftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
hipfftPlan1d(&handle, FFTSIZE, HIPFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
hipfftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, HIPFFT_R2C, batch);
}
hipfftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(hipMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex), hipMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
hipfftDestroy(handle);
gpuErrchk(hipFree(deviceOutputData));
gpuErrchk(hipFree(deviceInputData));
} | .text
.file "test1_planmany.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB0_1
# %bb.2:
movq %rsi, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r15d, %r15d
movq %rax, %r12
.p2align 4, 0x90
.LBB0_3: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss %xmm0, (%r12,%r13,4)
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r15), %rax
addq $40, %r12
testq %r15, %r15
movq %rax, %r15
je .LBB0_3
# %bb.6:
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $80, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit50
movl $8, 36(%rsp)
movl $0, 32(%rsp)
movl $0, 28(%rsp)
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
je .LBB0_25
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit50
cmpl $2, %eax
jne .LBB0_14
# %bb.13:
movl $.Lstr.1, %edi
callq puts@PLT
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 36(%rsp), %rax
leaq 8(%rsp), %rdi
leaq 44(%rsp), %rdx
leaq 40(%rsp), %rcx
movl $1, %esi
movl $1, %r8d
movl $8, %r9d
pushq $2
.cfi_adjust_cfa_offset 8
pushq $42
.cfi_adjust_cfa_offset 8
pushq $5
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq hipfftPlanMany
addq $48, %rsp
.cfi_adjust_cfa_offset -48
jmp .LBB0_14
.LBB0_1:
movl $.Lstr.2, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB0_24
.LBB0_25:
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movl $8, %esi
movl $42, %edx
movl $2, %ecx
callq hipfftPlan1d
.LBB0_14:
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipfftExecR2C
movq 8(%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_26
# %bb.15: # %.preheader.preheader
addq $4, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_17 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_17: # Parent Loop BB0_16 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx,%r15,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r14d, %esi
movl %r15d, %edx
movb $2, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB0_17
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit52
# in Loop: Header=BB0_16 Depth=1
leaq 1(%r14), %rax
addq $40, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB0_16
# %bb.19:
movq (%rsp), %rdi
callq hipfftDestroy
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit54
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit56
xorl %eax, %eax
.LBB0_24:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %r8d
jmp .LBB0_8
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %r8d
jmp .LBB0_8
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB0_8
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB0_8
.LBB0_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %r8d
.LBB0_8:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/leimingyu/cuda_fft/master/cufft/tests/test1_planmany.hip"
.size .L.str.3, 114
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%i %i %f %f\n"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "cufftplan1d"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "cufftplan2d"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Please specify 1 (plan1d) or 2 (planmany)."
.size .Lstr.2, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000444c9_00000000-6_test1_planmany.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2080:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Please specify 1 (plan1d) or 2 (planmany).\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/leimingyu/cuda_fft/master/cufft/tests/test1_planmany.cu"
.section .rodata.str1.1
.LC5:
.string "cufftplan1d\n"
.LC6:
.string "cufftplan2d\n"
.LC7:
.string "%i %i %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L26
movq %rsi, %r13
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L14:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L15:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 40(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L15
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $51, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $58, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $8, 28(%rsp)
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1, %eax
je .L27
cmpl $2, %eax
je .L28
.L17:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecR2C@PLT
movl $2, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $89, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC7(%rip), %r12
.L18:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,8), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbp,%rbx,8), %xmm1
movl %ebx, %ecx
movl $0, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L18
movl $0, %ebx
leaq .LC7(%rip), %r12
.L19:
pxor %xmm0, %xmm0
cvtss2sd 40(%rbp,%rbx,8), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 44(%rbp,%rbx,8), %xmm1
movl %ebx, %ecx
movl $1, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L19
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $96, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $42, %edx
movl $8, %esi
call cufftPlan1d@PLT
jmp .L17
.L28:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 4(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $2
.cfi_def_cfa_offset 112
pushq $42
.cfi_def_cfa_offset 120
pushq $5
.cfi_def_cfa_offset 128
pushq $1
.cfi_def_cfa_offset 136
leaq 76(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 144
movl $8, %r9d
movl $1, %r8d
movl $1, %esi
call cufftPlanMany@PLT
addq $48, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1_planmany.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB0_1
# %bb.2:
movq %rsi, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r15d, %r15d
movq %rax, %r12
.p2align 4, 0x90
.LBB0_3: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss %xmm0, (%r12,%r13,4)
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r15), %rax
addq $40, %r12
testq %r15, %r15
movq %rax, %r15
je .LBB0_3
# %bb.6:
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $80, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit50
movl $8, 36(%rsp)
movl $0, 32(%rsp)
movl $0, 28(%rsp)
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
je .LBB0_25
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit50
cmpl $2, %eax
jne .LBB0_14
# %bb.13:
movl $.Lstr.1, %edi
callq puts@PLT
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 36(%rsp), %rax
leaq 8(%rsp), %rdi
leaq 44(%rsp), %rdx
leaq 40(%rsp), %rcx
movl $1, %esi
movl $1, %r8d
movl $8, %r9d
pushq $2
.cfi_adjust_cfa_offset 8
pushq $42
.cfi_adjust_cfa_offset 8
pushq $5
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq hipfftPlanMany
addq $48, %rsp
.cfi_adjust_cfa_offset -48
jmp .LBB0_14
.LBB0_1:
movl $.Lstr.2, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB0_24
.LBB0_25:
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movl $8, %esi
movl $42, %edx
movl $2, %ecx
callq hipfftPlan1d
.LBB0_14:
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipfftExecR2C
movq 8(%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_26
# %bb.15: # %.preheader.preheader
addq $4, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_17 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_17: # Parent Loop BB0_16 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx,%r15,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r14d, %esi
movl %r15d, %edx
movb $2, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB0_17
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit52
# in Loop: Header=BB0_16 Depth=1
leaq 1(%r14), %rax
addq $40, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB0_16
# %bb.19:
movq (%rsp), %rdi
callq hipfftDestroy
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit54
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit56
xorl %eax, %eax
.LBB0_24:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %r8d
jmp .LBB0_8
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %r8d
jmp .LBB0_8
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB0_8
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB0_8
.LBB0_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %r8d
.LBB0_8:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/leimingyu/cuda_fft/master/cufft/tests/test1_planmany.hip"
.size .L.str.3, 114
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%i %i %f %f\n"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "cufftplan1d"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "cufftplan2d"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Please specify 1 (plan1d) or 2 (planmany)."
.size .Lstr.2, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} | code for sm_80
Function : _Z12skip_res_addmPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, P0, R0.reuse, c[0x0][0x180], RZ ; /* 0x0000600000037a10 */
/* 0x040fe20007f1e0ff */
/*0080*/ IMAD.SHL.U32 R8, R0, 0x4, RZ ; /* 0x0000000400087824 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.U32.HI R9, RZ, 0x1e, R0 ; /* 0x0000001eff097819 */
/* 0x000fe20000011600 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.X R0, RZ, RZ, c[0x0][0x184], P0 ; /* 0x00006100ff007624 */
/* 0x000fe200000e06ff */
/*00c0*/ LEA R6, P0, R3.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */
/* 0x040fe400078010ff */
/*00d0*/ IADD3 R2, P1, R8, c[0x0][0x178], RZ ; /* 0x00005e0008027a10 */
/* 0x000fe40007f3e0ff */
/*00e0*/ LEA.HI.X R7, R3, c[0x0][0x16c], R0, 0x2, P0 ; /* 0x00005b0003077a11 */
/* 0x000fc400000f1400 */
/*00f0*/ IADD3.X R3, R9, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0009037a10 */
/* 0x000fc80000ffe4ff */
/*0100*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R4, P0, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008047a10 */
/* 0x040fe40007f1e0ff */
/*0130*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0140*/ IADD3.X R5, R9.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009057a10 */
/* 0x040fe400007fe4ff */
/*0150*/ IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009097a10 */
/* 0x000fe20000ffe4ff */
/*0160*/ FADD R11, R0, R7 ; /* 0x00000007000b7221 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R13, R0, R9 ; /* 0x00000009000d7221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} | .file "tmpxft_0004696a_00000000-6_skip_res_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
.type _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m, @function
_Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12skip_res_addmPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m, .-_Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
.globl _Z12skip_res_addmPfS_S_m
.type _Z12skip_res_addmPfS_S_m, @function
_Z12skip_res_addmPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12skip_res_addmPfS_S_m, .-_Z12skip_res_addmPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12skip_res_addmPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12skip_res_addmPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12skip_res_addmPfS_S_m
.globl _Z12skip_res_addmPfS_S_m
.p2align 8
.type _Z12skip_res_addmPfS_S_m,@function
_Z12skip_res_addmPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
s_lshl_b64 s[0:1], s[6:7], 2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
global_load_b32 v8, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v8
global_store_b32 v[4:5], v6, off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12skip_res_addmPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12skip_res_addmPfS_S_m, .Lfunc_end0-_Z12skip_res_addmPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12skip_res_addmPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12skip_res_addmPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void skip_res_add(size_t sz, float_t* f5, float* f1, float_t* skip_out_sum, size_t stride)
{
size_t index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < sz)
{
skip_out_sum[index] += f5[index+stride];
f1[index] += f5[index];
}
} | .text
.file "skip_res_add.hip"
.globl _Z27__device_stub__skip_res_addmPfS_S_m # -- Begin function _Z27__device_stub__skip_res_addmPfS_S_m
.p2align 4, 0x90
.type _Z27__device_stub__skip_res_addmPfS_S_m,@function
_Z27__device_stub__skip_res_addmPfS_S_m: # @_Z27__device_stub__skip_res_addmPfS_S_m
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12skip_res_addmPfS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__skip_res_addmPfS_S_m, .Lfunc_end0-_Z27__device_stub__skip_res_addmPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12skip_res_addmPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12skip_res_addmPfS_S_m,@object # @_Z12skip_res_addmPfS_S_m
.section .rodata,"a",@progbits
.globl _Z12skip_res_addmPfS_S_m
.p2align 3, 0x0
_Z12skip_res_addmPfS_S_m:
.quad _Z27__device_stub__skip_res_addmPfS_S_m
.size _Z12skip_res_addmPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12skip_res_addmPfS_S_m"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__skip_res_addmPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12skip_res_addmPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12skip_res_addmPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, P0, R0.reuse, c[0x0][0x180], RZ ; /* 0x0000600000037a10 */
/* 0x040fe20007f1e0ff */
/*0080*/ IMAD.SHL.U32 R8, R0, 0x4, RZ ; /* 0x0000000400087824 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.U32.HI R9, RZ, 0x1e, R0 ; /* 0x0000001eff097819 */
/* 0x000fe20000011600 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.X R0, RZ, RZ, c[0x0][0x184], P0 ; /* 0x00006100ff007624 */
/* 0x000fe200000e06ff */
/*00c0*/ LEA R6, P0, R3.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */
/* 0x040fe400078010ff */
/*00d0*/ IADD3 R2, P1, R8, c[0x0][0x178], RZ ; /* 0x00005e0008027a10 */
/* 0x000fe40007f3e0ff */
/*00e0*/ LEA.HI.X R7, R3, c[0x0][0x16c], R0, 0x2, P0 ; /* 0x00005b0003077a11 */
/* 0x000fc400000f1400 */
/*00f0*/ IADD3.X R3, R9, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0009037a10 */
/* 0x000fc80000ffe4ff */
/*0100*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R4, P0, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008047a10 */
/* 0x040fe40007f1e0ff */
/*0130*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0140*/ IADD3.X R5, R9.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009057a10 */
/* 0x040fe400007fe4ff */
/*0150*/ IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009097a10 */
/* 0x000fe20000ffe4ff */
/*0160*/ FADD R11, R0, R7 ; /* 0x00000007000b7221 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R13, R0, R9 ; /* 0x00000009000d7221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12skip_res_addmPfS_S_m
.globl _Z12skip_res_addmPfS_S_m
.p2align 8
.type _Z12skip_res_addmPfS_S_m,@function
_Z12skip_res_addmPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
s_lshl_b64 s[0:1], s[6:7], 2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
global_load_b32 v8, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v8
global_store_b32 v[4:5], v6, off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12skip_res_addmPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12skip_res_addmPfS_S_m, .Lfunc_end0-_Z12skip_res_addmPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12skip_res_addmPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12skip_res_addmPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004696a_00000000-6_skip_res_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
.type _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m, @function
_Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12skip_res_addmPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m, .-_Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
.globl _Z12skip_res_addmPfS_S_m
.type _Z12skip_res_addmPfS_S_m, @function
_Z12skip_res_addmPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12skip_res_addmPfS_S_mmPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12skip_res_addmPfS_S_m, .-_Z12skip_res_addmPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12skip_res_addmPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12skip_res_addmPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "skip_res_add.hip"
.globl _Z27__device_stub__skip_res_addmPfS_S_m # -- Begin function _Z27__device_stub__skip_res_addmPfS_S_m
.p2align 4, 0x90
.type _Z27__device_stub__skip_res_addmPfS_S_m,@function
_Z27__device_stub__skip_res_addmPfS_S_m: # @_Z27__device_stub__skip_res_addmPfS_S_m
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12skip_res_addmPfS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__skip_res_addmPfS_S_m, .Lfunc_end0-_Z27__device_stub__skip_res_addmPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12skip_res_addmPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12skip_res_addmPfS_S_m,@object # @_Z12skip_res_addmPfS_S_m
.section .rodata,"a",@progbits
.globl _Z12skip_res_addmPfS_S_m
.p2align 3, 0x0
_Z12skip_res_addmPfS_S_m:
.quad _Z27__device_stub__skip_res_addmPfS_S_m
.size _Z12skip_res_addmPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12skip_res_addmPfS_S_m"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__skip_res_addmPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12skip_res_addmPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} | code for sm_80
Function : _Z18multi_scale_kernelPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x178], R0 ; /* 0x00005e0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} | .file "tmpxft_00181614_00000000-6_multi_scale_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
.type _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii, @function
_Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18multi_scale_kernelPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii, .-_Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
.globl _Z18multi_scale_kernelPKfS0_Pfii
.type _Z18multi_scale_kernelPKfS0_Pfii, @function
_Z18multi_scale_kernelPKfS0_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18multi_scale_kernelPKfS0_Pfii, .-_Z18multi_scale_kernelPKfS0_Pfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18multi_scale_kernelPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18multi_scale_kernelPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18multi_scale_kernelPKfS0_Pfii
.globl _Z18multi_scale_kernelPKfS0_Pfii
.p2align 8
.type _Z18multi_scale_kernelPKfS0_Pfii,@function
_Z18multi_scale_kernelPKfS0_Pfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18multi_scale_kernelPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18multi_scale_kernelPKfS0_Pfii, .Lfunc_end0-_Z18multi_scale_kernelPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18multi_scale_kernelPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18multi_scale_kernelPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multi_scale_kernel(const float *data_in, const float *scale, float *data_out, int width, int height) {
const int x = blockDim.x * blockIdx.x + threadIdx.x;
const int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x < width && y < height) {
int index = y * width + x;
data_out[index] = data_in[index] * scale[y];
}
} | .text
.file "multi_scale_kernel.hip"
.globl _Z33__device_stub__multi_scale_kernelPKfS0_Pfii # -- Begin function _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.p2align 4, 0x90
.type _Z33__device_stub__multi_scale_kernelPKfS0_Pfii,@function
_Z33__device_stub__multi_scale_kernelPKfS0_Pfii: # @_Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18multi_scale_kernelPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__multi_scale_kernelPKfS0_Pfii, .Lfunc_end0-_Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18multi_scale_kernelPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18multi_scale_kernelPKfS0_Pfii,@object # @_Z18multi_scale_kernelPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z18multi_scale_kernelPKfS0_Pfii
.p2align 3, 0x0
_Z18multi_scale_kernelPKfS0_Pfii:
.quad _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.size _Z18multi_scale_kernelPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18multi_scale_kernelPKfS0_Pfii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18multi_scale_kernelPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18multi_scale_kernelPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x178], R0 ; /* 0x00005e0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18multi_scale_kernelPKfS0_Pfii
.globl _Z18multi_scale_kernelPKfS0_Pfii
.p2align 8
.type _Z18multi_scale_kernelPKfS0_Pfii,@function
_Z18multi_scale_kernelPKfS0_Pfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18multi_scale_kernelPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18multi_scale_kernelPKfS0_Pfii, .Lfunc_end0-_Z18multi_scale_kernelPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18multi_scale_kernelPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18multi_scale_kernelPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00181614_00000000-6_multi_scale_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
.type _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii, @function
_Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18multi_scale_kernelPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii, .-_Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
.globl _Z18multi_scale_kernelPKfS0_Pfii
.type _Z18multi_scale_kernelPKfS0_Pfii, @function
_Z18multi_scale_kernelPKfS0_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z18multi_scale_kernelPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18multi_scale_kernelPKfS0_Pfii, .-_Z18multi_scale_kernelPKfS0_Pfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18multi_scale_kernelPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18multi_scale_kernelPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multi_scale_kernel.hip"
.globl _Z33__device_stub__multi_scale_kernelPKfS0_Pfii # -- Begin function _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.p2align 4, 0x90
.type _Z33__device_stub__multi_scale_kernelPKfS0_Pfii,@function
_Z33__device_stub__multi_scale_kernelPKfS0_Pfii: # @_Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18multi_scale_kernelPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__multi_scale_kernelPKfS0_Pfii, .Lfunc_end0-_Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18multi_scale_kernelPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18multi_scale_kernelPKfS0_Pfii,@object # @_Z18multi_scale_kernelPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z18multi_scale_kernelPKfS0_Pfii
.p2align 3, 0x0
_Z18multi_scale_kernelPKfS0_Pfii:
.quad _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.size _Z18multi_scale_kernelPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18multi_scale_kernelPKfS0_Pfii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__multi_scale_kernelPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18multi_scale_kernelPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel(double *Dens, double *VradInt, double *VthetaInt, double *TemperInt, int nrad, int nsec, double *invdiffRmed, double *invdiffRsup, double *DensInt, int Adiabatic, double *Rmed, double dt, double *VradNew, double *VthetaNew, double *Energy, double *EnergyInt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dens, densint, dxtheta, invdxtheta, dens2, tempint;
if (i>0 && i<nrad && j<nsec){
dens = Dens[i*nsec + j] + Dens[(i-1)*nsec + j];
densint = DensInt[i*nsec+j] - DensInt[(i-1)*nsec + j];
VradNew[i*nsec+j] = VradInt[i*nsec+j] - dt*2.0/dens*densint*invdiffRmed[i];
}
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
dens2 = Dens[i*nsec + j] + Dens[i*nsec + ((j-1)+nsec)%nsec];
tempint = (TemperInt[i*nsec+j] - TemperInt[i*nsec + ((j-1)+nsec)%nsec]);
VthetaNew[i*nsec + j] = VthetaInt[i*nsec + j] - dt*2.0/dens2*tempint*invdxtheta;
}
/* If gas disk is adiabatic, we add artificial viscosity as a source */
/* term for advection of thermal energy polargrid */
if (Adiabatic){
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
EnergyInt[i*nsec + j] = Energy[i*nsec + j] - dt*DensInt[i*nsec + j]* \
(VradInt[(i+1)*nsec + j] - VradInt[i*nsec + j])*invdiffRsup[i] - \
dt*TemperInt[i*nsec + j]*(VthetaInt[i*nsec + (j+1)%nsec] - VthetaInt[i*nsec + j])* invdxtheta;
}
}
} | .file "tmpxft_0012c599_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
.type _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_, @function
_Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movsd %xmm0, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 64(%rsp)
movq 344(%rsp), %rax
movq %rax, 56(%rsp)
movq 352(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 24(%rsp)
movq 384(%rsp), %rax
movq %rax, 16(%rsp)
movq 392(%rsp), %rax
movq %rax, 8(%rsp)
movq 400(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 76(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_, .-_Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
.globl _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.type _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, @function
_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, .-_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel(double *Dens, double *VradInt, double *VthetaInt, double *TemperInt, int nrad, int nsec, double *invdiffRmed, double *invdiffRsup, double *DensInt, int Adiabatic, double *Rmed, double dt, double *VradNew, double *VthetaNew, double *Energy, double *EnergyInt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dens, densint, dxtheta, invdxtheta, dens2, tempint;
if (i>0 && i<nrad && j<nsec){
dens = Dens[i*nsec + j] + Dens[(i-1)*nsec + j];
densint = DensInt[i*nsec+j] - DensInt[(i-1)*nsec + j];
VradNew[i*nsec+j] = VradInt[i*nsec+j] - dt*2.0/dens*densint*invdiffRmed[i];
}
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
dens2 = Dens[i*nsec + j] + Dens[i*nsec + ((j-1)+nsec)%nsec];
tempint = (TemperInt[i*nsec+j] - TemperInt[i*nsec + ((j-1)+nsec)%nsec]);
VthetaNew[i*nsec + j] = VthetaInt[i*nsec + j] - dt*2.0/dens2*tempint*invdxtheta;
}
/* If gas disk is adiabatic, we add artificial viscosity as a source */
/* term for advection of thermal energy polargrid */
if (Adiabatic){
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
EnergyInt[i*nsec + j] = Energy[i*nsec + j] - dt*DensInt[i*nsec + j]* \
(VradInt[(i+1)*nsec + j] - VradInt[i*nsec + j])*invdiffRsup[i] - \
dt*TemperInt[i*nsec + j]*(VthetaInt[i*nsec + (j+1)%nsec] - VthetaInt[i*nsec + j])* invdxtheta;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(double *Dens, double *VradInt, double *VthetaInt, double *TemperInt, int nrad, int nsec, double *invdiffRmed, double *invdiffRsup, double *DensInt, int Adiabatic, double *Rmed, double dt, double *VradNew, double *VthetaNew, double *Energy, double *EnergyInt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dens, densint, dxtheta, invdxtheta, dens2, tempint;
if (i>0 && i<nrad && j<nsec){
dens = Dens[i*nsec + j] + Dens[(i-1)*nsec + j];
densint = DensInt[i*nsec+j] - DensInt[(i-1)*nsec + j];
VradNew[i*nsec+j] = VradInt[i*nsec+j] - dt*2.0/dens*densint*invdiffRmed[i];
}
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
dens2 = Dens[i*nsec + j] + Dens[i*nsec + ((j-1)+nsec)%nsec];
tempint = (TemperInt[i*nsec+j] - TemperInt[i*nsec + ((j-1)+nsec)%nsec]);
VthetaNew[i*nsec + j] = VthetaInt[i*nsec + j] - dt*2.0/dens2*tempint*invdxtheta;
}
/* If gas disk is adiabatic, we add artificial viscosity as a source */
/* term for advection of thermal energy polargrid */
if (Adiabatic){
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
EnergyInt[i*nsec + j] = Energy[i*nsec + j] - dt*DensInt[i*nsec + j]* \
(VradInt[(i+1)*nsec + j] - VradInt[i*nsec + j])*invdiffRsup[i] - \
dt*TemperInt[i*nsec + j]*(VthetaInt[i*nsec + (j+1)%nsec] - VthetaInt[i*nsec + j])* invdxtheta;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(double *Dens, double *VradInt, double *VthetaInt, double *TemperInt, int nrad, int nsec, double *invdiffRmed, double *invdiffRsup, double *DensInt, int Adiabatic, double *Rmed, double dt, double *VradNew, double *VthetaNew, double *Energy, double *EnergyInt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dens, densint, dxtheta, invdxtheta, dens2, tempint;
if (i>0 && i<nrad && j<nsec){
dens = Dens[i*nsec + j] + Dens[(i-1)*nsec + j];
densint = DensInt[i*nsec+j] - DensInt[(i-1)*nsec + j];
VradNew[i*nsec+j] = VradInt[i*nsec+j] - dt*2.0/dens*densint*invdiffRmed[i];
}
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
dens2 = Dens[i*nsec + j] + Dens[i*nsec + ((j-1)+nsec)%nsec];
tempint = (TemperInt[i*nsec+j] - TemperInt[i*nsec + ((j-1)+nsec)%nsec]);
VthetaNew[i*nsec + j] = VthetaInt[i*nsec + j] - dt*2.0/dens2*tempint*invdxtheta;
}
/* If gas disk is adiabatic, we add artificial viscosity as a source */
/* term for advection of thermal energy polargrid */
if (Adiabatic){
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
EnergyInt[i*nsec + j] = Energy[i*nsec + j] - dt*DensInt[i*nsec + j]* \
(VradInt[(i+1)*nsec + j] - VradInt[i*nsec + j])*invdiffRsup[i] - \
dt*TemperInt[i*nsec + j]*(VthetaInt[i*nsec + (j+1)%nsec] - VthetaInt[i*nsec + j])* invdxtheta;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.globl _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.p2align 8
.type _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_,@function
_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_:
s_clause 0x4
s_load_b64 s[12:13], s[0:1], 0x50
s_load_b32 s2, s[0:1], 0x84
s_load_b64 s[18:19], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[16:17], s[0:1], 0x38
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[6:7], s[12:13], s[12:13]
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
v_cmp_gt_i32_e64 s2, s18, v2
v_cmp_lt_i32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s19, v0
s_and_b32 s8, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, s8, vcc_lo
s_and_saveexec_b32 s8, s9
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v1, -1, v2
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x28
s_load_b64 s[14:15], s[0:1], 0x58
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s19, v[0:1]
v_mad_u64_u32 v[8:9], null, v1, s19, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[4:5], 3, v[3:4]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[20:21], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v9, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v[12:13], off
v_add_co_u32 v14, vcc_lo, s16, v4
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
s_clause 0x1
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v22, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v23, vcc_lo, s7, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v20, vcc_lo, s10, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s11, v21, vcc_lo
global_load_b64 v[22:23], v[22:23], off
global_load_b64 v[20:21], v[20:21], off
s_waitcnt vmcnt(4)
v_add_f64 v[10:11], v[10:11], v[12:13]
s_waitcnt vmcnt(2)
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], v[6:7]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_div_scale_f64 v[18:19], vcc_lo, v[6:7], v[10:11], v[6:7]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
v_add_co_u32 v3, vcc_lo, s14, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[10:11], v[12:13], v[10:11], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[8:9]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[20:21], v[22:23]
global_store_b64 v[3:4], v[8:9], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_cvt_f64_i32_e32 v[4:5], s19
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[14:15], s[0:1], 0x48
v_mul_lo_u32 v1, v2, s19
v_ashrrev_i32_e32 v3, 31, v2
s_and_b32 s20, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s18, s20
s_cbranch_execz .LBB0_4
s_ashr_i32 s20, s19, 31
v_add3_u32 v9, s19, -1, v0
s_add_i32 s21, s19, s20
v_lshlrev_b64 v[16:17], 3, v[2:3]
s_xor_b32 s22, s21, s20
s_mov_b32 s21, 0x401921fb
v_cvt_f32_u32_e32 v8, s22
v_ashrrev_i32_e32 v11, 31, v9
s_sub_i32 s20, 0, s22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v8, v8
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v9, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x4f7ffffe, v8
v_cvt_u32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, s20, v8
s_mov_b32 s20, 0x54442d18
v_mul_hi_u32 v10, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v8, v10
v_mul_hi_u32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v8, s22
v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], s[20:21]
v_sub_nc_u32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v12, s22, v10
v_cmp_le_u32_e32 vcc_lo, s22, v10
v_cndmask_b32_e32 v10, v10, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v12, s22, v10
v_cmp_le_u32_e32 vcc_lo, s22, v10
v_cndmask_b32_e32 v10, v10, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s14, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v12, v10, v11
v_add_nc_u32_e32 v10, v1, v0
v_sub_nc_u32_e32 v14, v12, v11
v_rcp_f64_e32 v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v14, v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s4, v10
v_lshlrev_b64 v[14:15], 3, v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v20, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v15, vcc_lo
global_load_b64 v[16:17], v[16:17], off
s_clause 0x1
global_load_b64 v[18:19], v[18:19], off
global_load_b64 v[20:21], v[20:21], off
v_div_scale_f64 v[24:25], vcc_lo, s[20:21], v[4:5], s[20:21]
v_fma_f64 v[22:23], -v[8:9], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[22:23], v[12:13]
v_fma_f64 v[22:23], -v[8:9], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[22:23], v[12:13]
v_mul_f64 v[22:23], v[24:25], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[22:23], v[24:25]
v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[8:9], v[4:5], s[20:21]
s_waitcnt vmcnt(2)
v_mul_f64 v[8:9], v[8:9], v[16:17]
s_waitcnt vmcnt(0)
v_add_f64 v[12:13], v[18:19], v[20:21]
v_add_co_u32 v20, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v21, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
s_clause 0x1
global_load_b64 v[20:21], v[20:21], off
global_load_b64 v[14:15], v[14:15], off
v_add_co_u32 v30, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v31, vcc_lo, s9, v11, vcc_lo
global_load_b64 v[30:31], v[30:31], off
v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], -1.0
v_div_scale_f64 v[18:19], null, v[12:13], v[12:13], v[6:7]
v_div_scale_f64 v[32:33], vcc_lo, -1.0, v[8:9], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[22:23], v[16:17]
v_rcp_f64_e32 v[24:25], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[26:27], -v[16:17], v[22:23], 1.0
v_fma_f64 v[28:29], -v[18:19], v[24:25], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], -v[16:17], v[22:23], 1.0
v_fma_f64 v[28:29], -v[18:19], v[24:25], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
v_div_scale_f64 v[26:27], s4, v[6:7], v[12:13], v[6:7]
v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[28:29], v[32:33], v[22:23]
v_mul_f64 v[34:35], v[26:27], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[16:17], v[28:29], v[32:33]
v_fma_f64 v[18:19], -v[18:19], v[34:35], v[26:27]
s_waitcnt vmcnt(1)
v_add_f64 v[14:15], v[20:21], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[16:17], v[16:17], v[22:23], v[28:29]
s_mov_b32 vcc_lo, s4
s_load_b64 s[4:5], s[0:1], 0x60
v_div_fmas_f64 v[18:19], v[18:19], v[24:25], v[34:35]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[8:9], v[16:17], v[8:9], -1.0
v_div_fixup_f64 v[6:7], v[18:19], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], v[14:15]
s_waitcnt vmcnt(0)
v_fma_f64 v[6:7], v[8:9], v[6:7], v[30:31]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v11, vcc_lo
global_store_b64 v[8:9], v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s18
s_load_b32 s4, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x54442d18
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], s[2:3]
s_ashr_i32 s4, s19, 31
s_add_i32 s5, s19, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s15, v3, vcc_lo
v_div_scale_f64 v[14:15], vcc_lo, s[2:3], v[4:5], s[2:3]
s_xor_b32 s4, s5, s4
global_load_b64 v[10:11], v[10:11], off
s_sub_i32 s5, 0, s4
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_mul_f64 v[12:13], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
v_cvt_f32_u32_e32 v14, s4
v_rcp_iflag_f32_e32 v14, v14
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, 0x4f7ffffe, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v14, v14
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_mul_lo_u32 v9, s5, v14
v_add_nc_u32_e32 v8, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v16, 31, v8
v_mul_hi_u32 v9, v14, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v8, v16
v_xor_b32_e32 v15, v8, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v14, v9
v_add_nc_u32_e32 v8, v1, v0
v_mul_hi_u32 v0, v15, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, s19, v8
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_mul_lo_u32 v0, v0, s4
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s16, v8
v_sub_nc_u32_e32 v0, v15, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_subrev_nc_u32_e32 v14, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_load_b64 v[6:7], v[6:7], off
v_cndmask_b32_e32 v0, v0, v14, vcc_lo
v_add_co_u32 v14, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v17, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_clause 0x1
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[14:15], off
v_cndmask_b32_e32 v0, v0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v16
v_sub_nc_u32_e32 v0, v0, v16
s_waitcnt vmcnt(3)
v_mul_f64 v[4:5], v[4:5], v[10:11]
v_add_co_u32 v10, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v9, vcc_lo
v_add_nc_u32_e32 v0, v0, v1
v_add_co_u32 v16, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b64 v[10:11], v[10:11], off
s_clause 0x1
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[16:17], v[16:17], off
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x68
s_load_b64 s[0:1], s[0:1], 0x30
v_div_scale_f64 v[18:19], null, v[4:5], v[4:5], -1.0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v20, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[20:21], v[20:21], off
global_load_b64 v[2:3], v[2:3], off
v_div_scale_f64 v[26:27], vcc_lo, -1.0, v[4:5], -1.0
v_rcp_f64_e32 v[22:23], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[24:25], -v[18:19], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], v[22:23], v[24:25], v[22:23]
v_fma_f64 v[24:25], -v[18:19], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], v[22:23], v[24:25], v[22:23]
v_mul_f64 v[24:25], v[26:27], v[22:23]
s_waitcnt vmcnt(7)
v_mul_f64 v[6:7], v[6:7], s[12:13]
s_waitcnt vmcnt(5)
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], -v[18:19], v[24:25], v[26:27]
v_mul_f64 v[6:7], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[14:15], v[22:23], v[24:25]
s_waitcnt vmcnt(4)
v_mul_f64 v[10:11], v[10:11], s[12:13]
s_waitcnt vmcnt(2)
v_add_f64 v[0:1], v[0:1], -v[16:17]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[2:3], -v[2:3], v[6:7], v[20:21]
v_div_fixup_f64 v[4:5], v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[10:11], v[0:1]
v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v9, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 376
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, .Lfunc_end0-_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .offset: 120
.size: 4
.value_kind: hidden_block_count_x
- .offset: 124
.size: 4
.value_kind: hidden_block_count_y
- .offset: 128
.size: 4
.value_kind: hidden_block_count_z
- .offset: 132
.size: 2
.value_kind: hidden_group_size_x
- .offset: 134
.size: 2
.value_kind: hidden_group_size_y
- .offset: 136
.size: 2
.value_kind: hidden_group_size_z
- .offset: 138
.size: 2
.value_kind: hidden_remainder_x
- .offset: 140
.size: 2
.value_kind: hidden_remainder_y
- .offset: 142
.size: 2
.value_kind: hidden_remainder_z
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 184
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 376
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(double *Dens, double *VradInt, double *VthetaInt, double *TemperInt, int nrad, int nsec, double *invdiffRmed, double *invdiffRsup, double *DensInt, int Adiabatic, double *Rmed, double dt, double *VradNew, double *VthetaNew, double *Energy, double *EnergyInt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dens, densint, dxtheta, invdxtheta, dens2, tempint;
if (i>0 && i<nrad && j<nsec){
dens = Dens[i*nsec + j] + Dens[(i-1)*nsec + j];
densint = DensInt[i*nsec+j] - DensInt[(i-1)*nsec + j];
VradNew[i*nsec+j] = VradInt[i*nsec+j] - dt*2.0/dens*densint*invdiffRmed[i];
}
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
dens2 = Dens[i*nsec + j] + Dens[i*nsec + ((j-1)+nsec)%nsec];
tempint = (TemperInt[i*nsec+j] - TemperInt[i*nsec + ((j-1)+nsec)%nsec]);
VthetaNew[i*nsec + j] = VthetaInt[i*nsec + j] - dt*2.0/dens2*tempint*invdxtheta;
}
/* If gas disk is adiabatic, we add artificial viscosity as a source */
/* term for advection of thermal energy polargrid */
if (Adiabatic){
if (i<nrad && j<nsec){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
EnergyInt[i*nsec + j] = Energy[i*nsec + j] - dt*DensInt[i*nsec + j]* \
(VradInt[(i+1)*nsec + j] - VradInt[i*nsec + j])*invdiffRsup[i] - \
dt*TemperInt[i*nsec + j]*(VthetaInt[i*nsec + (j+1)%nsec] - VthetaInt[i*nsec + j])* invdxtheta;
}
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_ # -- Begin function _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_,@function
_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_: # @_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movsd %xmm0, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 280(%rsp), %rax
movq %rax, 192(%rsp)
leaq 288(%rsp), %rax
movq %rax, 200(%rsp)
leaq 296(%rsp), %rax
movq %rax, 208(%rsp)
leaq 304(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_,@object # @_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.p2align 3, 0x0
_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.quad _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.size _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c599_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
.type _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_, @function
_Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movsd %xmm0, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 64(%rsp)
movq 344(%rsp), %rax
movq %rax, 56(%rsp)
movq 352(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 24(%rsp)
movq 384(%rsp), %rax
movq %rax, 16(%rsp)
movq 392(%rsp), %rax
movq %rax, 8(%rsp)
movq 400(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 76(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_, .-_Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
.globl _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.type _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, @function
_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z51__device_stub__Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_PdS_S_S_iiS_S_S_iS_dS_S_S_S_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, .-_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_ # -- Begin function _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_,@function
_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_: # @_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movsd %xmm0, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 280(%rsp), %rax
movq %rax, 192(%rsp)
leaq 288(%rsp), %rax
movq %rax, 200(%rsp)
leaq 296(%rsp), %rax
movq %rax, 208(%rsp)
leaq 304(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_,@object # @_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.p2align 3, 0x0
_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_:
.quad _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.size _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_S_iiS_S_S_iS_dS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} | code for sm_80
Function : _Z6reduceP7double4S0_S0_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fe200078e0205 */
/*0070*/ SHF.L.U32 R0, R5, 0x5, RZ ; /* 0x0000000505007819 */
/* 0x000fc800000006ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x2e0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R5, R3, 0x1, RZ ; /* 0x0000000103057819 */
/* 0x000fc800000006ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06070 */
/*00c0*/ @!P0 BRA 0x1e0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.IADD R20, R2.reuse, 0x1, -R3 ; /* 0x0000000102147824 */
/* 0x040fe200078e0a03 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IADD3 R2, R2, -R5, RZ ; /* 0x8000000502027210 */
/* 0x000fd20007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fc800078e0003 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0003 */
/*0120*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1d00 */
/*0130*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0140*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000f28000c1e1d00 */
/*0150*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1d00 */
/*0160*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x004fe20000000c00 */
/*0170*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0180*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e220000000004 */
/*0190*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x010fe60000000c00 */
/*01a0*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x020e460000000008 */
/*01b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*01c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x20 ; /* 0x00000020ff047424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R3, R2, -R3, RZ ; /* 0x8000000302037210 */
/* 0x000fc60007ffe0ff */
/*0200*/ IMAD.WIDE.U32 R20, R2, R4, c[0x0][0x168] ; /* 0x00005a0002147625 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0004 */
/*0220*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000ea8000c1e1d00 */
/*0230*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1d00 */
/*0240*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0250*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f28000c1e1d00 */
/*0260*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x004fe20000000c00 */
/*0270*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0280*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e080000000004 */
/*0290*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x010e620000000008 */
/*02a0*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x000fe80000000c00 */
/*02b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*02c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R20, R2, R3, RZ ; /* 0x0000000302147210 */
/* 0x000fe40007ffe0ff */
/*02f0*/ MOV R3, 0x20 ; /* 0x0000002000037802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc800078e0003 */
/*0310*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0320*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1d00 */
/*0330*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0340*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000f28000c1e1d00 */
/*0350*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1d00 */
/*0360*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x004fe20000000c00 */
/*0370*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0380*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e220000000004 */
/*0390*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x010fe60000000c00 */
/*03a0*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x020e460000000008 */
/*03b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*03c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} | .file "tmpxft_0015257b_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
.type _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj, @function
_Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reduceP7double4S0_S0_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj, .-_Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
.globl _Z6reduceP7double4S0_S0_jj
.type _Z6reduceP7double4S0_S0_jj, @function
_Z6reduceP7double4S0_S0_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6reduceP7double4S0_S0_jj, .-_Z6reduceP7double4S0_S0_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reduceP7double4S0_S0_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reduceP7double4S0_S0_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.globl _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 8
.type _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@function
_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[7:8], null, s15, s4, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_u32_e64 s2, v7
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v11, s2, v7
s_lshl_b32 s5, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_le_u32_e64 s5, v7
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_subrev_nc_u32_e32 v1, s5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v12, v2
v_lshlrev_b64 v[1:2], 5, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 5, v[11:12]
v_lshl_add_u32 v12, v0, 5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[3:4], off
global_load_b128 v[17:20], v[3:4], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mov_b32_e32 v8, v12
s_waitcnt vmcnt(1)
v_lshlrev_b64 v[3:4], 5, v[11:12]
v_lshl_add_u32 v12, v0, 5, 0
v_lshlrev_b64 v[1:2], 5, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[1:2], off
global_load_b128 v[17:20], v[1:2], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v8, 0
v_lshl_add_u32 v12, v0, 5, 0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 5, v[7:8]
v_add_nc_u32_e32 v7, s2, v7
v_lshlrev_b64 v[3:4], 5, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[3:4], off
global_load_b128 v[17:20], v[3:4], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_lshl_add_u32 v0, v0, 5, 0
ds_load_b64 v[7:8], v12
ds_load_2addr_b64 v[11:14], v0 offset0:1 offset1:2
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[0:1], v[1:2], v[7:8]
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[3:4], v[11:12]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[9:10], v[13:14]
s_clause 0x1
global_store_b128 v[5:6], v[0:3], off
global_store_b64 v[5:6], v[7:8], off offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, .Lfunc_end0-_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double4 *ac, double4 *ac1, double4 *ac2, unsigned int bf_real, unsigned int dimension){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int k = dimension*bf_real;
double4 myacc;
extern __shared__ double4 shaccelerations[];
double4 *shacc = (double4*) shaccelerations;
if(i < k){
myacc = ac[i];
shacc[threadIdx.x] = ac[i + k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac[i] = myacc;
}
else if (i >= k && i < 2*k){
myacc = ac1[i - k];
shacc[threadIdx.x] = ac1[i];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac1[i - k] = myacc;
}
else {
myacc = ac2[i - 2*k];
shacc[threadIdx.x] = ac2[i - k];
myacc.x += shacc[threadIdx.x].x;
myacc.y += shacc[threadIdx.x].y;
myacc.z += shacc[threadIdx.x].z;
ac2[i - 2*k] = myacc;
}
} | .text
.file "reduce.hip"
.globl _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj # -- Begin function _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 4, 0x90
.type _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@function
_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj: # @_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj, .Lfunc_end0-_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@object # @_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.section .rodata,"a",@progbits
.globl _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 3, 0x0
_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj:
.quad _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.size _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reduceP7double4S0_S0_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fe200078e0205 */
/*0070*/ SHF.L.U32 R0, R5, 0x5, RZ ; /* 0x0000000505007819 */
/* 0x000fc800000006ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x2e0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R5, R3, 0x1, RZ ; /* 0x0000000103057819 */
/* 0x000fc800000006ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06070 */
/*00c0*/ @!P0 BRA 0x1e0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.IADD R20, R2.reuse, 0x1, -R3 ; /* 0x0000000102147824 */
/* 0x040fe200078e0a03 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IADD3 R2, R2, -R5, RZ ; /* 0x8000000502027210 */
/* 0x000fd20007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fc800078e0003 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0003 */
/*0120*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1d00 */
/*0130*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0140*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000f28000c1e1d00 */
/*0150*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1d00 */
/*0160*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x004fe20000000c00 */
/*0170*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0180*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e220000000004 */
/*0190*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x010fe60000000c00 */
/*01a0*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x020e460000000008 */
/*01b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*01c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x20 ; /* 0x00000020ff047424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R3, R2, -R3, RZ ; /* 0x8000000302037210 */
/* 0x000fc60007ffe0ff */
/*0200*/ IMAD.WIDE.U32 R20, R2, R4, c[0x0][0x168] ; /* 0x00005a0002147625 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0004 */
/*0220*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000ea8000c1e1d00 */
/*0230*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1d00 */
/*0240*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0250*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f28000c1e1d00 */
/*0260*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x004fe20000000c00 */
/*0270*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0280*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e080000000004 */
/*0290*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x010e620000000008 */
/*02a0*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x000fe80000000c00 */
/*02b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*02c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R20, R2, R3, RZ ; /* 0x0000000302147210 */
/* 0x000fe40007ffe0ff */
/*02f0*/ MOV R3, 0x20 ; /* 0x0000002000037802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc800078e0003 */
/*0310*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0320*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1d00 */
/*0330*/ LDG.E.128 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee8000c1e1d00 */
/*0340*/ LDG.E.128 R8, [R20.64+0x10] ; /* 0x0000100414087981 */
/* 0x000f28000c1e1d00 */
/*0350*/ LDG.E.128 R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1d00 */
/*0360*/ STS.128 [R0], R4 ; /* 0x0000000400007388 */
/* 0x004fe20000000c00 */
/*0370*/ DADD R18, R18, R6 ; /* 0x0000000012127229 */
/* 0x008fc80000000006 */
/*0380*/ DADD R16, R16, R4 ; /* 0x0000000010107229 */
/* 0x000e220000000004 */
/*0390*/ STS.128 [R0+0x10], R8 ; /* 0x0000100800007388 */
/* 0x010fe60000000c00 */
/*03a0*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x020e460000000008 */
/*03b0*/ STG.E.128 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x001fe8000c101d04 */
/*03c0*/ STG.E.128 [R2.64+0x10], R12 ; /* 0x0000100c02007986 */
/* 0x002fe2000c101d04 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.globl _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 8
.type _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@function
_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[7:8], null, s15, s4, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_u32_e64 s2, v7
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v11, s2, v7
s_lshl_b32 s5, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_le_u32_e64 s5, v7
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_subrev_nc_u32_e32 v1, s5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v12, v2
v_lshlrev_b64 v[1:2], 5, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 5, v[11:12]
v_lshl_add_u32 v12, v0, 5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[3:4], off
global_load_b128 v[17:20], v[3:4], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mov_b32_e32 v8, v12
s_waitcnt vmcnt(1)
v_lshlrev_b64 v[3:4], 5, v[11:12]
v_lshl_add_u32 v12, v0, 5, 0
v_lshlrev_b64 v[1:2], 5, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[1:2], off
global_load_b128 v[17:20], v[1:2], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v8, 0
v_lshl_add_u32 v12, v0, 5, 0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 5, v[7:8]
v_add_nc_u32_e32 v7, s2, v7
v_lshlrev_b64 v[3:4], 5, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
s_clause 0x3
global_load_b128 v[13:16], v[3:4], off
global_load_b128 v[17:20], v[3:4], off offset:16
global_load_b128 v[1:4], v[5:6], off
global_load_b64 v[9:10], v[5:6], off offset:16
s_waitcnt vmcnt(3)
ds_store_b128 v12, v[13:16]
s_waitcnt vmcnt(2)
ds_store_b128 v12, v[17:20] offset:16
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_lshl_add_u32 v0, v0, 5, 0
ds_load_b64 v[7:8], v12
ds_load_2addr_b64 v[11:14], v0 offset0:1 offset1:2
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[0:1], v[1:2], v[7:8]
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[3:4], v[11:12]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[9:10], v[13:14]
s_clause 0x1
global_store_b128 v[5:6], v[0:3], off
global_store_b64 v[5:6], v[7:8], off offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, .Lfunc_end0-_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015257b_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
.type _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj, @function
_Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reduceP7double4S0_S0_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj, .-_Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
.globl _Z6reduceP7double4S0_S0_jj
.type _Z6reduceP7double4S0_S0_jj, @function
_Z6reduceP7double4S0_S0_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z6reduceP7double4S0_S0_jjP7double4S0_S0_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6reduceP7double4S0_S0_jj, .-_Z6reduceP7double4S0_S0_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reduceP7double4S0_S0_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reduceP7double4S0_S0_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce.hip"
.globl _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj # -- Begin function _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 4, 0x90
.type _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@function
_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj: # @_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj, .Lfunc_end0-_Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj,@object # @_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.section .rodata,"a",@progbits
.globl _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.p2align 3, 0x0
_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj:
.quad _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.size _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reduceP15HIP_vector_typeIdLj4EES1_S1_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /// LSU EE 7700-2 (Spring 2013), GPU Microarchitecture
//
/// Homework 3
//
// Assignment in: http://www.ece.lsu.edu/koppel/gp/2013/hw03.pdf
//
/// Your Name:
#include <pthread.h>
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <ctype.h>
#include <time.h>
#include <new>
#include <cuda_runtime.h>
#define N 4
/// CUDA API Error-Checking Wrapper
///
#define CE(call) \
{ \
const cudaError_t rv = call; \
if ( rv != cudaSuccess ) \
{ \
printf("CUDA error %d, %s\n",rv,cudaGetErrorString(rv)); \
exit(1); \
} \
}
double
time_fp()
{
struct timespec tp;
clock_gettime(CLOCK_REALTIME,&tp);
return ((double)tp.tv_sec)+((double)tp.tv_nsec) * 0.000000001;
}
// Make it easy to switch between float and double for vertex and matrix
// elements.
//
typedef float Elt_Type;
struct __align__(16) Vertex
{
Elt_Type a[N];
};
struct App
{
int num_threads;
Elt_Type matrix[N][N];
int array_size; // Number of vertices.
bool find_minimum_magnitude; // For problem 2.
Vertex *v_in, *v_out;
Vertex *d_v_in, *d_v_out;
};
// In host address space.
App app;
// In device constant address space.
__constant__ App d_app;
// The entry point for the GPU code.
//
__global__ void
cuda_thread_start()
{
// Compute an id number that will be in the range from 0 to num_threads-1.
//
const int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Number of elements that each thread should work on. We are ignoring
// rounding errors.
//
const int elt_per_thread = d_app.array_size / d_app.num_threads;
/// WARNING:
//
// The order in which the threads examine elements here is poorly
// chosen and will unnecessarily make inefficient use of the memory
// system.
// Compute element number to start at.
//
const int start = elt_per_thread * tid;
// Compute element number to stop at.
//
const int stop = start + elt_per_thread;
// WARNING: This code accesses elements in an inefficient order.
for ( int h=start; h<stop; h++ )
{
Vertex p = d_app.d_v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += d_app.matrix[i][j] * p.a[j];
}
d_app.d_v_out[h] = q;
}
}
void
print_gpu_info()
{
// Get information about GPU and its ability to run CUDA.
//
int device_count;
cudaGetDeviceCount(&device_count); // Get number of GPUs.
if ( device_count == 0 )
{
fprintf(stderr,"No GPU found, exiting.\n");
exit(1);
}
int dev = 0;
CE(cudaGetDevice(&dev));
printf("Using GPU %d\n",dev);
cudaDeviceProp cuda_prop; // Properties of cuda device (GPU, cuda version).
/// Print information about the available GPUs.
//
{
CE(cudaGetDeviceProperties(&cuda_prop,dev));
printf
("GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n",
dev, cuda_prop.name, cuda_prop.clockRate/1e6,
int(cuda_prop.totalGlobalMem >> 20));
printf
("GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n",
dev, cuda_prop.major, cuda_prop.minor,
cuda_prop.multiProcessorCount,
cuda_prop.warpSize,
cuda_prop.maxThreadsPerBlock
);
printf
("GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n",
dev,
int(cuda_prop.sharedMemPerBlock), int(cuda_prop.totalConstMem),
cuda_prop.regsPerBlock
);
}
cudaFuncAttributes cfa_prob1; // Properties of code to run on device.
CE( cudaFuncGetAttributes(&cfa_prob1,cuda_thread_start) );
// Print information about time_step routine.
//
printf("\nCUDA Routine Resource Usage:\n");
printf(" Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; "
"%d max threads per block.\n",
cfa_prob1.sharedSizeBytes,
cfa_prob1.constSizeBytes,
cfa_prob1.localSizeBytes,
cfa_prob1.numRegs,
cfa_prob1.maxThreadsPerBlock);
}
void*
pt_thread_start(void *arg)
{
const int tid = (ptrdiff_t) arg;
printf("Hello from %d\n",tid);
const int elt_per_thread = app.array_size / app.num_threads;
const int start = elt_per_thread * tid;
const int stop = start + elt_per_thread;
for ( int h=start; h<stop; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
app.v_out[h] = q;
}
return NULL;
}
int
main(int argc, char **argv)
{
// Examine argument 1, block size, if negative, find minimum magnitude.
//
const int arg1_int = argc < 2 ? 1 : atoi(argv[1]);
const bool find_mag = arg1_int < 0;
const int num_blocks = abs(arg1_int);
const bool use_pthreads = false;
// For Problem 2.
app.find_minimum_magnitude = find_mag;
// Examine argument 2, number of threads per block.
//
const int thd_per_block = argc < 3 ? 1 : atoi(argv[2]);
app.num_threads = use_pthreads ? -arg1_int : num_blocks * thd_per_block;
// Examine argument 3, size of array in MiB. Fractional values okay.
//
app.array_size = argc < 4 ? 1 << 20 : int( atof(argv[3]) * (1<<20) );
if ( app.num_threads <= 0 || app.array_size <= 0 )
{
printf("Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n",
argv[0]);
exit(1);
}
if ( !use_pthreads )
print_gpu_info();
const int array_size_bytes = app.array_size * sizeof(app.v_in[0]);
// Allocate storage for CPU copy of data.
//
app.v_in = new Vertex[app.array_size];
app.v_out = new Vertex[app.array_size];
// Allocate storage for GPU copy of data.
//
CE( cudaMalloc( &app.d_v_in, app.array_size * sizeof(Vertex) ) );
CE( cudaMalloc( &app.d_v_out, app.array_size * sizeof(Vertex) ) );
printf
("\nPreparing for %d %s threads operating on %d vectors of %d elements.\n",
app.num_threads,
use_pthreads ? "CPU" : "GPU",
app.array_size, N);
// Initialize input array.
//
for ( int i=0; i<app.array_size; i++ )
for ( int j=0; j<N; j++ ) app.v_in[i].a[j] = drand48();
// Initialize transformation matrix.
//
for ( int i=0; i<N; i++ )
for ( int j=0; j<N; j++ )
app.matrix[i][j] = drand48();
double elapsed_time_s;
int minimum_mag_index = 0; // For Problem 2.
Elt_Type minimum_mag_val = 0; // For Problem 2.
if ( use_pthreads )
{
const double time_start = time_fp();
// Allocate a structure to hold pthread thread ids.
//
pthread_t* const ptid = new pthread_t[app.num_threads];
// Set up a pthread attribute, used for specifying options.
//
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
// Launch the threads.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_create(&ptid[i], &attr, pt_thread_start, (void*)i);
// Wait for each thread to finish.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_join( ptid[i], NULL );
elapsed_time_s = time_fp() - time_start;
}
else
{
// Prepare events used for timing.
//
cudaEvent_t gpu_start_ce, gpu_stop_ce;
CE(cudaEventCreate(&gpu_start_ce));
CE(cudaEventCreate(&gpu_stop_ce));
// Copy input array from CPU to GPU.
//
CE( cudaMemcpy
( app.d_v_in, app.v_in, array_size_bytes, cudaMemcpyHostToDevice ) );
// Copy App structure to GPU.
//
CE( cudaMemcpyToSymbol
( d_app, &app, sizeof(app), 0, cudaMemcpyHostToDevice ) );
// Measure execution time starting "now", which is after data
// set to GPU.
//
CE(cudaEventRecord(gpu_start_ce,0));
printf("Launching with %d blocks of %d threads.\n",
num_blocks, thd_per_block);
// Tell CUDA to start our threads on the GPU.
//
cuda_thread_start<<<num_blocks,thd_per_block>>>();
// Stop measuring execution time now, which is before is data
// returned from GPU.
//
CE(cudaEventRecord(gpu_stop_ce,0));
CE(cudaEventSynchronize(gpu_stop_ce));
float cuda_time_ms = -1.1;
CE(cudaEventElapsedTime(&cuda_time_ms,gpu_start_ce,gpu_stop_ce));
elapsed_time_s = cuda_time_ms * 0.001;
// Copy output array from GPU to CPU.
//
CE( cudaMemcpy
( app.v_out, app.d_v_out, array_size_bytes, cudaMemcpyDeviceToHost) );
// PROBLEM 2
//
// Insert code for reading magnitude information and having
// CPU finish up finding the minimum.
minimum_mag_index = -1; // PROBLEM 2 - change this line.
minimum_mag_val = 0.0; // PROBLEM 2 - change this line too.
}
const double data_size = app.array_size * sizeof(Vertex) * 2;
const double fp_op_count = app.array_size * ( 2 * N * N - N );
printf("Elapsed time for %d threads and %d elements is %.3f µs\n",
app.num_threads, app.array_size, 1e6 * elapsed_time_s);
printf("Rate %.3f GFLOPS, %.3f GB/s\n",
1e-9 * fp_op_count / elapsed_time_s,
1e-9 * data_size / elapsed_time_s);
if ( app.find_minimum_magnitude )
{
// Compute correct answer.
Elt_Type min_val = 0;
int min_idx = -1;
for ( int h=0; h<app.array_size; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
Elt_Type sos = 0; for(int i=0; i<N; i++ ) sos+= q.a[i]*q.a[i];
Elt_Type mag = sqrt(sos);
if ( min_idx < 0 || mag < min_val ) { min_val = mag; min_idx = h; }
}
Elt_Type diff = fabs(min_val-minimum_mag_val);
printf
("\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n",
diff < 1e-5 ? "correct" : "**wrong**",
minimum_mag_index,
min_idx == minimum_mag_index ? "==" : "!=",
min_idx,
minimum_mag_val,
min_val == minimum_mag_val ? "==" : diff < 1e-5 ? "~" : "!=",
min_val
);
}
} | .file "tmpxft_000a4712_00000000-6_hw3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7time_fpv
.type _Z7time_fpv, @function
_Z7time_fpv:
.LFB2094:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z7time_fpv, .-_Z7time_fpv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "No GPU found, exiting.\n"
.LC2:
.string "CUDA error %d, %s\n"
.LC3:
.string "Using GPU %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n"
.align 8
.LC6:
.string "GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n"
.align 8
.LC7:
.string "GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n"
.align 8
.LC8:
.string "\nCUDA Routine Resource Usage:\n"
.align 8
.LC9:
.string " Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; %d max threads per block.\n"
.text
.globl _Z14print_gpu_infov
.type _Z14print_gpu_infov, @function
_Z14print_gpu_infov:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1200, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
je .L14
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L15
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
movq 448(%rsp), %r8
shrq $20, %r8
pxor %xmm0, %xmm0
cvtsi2sdl 508(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq 160(%rsp), %rcx
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 480(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1224
movl 476(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1232
movl 564(%rsp), %r9d
movl 540(%rsp), %r8d
movl 536(%rsp), %ecx
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1216
movl 464(%rsp), %r9d
movl 512(%rsp), %r8d
movl 456(%rsp), %ecx
movl 12(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
leaq _Z17cuda_thread_startv(%rip), %rsi
call cudaFuncGetAttributes@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L17
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 1224
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1232
movl 60(%rsp), %r9d
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1216
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $1200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z14print_gpu_infov, .-_Z14print_gpu_infov
.section .rodata.str1.1
.LC11:
.string "Hello from %d\n"
.text
.globl _Z15pt_thread_startPv
.type _Z15pt_thread_startPv, @function
_Z15pt_thread_startPv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl 68+app(%rip), %eax
cltd
idivl app(%rip)
movl %ebx, %edx
imull %eax, %edx
leal (%rax,%rdx), %ecx
cmpl %ecx, %edx
jge .L20
movslq %edx, %rdx
movq %rdx, %r8
salq $4, %r8
movl %eax, %r11d
addq %rdx, %r11
salq $4, %r11
leaq app(%rip), %r10
leaq 64(%r10), %r9
movq %rsp, %rcx
jmp .L23
.L29:
movq 88(%r10), %rax
movdqa 16(%rsp), %xmm3
movaps %xmm3, (%rax,%r8)
addq $16, %r8
cmpq %r11, %r8
je .L20
.L23:
movq 80(%r10), %rax
movdqa (%rax,%r8), %xmm2
movaps %xmm2, (%rsp)
leaq 16(%rsp), %rsi
movq %r10, %rdx
.L22:
movq %rsi, %rdi
movl $0, %eax
pxor %xmm1, %xmm1
.L21:
movss 4(%rdx,%rax), %xmm0
mulss (%rax,%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $16, %rax
jne .L21
movss %xmm1, (%rdi)
addq $4, %rsi
addq $16, %rdx
cmpq %r9, %rdx
jne .L22
jmp .L29
.L20:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z15pt_thread_startPv, .-_Z15pt_thread_startPv
.globl _Z36__device_stub__Z17cuda_thread_startvv
.type _Z36__device_stub__Z17cuda_thread_startvv, @function
_Z36__device_stub__Z17cuda_thread_startvv:
.LFB2122:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17cuda_thread_startv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2122:
.size _Z36__device_stub__Z17cuda_thread_startvv, .-_Z36__device_stub__Z17cuda_thread_startvv
.globl _Z17cuda_thread_startv
.type _Z17cuda_thread_startv, @function
_Z17cuda_thread_startv:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17cuda_thread_startvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z17cuda_thread_startv, .-_Z17cuda_thread_startv
.section .rodata.str1.1
.LC12:
.string "=="
.LC13:
.string "!="
.LC15:
.string "correct"
.LC16:
.string "**wrong**"
.LC17:
.string "~"
.section .rodata.str1.8
.align 8
.LC19:
.string "Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n"
.section .rodata.str1.1
.LC20:
.string "GPU"
.section .rodata.str1.8
.align 8
.LC21:
.string "\nPreparing for %d %s threads operating on %d vectors of %d elements.\n"
.align 8
.LC22:
.string "Launching with %d blocks of %d threads.\n"
.align 8
.LC25:
.string "Elapsed time for %d threads and %d elements is %.3f \302\265s\n"
.section .rodata.str1.1
.LC26:
.string "Rate %.3f GFLOPS, %.3f GB/s\n"
.section .rodata.str1.8
.align 8
.LC29:
.string "\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n"
.text
.globl main
.type main, @function
main:
.LFB2097:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L114
movb $0, 72+app(%rip)
movl $1, %r14d
.L41:
movl %r14d, app(%rip)
movl $1, %r15d
movl $1048576, %eax
.L42:
movl %eax, 68+app(%rip)
cmpl $0, app(%rip)
jle .L97
testl %eax, %eax
jle .L97
call _Z14print_gpu_infov
movl 68+app(%rip), %eax
movslq %eax, %rdi
sall $4, %eax
movl %eax, (%rsp)
movq %rdi, %rax
shrq $59, %rax
jne .L45
salq $4, %rdi
call _Znam@PLT
movq %rax, 80+app(%rip)
movslq 68+app(%rip), %rdi
movq %rdi, %rax
shrq $59, %rax
jne .L115
salq $4, %rdi
call _Znam@PLT
movq %rax, 88+app(%rip)
movslq 68+app(%rip), %rsi
salq $4, %rsi
leaq 96+app(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L116
movslq 68+app(%rip), %rsi
salq $4, %rsi
leaq 104+app(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L117
movl $4, %r9d
movl 68+app(%rip), %r8d
leaq .LC20(%rip), %rcx
movl app(%rip), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
cmpl $0, 68+app(%rip)
jg .L53
.L54:
leaq app(%rip), %r12
leaq 16(%r12), %rbp
leaq 64(%rbp), %r13
.L56:
leaq -16(%rbp), %rbx
.L57:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L57
addq $16, %rbp
cmpq %r13, %rbp
jne .L56
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L118
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L119
movslq (%rsp), %rbp
movl $1, %ecx
movq %rbp, %rdx
movq 80+app(%rip), %rsi
movq 96+app(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L120
movl $1, %r8d
movl $0, %ecx
movl $112, %edx
leaq app(%rip), %rsi
leaq _ZL5d_app(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L121
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L122
movl %r15d, %ecx
movl %r14d, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r14d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L123
.L64:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L124
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L125
movl $0xbf8ccccd, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L126
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
mulsd .LC24(%rip), %xmm0
movsd %xmm0, (%rsp)
movl $2, %ecx
movq %rbp, %rdx
movq 104+app(%rip), %rsi
movq 88+app(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L127
movl 68+app(%rip), %ecx
movslq %ecx, %rax
salq $5, %rax
js .L69
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
.L70:
imull $28, %ecx, %eax
pxor %xmm7, %xmm7
cvtsi2sdl %eax, %xmm7
movsd %xmm7, 8(%rsp)
movsd (%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
movl app(%rip), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC0(%rip), %xmm0
movq %rbx, %xmm1
mulsd %xmm0, %xmm1
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm5
divsd %xmm5, %xmm0
divsd %xmm5, %xmm1
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
cmpb $0, 72+app(%rip)
je .L71
movl 68+app(%rip), %r15d
testl %r15d, %r15d
jle .L90
movslq %r15d, %r15
movl $0, %ebx
movl $0x00000000, (%rsp)
movl $-1, %r13d
leaq 64(%r12), %rbp
jmp .L80
.L114:
movl %edi, %ebx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
negl %r14d
cmovs %eax, %r14d
shrl $31, %eax
movb %al, 72+app(%rip)
cmpl $2, %ebx
jle .L41
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
imull %r14d, %eax
movl %eax, app(%rip)
cmpl $3, %ebx
jle .L88
movq 24(%rbp), %rdi
movl $0, %esi
call strtod@PLT
mulsd .LC18(%rip), %xmm0
cvttsd2sil %xmm0, %eax
jmp .L42
.L88:
movl $1048576, %eax
jmp .L42
.L97:
movq 0(%rbp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
call __cxa_throw_bad_array_new_length@PLT
.L115:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
call __cxa_throw_bad_array_new_length@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L117:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L128:
addq $1, %r12
cmpl %r12d, 68+app(%rip)
jle .L54
.L53:
movq %r12, %rbp
salq $4, %rbp
movl $0, %ebx
.L55:
call drand48@PLT
movslq %ebx, %rax
salq $2, %rax
addq 80+app(%rip), %rax
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax,%rbp)
addl $1, %ebx
cmpl $4, %ebx
jne .L55
jmp .L128
.L118:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L119:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L120:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L121:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L122:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L123:
call _Z36__device_stub__Z17cuda_thread_startvv
jmp .L64
.L124:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L125:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L126:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L127:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
shrq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
movq %xmm1, %rbx
jmp .L70
.L110:
call sqrtf@PLT
jmp .L78
.L91:
movl %r14d, %r13d
movss %xmm0, (%rsp)
.L79:
addq $1, %rbx
cmpq %r15, %rbx
je .L129
.L80:
movl %ebx, %r14d
movq %rbx, %rax
salq $4, %rax
addq 80+app(%rip), %rax
movdqa (%rax), %xmm3
movaps %xmm3, 64(%rsp)
leaq 80(%rsp), %rcx
movq %r12, %rdx
movq %rcx, %rdi
leaq 64(%rsp), %rsi
.L74:
movq %rdi, %r8
movl $0, %eax
pxor %xmm1, %xmm1
.L73:
movss 4(%rdx,%rax), %xmm0
mulss (%rax,%rsi), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $16, %rax
jne .L73
movss %xmm1, (%r8)
addq $4, %rdi
addq $16, %rdx
cmpq %rbp, %rdx
jne .L74
leaq 16(%rcx), %rax
pxor %xmm0, %xmm0
.L75:
movss (%rcx), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rcx
cmpq %rax, %rcx
jne .L75
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L110
sqrtss %xmm0, %xmm0
.L78:
testl %r13d, %r13d
js .L91
movss (%rsp), %xmm4
comiss %xmm0, %xmm4
cmova %r14d, %r13d
minss %xmm4, %xmm0
movss %xmm0, (%rsp)
jmp .L79
.L129:
movss (%rsp), %xmm6
movaps %xmm6, %xmm0
andps .LC27(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm6, %xmm1
pxor %xmm2, %xmm2
ucomiss %xmm2, %xmm6
jp .L99
je .L81
.L99:
cvtss2sd %xmm0, %xmm0
movsd .LC28(%rip), %xmm2
comisd %xmm0, %xmm2
ja .L83
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
leaq .LC16(%rip), %rdx
cmpl $-1, %r13d
je .L85
movq %rax, %r8
jmp .L85
.L81:
cmpl $-1, %r13d
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
cmovne %rax, %r8
.L72:
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rax
movsd .LC28(%rip), %xmm2
comisd %xmm0, %xmm2
leaq .LC15(%rip), %rdx
leaq .LC16(%rip), %rcx
cmovbe %rcx, %rdx
.L85:
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %rax
.cfi_def_cfa_offset 192
pxor %xmm0, %xmm0
movl %r13d, %r9d
movl $-1, %ecx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
.L71:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L130
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
movl $-1, %r13d
pxor %xmm0, %xmm0
pxor %xmm1, %xmm1
leaq .LC12(%rip), %r8
jmp .L72
.L83:
cmpl $-1, %r13d
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
cmovne %rax, %r8
leaq .LC17(%rip), %rax
leaq .LC15(%rip), %rdx
jmp .L85
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size main, .-main
.section .rodata.str1.1
.LC30:
.string "_Z17cuda_thread_startv"
.LC31:
.string "d_app"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2125:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_thread_startv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $112, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5d_app(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5d_app
.comm _ZL5d_app,112,32
.globl app
.bss
.align 32
.type app, @object
.size app, 112
app:
.zero 112
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -400107883
.long 1041313291
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC18:
.long 0
.long 1093664768
.align 8
.LC24:
.long -755914244
.long 1062232653
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC27:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC28:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /// LSU EE 7700-2 (Spring 2013), GPU Microarchitecture
//
/// Homework 3
//
// Assignment in: http://www.ece.lsu.edu/koppel/gp/2013/hw03.pdf
//
/// Your Name:
#include <pthread.h>
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <ctype.h>
#include <time.h>
#include <new>
#include <cuda_runtime.h>
#define N 4
/// CUDA API Error-Checking Wrapper
///
#define CE(call) \
{ \
const cudaError_t rv = call; \
if ( rv != cudaSuccess ) \
{ \
printf("CUDA error %d, %s\n",rv,cudaGetErrorString(rv)); \
exit(1); \
} \
}
double
time_fp()
{
struct timespec tp;
clock_gettime(CLOCK_REALTIME,&tp);
return ((double)tp.tv_sec)+((double)tp.tv_nsec) * 0.000000001;
}
// Make it easy to switch between float and double for vertex and matrix
// elements.
//
typedef float Elt_Type;
struct __align__(16) Vertex
{
Elt_Type a[N];
};
struct App
{
int num_threads;
Elt_Type matrix[N][N];
int array_size; // Number of vertices.
bool find_minimum_magnitude; // For problem 2.
Vertex *v_in, *v_out;
Vertex *d_v_in, *d_v_out;
};
// In host address space.
App app;
// In device constant address space.
__constant__ App d_app;
// The entry point for the GPU code.
//
__global__ void
cuda_thread_start()
{
// Compute an id number that will be in the range from 0 to num_threads-1.
//
const int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Number of elements that each thread should work on. We are ignoring
// rounding errors.
//
const int elt_per_thread = d_app.array_size / d_app.num_threads;
/// WARNING:
//
// The order in which the threads examine elements here is poorly
// chosen and will unnecessarily make inefficient use of the memory
// system.
// Compute element number to start at.
//
const int start = elt_per_thread * tid;
// Compute element number to stop at.
//
const int stop = start + elt_per_thread;
// WARNING: This code accesses elements in an inefficient order.
for ( int h=start; h<stop; h++ )
{
Vertex p = d_app.d_v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += d_app.matrix[i][j] * p.a[j];
}
d_app.d_v_out[h] = q;
}
}
void
print_gpu_info()
{
// Get information about GPU and its ability to run CUDA.
//
int device_count;
cudaGetDeviceCount(&device_count); // Get number of GPUs.
if ( device_count == 0 )
{
fprintf(stderr,"No GPU found, exiting.\n");
exit(1);
}
int dev = 0;
CE(cudaGetDevice(&dev));
printf("Using GPU %d\n",dev);
cudaDeviceProp cuda_prop; // Properties of cuda device (GPU, cuda version).
/// Print information about the available GPUs.
//
{
CE(cudaGetDeviceProperties(&cuda_prop,dev));
printf
("GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n",
dev, cuda_prop.name, cuda_prop.clockRate/1e6,
int(cuda_prop.totalGlobalMem >> 20));
printf
("GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n",
dev, cuda_prop.major, cuda_prop.minor,
cuda_prop.multiProcessorCount,
cuda_prop.warpSize,
cuda_prop.maxThreadsPerBlock
);
printf
("GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n",
dev,
int(cuda_prop.sharedMemPerBlock), int(cuda_prop.totalConstMem),
cuda_prop.regsPerBlock
);
}
cudaFuncAttributes cfa_prob1; // Properties of code to run on device.
CE( cudaFuncGetAttributes(&cfa_prob1,cuda_thread_start) );
// Print information about time_step routine.
//
printf("\nCUDA Routine Resource Usage:\n");
printf(" Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; "
"%d max threads per block.\n",
cfa_prob1.sharedSizeBytes,
cfa_prob1.constSizeBytes,
cfa_prob1.localSizeBytes,
cfa_prob1.numRegs,
cfa_prob1.maxThreadsPerBlock);
}
void*
pt_thread_start(void *arg)
{
const int tid = (ptrdiff_t) arg;
printf("Hello from %d\n",tid);
const int elt_per_thread = app.array_size / app.num_threads;
const int start = elt_per_thread * tid;
const int stop = start + elt_per_thread;
for ( int h=start; h<stop; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
app.v_out[h] = q;
}
return NULL;
}
int
main(int argc, char **argv)
{
// Examine argument 1, block size, if negative, find minimum magnitude.
//
const int arg1_int = argc < 2 ? 1 : atoi(argv[1]);
const bool find_mag = arg1_int < 0;
const int num_blocks = abs(arg1_int);
const bool use_pthreads = false;
// For Problem 2.
app.find_minimum_magnitude = find_mag;
// Examine argument 2, number of threads per block.
//
const int thd_per_block = argc < 3 ? 1 : atoi(argv[2]);
app.num_threads = use_pthreads ? -arg1_int : num_blocks * thd_per_block;
// Examine argument 3, size of array in MiB. Fractional values okay.
//
app.array_size = argc < 4 ? 1 << 20 : int( atof(argv[3]) * (1<<20) );
if ( app.num_threads <= 0 || app.array_size <= 0 )
{
printf("Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n",
argv[0]);
exit(1);
}
if ( !use_pthreads )
print_gpu_info();
const int array_size_bytes = app.array_size * sizeof(app.v_in[0]);
// Allocate storage for CPU copy of data.
//
app.v_in = new Vertex[app.array_size];
app.v_out = new Vertex[app.array_size];
// Allocate storage for GPU copy of data.
//
CE( cudaMalloc( &app.d_v_in, app.array_size * sizeof(Vertex) ) );
CE( cudaMalloc( &app.d_v_out, app.array_size * sizeof(Vertex) ) );
printf
("\nPreparing for %d %s threads operating on %d vectors of %d elements.\n",
app.num_threads,
use_pthreads ? "CPU" : "GPU",
app.array_size, N);
// Initialize input array.
//
for ( int i=0; i<app.array_size; i++ )
for ( int j=0; j<N; j++ ) app.v_in[i].a[j] = drand48();
// Initialize transformation matrix.
//
for ( int i=0; i<N; i++ )
for ( int j=0; j<N; j++ )
app.matrix[i][j] = drand48();
double elapsed_time_s;
int minimum_mag_index = 0; // For Problem 2.
Elt_Type minimum_mag_val = 0; // For Problem 2.
if ( use_pthreads )
{
const double time_start = time_fp();
// Allocate a structure to hold pthread thread ids.
//
pthread_t* const ptid = new pthread_t[app.num_threads];
// Set up a pthread attribute, used for specifying options.
//
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
// Launch the threads.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_create(&ptid[i], &attr, pt_thread_start, (void*)i);
// Wait for each thread to finish.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_join( ptid[i], NULL );
elapsed_time_s = time_fp() - time_start;
}
else
{
// Prepare events used for timing.
//
cudaEvent_t gpu_start_ce, gpu_stop_ce;
CE(cudaEventCreate(&gpu_start_ce));
CE(cudaEventCreate(&gpu_stop_ce));
// Copy input array from CPU to GPU.
//
CE( cudaMemcpy
( app.d_v_in, app.v_in, array_size_bytes, cudaMemcpyHostToDevice ) );
// Copy App structure to GPU.
//
CE( cudaMemcpyToSymbol
( d_app, &app, sizeof(app), 0, cudaMemcpyHostToDevice ) );
// Measure execution time starting "now", which is after data
// set to GPU.
//
CE(cudaEventRecord(gpu_start_ce,0));
printf("Launching with %d blocks of %d threads.\n",
num_blocks, thd_per_block);
// Tell CUDA to start our threads on the GPU.
//
cuda_thread_start<<<num_blocks,thd_per_block>>>();
// Stop measuring execution time now, which is before is data
// returned from GPU.
//
CE(cudaEventRecord(gpu_stop_ce,0));
CE(cudaEventSynchronize(gpu_stop_ce));
float cuda_time_ms = -1.1;
CE(cudaEventElapsedTime(&cuda_time_ms,gpu_start_ce,gpu_stop_ce));
elapsed_time_s = cuda_time_ms * 0.001;
// Copy output array from GPU to CPU.
//
CE( cudaMemcpy
( app.v_out, app.d_v_out, array_size_bytes, cudaMemcpyDeviceToHost) );
// PROBLEM 2
//
// Insert code for reading magnitude information and having
// CPU finish up finding the minimum.
minimum_mag_index = -1; // PROBLEM 2 - change this line.
minimum_mag_val = 0.0; // PROBLEM 2 - change this line too.
}
const double data_size = app.array_size * sizeof(Vertex) * 2;
const double fp_op_count = app.array_size * ( 2 * N * N - N );
printf("Elapsed time for %d threads and %d elements is %.3f µs\n",
app.num_threads, app.array_size, 1e6 * elapsed_time_s);
printf("Rate %.3f GFLOPS, %.3f GB/s\n",
1e-9 * fp_op_count / elapsed_time_s,
1e-9 * data_size / elapsed_time_s);
if ( app.find_minimum_magnitude )
{
// Compute correct answer.
Elt_Type min_val = 0;
int min_idx = -1;
for ( int h=0; h<app.array_size; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
Elt_Type sos = 0; for(int i=0; i<N; i++ ) sos+= q.a[i]*q.a[i];
Elt_Type mag = sqrt(sos);
if ( min_idx < 0 || mag < min_val ) { min_val = mag; min_idx = h; }
}
Elt_Type diff = fabs(min_val-minimum_mag_val);
printf
("\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n",
diff < 1e-5 ? "correct" : "**wrong**",
minimum_mag_index,
min_idx == minimum_mag_index ? "==" : "!=",
min_idx,
minimum_mag_val,
min_val == minimum_mag_val ? "==" : diff < 1e-5 ? "~" : "!=",
min_val
);
}
} | /// LSU EE 7700-2 (Spring 2013), GPU Microarchitecture
//
/// Homework 3
//
// Assignment in: http://www.ece.lsu.edu/koppel/gp/2013/hw03.pdf
//
/// Your Name:
#include <pthread.h>
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <ctype.h>
#include <time.h>
#include <new>
#include <hip/hip_runtime.h>
#define N 4
/// CUDA API Error-Checking Wrapper
///
#define CE(call) \
{ \
const hipError_t rv = call; \
if ( rv != hipSuccess ) \
{ \
printf("CUDA error %d, %s\n",rv,hipGetErrorString(rv)); \
exit(1); \
} \
}
double
time_fp()
{
struct timespec tp;
clock_gettime(CLOCK_REALTIME,&tp);
return ((double)tp.tv_sec)+((double)tp.tv_nsec) * 0.000000001;
}
// Make it easy to switch between float and double for vertex and matrix
// elements.
//
typedef float Elt_Type;
struct __align__(16) Vertex
{
Elt_Type a[N];
};
struct App
{
int num_threads;
Elt_Type matrix[N][N];
int array_size; // Number of vertices.
bool find_minimum_magnitude; // For problem 2.
Vertex *v_in, *v_out;
Vertex *d_v_in, *d_v_out;
};
// In host address space.
App app;
// In device constant address space.
__constant__ App d_app;
// The entry point for the GPU code.
//
__global__ void
cuda_thread_start()
{
// Compute an id number that will be in the range from 0 to num_threads-1.
//
const int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Number of elements that each thread should work on. We are ignoring
// rounding errors.
//
const int elt_per_thread = d_app.array_size / d_app.num_threads;
/// WARNING:
//
// The order in which the threads examine elements here is poorly
// chosen and will unnecessarily make inefficient use of the memory
// system.
// Compute element number to start at.
//
const int start = elt_per_thread * tid;
// Compute element number to stop at.
//
const int stop = start + elt_per_thread;
// WARNING: This code accesses elements in an inefficient order.
for ( int h=start; h<stop; h++ )
{
Vertex p = d_app.d_v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += d_app.matrix[i][j] * p.a[j];
}
d_app.d_v_out[h] = q;
}
}
void
print_gpu_info()
{
// Get information about GPU and its ability to run CUDA.
//
int device_count;
hipGetDeviceCount(&device_count); // Get number of GPUs.
if ( device_count == 0 )
{
fprintf(stderr,"No GPU found, exiting.\n");
exit(1);
}
int dev = 0;
CE(hipGetDevice(&dev));
printf("Using GPU %d\n",dev);
hipDeviceProp_t cuda_prop; // Properties of cuda device (GPU, cuda version).
/// Print information about the available GPUs.
//
{
CE(hipGetDeviceProperties(&cuda_prop,dev));
printf
("GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n",
dev, cuda_prop.name, cuda_prop.clockRate/1e6,
int(cuda_prop.totalGlobalMem >> 20));
printf
("GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n",
dev, cuda_prop.major, cuda_prop.minor,
cuda_prop.multiProcessorCount,
cuda_prop.warpSize,
cuda_prop.maxThreadsPerBlock
);
printf
("GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n",
dev,
int(cuda_prop.sharedMemPerBlock), int(cuda_prop.totalConstMem),
cuda_prop.regsPerBlock
);
}
hipFuncAttributes cfa_prob1; // Properties of code to run on device.
CE( hipFuncGetAttributes(&cfa_prob1,reinterpret_cast<const void*>(cuda_thread_start)) );
// Print information about time_step routine.
//
printf("\nCUDA Routine Resource Usage:\n");
printf(" Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; "
"%d max threads per block.\n",
cfa_prob1.sharedSizeBytes,
cfa_prob1.constSizeBytes,
cfa_prob1.localSizeBytes,
cfa_prob1.numRegs,
cfa_prob1.maxThreadsPerBlock);
}
void*
pt_thread_start(void *arg)
{
const int tid = (ptrdiff_t) arg;
printf("Hello from %d\n",tid);
const int elt_per_thread = app.array_size / app.num_threads;
const int start = elt_per_thread * tid;
const int stop = start + elt_per_thread;
for ( int h=start; h<stop; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
app.v_out[h] = q;
}
return NULL;
}
int
main(int argc, char **argv)
{
// Examine argument 1, block size, if negative, find minimum magnitude.
//
const int arg1_int = argc < 2 ? 1 : atoi(argv[1]);
const bool find_mag = arg1_int < 0;
const int num_blocks = abs(arg1_int);
const bool use_pthreads = false;
// For Problem 2.
app.find_minimum_magnitude = find_mag;
// Examine argument 2, number of threads per block.
//
const int thd_per_block = argc < 3 ? 1 : atoi(argv[2]);
app.num_threads = use_pthreads ? -arg1_int : num_blocks * thd_per_block;
// Examine argument 3, size of array in MiB. Fractional values okay.
//
app.array_size = argc < 4 ? 1 << 20 : int( atof(argv[3]) * (1<<20) );
if ( app.num_threads <= 0 || app.array_size <= 0 )
{
printf("Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n",
argv[0]);
exit(1);
}
if ( !use_pthreads )
print_gpu_info();
const int array_size_bytes = app.array_size * sizeof(app.v_in[0]);
// Allocate storage for CPU copy of data.
//
app.v_in = new Vertex[app.array_size];
app.v_out = new Vertex[app.array_size];
// Allocate storage for GPU copy of data.
//
CE( hipMalloc( &app.d_v_in, app.array_size * sizeof(Vertex) ) );
CE( hipMalloc( &app.d_v_out, app.array_size * sizeof(Vertex) ) );
printf
("\nPreparing for %d %s threads operating on %d vectors of %d elements.\n",
app.num_threads,
use_pthreads ? "CPU" : "GPU",
app.array_size, N);
// Initialize input array.
//
for ( int i=0; i<app.array_size; i++ )
for ( int j=0; j<N; j++ ) app.v_in[i].a[j] = drand48();
// Initialize transformation matrix.
//
for ( int i=0; i<N; i++ )
for ( int j=0; j<N; j++ )
app.matrix[i][j] = drand48();
double elapsed_time_s;
int minimum_mag_index = 0; // For Problem 2.
Elt_Type minimum_mag_val = 0; // For Problem 2.
if ( use_pthreads )
{
const double time_start = time_fp();
// Allocate a structure to hold pthread thread ids.
//
pthread_t* const ptid = new pthread_t[app.num_threads];
// Set up a pthread attribute, used for specifying options.
//
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
// Launch the threads.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_create(&ptid[i], &attr, pt_thread_start, (void*)i);
// Wait for each thread to finish.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_join( ptid[i], NULL );
elapsed_time_s = time_fp() - time_start;
}
else
{
// Prepare events used for timing.
//
hipEvent_t gpu_start_ce, gpu_stop_ce;
CE(hipEventCreate(&gpu_start_ce));
CE(hipEventCreate(&gpu_stop_ce));
// Copy input array from CPU to GPU.
//
CE( hipMemcpy
( app.d_v_in, app.v_in, array_size_bytes, hipMemcpyHostToDevice ) );
// Copy App structure to GPU.
//
CE( hipMemcpyToSymbol
( HIP_SYMBOL(d_app), &app, sizeof(app), 0, hipMemcpyHostToDevice ) );
// Measure execution time starting "now", which is after data
// set to GPU.
//
CE(hipEventRecord(gpu_start_ce,0));
printf("Launching with %d blocks of %d threads.\n",
num_blocks, thd_per_block);
// Tell CUDA to start our threads on the GPU.
//
cuda_thread_start<<<num_blocks,thd_per_block>>>();
// Stop measuring execution time now, which is before is data
// returned from GPU.
//
CE(hipEventRecord(gpu_stop_ce,0));
CE(hipEventSynchronize(gpu_stop_ce));
float cuda_time_ms = -1.1;
CE(hipEventElapsedTime(&cuda_time_ms,gpu_start_ce,gpu_stop_ce));
elapsed_time_s = cuda_time_ms * 0.001;
// Copy output array from GPU to CPU.
//
CE( hipMemcpy
( app.v_out, app.d_v_out, array_size_bytes, hipMemcpyDeviceToHost) );
// PROBLEM 2
//
// Insert code for reading magnitude information and having
// CPU finish up finding the minimum.
minimum_mag_index = -1; // PROBLEM 2 - change this line.
minimum_mag_val = 0.0; // PROBLEM 2 - change this line too.
}
const double data_size = app.array_size * sizeof(Vertex) * 2;
const double fp_op_count = app.array_size * ( 2 * N * N - N );
printf("Elapsed time for %d threads and %d elements is %.3f µs\n",
app.num_threads, app.array_size, 1e6 * elapsed_time_s);
printf("Rate %.3f GFLOPS, %.3f GB/s\n",
1e-9 * fp_op_count / elapsed_time_s,
1e-9 * data_size / elapsed_time_s);
if ( app.find_minimum_magnitude )
{
// Compute correct answer.
Elt_Type min_val = 0;
int min_idx = -1;
for ( int h=0; h<app.array_size; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
Elt_Type sos = 0; for(int i=0; i<N; i++ ) sos+= q.a[i]*q.a[i];
Elt_Type mag = sqrt(sos);
if ( min_idx < 0 || mag < min_val ) { min_val = mag; min_idx = h; }
}
Elt_Type diff = fabs(min_val-minimum_mag_val);
printf
("\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n",
diff < 1e-5 ? "correct" : "**wrong**",
minimum_mag_index,
min_idx == minimum_mag_index ? "==" : "!=",
min_idx,
minimum_mag_val,
min_val == minimum_mag_val ? "==" : diff < 1e-5 ? "~" : "!=",
min_val
);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /// LSU EE 7700-2 (Spring 2013), GPU Microarchitecture
//
/// Homework 3
//
// Assignment in: http://www.ece.lsu.edu/koppel/gp/2013/hw03.pdf
//
/// Your Name:
#include <pthread.h>
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <ctype.h>
#include <time.h>
#include <new>
#include <hip/hip_runtime.h>
#define N 4
/// CUDA API Error-Checking Wrapper
///
#define CE(call) \
{ \
const hipError_t rv = call; \
if ( rv != hipSuccess ) \
{ \
printf("CUDA error %d, %s\n",rv,hipGetErrorString(rv)); \
exit(1); \
} \
}
double
time_fp()
{
struct timespec tp;
clock_gettime(CLOCK_REALTIME,&tp);
return ((double)tp.tv_sec)+((double)tp.tv_nsec) * 0.000000001;
}
// Make it easy to switch between float and double for vertex and matrix
// elements.
//
typedef float Elt_Type;
struct __align__(16) Vertex
{
Elt_Type a[N];
};
struct App
{
int num_threads;
Elt_Type matrix[N][N];
int array_size; // Number of vertices.
bool find_minimum_magnitude; // For problem 2.
Vertex *v_in, *v_out;
Vertex *d_v_in, *d_v_out;
};
// In host address space.
App app;
// In device constant address space.
__constant__ App d_app;
// The entry point for the GPU code.
//
__global__ void
cuda_thread_start()
{
// Compute an id number that will be in the range from 0 to num_threads-1.
//
const int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Number of elements that each thread should work on. We are ignoring
// rounding errors.
//
const int elt_per_thread = d_app.array_size / d_app.num_threads;
/// WARNING:
//
// The order in which the threads examine elements here is poorly
// chosen and will unnecessarily make inefficient use of the memory
// system.
// Compute element number to start at.
//
const int start = elt_per_thread * tid;
// Compute element number to stop at.
//
const int stop = start + elt_per_thread;
// WARNING: This code accesses elements in an inefficient order.
for ( int h=start; h<stop; h++ )
{
Vertex p = d_app.d_v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += d_app.matrix[i][j] * p.a[j];
}
d_app.d_v_out[h] = q;
}
}
void
print_gpu_info()
{
// Get information about GPU and its ability to run CUDA.
//
int device_count;
hipGetDeviceCount(&device_count); // Get number of GPUs.
if ( device_count == 0 )
{
fprintf(stderr,"No GPU found, exiting.\n");
exit(1);
}
int dev = 0;
CE(hipGetDevice(&dev));
printf("Using GPU %d\n",dev);
hipDeviceProp_t cuda_prop; // Properties of cuda device (GPU, cuda version).
/// Print information about the available GPUs.
//
{
CE(hipGetDeviceProperties(&cuda_prop,dev));
printf
("GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n",
dev, cuda_prop.name, cuda_prop.clockRate/1e6,
int(cuda_prop.totalGlobalMem >> 20));
printf
("GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n",
dev, cuda_prop.major, cuda_prop.minor,
cuda_prop.multiProcessorCount,
cuda_prop.warpSize,
cuda_prop.maxThreadsPerBlock
);
printf
("GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n",
dev,
int(cuda_prop.sharedMemPerBlock), int(cuda_prop.totalConstMem),
cuda_prop.regsPerBlock
);
}
hipFuncAttributes cfa_prob1; // Properties of code to run on device.
CE( hipFuncGetAttributes(&cfa_prob1,reinterpret_cast<const void*>(cuda_thread_start)) );
// Print information about time_step routine.
//
printf("\nCUDA Routine Resource Usage:\n");
printf(" Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; "
"%d max threads per block.\n",
cfa_prob1.sharedSizeBytes,
cfa_prob1.constSizeBytes,
cfa_prob1.localSizeBytes,
cfa_prob1.numRegs,
cfa_prob1.maxThreadsPerBlock);
}
void*
pt_thread_start(void *arg)
{
const int tid = (ptrdiff_t) arg;
printf("Hello from %d\n",tid);
const int elt_per_thread = app.array_size / app.num_threads;
const int start = elt_per_thread * tid;
const int stop = start + elt_per_thread;
for ( int h=start; h<stop; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
app.v_out[h] = q;
}
return NULL;
}
int
main(int argc, char **argv)
{
// Examine argument 1, block size, if negative, find minimum magnitude.
//
const int arg1_int = argc < 2 ? 1 : atoi(argv[1]);
const bool find_mag = arg1_int < 0;
const int num_blocks = abs(arg1_int);
const bool use_pthreads = false;
// For Problem 2.
app.find_minimum_magnitude = find_mag;
// Examine argument 2, number of threads per block.
//
const int thd_per_block = argc < 3 ? 1 : atoi(argv[2]);
app.num_threads = use_pthreads ? -arg1_int : num_blocks * thd_per_block;
// Examine argument 3, size of array in MiB. Fractional values okay.
//
app.array_size = argc < 4 ? 1 << 20 : int( atof(argv[3]) * (1<<20) );
if ( app.num_threads <= 0 || app.array_size <= 0 )
{
printf("Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n",
argv[0]);
exit(1);
}
if ( !use_pthreads )
print_gpu_info();
const int array_size_bytes = app.array_size * sizeof(app.v_in[0]);
// Allocate storage for CPU copy of data.
//
app.v_in = new Vertex[app.array_size];
app.v_out = new Vertex[app.array_size];
// Allocate storage for GPU copy of data.
//
CE( hipMalloc( &app.d_v_in, app.array_size * sizeof(Vertex) ) );
CE( hipMalloc( &app.d_v_out, app.array_size * sizeof(Vertex) ) );
printf
("\nPreparing for %d %s threads operating on %d vectors of %d elements.\n",
app.num_threads,
use_pthreads ? "CPU" : "GPU",
app.array_size, N);
// Initialize input array.
//
for ( int i=0; i<app.array_size; i++ )
for ( int j=0; j<N; j++ ) app.v_in[i].a[j] = drand48();
// Initialize transformation matrix.
//
for ( int i=0; i<N; i++ )
for ( int j=0; j<N; j++ )
app.matrix[i][j] = drand48();
double elapsed_time_s;
int minimum_mag_index = 0; // For Problem 2.
Elt_Type minimum_mag_val = 0; // For Problem 2.
if ( use_pthreads )
{
const double time_start = time_fp();
// Allocate a structure to hold pthread thread ids.
//
pthread_t* const ptid = new pthread_t[app.num_threads];
// Set up a pthread attribute, used for specifying options.
//
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
// Launch the threads.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_create(&ptid[i], &attr, pt_thread_start, (void*)i);
// Wait for each thread to finish.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_join( ptid[i], NULL );
elapsed_time_s = time_fp() - time_start;
}
else
{
// Prepare events used for timing.
//
hipEvent_t gpu_start_ce, gpu_stop_ce;
CE(hipEventCreate(&gpu_start_ce));
CE(hipEventCreate(&gpu_stop_ce));
// Copy input array from CPU to GPU.
//
CE( hipMemcpy
( app.d_v_in, app.v_in, array_size_bytes, hipMemcpyHostToDevice ) );
// Copy App structure to GPU.
//
CE( hipMemcpyToSymbol
( HIP_SYMBOL(d_app), &app, sizeof(app), 0, hipMemcpyHostToDevice ) );
// Measure execution time starting "now", which is after data
// set to GPU.
//
CE(hipEventRecord(gpu_start_ce,0));
printf("Launching with %d blocks of %d threads.\n",
num_blocks, thd_per_block);
// Tell CUDA to start our threads on the GPU.
//
cuda_thread_start<<<num_blocks,thd_per_block>>>();
// Stop measuring execution time now, which is before is data
// returned from GPU.
//
CE(hipEventRecord(gpu_stop_ce,0));
CE(hipEventSynchronize(gpu_stop_ce));
float cuda_time_ms = -1.1;
CE(hipEventElapsedTime(&cuda_time_ms,gpu_start_ce,gpu_stop_ce));
elapsed_time_s = cuda_time_ms * 0.001;
// Copy output array from GPU to CPU.
//
CE( hipMemcpy
( app.v_out, app.d_v_out, array_size_bytes, hipMemcpyDeviceToHost) );
// PROBLEM 2
//
// Insert code for reading magnitude information and having
// CPU finish up finding the minimum.
minimum_mag_index = -1; // PROBLEM 2 - change this line.
minimum_mag_val = 0.0; // PROBLEM 2 - change this line too.
}
const double data_size = app.array_size * sizeof(Vertex) * 2;
const double fp_op_count = app.array_size * ( 2 * N * N - N );
printf("Elapsed time for %d threads and %d elements is %.3f µs\n",
app.num_threads, app.array_size, 1e6 * elapsed_time_s);
printf("Rate %.3f GFLOPS, %.3f GB/s\n",
1e-9 * fp_op_count / elapsed_time_s,
1e-9 * data_size / elapsed_time_s);
if ( app.find_minimum_magnitude )
{
// Compute correct answer.
Elt_Type min_val = 0;
int min_idx = -1;
for ( int h=0; h<app.array_size; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
Elt_Type sos = 0; for(int i=0; i<N; i++ ) sos+= q.a[i]*q.a[i];
Elt_Type mag = sqrt(sos);
if ( min_idx < 0 || mag < min_val ) { min_val = mag; min_idx = h; }
}
Elt_Type diff = fabs(min_val-minimum_mag_val);
printf
("\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n",
diff < 1e-5 ? "correct" : "**wrong**",
minimum_mag_index,
min_idx == minimum_mag_index ? "==" : "!=",
min_idx,
minimum_mag_val,
min_val == minimum_mag_val ? "==" : diff < 1e-5 ? "~" : "!=",
min_val
);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cuda_thread_startv
.globl _Z17cuda_thread_startv
.p2align 8
.type _Z17cuda_thread_startv,@function
_Z17cuda_thread_startv:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_app@rel32@lo+4
s_addc_u32 s5, s5, d_app@rel32@hi+12
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s6
s_xor_b32 s7, s4, s6
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_app@rel32@lo+72
s_addc_u32 s5, s5, d_app@rel32@hi+80
v_cvt_f32_u32_e32 v1, s7
s_load_b32 s4, s[4:5], 0x0
s_sub_i32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_add_i32 s4, s4, s9
s_xor_b32 s6, s9, s6
v_readfirstlane_b32 s5, v1
s_xor_b32 s4, s4, s9
s_mul_i32 s8, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s5, s8
s_add_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_mul_i32 s8, s5, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s4, s8
s_add_i32 s8, s5, 1
s_sub_i32 s9, s4, s7
s_cmp_ge_u32 s4, s7
s_cselect_b32 s5, s8, s5
s_cselect_b32 s4, s9, s4
s_add_i32 s8, s5, 1
s_cmp_ge_u32 s4, s7
s_cselect_b32 s4, s8, s5
s_mov_b32 s8, 0
s_xor_b32 s4, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s6, s4, s6
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x4
s_load_b32 s7, s[2:3], 0xc
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_app@rel32@lo+100
s_addc_u32 s3, s3, d_app@rel32@hi+108
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_app@rel32@lo+108
s_addc_u32 s5, s5, d_app@rel32@hi+116
s_mul_i32 s0, s0, s1
s_and_b32 s7, s7, 0xffff
v_mul_lo_u32 v4, s0, v1
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[4:5], s[4:5], 0x0
v_bfe_u32 v3, v0, 20, 10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u32_u24 v1, v1, s1, v4
v_mul_lo_u32 v0, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v3, v1, v3, 4
v_add_nc_u32_e32 v4, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x4000, v3
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s9, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_app@rel32@lo+8
s_addc_u32 s1, s1, d_app@rel32@hi+16
v_lshlrev_b64 v[1:2], 4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v2, vcc_lo
global_load_b128 v[7:10], v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b128 v5, v[7:10]
.p2align 6
.LBB0_3:
v_lshl_add_u32 v7, s9, 2, v3
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v5
s_mov_b64 s[6:7], 0
ds_store_b32 v7, v6
.LBB0_4:
s_add_u32 s10, s0, s6
s_addc_u32 s11, s1, s7
ds_load_b32 v10, v9
s_load_b32 s10, s[10:11], 0x0
v_add_nc_u32_e32 v9, 4, v9
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s6, 16
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v8, s10, v10
s_cbranch_scc0 .LBB0_4
s_add_i32 s9, s9, 1
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s9, 4
ds_store_b32 v7, v8
s_cbranch_scc0 .LBB0_3
ds_load_b128 v[7:10], v3
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, s0, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v4
s_or_b32 s8, vcc_lo, s8
s_waitcnt lgkmcnt(0)
global_store_b128 v[1:2], v[7:10], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cuda_thread_startv
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cuda_thread_startv, .Lfunc_end0-_Z17cuda_thread_startv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_app
.type d_app,@object
.section .bss,"aw",@nobits
.globl d_app
.p2align 3, 0x0
d_app:
.zero 112
.size d_app, 112
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_app
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32768
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cuda_thread_startv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cuda_thread_startv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /// LSU EE 7700-2 (Spring 2013), GPU Microarchitecture
//
/// Homework 3
//
// Assignment in: http://www.ece.lsu.edu/koppel/gp/2013/hw03.pdf
//
/// Your Name:
#include <pthread.h>
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <ctype.h>
#include <time.h>
#include <new>
#include <hip/hip_runtime.h>
#define N 4
/// CUDA API Error-Checking Wrapper
///
#define CE(call) \
{ \
const hipError_t rv = call; \
if ( rv != hipSuccess ) \
{ \
printf("CUDA error %d, %s\n",rv,hipGetErrorString(rv)); \
exit(1); \
} \
}
double
time_fp()
{
struct timespec tp;
clock_gettime(CLOCK_REALTIME,&tp);
return ((double)tp.tv_sec)+((double)tp.tv_nsec) * 0.000000001;
}
// Make it easy to switch between float and double for vertex and matrix
// elements.
//
typedef float Elt_Type;
struct __align__(16) Vertex
{
Elt_Type a[N];
};
struct App
{
int num_threads;
Elt_Type matrix[N][N];
int array_size; // Number of vertices.
bool find_minimum_magnitude; // For problem 2.
Vertex *v_in, *v_out;
Vertex *d_v_in, *d_v_out;
};
// In host address space.
App app;
// In device constant address space.
__constant__ App d_app;
// The entry point for the GPU code.
//
__global__ void
cuda_thread_start()
{
// Compute an id number that will be in the range from 0 to num_threads-1.
//
const int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Number of elements that each thread should work on. We are ignoring
// rounding errors.
//
const int elt_per_thread = d_app.array_size / d_app.num_threads;
/// WARNING:
//
// The order in which the threads examine elements here is poorly
// chosen and will unnecessarily make inefficient use of the memory
// system.
// Compute element number to start at.
//
const int start = elt_per_thread * tid;
// Compute element number to stop at.
//
const int stop = start + elt_per_thread;
// WARNING: This code accesses elements in an inefficient order.
for ( int h=start; h<stop; h++ )
{
Vertex p = d_app.d_v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += d_app.matrix[i][j] * p.a[j];
}
d_app.d_v_out[h] = q;
}
}
void
print_gpu_info()
{
// Get information about GPU and its ability to run CUDA.
//
int device_count;
hipGetDeviceCount(&device_count); // Get number of GPUs.
if ( device_count == 0 )
{
fprintf(stderr,"No GPU found, exiting.\n");
exit(1);
}
int dev = 0;
CE(hipGetDevice(&dev));
printf("Using GPU %d\n",dev);
hipDeviceProp_t cuda_prop; // Properties of cuda device (GPU, cuda version).
/// Print information about the available GPUs.
//
{
CE(hipGetDeviceProperties(&cuda_prop,dev));
printf
("GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n",
dev, cuda_prop.name, cuda_prop.clockRate/1e6,
int(cuda_prop.totalGlobalMem >> 20));
printf
("GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n",
dev, cuda_prop.major, cuda_prop.minor,
cuda_prop.multiProcessorCount,
cuda_prop.warpSize,
cuda_prop.maxThreadsPerBlock
);
printf
("GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n",
dev,
int(cuda_prop.sharedMemPerBlock), int(cuda_prop.totalConstMem),
cuda_prop.regsPerBlock
);
}
hipFuncAttributes cfa_prob1; // Properties of code to run on device.
CE( hipFuncGetAttributes(&cfa_prob1,reinterpret_cast<const void*>(cuda_thread_start)) );
// Print information about time_step routine.
//
printf("\nCUDA Routine Resource Usage:\n");
printf(" Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; "
"%d max threads per block.\n",
cfa_prob1.sharedSizeBytes,
cfa_prob1.constSizeBytes,
cfa_prob1.localSizeBytes,
cfa_prob1.numRegs,
cfa_prob1.maxThreadsPerBlock);
}
void*
pt_thread_start(void *arg)
{
const int tid = (ptrdiff_t) arg;
printf("Hello from %d\n",tid);
const int elt_per_thread = app.array_size / app.num_threads;
const int start = elt_per_thread * tid;
const int stop = start + elt_per_thread;
for ( int h=start; h<stop; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
app.v_out[h] = q;
}
return NULL;
}
int
main(int argc, char **argv)
{
// Examine argument 1, block size, if negative, find minimum magnitude.
//
const int arg1_int = argc < 2 ? 1 : atoi(argv[1]);
const bool find_mag = arg1_int < 0;
const int num_blocks = abs(arg1_int);
const bool use_pthreads = false;
// For Problem 2.
app.find_minimum_magnitude = find_mag;
// Examine argument 2, number of threads per block.
//
const int thd_per_block = argc < 3 ? 1 : atoi(argv[2]);
app.num_threads = use_pthreads ? -arg1_int : num_blocks * thd_per_block;
// Examine argument 3, size of array in MiB. Fractional values okay.
//
app.array_size = argc < 4 ? 1 << 20 : int( atof(argv[3]) * (1<<20) );
if ( app.num_threads <= 0 || app.array_size <= 0 )
{
printf("Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n",
argv[0]);
exit(1);
}
if ( !use_pthreads )
print_gpu_info();
const int array_size_bytes = app.array_size * sizeof(app.v_in[0]);
// Allocate storage for CPU copy of data.
//
app.v_in = new Vertex[app.array_size];
app.v_out = new Vertex[app.array_size];
// Allocate storage for GPU copy of data.
//
CE( hipMalloc( &app.d_v_in, app.array_size * sizeof(Vertex) ) );
CE( hipMalloc( &app.d_v_out, app.array_size * sizeof(Vertex) ) );
printf
("\nPreparing for %d %s threads operating on %d vectors of %d elements.\n",
app.num_threads,
use_pthreads ? "CPU" : "GPU",
app.array_size, N);
// Initialize input array.
//
for ( int i=0; i<app.array_size; i++ )
for ( int j=0; j<N; j++ ) app.v_in[i].a[j] = drand48();
// Initialize transformation matrix.
//
for ( int i=0; i<N; i++ )
for ( int j=0; j<N; j++ )
app.matrix[i][j] = drand48();
double elapsed_time_s;
int minimum_mag_index = 0; // For Problem 2.
Elt_Type minimum_mag_val = 0; // For Problem 2.
if ( use_pthreads )
{
const double time_start = time_fp();
// Allocate a structure to hold pthread thread ids.
//
pthread_t* const ptid = new pthread_t[app.num_threads];
// Set up a pthread attribute, used for specifying options.
//
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
// Launch the threads.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_create(&ptid[i], &attr, pt_thread_start, (void*)i);
// Wait for each thread to finish.
//
for ( int i=0; i<app.num_threads; i++ )
pthread_join( ptid[i], NULL );
elapsed_time_s = time_fp() - time_start;
}
else
{
// Prepare events used for timing.
//
hipEvent_t gpu_start_ce, gpu_stop_ce;
CE(hipEventCreate(&gpu_start_ce));
CE(hipEventCreate(&gpu_stop_ce));
// Copy input array from CPU to GPU.
//
CE( hipMemcpy
( app.d_v_in, app.v_in, array_size_bytes, hipMemcpyHostToDevice ) );
// Copy App structure to GPU.
//
CE( hipMemcpyToSymbol
( HIP_SYMBOL(d_app), &app, sizeof(app), 0, hipMemcpyHostToDevice ) );
// Measure execution time starting "now", which is after data
// set to GPU.
//
CE(hipEventRecord(gpu_start_ce,0));
printf("Launching with %d blocks of %d threads.\n",
num_blocks, thd_per_block);
// Tell CUDA to start our threads on the GPU.
//
cuda_thread_start<<<num_blocks,thd_per_block>>>();
// Stop measuring execution time now, which is before is data
// returned from GPU.
//
CE(hipEventRecord(gpu_stop_ce,0));
CE(hipEventSynchronize(gpu_stop_ce));
float cuda_time_ms = -1.1;
CE(hipEventElapsedTime(&cuda_time_ms,gpu_start_ce,gpu_stop_ce));
elapsed_time_s = cuda_time_ms * 0.001;
// Copy output array from GPU to CPU.
//
CE( hipMemcpy
( app.v_out, app.d_v_out, array_size_bytes, hipMemcpyDeviceToHost) );
// PROBLEM 2
//
// Insert code for reading magnitude information and having
// CPU finish up finding the minimum.
minimum_mag_index = -1; // PROBLEM 2 - change this line.
minimum_mag_val = 0.0; // PROBLEM 2 - change this line too.
}
const double data_size = app.array_size * sizeof(Vertex) * 2;
const double fp_op_count = app.array_size * ( 2 * N * N - N );
printf("Elapsed time for %d threads and %d elements is %.3f µs\n",
app.num_threads, app.array_size, 1e6 * elapsed_time_s);
printf("Rate %.3f GFLOPS, %.3f GB/s\n",
1e-9 * fp_op_count / elapsed_time_s,
1e-9 * data_size / elapsed_time_s);
if ( app.find_minimum_magnitude )
{
// Compute correct answer.
Elt_Type min_val = 0;
int min_idx = -1;
for ( int h=0; h<app.array_size; h++ )
{
Vertex p = app.v_in[h];
Vertex q;
for ( int i=0; i<N; i++ )
{
q.a[i] = 0;
for ( int j=0; j<N; j++ ) q.a[i] += app.matrix[i][j] * p.a[j];
}
Elt_Type sos = 0; for(int i=0; i<N; i++ ) sos+= q.a[i]*q.a[i];
Elt_Type mag = sqrt(sos);
if ( min_idx < 0 || mag < min_val ) { min_val = mag; min_idx = h; }
}
Elt_Type diff = fabs(min_val-minimum_mag_val);
printf
("\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n",
diff < 1e-5 ? "correct" : "**wrong**",
minimum_mag_index,
min_idx == minimum_mag_index ? "==" : "!=",
min_idx,
minimum_mag_val,
min_val == minimum_mag_val ? "==" : diff < 1e-5 ? "~" : "!=",
min_val
);
}
} | .text
.file "hw3.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7time_fpv
.LCPI0_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z7time_fpv
.p2align 4, 0x90
.type _Z7time_fpv,@function
_Z7time_fpv: # @_Z7time_fpv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7time_fpv, .Lfunc_end0-_Z7time_fpv
.cfi_endproc
# -- End function
.globl _Z32__device_stub__cuda_thread_startv # -- Begin function _Z32__device_stub__cuda_thread_startv
.p2align 4, 0x90
.type _Z32__device_stub__cuda_thread_startv,@function
_Z32__device_stub__cuda_thread_startv: # @_Z32__device_stub__cuda_thread_startv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17cuda_thread_startv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z32__device_stub__cuda_thread_startv, .Lfunc_end1-_Z32__device_stub__cuda_thread_startv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14print_gpu_infov
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z14print_gpu_infov
.p2align 4, 0x90
.type _Z14print_gpu_infov,@function
_Z14print_gpu_infov: # @_Z14print_gpu_infov
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 20(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 20(%rsp)
je .LBB2_5
# %bb.1:
movl $0, 16(%rsp)
leaq 16(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movl 16(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 16(%rsp), %esi
leaq 80(%rsp), %rdi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_6
# %bb.3:
movl 16(%rsp), %esi
cvtsi2sdl 428(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
movq 368(%rsp), %rcx
shrq $20, %rcx
leaq 80(%rsp), %rdx
movl $.L.str.3, %edi
# kill: def $ecx killed $ecx killed $rcx
movb $1, %al
callq printf
movl 16(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl 468(%rsp), %r8d
movl 388(%rsp), %r9d
movl 400(%rsp), %eax
movl %eax, (%rsp)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 16(%rsp), %esi
movl 432(%rsp), %ecx
movl 376(%rsp), %edx
movl 384(%rsp), %r8d
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $_Z17cuda_thread_startv, %esi
callq hipFuncGetAttributes
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
movq 40(%rsp), %rcx
movl 56(%rsp), %r8d
movl 52(%rsp), %r9d
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 1568
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14print_gpu_infov, .Lfunc_end2-_Z14print_gpu_infov
.cfi_endproc
# -- End function
.globl _Z15pt_thread_startPv # -- Begin function _Z15pt_thread_startPv
.p2align 4, 0x90
.type _Z15pt_thread_startPv,@function
_Z15pt_thread_startPv: # @_Z15pt_thread_startPv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str.8, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl app+68(%rip), %eax
cltd
idivl app(%rip)
testl %eax, %eax
jle .LBB3_7
# %bb.1: # %.lr.ph.preheader
imull %eax, %ebx
addl %ebx, %eax
movslq %ebx, %rcx
cltq
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq app+80(%rip), %rsi
movq %rcx, %rdx
shlq $4, %rdx
movaps (%rsi,%rdx), %xmm0
movaps %xmm0, 16(%rsp)
movl $app+4, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movl $0, (%rsp,%rdi,4)
xorps %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 16(%rsp,%r8,4), %xmm1
addss %xmm1, %xmm0
incq %r8
cmpq $4, %r8
jne .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=2
movss %xmm0, (%rsp,%rdi,4)
incq %rdi
addq $16, %rsi
cmpq $4, %rdi
jne .LBB3_3
# %bb.6: # in Loop: Header=BB3_2 Depth=1
movq app+88(%rip), %rsi
movaps (%rsp), %xmm0
movaps %xmm0, (%rsi,%rdx)
incq %rcx
cmpq %rax, %rcx
jl .LBB3_2
.LBB3_7: # %._crit_edge
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15pt_thread_startPv, .Lfunc_end3-_Z15pt_thread_startPv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x4130000000000000 # double 1048576
.LCPI4_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI4_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_5:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.LCPI4_7:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI4_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.LCPI4_6:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_8:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %r15d
movl $1, %ebx
movl $1, %eax
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB4_2:
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %ebp
negl %ebp
cmovsl %eax, %ebp
movb %cl, app+72(%rip)
cmpl $3, %r15d
jl .LBB4_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB4_4:
movl %ebx, %eax
imull %ebp, %eax
movl %eax, app(%rip)
movl $1048576, %eax # imm = 0x100000
cmpl $4, %r15d
jl .LBB4_6
# %bb.5:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
mulsd .LCPI4_0(%rip), %xmm0
cvttsd2si %xmm0, %eax
.LBB4_6:
movl %eax, app+68(%rip)
cmpl $0, app(%rip)
jle .LBB4_48
# %bb.7:
testl %eax, %eax
jle .LBB4_48
# %bb.8:
callq _Z14print_gpu_infov
movslq app+68(%rip), %r12
movq %r12, %r14
shlq $4, %r14
testq %r12, %r12
movq $-1, %r15
cmovnsq %r14, %r15
movq %r15, %rdi
callq _Znam
movq %rax, app+80(%rip)
movq %r15, %rdi
callq _Znam
movq %rax, app+88(%rip)
movl $app+96, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_49
# %bb.9:
movslq app+68(%rip), %rsi
shlq $4, %rsi
movl $app+104, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB4_49
# %bb.10:
movl app(%rip), %esi
movl app+68(%rip), %ecx
movl $.L.str.10, %edi
movl $.L.str.11, %edx
movl $4, %r8d
xorl %eax, %eax
callq printf
cmpl $0, app+68(%rip)
jle .LBB4_15
# %bb.11: # %.preheader147.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_12: # %.preheader147
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_12 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movq app+80(%rip), %rax
addq %r14, %rax
movss %xmm0, (%rax,%r13,4)
incq %r13
cmpq $4, %r13
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=1
incq %r15
movslq app+68(%rip), %rax
addq $16, %r14
cmpq %rax, %r15
jl .LBB4_12
.LBB4_15: # %.preheader145.preheader
shll $4, %r12d
movl $app+4, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.preheader145
# =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_17: # Parent Loop BB4_16 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq $4, %r13
jne .LBB4_17
# %bb.18: # in Loop: Header=BB4_16 Depth=1
incq %r15
addq $16, %r14
cmpq $4, %r15
jne .LBB4_16
# %bb.19:
leaq 72(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB4_49
# %bb.20:
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB4_49
# %bb.21:
movq app+96(%rip), %rdi
movq app+80(%rip), %rsi
movslq %r12d, %r14
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_49
# %bb.22:
movl $d_app, %edi
movl $app, %esi
movl $112, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_49
# %bb.23:
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB4_49
# %bb.24:
movl $.L.str.12, %edi
movl %ebp, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebx, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17cuda_thread_startv, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB4_49
# %bb.27:
movq 24(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB4_49
# %bb.28:
movl $-1081291571, (%rsp) # imm = 0xBF8CCCCD
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB4_49
# %bb.29:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp) # 4-byte Spill
movq app+88(%rip), %rdi
movq app+104(%rip), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_49
# %bb.30:
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
movsd %xmm0, 80(%rsp) # 8-byte Spill
movslq app+68(%rip), %rdx
movq %rdx, %rax
shlq $5, %rax
movq %rax, %xmm0
punpckldq .LCPI4_2(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI4_3(%rip), %xmm0
movapd %xmm0, %xmm2
unpckhpd %xmm0, %xmm2 # xmm2 = xmm2[1],xmm0[1]
leal (%rdx,%rdx,8), %eax
leal (%rax,%rax,2), %eax
addl %edx, %eax
cvtsi2sd %eax, %xmm3
movsd %xmm3, 88(%rsp) # 8-byte Spill
addsd %xmm0, %xmm2
movapd %xmm2, 32(%rsp) # 16-byte Spill
movl app(%rip), %esi
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movl $.L.str.13, %edi
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm3 # xmm3 = mem[0],zero
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm3, %xmm0
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movapd 32(%rsp), %xmm2 # 16-byte Reload
mulsd %xmm3, %xmm2
divsd %xmm1, %xmm2
movapd %xmm2, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
cmpb $0, app+72(%rip)
je .LBB4_34
# %bb.31: # %.preheader144
cmpl $0, app+68(%rip)
jle .LBB4_32
# %bb.35: # %.lr.ph.preheader
xorpd %xmm2, %xmm2
movl $-1, %ebx
xorl %r14d, %r14d
xorpd %xmm3, %xmm3
jmp .LBB4_36
.p2align 4, 0x90
.LBB4_47: # %.split
# in Loop: Header=BB4_36 Depth=1
cmovnel %r14d, %ebx
incq %r14
movslq app+68(%rip), %rax
movaps %xmm0, %xmm3
cmpq %rax, %r14
jge .LBB4_33
.LBB4_36: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_37 Depth 2
# Child Loop BB4_38 Depth 3
# Child Loop BB4_41 Depth 2
movq app+80(%rip), %rax
movq %r14, %rcx
shlq $4, %rcx
movaps (%rax,%rcx), %xmm0
movaps %xmm0, (%rsp)
movl $app+4, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_37: # Parent Loop BB4_36 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_38 Depth 3
movl $0, 48(%rsp,%rcx,4)
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_38: # Parent Loop BB4_36 Depth=1
# Parent Loop BB4_37 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsp,%rdx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq $4, %rdx
jne .LBB4_38
# %bb.39: # in Loop: Header=BB4_37 Depth=2
movss %xmm0, 48(%rsp,%rcx,4)
incq %rcx
addq $16, %rax
cmpq $4, %rcx
jne .LBB4_37
# %bb.40: # %.preheader.preheader
# in Loop: Header=BB4_36 Depth=1
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_41: # %.preheader
# Parent Loop BB4_36 Depth=1
# => This Inner Loop Header: Depth=2
movss 48(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $4, %rax
jne .LBB4_41
# %bb.42: # in Loop: Header=BB4_36 Depth=1
ucomiss %xmm2, %xmm0
jb .LBB4_44
# %bb.43: # in Loop: Header=BB4_36 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_45
.p2align 4, 0x90
.LBB4_44: # %call.sqrt
# in Loop: Header=BB4_36 Depth=1
movss %xmm3, 32(%rsp) # 4-byte Spill
callq sqrtf@PLT
movss 32(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB4_45: # %.split
# in Loop: Header=BB4_36 Depth=1
testl %ebx, %ebx
sets %al
ucomiss %xmm0, %xmm3
seta %cl
orb %al, %cl
testb %cl, %cl
jne .LBB4_47
# %bb.46: # %.split
# in Loop: Header=BB4_36 Depth=1
movaps %xmm3, %xmm0
jmp .LBB4_47
.LBB4_32:
movl $-1, %ebx
xorpd %xmm0, %xmm0
.LBB4_33: # %._crit_edge
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movaps .LCPI4_6(%rip), %xmm2 # xmm2 = [NaN,NaN]
andps %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
cvtss2sd %xmm2, %xmm2
cmpl $-1, %ebx
movl $.L.str.18, %r9d
movl $.L.str.19, %eax
movl $.L.str.19, %ecx
cmoveq %r9, %rcx
movsd .LCPI4_7(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
movl $.L.str.16, %edx
movl $.L.str.17, %esi
cmovaq %rdx, %rsi
movl $.L.str.20, %edx
cmovbeq %rax, %rdx
ucomiss .LCPI4_8(%rip), %xmm0
cmovneq %rdx, %r9
cmovpq %rdx, %r9
movl $.L.str.15, %edi
xorps %xmm0, %xmm0
movl $-1, %edx
movl %ebx, %r8d
movb $2, %al
callq printf
.LBB4_34:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_49:
.cfi_def_cfa_offset 176
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB4_48:
movq (%r14), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_thread_startv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_app, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $112, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type app,@object # @app
.bss
.globl app
.p2align 3, 0x0
app:
.zero 112
.size app, 112
.type d_app,@object # @d_app
.local d_app
.comm d_app,112,8
.type _Z17cuda_thread_startv,@object # @_Z17cuda_thread_startv
.section .rodata,"a",@progbits
.globl _Z17cuda_thread_startv
.p2align 3, 0x0
_Z17cuda_thread_startv:
.quad _Z32__device_stub__cuda_thread_startv
.size _Z17cuda_thread_startv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No GPU found, exiting.\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error %d, %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Using GPU %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n"
.size .L.str.5, 46
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs
.size .L.str.7, 87
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Hello from %d\n"
.size .L.str.8, 15
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n"
.size .L.str.9, 80
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nPreparing for %d %s threads operating on %d vectors of %d elements.\n"
.size .L.str.10, 70
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU"
.size .L.str.11, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Launching with %d blocks of %d threads.\n"
.size .L.str.12, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Elapsed time for %d threads and %d elements is %.3f \302\265s\n"
.size .L.str.13, 57
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Rate %.3f GFLOPS, %.3f GB/s\n"
.size .L.str.14, 30
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n"
.size .L.str.15, 65
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "correct"
.size .L.str.16, 8
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "**wrong**"
.size .L.str.17, 10
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "=="
.size .L.str.18, 3
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "!="
.size .L.str.19, 3
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "~"
.size .L.str.20, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17cuda_thread_startv"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_app"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nCUDA Routine Resource Usage:"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_thread_startv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym app
.addrsig_sym d_app
.addrsig_sym _Z17cuda_thread_startv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4712_00000000-6_hw3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7time_fpv
.type _Z7time_fpv, @function
_Z7time_fpv:
.LFB2094:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z7time_fpv, .-_Z7time_fpv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "No GPU found, exiting.\n"
.LC2:
.string "CUDA error %d, %s\n"
.LC3:
.string "Using GPU %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n"
.align 8
.LC6:
.string "GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n"
.align 8
.LC7:
.string "GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n"
.align 8
.LC8:
.string "\nCUDA Routine Resource Usage:\n"
.align 8
.LC9:
.string " Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs; %d max threads per block.\n"
.text
.globl _Z14print_gpu_infov
.type _Z14print_gpu_infov, @function
_Z14print_gpu_infov:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1200, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
je .L14
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L15
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
movq 448(%rsp), %r8
shrq $20, %r8
pxor %xmm0, %xmm0
cvtsi2sdl 508(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq 160(%rsp), %rcx
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 480(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1224
movl 476(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1232
movl 564(%rsp), %r9d
movl 540(%rsp), %r8d
movl 536(%rsp), %ecx
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1216
movl 464(%rsp), %r9d
movl 512(%rsp), %r8d
movl 456(%rsp), %ecx
movl 12(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
leaq _Z17cuda_thread_startv(%rip), %rsi
call cudaFuncGetAttributes@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L17
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 1224
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1232
movl 60(%rsp), %r9d
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1216
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $1200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z14print_gpu_infov, .-_Z14print_gpu_infov
.section .rodata.str1.1
.LC11:
.string "Hello from %d\n"
.text
.globl _Z15pt_thread_startPv
.type _Z15pt_thread_startPv, @function
_Z15pt_thread_startPv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl 68+app(%rip), %eax
cltd
idivl app(%rip)
movl %ebx, %edx
imull %eax, %edx
leal (%rax,%rdx), %ecx
cmpl %ecx, %edx
jge .L20
movslq %edx, %rdx
movq %rdx, %r8
salq $4, %r8
movl %eax, %r11d
addq %rdx, %r11
salq $4, %r11
leaq app(%rip), %r10
leaq 64(%r10), %r9
movq %rsp, %rcx
jmp .L23
.L29:
movq 88(%r10), %rax
movdqa 16(%rsp), %xmm3
movaps %xmm3, (%rax,%r8)
addq $16, %r8
cmpq %r11, %r8
je .L20
.L23:
movq 80(%r10), %rax
movdqa (%rax,%r8), %xmm2
movaps %xmm2, (%rsp)
leaq 16(%rsp), %rsi
movq %r10, %rdx
.L22:
movq %rsi, %rdi
movl $0, %eax
pxor %xmm1, %xmm1
.L21:
movss 4(%rdx,%rax), %xmm0
mulss (%rax,%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $16, %rax
jne .L21
movss %xmm1, (%rdi)
addq $4, %rsi
addq $16, %rdx
cmpq %r9, %rdx
jne .L22
jmp .L29
.L20:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z15pt_thread_startPv, .-_Z15pt_thread_startPv
.globl _Z36__device_stub__Z17cuda_thread_startvv
.type _Z36__device_stub__Z17cuda_thread_startvv, @function
_Z36__device_stub__Z17cuda_thread_startvv:
.LFB2122:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17cuda_thread_startv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2122:
.size _Z36__device_stub__Z17cuda_thread_startvv, .-_Z36__device_stub__Z17cuda_thread_startvv
.globl _Z17cuda_thread_startv
.type _Z17cuda_thread_startv, @function
_Z17cuda_thread_startv:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17cuda_thread_startvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z17cuda_thread_startv, .-_Z17cuda_thread_startv
.section .rodata.str1.1
.LC12:
.string "=="
.LC13:
.string "!="
.LC15:
.string "correct"
.LC16:
.string "**wrong**"
.LC17:
.string "~"
.section .rodata.str1.8
.align 8
.LC19:
.string "Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n"
.section .rodata.str1.1
.LC20:
.string "GPU"
.section .rodata.str1.8
.align 8
.LC21:
.string "\nPreparing for %d %s threads operating on %d vectors of %d elements.\n"
.align 8
.LC22:
.string "Launching with %d blocks of %d threads.\n"
.align 8
.LC25:
.string "Elapsed time for %d threads and %d elements is %.3f \302\265s\n"
.section .rodata.str1.1
.LC26:
.string "Rate %.3f GFLOPS, %.3f GB/s\n"
.section .rodata.str1.8
.align 8
.LC29:
.string "\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n"
.text
.globl main
.type main, @function
main:
.LFB2097:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L114
movb $0, 72+app(%rip)
movl $1, %r14d
.L41:
movl %r14d, app(%rip)
movl $1, %r15d
movl $1048576, %eax
.L42:
movl %eax, 68+app(%rip)
cmpl $0, app(%rip)
jle .L97
testl %eax, %eax
jle .L97
call _Z14print_gpu_infov
movl 68+app(%rip), %eax
movslq %eax, %rdi
sall $4, %eax
movl %eax, (%rsp)
movq %rdi, %rax
shrq $59, %rax
jne .L45
salq $4, %rdi
call _Znam@PLT
movq %rax, 80+app(%rip)
movslq 68+app(%rip), %rdi
movq %rdi, %rax
shrq $59, %rax
jne .L115
salq $4, %rdi
call _Znam@PLT
movq %rax, 88+app(%rip)
movslq 68+app(%rip), %rsi
salq $4, %rsi
leaq 96+app(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L116
movslq 68+app(%rip), %rsi
salq $4, %rsi
leaq 104+app(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L117
movl $4, %r9d
movl 68+app(%rip), %r8d
leaq .LC20(%rip), %rcx
movl app(%rip), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
cmpl $0, 68+app(%rip)
jg .L53
.L54:
leaq app(%rip), %r12
leaq 16(%r12), %rbp
leaq 64(%rbp), %r13
.L56:
leaq -16(%rbp), %rbx
.L57:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L57
addq $16, %rbp
cmpq %r13, %rbp
jne .L56
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L118
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L119
movslq (%rsp), %rbp
movl $1, %ecx
movq %rbp, %rdx
movq 80+app(%rip), %rsi
movq 96+app(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L120
movl $1, %r8d
movl $0, %ecx
movl $112, %edx
leaq app(%rip), %rsi
leaq _ZL5d_app(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L121
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L122
movl %r15d, %ecx
movl %r14d, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r14d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L123
.L64:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L124
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L125
movl $0xbf8ccccd, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L126
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
mulsd .LC24(%rip), %xmm0
movsd %xmm0, (%rsp)
movl $2, %ecx
movq %rbp, %rdx
movq 104+app(%rip), %rsi
movq 88+app(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L127
movl 68+app(%rip), %ecx
movslq %ecx, %rax
salq $5, %rax
js .L69
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
.L70:
imull $28, %ecx, %eax
pxor %xmm7, %xmm7
cvtsi2sdl %eax, %xmm7
movsd %xmm7, 8(%rsp)
movsd (%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
movl app(%rip), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC0(%rip), %xmm0
movq %rbx, %xmm1
mulsd %xmm0, %xmm1
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm5
divsd %xmm5, %xmm0
divsd %xmm5, %xmm1
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
cmpb $0, 72+app(%rip)
je .L71
movl 68+app(%rip), %r15d
testl %r15d, %r15d
jle .L90
movslq %r15d, %r15
movl $0, %ebx
movl $0x00000000, (%rsp)
movl $-1, %r13d
leaq 64(%r12), %rbp
jmp .L80
.L114:
movl %edi, %ebx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
negl %r14d
cmovs %eax, %r14d
shrl $31, %eax
movb %al, 72+app(%rip)
cmpl $2, %ebx
jle .L41
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
imull %r14d, %eax
movl %eax, app(%rip)
cmpl $3, %ebx
jle .L88
movq 24(%rbp), %rdi
movl $0, %esi
call strtod@PLT
mulsd .LC18(%rip), %xmm0
cvttsd2sil %xmm0, %eax
jmp .L42
.L88:
movl $1048576, %eax
jmp .L42
.L97:
movq 0(%rbp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
call __cxa_throw_bad_array_new_length@PLT
.L115:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
call __cxa_throw_bad_array_new_length@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L117:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L128:
addq $1, %r12
cmpl %r12d, 68+app(%rip)
jle .L54
.L53:
movq %r12, %rbp
salq $4, %rbp
movl $0, %ebx
.L55:
call drand48@PLT
movslq %ebx, %rax
salq $2, %rax
addq 80+app(%rip), %rax
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax,%rbp)
addl $1, %ebx
cmpl $4, %ebx
jne .L55
jmp .L128
.L118:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L119:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L120:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L121:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L122:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L123:
call _Z36__device_stub__Z17cuda_thread_startvv
jmp .L64
.L124:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L125:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L126:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L127:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
shrq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
movq %xmm1, %rbx
jmp .L70
.L110:
call sqrtf@PLT
jmp .L78
.L91:
movl %r14d, %r13d
movss %xmm0, (%rsp)
.L79:
addq $1, %rbx
cmpq %r15, %rbx
je .L129
.L80:
movl %ebx, %r14d
movq %rbx, %rax
salq $4, %rax
addq 80+app(%rip), %rax
movdqa (%rax), %xmm3
movaps %xmm3, 64(%rsp)
leaq 80(%rsp), %rcx
movq %r12, %rdx
movq %rcx, %rdi
leaq 64(%rsp), %rsi
.L74:
movq %rdi, %r8
movl $0, %eax
pxor %xmm1, %xmm1
.L73:
movss 4(%rdx,%rax), %xmm0
mulss (%rax,%rsi), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $16, %rax
jne .L73
movss %xmm1, (%r8)
addq $4, %rdi
addq $16, %rdx
cmpq %rbp, %rdx
jne .L74
leaq 16(%rcx), %rax
pxor %xmm0, %xmm0
.L75:
movss (%rcx), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rcx
cmpq %rax, %rcx
jne .L75
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L110
sqrtss %xmm0, %xmm0
.L78:
testl %r13d, %r13d
js .L91
movss (%rsp), %xmm4
comiss %xmm0, %xmm4
cmova %r14d, %r13d
minss %xmm4, %xmm0
movss %xmm0, (%rsp)
jmp .L79
.L129:
movss (%rsp), %xmm6
movaps %xmm6, %xmm0
andps .LC27(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm6, %xmm1
pxor %xmm2, %xmm2
ucomiss %xmm2, %xmm6
jp .L99
je .L81
.L99:
cvtss2sd %xmm0, %xmm0
movsd .LC28(%rip), %xmm2
comisd %xmm0, %xmm2
ja .L83
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
leaq .LC16(%rip), %rdx
cmpl $-1, %r13d
je .L85
movq %rax, %r8
jmp .L85
.L81:
cmpl $-1, %r13d
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
cmovne %rax, %r8
.L72:
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rax
movsd .LC28(%rip), %xmm2
comisd %xmm0, %xmm2
leaq .LC15(%rip), %rdx
leaq .LC16(%rip), %rcx
cmovbe %rcx, %rdx
.L85:
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %rax
.cfi_def_cfa_offset 192
pxor %xmm0, %xmm0
movl %r13d, %r9d
movl $-1, %ecx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
.L71:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L130
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
movl $-1, %r13d
pxor %xmm0, %xmm0
pxor %xmm1, %xmm1
leaq .LC12(%rip), %r8
jmp .L72
.L83:
cmpl $-1, %r13d
leaq .LC12(%rip), %r8
leaq .LC13(%rip), %rax
cmovne %rax, %r8
leaq .LC17(%rip), %rax
leaq .LC15(%rip), %rdx
jmp .L85
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size main, .-main
.section .rodata.str1.1
.LC30:
.string "_Z17cuda_thread_startv"
.LC31:
.string "d_app"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2125:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_thread_startv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $112, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5d_app(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5d_app
.comm _ZL5d_app,112,32
.globl app
.bss
.align 32
.type app, @object
.size app, 112
app:
.zero 112
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -400107883
.long 1041313291
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC18:
.long 0
.long 1093664768
.align 8
.LC24:
.long -755914244
.long 1062232653
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC27:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC28:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw3.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7time_fpv
.LCPI0_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z7time_fpv
.p2align 4, 0x90
.type _Z7time_fpv,@function
_Z7time_fpv: # @_Z7time_fpv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7time_fpv, .Lfunc_end0-_Z7time_fpv
.cfi_endproc
# -- End function
.globl _Z32__device_stub__cuda_thread_startv # -- Begin function _Z32__device_stub__cuda_thread_startv
.p2align 4, 0x90
.type _Z32__device_stub__cuda_thread_startv,@function
_Z32__device_stub__cuda_thread_startv: # @_Z32__device_stub__cuda_thread_startv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17cuda_thread_startv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z32__device_stub__cuda_thread_startv, .Lfunc_end1-_Z32__device_stub__cuda_thread_startv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14print_gpu_infov
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z14print_gpu_infov
.p2align 4, 0x90
.type _Z14print_gpu_infov,@function
_Z14print_gpu_infov: # @_Z14print_gpu_infov
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 20(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 20(%rsp)
je .LBB2_5
# %bb.1:
movl $0, 16(%rsp)
leaq 16(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movl 16(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 16(%rsp), %esi
leaq 80(%rsp), %rdi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_6
# %bb.3:
movl 16(%rsp), %esi
cvtsi2sdl 428(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
movq 368(%rsp), %rcx
shrq $20, %rcx
leaq 80(%rsp), %rdx
movl $.L.str.3, %edi
# kill: def $ecx killed $ecx killed $rcx
movb $1, %al
callq printf
movl 16(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl 468(%rsp), %r8d
movl 388(%rsp), %r9d
movl 400(%rsp), %eax
movl %eax, (%rsp)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 16(%rsp), %esi
movl 432(%rsp), %ecx
movl 376(%rsp), %edx
movl 384(%rsp), %r8d
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $_Z17cuda_thread_startv, %esi
callq hipFuncGetAttributes
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
movq 40(%rsp), %rcx
movl 56(%rsp), %r8d
movl 52(%rsp), %r9d
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 1568
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14print_gpu_infov, .Lfunc_end2-_Z14print_gpu_infov
.cfi_endproc
# -- End function
.globl _Z15pt_thread_startPv # -- Begin function _Z15pt_thread_startPv
.p2align 4, 0x90
.type _Z15pt_thread_startPv,@function
_Z15pt_thread_startPv: # @_Z15pt_thread_startPv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str.8, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl app+68(%rip), %eax
cltd
idivl app(%rip)
testl %eax, %eax
jle .LBB3_7
# %bb.1: # %.lr.ph.preheader
imull %eax, %ebx
addl %ebx, %eax
movslq %ebx, %rcx
cltq
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq app+80(%rip), %rsi
movq %rcx, %rdx
shlq $4, %rdx
movaps (%rsi,%rdx), %xmm0
movaps %xmm0, 16(%rsp)
movl $app+4, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movl $0, (%rsp,%rdi,4)
xorps %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 16(%rsp,%r8,4), %xmm1
addss %xmm1, %xmm0
incq %r8
cmpq $4, %r8
jne .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=2
movss %xmm0, (%rsp,%rdi,4)
incq %rdi
addq $16, %rsi
cmpq $4, %rdi
jne .LBB3_3
# %bb.6: # in Loop: Header=BB3_2 Depth=1
movq app+88(%rip), %rsi
movaps (%rsp), %xmm0
movaps %xmm0, (%rsi,%rdx)
incq %rcx
cmpq %rax, %rcx
jl .LBB3_2
.LBB3_7: # %._crit_edge
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15pt_thread_startPv, .Lfunc_end3-_Z15pt_thread_startPv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x4130000000000000 # double 1048576
.LCPI4_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI4_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_5:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.LCPI4_7:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI4_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.LCPI4_6:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_8:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %r15d
movl $1, %ebx
movl $1, %eax
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB4_2:
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %ebp
negl %ebp
cmovsl %eax, %ebp
movb %cl, app+72(%rip)
cmpl $3, %r15d
jl .LBB4_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB4_4:
movl %ebx, %eax
imull %ebp, %eax
movl %eax, app(%rip)
movl $1048576, %eax # imm = 0x100000
cmpl $4, %r15d
jl .LBB4_6
# %bb.5:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
mulsd .LCPI4_0(%rip), %xmm0
cvttsd2si %xmm0, %eax
.LBB4_6:
movl %eax, app+68(%rip)
cmpl $0, app(%rip)
jle .LBB4_48
# %bb.7:
testl %eax, %eax
jle .LBB4_48
# %bb.8:
callq _Z14print_gpu_infov
movslq app+68(%rip), %r12
movq %r12, %r14
shlq $4, %r14
testq %r12, %r12
movq $-1, %r15
cmovnsq %r14, %r15
movq %r15, %rdi
callq _Znam
movq %rax, app+80(%rip)
movq %r15, %rdi
callq _Znam
movq %rax, app+88(%rip)
movl $app+96, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_49
# %bb.9:
movslq app+68(%rip), %rsi
shlq $4, %rsi
movl $app+104, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB4_49
# %bb.10:
movl app(%rip), %esi
movl app+68(%rip), %ecx
movl $.L.str.10, %edi
movl $.L.str.11, %edx
movl $4, %r8d
xorl %eax, %eax
callq printf
cmpl $0, app+68(%rip)
jle .LBB4_15
# %bb.11: # %.preheader147.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_12: # %.preheader147
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_12 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movq app+80(%rip), %rax
addq %r14, %rax
movss %xmm0, (%rax,%r13,4)
incq %r13
cmpq $4, %r13
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=1
incq %r15
movslq app+68(%rip), %rax
addq $16, %r14
cmpq %rax, %r15
jl .LBB4_12
.LBB4_15: # %.preheader145.preheader
shll $4, %r12d
movl $app+4, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.preheader145
# =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_17: # Parent Loop BB4_16 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq $4, %r13
jne .LBB4_17
# %bb.18: # in Loop: Header=BB4_16 Depth=1
incq %r15
addq $16, %r14
cmpq $4, %r15
jne .LBB4_16
# %bb.19:
leaq 72(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB4_49
# %bb.20:
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB4_49
# %bb.21:
movq app+96(%rip), %rdi
movq app+80(%rip), %rsi
movslq %r12d, %r14
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_49
# %bb.22:
movl $d_app, %edi
movl $app, %esi
movl $112, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_49
# %bb.23:
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB4_49
# %bb.24:
movl $.L.str.12, %edi
movl %ebp, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebx, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17cuda_thread_startv, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB4_49
# %bb.27:
movq 24(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB4_49
# %bb.28:
movl $-1081291571, (%rsp) # imm = 0xBF8CCCCD
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB4_49
# %bb.29:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp) # 4-byte Spill
movq app+88(%rip), %rdi
movq app+104(%rip), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_49
# %bb.30:
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
movsd %xmm0, 80(%rsp) # 8-byte Spill
movslq app+68(%rip), %rdx
movq %rdx, %rax
shlq $5, %rax
movq %rax, %xmm0
punpckldq .LCPI4_2(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI4_3(%rip), %xmm0
movapd %xmm0, %xmm2
unpckhpd %xmm0, %xmm2 # xmm2 = xmm2[1],xmm0[1]
leal (%rdx,%rdx,8), %eax
leal (%rax,%rax,2), %eax
addl %edx, %eax
cvtsi2sd %eax, %xmm3
movsd %xmm3, 88(%rsp) # 8-byte Spill
addsd %xmm0, %xmm2
movapd %xmm2, 32(%rsp) # 16-byte Spill
movl app(%rip), %esi
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movl $.L.str.13, %edi
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm3 # xmm3 = mem[0],zero
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm3, %xmm0
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movapd 32(%rsp), %xmm2 # 16-byte Reload
mulsd %xmm3, %xmm2
divsd %xmm1, %xmm2
movapd %xmm2, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
cmpb $0, app+72(%rip)
je .LBB4_34
# %bb.31: # %.preheader144
cmpl $0, app+68(%rip)
jle .LBB4_32
# %bb.35: # %.lr.ph.preheader
xorpd %xmm2, %xmm2
movl $-1, %ebx
xorl %r14d, %r14d
xorpd %xmm3, %xmm3
jmp .LBB4_36
.p2align 4, 0x90
.LBB4_47: # %.split
# in Loop: Header=BB4_36 Depth=1
cmovnel %r14d, %ebx
incq %r14
movslq app+68(%rip), %rax
movaps %xmm0, %xmm3
cmpq %rax, %r14
jge .LBB4_33
.LBB4_36: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_37 Depth 2
# Child Loop BB4_38 Depth 3
# Child Loop BB4_41 Depth 2
movq app+80(%rip), %rax
movq %r14, %rcx
shlq $4, %rcx
movaps (%rax,%rcx), %xmm0
movaps %xmm0, (%rsp)
movl $app+4, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_37: # Parent Loop BB4_36 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_38 Depth 3
movl $0, 48(%rsp,%rcx,4)
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_38: # Parent Loop BB4_36 Depth=1
# Parent Loop BB4_37 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsp,%rdx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq $4, %rdx
jne .LBB4_38
# %bb.39: # in Loop: Header=BB4_37 Depth=2
movss %xmm0, 48(%rsp,%rcx,4)
incq %rcx
addq $16, %rax
cmpq $4, %rcx
jne .LBB4_37
# %bb.40: # %.preheader.preheader
# in Loop: Header=BB4_36 Depth=1
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_41: # %.preheader
# Parent Loop BB4_36 Depth=1
# => This Inner Loop Header: Depth=2
movss 48(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $4, %rax
jne .LBB4_41
# %bb.42: # in Loop: Header=BB4_36 Depth=1
ucomiss %xmm2, %xmm0
jb .LBB4_44
# %bb.43: # in Loop: Header=BB4_36 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_45
.p2align 4, 0x90
.LBB4_44: # %call.sqrt
# in Loop: Header=BB4_36 Depth=1
movss %xmm3, 32(%rsp) # 4-byte Spill
callq sqrtf@PLT
movss 32(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB4_45: # %.split
# in Loop: Header=BB4_36 Depth=1
testl %ebx, %ebx
sets %al
ucomiss %xmm0, %xmm3
seta %cl
orb %al, %cl
testb %cl, %cl
jne .LBB4_47
# %bb.46: # %.split
# in Loop: Header=BB4_36 Depth=1
movaps %xmm3, %xmm0
jmp .LBB4_47
.LBB4_32:
movl $-1, %ebx
xorpd %xmm0, %xmm0
.LBB4_33: # %._crit_edge
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movaps .LCPI4_6(%rip), %xmm2 # xmm2 = [NaN,NaN]
andps %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
cvtss2sd %xmm2, %xmm2
cmpl $-1, %ebx
movl $.L.str.18, %r9d
movl $.L.str.19, %eax
movl $.L.str.19, %ecx
cmoveq %r9, %rcx
movsd .LCPI4_7(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
movl $.L.str.16, %edx
movl $.L.str.17, %esi
cmovaq %rdx, %rsi
movl $.L.str.20, %edx
cmovbeq %rax, %rdx
ucomiss .LCPI4_8(%rip), %xmm0
cmovneq %rdx, %r9
cmovpq %rdx, %r9
movl $.L.str.15, %edi
xorps %xmm0, %xmm0
movl $-1, %edx
movl %ebx, %r8d
movb $2, %al
callq printf
.LBB4_34:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_49:
.cfi_def_cfa_offset 176
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB4_48:
movq (%r14), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_thread_startv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_app, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $112, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type app,@object # @app
.bss
.globl app
.p2align 3, 0x0
app:
.zero 112
.size app, 112
.type d_app,@object # @d_app
.local d_app
.comm d_app,112,8
.type _Z17cuda_thread_startv,@object # @_Z17cuda_thread_startv
.section .rodata,"a",@progbits
.globl _Z17cuda_thread_startv
.p2align 3, 0x0
_Z17cuda_thread_startv:
.quad _Z32__device_stub__cuda_thread_startv
.size _Z17cuda_thread_startv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No GPU found, exiting.\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error %d, %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Using GPU %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU %d: %s @ %.2f GHz WITH %d MiB GLOBAL MEM\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU %d: CC: %d.%d MP: %2d TH/WP: %3d TH/BL: %4d\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU %d: SHARED: %5d CONST: %5d # REGS: %5d\n"
.size .L.str.5, 46
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Our CUDA Thread: %6zd shared, %zd const, %zd loc, %d regs
.size .L.str.7, 87
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Hello from %d\n"
.size .L.str.8, 15
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Usage: %s [ NUM_PTHREADS | - NUM_CUDA_BLOCKS ] [THD_PER_BLOCK] [DATA_SIZE_MiB]\n"
.size .L.str.9, 80
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nPreparing for %d %s threads operating on %d vectors of %d elements.\n"
.size .L.str.10, 70
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU"
.size .L.str.11, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Launching with %d blocks of %d threads.\n"
.size .L.str.12, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Elapsed time for %d threads and %d elements is %.3f \302\265s\n"
.size .L.str.13, 57
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Rate %.3f GFLOPS, %.3f GB/s\n"
.size .L.str.14, 30
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nMinimum mag is %s, %d %s %d (correct) %.4f %s %.4f (correct)\n"
.size .L.str.15, 65
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "correct"
.size .L.str.16, 8
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "**wrong**"
.size .L.str.17, 10
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "=="
.size .L.str.18, 3
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "!="
.size .L.str.19, 3
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "~"
.size .L.str.20, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17cuda_thread_startv"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_app"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nCUDA Routine Resource Usage:"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_thread_startv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym app
.addrsig_sym d_app
.addrsig_sym _Z17cuda_thread_startv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuConvertRGBToLABKernel(const float4* src, float4* dst, size_t stride, int width, int height, bool isNormalized)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int c = y*stride + x;
if (x<width && y<height)
{
// Read
float4 in = src[c];
if (!isNormalized)
{
in.x /= 255.0f;
in.y /= 255.0f;
in.z /= 255.0f;
in.w /= 255.0f;
}
float R = in.x;
float G = in.y;
float B = in.z;
// convert to XYZ
float4 XYZ;
XYZ.x = 0.4124564f*R + 0.3575761f*G + 0.1804375f*B;
XYZ.y = 0.2126729f*R + 0.7151522f*G + 0.0721750f*B;
XYZ.z = 0.0193339f*R + 0.1191920f*G + 0.9503041f*B;
// normalize for D65 white point
XYZ.x /= 0.950456f;
XYZ.z /= 1.088754f;
float cubeRootX, cubeRootY, cubeRootZ;
const float T1 = 216/24389.0f;
const float T2 = 24389/27.0f;
if (XYZ.x > T1)
cubeRootX = cbrtf(XYZ.x);
else
cubeRootX = (T2 * XYZ.x + 16) / 116;
if (XYZ.y > T1)
cubeRootY = cbrtf(XYZ.y);
else
cubeRootY = (T2 * XYZ.y + 16) / 116;
if (XYZ.z > T1)
cubeRootZ = cbrtf(XYZ.z);
else
cubeRootZ = (T2 * XYZ.z + 16) / 116;
dst[c] = make_float4(116*cubeRootY-16, 500*(cubeRootX-cubeRootY), 200*(cubeRootY-cubeRootZ), in.w);
}
} | .file "tmpxft_000c67e0_00000000-6_cuConvertRGBToLABKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
.type _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib, @function
_Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23cuConvertRGBToLABKernelPK6float4PS_miib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib, .-_Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
.globl _Z23cuConvertRGBToLABKernelPK6float4PS_miib
.type _Z23cuConvertRGBToLABKernelPK6float4PS_miib, @function
_Z23cuConvertRGBToLABKernelPK6float4PS_miib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r9b, %r9d
call _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23cuConvertRGBToLABKernelPK6float4PS_miib, .-_Z23cuConvertRGBToLABKernelPK6float4PS_miib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuConvertRGBToLABKernelPK6float4PS_miib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuConvertRGBToLABKernelPK6float4PS_miib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuConvertRGBToLABKernel(const float4* src, float4* dst, size_t stride, int width, int height, bool isNormalized)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int c = y*stride + x;
if (x<width && y<height)
{
// Read
float4 in = src[c];
if (!isNormalized)
{
in.x /= 255.0f;
in.y /= 255.0f;
in.z /= 255.0f;
in.w /= 255.0f;
}
float R = in.x;
float G = in.y;
float B = in.z;
// convert to XYZ
float4 XYZ;
XYZ.x = 0.4124564f*R + 0.3575761f*G + 0.1804375f*B;
XYZ.y = 0.2126729f*R + 0.7151522f*G + 0.0721750f*B;
XYZ.z = 0.0193339f*R + 0.1191920f*G + 0.9503041f*B;
// normalize for D65 white point
XYZ.x /= 0.950456f;
XYZ.z /= 1.088754f;
float cubeRootX, cubeRootY, cubeRootZ;
const float T1 = 216/24389.0f;
const float T2 = 24389/27.0f;
if (XYZ.x > T1)
cubeRootX = cbrtf(XYZ.x);
else
cubeRootX = (T2 * XYZ.x + 16) / 116;
if (XYZ.y > T1)
cubeRootY = cbrtf(XYZ.y);
else
cubeRootY = (T2 * XYZ.y + 16) / 116;
if (XYZ.z > T1)
cubeRootZ = cbrtf(XYZ.z);
else
cubeRootZ = (T2 * XYZ.z + 16) / 116;
dst[c] = make_float4(116*cubeRootY-16, 500*(cubeRootX-cubeRootY), 200*(cubeRootY-cubeRootZ), in.w);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvertRGBToLABKernel(const float4* src, float4* dst, size_t stride, int width, int height, bool isNormalized)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int c = y*stride + x;
if (x<width && y<height)
{
// Read
float4 in = src[c];
if (!isNormalized)
{
in.x /= 255.0f;
in.y /= 255.0f;
in.z /= 255.0f;
in.w /= 255.0f;
}
float R = in.x;
float G = in.y;
float B = in.z;
// convert to XYZ
float4 XYZ;
XYZ.x = 0.4124564f*R + 0.3575761f*G + 0.1804375f*B;
XYZ.y = 0.2126729f*R + 0.7151522f*G + 0.0721750f*B;
XYZ.z = 0.0193339f*R + 0.1191920f*G + 0.9503041f*B;
// normalize for D65 white point
XYZ.x /= 0.950456f;
XYZ.z /= 1.088754f;
float cubeRootX, cubeRootY, cubeRootZ;
const float T1 = 216/24389.0f;
const float T2 = 24389/27.0f;
if (XYZ.x > T1)
cubeRootX = cbrtf(XYZ.x);
else
cubeRootX = (T2 * XYZ.x + 16) / 116;
if (XYZ.y > T1)
cubeRootY = cbrtf(XYZ.y);
else
cubeRootY = (T2 * XYZ.y + 16) / 116;
if (XYZ.z > T1)
cubeRootZ = cbrtf(XYZ.z);
else
cubeRootZ = (T2 * XYZ.z + 16) / 116;
dst[c] = make_float4(116*cubeRootY-16, 500*(cubeRootX-cubeRootY), 200*(cubeRootY-cubeRootZ), in.w);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvertRGBToLABKernel(const float4* src, float4* dst, size_t stride, int width, int height, bool isNormalized)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int c = y*stride + x;
if (x<width && y<height)
{
// Read
float4 in = src[c];
if (!isNormalized)
{
in.x /= 255.0f;
in.y /= 255.0f;
in.z /= 255.0f;
in.w /= 255.0f;
}
float R = in.x;
float G = in.y;
float B = in.z;
// convert to XYZ
float4 XYZ;
XYZ.x = 0.4124564f*R + 0.3575761f*G + 0.1804375f*B;
XYZ.y = 0.2126729f*R + 0.7151522f*G + 0.0721750f*B;
XYZ.z = 0.0193339f*R + 0.1191920f*G + 0.9503041f*B;
// normalize for D65 white point
XYZ.x /= 0.950456f;
XYZ.z /= 1.088754f;
float cubeRootX, cubeRootY, cubeRootZ;
const float T1 = 216/24389.0f;
const float T2 = 24389/27.0f;
if (XYZ.x > T1)
cubeRootX = cbrtf(XYZ.x);
else
cubeRootX = (T2 * XYZ.x + 16) / 116;
if (XYZ.y > T1)
cubeRootY = cbrtf(XYZ.y);
else
cubeRootY = (T2 * XYZ.y + 16) / 116;
if (XYZ.z > T1)
cubeRootZ = cbrtf(XYZ.z);
else
cubeRootZ = (T2 * XYZ.z + 16) / 116;
dst[c] = make_float4(116*cubeRootY-16, 500*(cubeRootX-cubeRootY), 200*(cubeRootY-cubeRootZ), in.w);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.globl _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.p2align 8
.type _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib,@function
_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
s_bitcmp1_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
global_load_b128 v[0:3], v[0:1], off
s_cbranch_vccnz .LBB0_3
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, 0x437f0000, 0x437f0000, v0
v_div_scale_f32 v7, null, 0x437f0000, 0x437f0000, v1
v_div_scale_f32 v9, null, 0x437f0000, 0x437f0000, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v8, v6
v_div_scale_f32 v10, null, 0x437f0000, 0x437f0000, v3
v_rcp_f32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v12, v9
v_div_scale_f32 v16, vcc_lo, v0, 0x437f0000, v0
v_rcp_f32_e32 v13, v10
v_fma_f32 v14, -v6, v8, 1.0
s_delay_alu instid0(TRANS32_DEP_3)
v_fma_f32 v15, -v7, v11, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v9, v12, 1.0
v_fmac_f32_e32 v8, v14, v8
v_div_scale_f32 v14, s2, v1, 0x437f0000, v1
v_fmac_f32_e32 v11, v15, v11
v_fma_f32 v18, -v10, v13, 1.0
v_fmac_f32_e32 v12, v17, v12
v_div_scale_f32 v15, s3, v2, 0x437f0000, v2
v_div_scale_f32 v17, s4, v3, 0x437f0000, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v13, v18, v13 :: v_dual_mul_f32 v18, v16, v8
v_dual_mul_f32 v19, v14, v11 :: v_dual_mul_f32 v20, v15, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v21, v17, v13
v_fma_f32 v22, -v6, v18, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v23, -v7, v19, v14
v_fma_f32 v24, -v9, v20, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v25, -v10, v21, v17
v_dual_fmac_f32 v18, v22, v8 :: v_dual_fmac_f32 v19, v23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v20, v24, v12 :: v_dual_fmac_f32 v21, v25, v13
v_fma_f32 v6, -v6, v18, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v7, -v7, v19, v14
v_fma_f32 v9, -v9, v20, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v10, -v10, v21, v17
v_div_fmas_f32 v6, v6, v8, v18
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v7, v7, v11, v19
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_div_fixup_f32 v0, v6, 0x437f0000, v0
v_div_fmas_f32 v8, v9, v12, v20
s_mov_b32 vcc_lo, s4
v_div_fixup_f32 v1, v7, 0x437f0000, v1
v_div_fmas_f32 v9, v10, v13, v21
v_div_fixup_f32 v2, v8, 0x437f0000, v2
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v3, v9, 0x437f0000, v3
.LBB0_3:
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, 0x3eb71437, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v6, v0, 0x3ed32d7c, v6
v_fmamk_f32 v6, v2, 0x3e38c49c, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v7, null, 0x3f735116, 0x3f735116, v6
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v6, 0x3f735116, v6
v_mul_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v10, v9
v_fmac_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v9
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v7, v7, 0x3f735116, v6
v_cmpx_nlt_f32_e32 0x3c111aa7, v7
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_mov_b32 s3, 0x4461d2f7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v6, s3, v7, 0x41800000
v_div_scale_f32 v7, null, 0x42e80000, 0x42e80000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v6, 0x42e80000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v7, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v7, -v7, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v8, v10
v_div_fixup_f32 v6, v7, 0x42e80000, v6
.LBB0_5:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_7
v_ldexp_f32 v6, |v7|, 24
v_cmp_gt_f32_e64 vcc_lo, 0x800000, |v7|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, |v7|, v6, vcc_lo
v_log_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x3eaaaaab, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, v8, v8
v_rcp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v6, v9, -v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v6, v6, 0xbeaaaaab, v8
v_ldexp_f32 v8, v6, -8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x198
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v6, 0x7fffffff, v6, v7
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v7, 0x3f371437, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v0, 0x3e59c6ed, v7
v_fmamk_f32 v8, v2, 0x3d93d07d, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nlt_f32_e32 0x3c111aa7, v8
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_9
s_mov_b32 s3, 0x4461d2f7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, s3, v8, 0x41800000
v_div_scale_f32 v8, null, 0x42e80000, 0x42e80000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v8, v9, 1.0
v_fmac_f32_e32 v9, v10, v9
v_div_scale_f32 v10, vcc_lo, v7, 0x42e80000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v9
v_fma_f32 v12, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v9
v_fma_f32 v8, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v8, v8, v9, v11
v_div_fixup_f32 v7, v8, 0x42e80000, v7
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_11
v_ldexp_f32 v7, |v8|, 24
v_cmp_gt_f32_e64 vcc_lo, 0x800000, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, |v8|, v7, vcc_lo
v_log_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x3eaaaaab, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, v9, v9
v_rcp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v7, v10, -v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v7, 0xbeaaaaab, v9
v_ldexp_f32 v9, v7, -8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v7, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x198
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v7, 0x7fffffff, v7, v8
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v1, 0x3df41aef, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v0, 0x3c9e6221, v1
v_fmamk_f32 v0, v2, 0x3f734721, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v1, null, 0x3f8b5c4b, 0x3f8b5c4b, v0
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v8, v2
v_div_scale_f32 v8, vcc_lo, v0, 0x3f8b5c4b, v0
v_mul_f32_e32 v9, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v1, v9, v8
v_fmac_f32_e32 v9, v10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v9, v8
v_div_fmas_f32 v1, v1, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v1, 0x3f8b5c4b, v0
v_cmpx_nlt_f32_e32 0x3c111aa7, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_13
s_mov_b32 s3, 0x4461d2f7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v0, s3, v0, 0x41800000
v_div_scale_f32 v1, null, 0x42e80000, 0x42e80000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v1, v2, 1.0
v_fmac_f32_e32 v2, v8, v2
v_div_scale_f32 v8, vcc_lo, v0, 0x42e80000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v2
v_fma_f32 v10, -v1, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v2
v_fma_f32 v1, -v1, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v2, v9
v_div_fixup_f32 v1, v1, 0x42e80000, v0
.LBB0_13:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_15
v_ldexp_f32 v1, |v0|, 24
v_cmp_gt_f32_e64 vcc_lo, 0x800000, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, |v0|, v1, vcc_lo
v_log_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x3eaaaaab, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, v2, v2
v_rcp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v1, v8, -v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v1, 0xbeaaaaab, v2
v_ldexp_f32 v2, v1, -8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x198
v_cndmask_b32_e32 v1, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v1, 0x7fffffff, v1, v0
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[4:5], 4, v[4:5]
v_sub_f32_e32 v2, v6, v7
v_sub_f32_e32 v6, v7, v1
s_mov_b32 s2, 0x42e80000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v0, s2, v7, 0xc1800000
v_mul_f32_e32 v1, 0x43fa0000, v2
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, 0x43480000, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b128 v[4:5], v[0:3], off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, .Lfunc_end0-_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 1
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvertRGBToLABKernel(const float4* src, float4* dst, size_t stride, int width, int height, bool isNormalized)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int c = y*stride + x;
if (x<width && y<height)
{
// Read
float4 in = src[c];
if (!isNormalized)
{
in.x /= 255.0f;
in.y /= 255.0f;
in.z /= 255.0f;
in.w /= 255.0f;
}
float R = in.x;
float G = in.y;
float B = in.z;
// convert to XYZ
float4 XYZ;
XYZ.x = 0.4124564f*R + 0.3575761f*G + 0.1804375f*B;
XYZ.y = 0.2126729f*R + 0.7151522f*G + 0.0721750f*B;
XYZ.z = 0.0193339f*R + 0.1191920f*G + 0.9503041f*B;
// normalize for D65 white point
XYZ.x /= 0.950456f;
XYZ.z /= 1.088754f;
float cubeRootX, cubeRootY, cubeRootZ;
const float T1 = 216/24389.0f;
const float T2 = 24389/27.0f;
if (XYZ.x > T1)
cubeRootX = cbrtf(XYZ.x);
else
cubeRootX = (T2 * XYZ.x + 16) / 116;
if (XYZ.y > T1)
cubeRootY = cbrtf(XYZ.y);
else
cubeRootY = (T2 * XYZ.y + 16) / 116;
if (XYZ.z > T1)
cubeRootZ = cbrtf(XYZ.z);
else
cubeRootZ = (T2 * XYZ.z + 16) / 116;
dst[c] = make_float4(116*cubeRootY-16, 500*(cubeRootX-cubeRootY), 200*(cubeRootY-cubeRootZ), in.w);
}
} | .text
.file "cuConvertRGBToLABKernel.hip"
.globl _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib # -- Begin function _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.p2align 4, 0x90
.type _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib,@function
_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib: # @_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 15(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 15(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, .Lfunc_end0-_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib,@object # @_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.section .rodata,"a",@progbits
.globl _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.p2align 3, 0x0
_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib:
.quad _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.size _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib"
.size .L__unnamed_1, 62
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c67e0_00000000-6_cuConvertRGBToLABKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
.type _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib, @function
_Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23cuConvertRGBToLABKernelPK6float4PS_miib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib, .-_Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
.globl _Z23cuConvertRGBToLABKernelPK6float4PS_miib
.type _Z23cuConvertRGBToLABKernelPK6float4PS_miib, @function
_Z23cuConvertRGBToLABKernelPK6float4PS_miib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r9b, %r9d
call _Z57__device_stub__Z23cuConvertRGBToLABKernelPK6float4PS_miibPK6float4PS_miib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23cuConvertRGBToLABKernelPK6float4PS_miib, .-_Z23cuConvertRGBToLABKernelPK6float4PS_miib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuConvertRGBToLABKernelPK6float4PS_miib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuConvertRGBToLABKernelPK6float4PS_miib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuConvertRGBToLABKernel.hip"
.globl _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib # -- Begin function _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.p2align 4, 0x90
.type _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib,@function
_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib: # @_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 15(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 15(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, .Lfunc_end0-_Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib,@object # @_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.section .rodata,"a",@progbits
.globl _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.p2align 3, 0x0
_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib:
.quad _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.size _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib"
.size .L__unnamed_1, 62
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuConvertRGBToLABKernelPK15HIP_vector_typeIfLj4EEPS0_miib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
cudaMalloc(&ad, n*n*sizeof(int));
cudaMalloc(&bd, n*n*sizeof(int));
cudaMalloc(&cd, n*n*sizeof(int));
cudaMemcpy(ad, a, n*n*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, n*n*sizeof(int), cudaMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
cudaMemcpy(c, cd, n*n*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} | code for sm_80
Function : _Z6matMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
cudaMalloc(&ad, n*n*sizeof(int));
cudaMalloc(&bd, n*n*sizeof(int));
cudaMalloc(&cd, n*n*sizeof(int));
cudaMemcpy(ad, a, n*n*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, n*n*sizeof(int), cudaMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
cudaMemcpy(c, cd, n*n*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} | .file "tmpxft_00095824_00000000-6_A2_MATRIX_MATRIX.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6matMulPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
.globl _Z6matMulPiS_S_i
.type _Z6matMulPiS_S_i, @function
_Z6matMulPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matMulPiS_S_i, .-_Z6matMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbx
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 4(%rsp), %r9d
testl %r9d, %r9d
jle .L12
movl $0, %r10d
movl $1, %esi
movslq %r9d, %r8
.L13:
movslq %r10d, %rcx
salq $2, %rcx
leaq 0(%rbp,%rcx), %rdi
addq %rbx, %rcx
movl $1, %eax
.L14:
movl %esi, -4(%rdi,%rax,4)
movl %eax, -4(%rcx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %r8
jne .L14
leal 1(%rsi), %eax
addl %r9d, %r10d
cmpl %r9d, %esi
je .L12
movl %eax, %esi
jmp .L13
.L12:
imull %r9d, %r9d
movslq %r9d, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
cmpl $0, 4(%rsp)
jg .L16
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl 4(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
jmp .L15
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 4(%rsp)
jle .L17
.L16:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jle .L23
.L18:
imull %r12d, %eax
addl %ebx, %eax
cltq
movl 0(%r13,%rax,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L18
.L23:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %esi
jmp .L22
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6matMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
cudaMalloc(&ad, n*n*sizeof(int));
cudaMalloc(&bd, n*n*sizeof(int));
cudaMalloc(&cd, n*n*sizeof(int));
cudaMemcpy(ad, a, n*n*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, n*n*sizeof(int), cudaMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
cudaMemcpy(c, cd, n*n*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
hipMalloc(&ad, n*n*sizeof(int));
hipMalloc(&bd, n*n*sizeof(int));
hipMalloc(&cd, n*n*sizeof(int));
hipMemcpy(ad, a, n*n*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(bd, b, n*n*sizeof(int), hipMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
hipMemcpy(c, cd, n*n*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
hipMalloc(&ad, n*n*sizeof(int));
hipMalloc(&bd, n*n*sizeof(int));
hipMalloc(&cd, n*n*sizeof(int));
hipMemcpy(ad, a, n*n*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(bd, b, n*n*sizeof(int), hipMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
hipMemcpy(c, cd, n*n*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPiS_S_i
.globl _Z6matMulPiS_S_i
.p2align 8
.type _Z6matMulPiS_S_i,@function
_Z6matMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPiS_S_i, .Lfunc_end0-_Z6matMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void matMul(int *a, int *b, int *c, int n){
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int sum=0;
for(int j=0;j<n;j++)
{
sum=sum+a[row*n+j]*b[j*n+col];
}
c[n*row+col]=sum;
}
int main(){
int n;
cin>>n;
int *a= new int[n*n];
int *b = new int[n*n];
int *c = new int[n*n];
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
a[i*n+j] = i+1;
b[i*n+j] = j+1;
}
}
int *ad, *bd, *cd;
hipMalloc(&ad, n*n*sizeof(int));
hipMalloc(&bd, n*n*sizeof(int));
hipMalloc(&cd, n*n*sizeof(int));
hipMemcpy(ad, a, n*n*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(bd, b, n*n*sizeof(int), hipMemcpyHostToDevice);
dim3 grids(n, n, 1);
matMul<<<grids, 1>>>(ad, bd, cd, n);
hipMemcpy(c, cd, n*n*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
cout<<c[i*n+j]<<" ";
}
cout<<endl;
}
} | .text
.file "A2_MATRIX_MATRIX.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matMulPiS_S_i # -- Begin function _Z21__device_stub__matMulPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matMulPiS_S_i,@function
_Z21__device_stub__matMulPiS_S_i: # @_Z21__device_stub__matMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPiS_S_i, .Lfunc_end0-_Z21__device_stub__matMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 8(%rsp), %r13d
movl %r13d, %r12d
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
testl %r13d, %r13d
jle .LBB1_5
# %bb.1: # %.preheader32.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %esi
leaq (%r14,%rsi,4), %rdx
leaq (%r15,%rsi,4), %rsi
leal 1(%rcx), %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, (%rsi,%r8,4)
leaq 1(%r8), %r9
movl %r9d, (%rdx,%r8,4)
movq %r9, %r8
cmpq %r9, %r13
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r13d, %eax
cmpq %r13, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge35
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl 8(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl 8(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 16(%rsp), %rsi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.8: # %.preheader.preheader
xorl %r15d, %r15d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_9 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r15d
cmpl 8(%rsp), %r15d
jge .LBB1_17
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_12
# %bb.10: # %.lr.ph37.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph37
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
imull %r15d, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_11
.LBB1_12: # %._crit_edge38
# in Loop: Header=BB1_9 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_18
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_16
.LBB1_17: # %._crit_edge40
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPiS_S_i,@object # @_Z6matMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6matMulPiS_S_i
.p2align 3, 0x0
_Z6matMulPiS_S_i:
.quad _Z21__device_stub__matMulPiS_S_i
.size _Z6matMulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPiS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPiS_S_i
.globl _Z6matMulPiS_S_i
.p2align 8
.type _Z6matMulPiS_S_i,@function
_Z6matMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPiS_S_i, .Lfunc_end0-_Z6matMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00095824_00000000-6_A2_MATRIX_MATRIX.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6matMulPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
.globl _Z6matMulPiS_S_i
.type _Z6matMulPiS_S_i, @function
_Z6matMulPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matMulPiS_S_i, .-_Z6matMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbx
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 4(%rsp), %r9d
testl %r9d, %r9d
jle .L12
movl $0, %r10d
movl $1, %esi
movslq %r9d, %r8
.L13:
movslq %r10d, %rcx
salq $2, %rcx
leaq 0(%rbp,%rcx), %rdi
addq %rbx, %rcx
movl $1, %eax
.L14:
movl %esi, -4(%rdi,%rax,4)
movl %eax, -4(%rcx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %r8
jne .L14
leal 1(%rsi), %eax
addl %r9d, %r10d
cmpl %r9d, %esi
je .L12
movl %eax, %esi
jmp .L13
.L12:
imull %r9d, %r9d
movslq %r9d, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
movl 4(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
cmpl $0, 4(%rsp)
jg .L16
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl 4(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6matMulPiS_S_iPiS_S_i
jmp .L15
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 4(%rsp)
jle .L17
.L16:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jle .L23
.L18:
imull %r12d, %eax
addl %ebx, %eax
cltq
movl 0(%r13,%rax,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L18
.L23:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %esi
jmp .L22
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6matMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A2_MATRIX_MATRIX.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matMulPiS_S_i # -- Begin function _Z21__device_stub__matMulPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matMulPiS_S_i,@function
_Z21__device_stub__matMulPiS_S_i: # @_Z21__device_stub__matMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPiS_S_i, .Lfunc_end0-_Z21__device_stub__matMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 8(%rsp), %r13d
movl %r13d, %r12d
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
testl %r13d, %r13d
jle .LBB1_5
# %bb.1: # %.preheader32.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %esi
leaq (%r14,%rsi,4), %rdx
leaq (%r15,%rsi,4), %rsi
leal 1(%rcx), %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, (%rsi,%r8,4)
leaq 1(%r8), %r9
movl %r9d, (%rdx,%r8,4)
movq %r9, %r8
cmpq %r9, %r13
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r13d, %eax
cmpq %r13, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge35
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl 8(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl 8(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 16(%rsp), %rsi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.8: # %.preheader.preheader
xorl %r15d, %r15d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_9 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r15d
cmpl 8(%rsp), %r15d
jge .LBB1_17
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_12
# %bb.10: # %.lr.ph37.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph37
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
imull %r15d, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_11
.LBB1_12: # %._crit_edge38
# in Loop: Header=BB1_9 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_18
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_16
.LBB1_17: # %._crit_edge40
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPiS_S_i,@object # @_Z6matMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6matMulPiS_S_i
.p2align 3, 0x0
_Z6matMulPiS_S_i:
.quad _Z21__device_stub__matMulPiS_S_i
.size _Z6matMulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPiS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
cudaMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
cudaMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
cudaMemcpy(_const_mult,const_mult,sizeof(double),cudaMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
cudaThreadSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
cudaThreadSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
cudaThreadSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
cudaMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
cudaFree(_u);
cudaFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} | code for sm_80
Function : _Z11copy_arraysPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.SHL.U32 R3, R0, 0x100, RZ ; /* 0x0000010000037824 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fca00078e0205 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fe40000011402 */
/*00a0*/ IADD3 R2, P0, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R3, R0, 0x1, P0 ; /* 0x0000000003037211 */
/* 0x000fe200000f0eff */
/*00c0*/ IMAD.SHL.U32 R4, R2, 0x8, RZ ; /* 0x0000000802047824 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U64.HI R0, R2, 0x3, R3 ; /* 0x0000000302007819 */
/* 0x000fe40000010203 */
/*00e0*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fcc00007fe4ff */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*0130*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15update_solutionPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*0070*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*0090*/ ISETP.GT.U32.AND P0, PT, R2, 0xfd, PT ; /* 0x000000fd0200780c */
/* 0x000fc80003f04070 */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R4, 0xfd, P0 ; /* 0x000000fd0400780c */
/* 0x000fda0000704470 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LEA R0, R0, R3, 0x8 ; /* 0x0000000300007211 */
/* 0x000fe200078e40ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x040fe200078e0205 */
/*0100*/ IADD3 R12, R0, -0x100, RZ ; /* 0xffffff00000c7810 */
/* 0x000fc80007ffe0ff */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ IMAD.WIDE R12, R12, R5, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc600078e0205 */
/*0140*/ LDG.E.64 R10, [R6.64+-0x8] ; /* 0xfffff804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000f22000c1e1b00 */
/*0160*/ MOV R18, c[0x0][0x170] ; /* 0x00005c0000127a02 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff137624 */
/* 0x000fe400078e00ff */
/*0180*/ LDG.E.64 R16, [R12.64+0x1000] ; /* 0x001000040c107981 */
/* 0x000f68000c1e1b00 */
/*0190*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ DFMA R8, R2, -4, R8 ; /* 0xc01000000208782b */
/* 0x004ecc0000000008 */
/*01b0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008f0c000000000a */
/*01c0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x010f4c000000000e */
/*01d0*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x020e0c0000000010 */
/*01e0*/ DFMA R8, R8, R18, R2 ; /* 0x000000120808722b */
/* 0x0010640000000002 */
/*01f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0205 */
/*0200*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26update_periodic_boundariesPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R2, 0xfd, PT ; /* 0x000000fd0200780c */
/* 0x000fe20003f24070 */
/*00b0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc600078e0209 */
/*00c0*/ ISETP.NE.OR P3, PT, R0, 0xff, P1 ; /* 0x000000ff0000780c */
/* 0x000fda0000f65670 */
/*00d0*/ @!P3 LDG.E.64 R6, [R2.64+0x800] ; /* 0x000800040206b981 */
/* 0x000162000c1e1b00 */
/*00e0*/ ISETP.NE.OR P1, PT, R0.reuse, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x040fe20000f25670 */
/*00f0*/ BSSY B0, 0x180 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe20003f04070 */
/*0110*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fc600078e00ff */
/*0120*/ ISETP.NE.OR P2, PT, R4.reuse, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x040fe40000745670 */
/*0130*/ ISETP.NE.OR P0, PT, R4, 0xff, P0 ; /* 0x000000ff0400780c */
/* 0x000fca0000705670 */
/*0140*/ @P1 BRA 0x170 ; /* 0x0000002000001947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R2.64+0x7f000] ; /* 0x07f0000402047981 */
/* 0x001ea8000c1e1b00 */
/*0160*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041e4000c101b04 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0180*/ @!P3 STG.E.64 [R2.64+0x7f800], R6 ; /* 0x07f800060200b986 */
/* 0x0201e2000c101b04 */
/*0190*/ BSSY B0, 0x1f0 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0209 */
/*01b0*/ @P2 BRA 0x1e0 ; /* 0x0000002000002947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E.64 R2, [R4.64+0x7f0] ; /* 0x0007f00404027981 */
/* 0x001ea8000c1e1b00 */
/*01d0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041e4000c101b04 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x001ea8000c1e1b00 */
/*0210*/ STG.E.64 [R4.64+0x7f8], R2 ; /* 0x0007f80204007986 */
/* 0x004fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
cudaMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
cudaMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
cudaMemcpy(_const_mult,const_mult,sizeof(double),cudaMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
cudaThreadSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
cudaThreadSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
cudaThreadSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
cudaMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
cudaFree(_u);
cudaFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} | .file "tmpxft_001494a9_00000000-6_cuda_heat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16initialize_arrayPd
.type _Z16initialize_arrayPd, @function
_Z16initialize_arrayPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
leaq 2048(%rdi), %rbp
movl $0, %r12d
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
divsd .LC0(%rip), %xmm0
addsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movl $0, %ebx
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
divsd .LC0(%rip), %xmm0
addsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
addsd 8(%rsp), %xmm0
call sin@PLT
movsd %xmm0, 8(%rbp,%rbx,8)
addq $1, %rbx
cmpq $254, %rbx
jne .L5
addq $1, %r12
addq $2048, %rbp
cmpq $254, %r12
jne .L4
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16initialize_arrayPd, .-_Z16initialize_arrayPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "wb"
.LC3:
.string "Temperature.txt"
.LC4:
.string "%f "
.LC5:
.string "\n"
.text
.globl _Z11write_arrayPd
.type _Z11write_arrayPd, @function
_Z11write_arrayPd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 2048(%r14), %rbp
addq $526336, %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r15
.L10:
leaq -2048(%rbp), %rbx
.L11:
movsd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L11
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $2048, %rbp
cmpq %r14, %rbp
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11write_arrayPd, .-_Z11write_arrayPd
.globl _Z46__device_stub__Z26update_periodic_boundariesPdPd
.type _Z46__device_stub__Z26update_periodic_boundariesPdPd, @function
_Z46__device_stub__Z26update_periodic_boundariesPdPd:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26update_periodic_boundariesPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z26update_periodic_boundariesPdPd, .-_Z46__device_stub__Z26update_periodic_boundariesPdPd
.globl _Z26update_periodic_boundariesPd
.type _Z26update_periodic_boundariesPd, @function
_Z26update_periodic_boundariesPd:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26update_periodic_boundariesPd, .-_Z26update_periodic_boundariesPd
.globl _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
.type _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_, @function
_Z39__device_stub__Z15update_solutionPdS_S_PdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15update_solutionPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_, .-_Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
.globl _Z15update_solutionPdS_S_
.type _Z15update_solutionPdS_S_, @function
_Z15update_solutionPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15update_solutionPdS_S_, .-_Z15update_solutionPdS_S_
.globl _Z33__device_stub__Z11copy_arraysPdS_PdS_
.type _Z33__device_stub__Z11copy_arraysPdS_PdS_, @function
_Z33__device_stub__Z11copy_arraysPdS_PdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11copy_arraysPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z11copy_arraysPdS_PdS_, .-_Z33__device_stub__Z11copy_arraysPdS_PdS_
.globl _Z11copy_arraysPdS_
.type _Z11copy_arraysPdS_, @function
_Z11copy_arraysPdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11copy_arraysPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11copy_arraysPdS_, .-_Z11copy_arraysPdS_
.section .rodata.str1.1
.LC11:
.string "CPU time used = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $524288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rbx, %rdi
call _Z16initialize_arrayPd
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $524288, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movq .LC7(%rip), %rax
movq %rax, 0(%rbp)
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbp
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L40:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L41:
call cudaThreadSynchronize@PLT
movq $0x000000000, 8(%rsp)
jmp .L45
.L49:
movq 24(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L40
.L50:
movq 32(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L41
.L52:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
jmp .L42
.L53:
movq 24(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L43
.L44:
call cudaThreadSynchronize@PLT
movsd .LC8(%rip), %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 8(%rsp)
movsd .LC9(%rip), %xmm3
comisd %xmm1, %xmm3
jbe .L51
.L45:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L42:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L43:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L44
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11copy_arraysPdS_PdS_
jmp .L44
.L51:
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _Z11write_arrayPd
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11copy_arraysPdS_"
.LC13:
.string "_Z15update_solutionPdS_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "_Z26update_periodic_boundariesPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11copy_arraysPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z15update_solutionPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z26update_periodic_boundariesPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081065472
.align 8
.LC1:
.long 1413551940
.long 1074340347
.align 8
.LC7:
.long -1717986918
.long 1070176665
.align 8
.LC8:
.long 429618330
.long 1059327265
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
cudaMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
cudaMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
cudaMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
cudaMemcpy(_const_mult,const_mult,sizeof(double),cudaMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
cudaThreadSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
cudaThreadSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
cudaThreadSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
cudaThreadSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
cudaMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
cudaFree(_u);
cudaFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
hipMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
hipMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
hipMemcpy(_const_mult,const_mult,sizeof(double),hipMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
hipDeviceSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
hipDeviceSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
hipDeviceSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
hipMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
hipFree(_u);
hipFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
hipMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
hipMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
hipMemcpy(_const_mult,const_mult,sizeof(double),hipMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
hipDeviceSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
hipDeviceSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
hipDeviceSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
hipMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
hipFree(_u);
hipFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26update_periodic_boundariesPd
.globl _Z26update_periodic_boundariesPd
.p2align 8
.type _Z26update_periodic_boundariesPd,@function
_Z26update_periodic_boundariesPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s0, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, -1, v2
v_cmp_gt_u32_e32 vcc_lo, 0xfe, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v0
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
v_add_co_u32 v5, s0, 0x7f000, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v4, s0
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[5:6], v[3:4], off offset:2048
v_add_co_u32 v3, vcc_lo, 0x7f000, v3
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off offset:2048
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
v_cmp_eq_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_b64 v[5:6], v[3:4], off offset:2032
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0xff, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off offset:8
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off offset:2040
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26update_periodic_boundariesPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26update_periodic_boundariesPd, .Lfunc_end0-_Z26update_periodic_boundariesPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15update_solutionPdS_S_
.globl _Z15update_solutionPdS_S_
.p2align 8
.type _Z15update_solutionPdS_S_,@function
_Z15update_solutionPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v2, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, -1, v1
v_max_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xfe, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v4, v0, 8, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v9, 0xffffff00, v4
v_add_nc_u32_e32 v11, 0x100, v4
v_lshlrev_b64 v[5:6], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[7:8], off
global_load_b64 v[7:8], v[7:8], off offset:-8
v_add_co_u32 v11, vcc_lo, s6, v11
global_load_b64 v[9:10], v[9:10], off
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(3)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[9:10]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[11:12]
s_waitcnt lgkmcnt(0)
v_fma_f64 v[0:1], s[0:1], v[2:3], v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15update_solutionPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15update_solutionPdS_S_, .Lfunc_end1-_Z15update_solutionPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11copy_arraysPdS_
.globl _Z11copy_arraysPdS_
.p2align 8
.type _Z11copy_arraysPdS_,@function
_Z11copy_arraysPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s14, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v1, s14, v1, 8
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[3:4]
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11copy_arraysPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11copy_arraysPdS_, .Lfunc_end2-_Z11copy_arraysPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26update_periodic_boundariesPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26update_periodic_boundariesPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15update_solutionPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15update_solutionPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11copy_arraysPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11copy_arraysPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Compile using nvcc cuda_heat.cu
Author: Romit Maulik - romit.maulik@okstate.edu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
const double PI = 3.1415926535;
const double lx = 2.0*PI, ly = 2.0*PI;
const int nx = 254, ny = 254;
const double ALPHA = 0.8, STAB_PARAM = 0.8;
const double dx = lx/nx, dy = ly/ny;
/*
Host Functions
*/
void initialize_array(double *u);
void write_array(double *u);
/*
Device Functions
*/
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult);
__global__ void update_periodic_boundaries(double *_u);
__global__ void copy_arrays(double *_u, double *_utemp);
int main (int argc, char** argv)
{
double *u = new double [(nx+2)*(ny+2)];
//double *u = malloc(sizeof(double) * (nx+2) * (ny+2)); //Pointer to host memory
double *_u, *_utemp; //Pointer to device memory
double *const_mult = new double[1];
double *_const_mult;
initialize_array(u); //Initialize solution on host
// allocate storage space on the GPU
hipMalloc((void **)&_u, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_utemp, (nx+2) * (ny+2) * sizeof(double));
hipMalloc((void **)&_const_mult,sizeof(double));
//Copy data to device
hipMemcpy(_u,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(_utemp,u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyHostToDevice);
// assign a 2D distribution of CUDA "threads" within each CUDA "block"
int ThreadsPerBlock=16;
dim3 dimBlock( ThreadsPerBlock, ThreadsPerBlock );
// calculate number of blocks along X and Y in a 2D CUDA "grid"
dim3 dimGrid( ceil(float(nx+2)/float(dimBlock.x)), ceil(float(ny+2)/float(dimBlock.y)), 1 );
double t,dt;
const double ft=1.0;
dt = STAB_PARAM*dx*dx/(4.0*ALPHA);
((*const_mult)) = ALPHA*dt/(dx*dx);
//Copy constant to device
hipMemcpy(_const_mult,const_mult,sizeof(double),hipMemcpyHostToDevice);
clock_t start, end;
double cpu_time_used;
start = clock();
//FTCS integration - CUDA
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_utemp);
hipDeviceSynchronize();
t = 0.0;
do{
//Update solution
update_solution<<<dimGrid, dimBlock>>>(_u,_utemp,_const_mult); // update T1 using data stored in T2
hipDeviceSynchronize();
//Boundary conditions
update_periodic_boundaries<<<dimGrid, dimBlock>>>(_u);
hipDeviceSynchronize();
//Copy arrays
copy_arrays<<<dimGrid, dimBlock>>>(_u,_utemp);
hipDeviceSynchronize();
t = t + dt;
}while(t<ft);
// copy final array to the CPU from the GPU
hipMemcpy(u,_u,(nx+2)*(ny+2)*sizeof(double),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("CPU time used = %f\n", cpu_time_used);
//Write temperature to disk
write_array(u);
// release memory on the host
delete u;
// release memory on the device
hipFree(_u);
hipFree(_utemp);
return 0;
}
void initialize_array(double *u)
{
double x,y;
for (int i = 1; i < nx+1; i++)
{
for (int j = 1; j < ny+1; j++)
{
x = (double) (i-1)/nx * 2.0 * PI;
y = (double) (j-1)/ny * 2.0 * PI;
(*(u + (ny+2)*i + j)) = sin(x+y);
}
}
}
__global__ void update_periodic_boundaries(double *_u)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// Left boundary
if(j>0 && j<ny+1 && i == 0)
{
(*(_u + j)) = (*(_u + (ny+2)*nx + j));//Correct
}
// Right boundary
if(j>0 && j<ny+1 && i == nx + 1)
{
(*(_u + (ny+2)*(nx+1) + j)) = (*(_u + (ny+2) + j));//Correct
}
// Bottom boundary
if(i>=0 && i<nx+2 && j == 0)
{
(*(_u + (ny+2)*i)) = (*(_u + (ny+2)*i + ny)); //Correct
}
// top boundary
if(i>=0 && i<nx+2 && j == ny + 1)
{
(*(_u + (ny+2)*i + ny + 1)) = (*(_u + (ny+2)*i + 1)); //Correct
}
}
__global__ void update_solution(double *_u, double *_utemp, double *_const_mult)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
// get the natural index values of node (i,j) and its neighboring nodes
int p = (ny+2)*i + j;
int n = (ny+2)*i + j + 1;
int s = (ny+2)*i + j - 1;
int w = (ny+2)*(i-1) + j;
int e = (ny+2)*(i+1) + j;
// only update "interior" node points
if(i>0 && i<nx+1 && j>0 && j<ny+1)
{
(*(_u + p)) = (*(_utemp + p)) + (*_const_mult)*(-4.0*(*(_utemp + p)) + (*(_utemp + n)) + (*(_utemp + s)) + (*(_utemp + w)) + (*(_utemp + e)));
}
}
__global__ void copy_arrays(double *_u, double *_utemp)
{
// compute the "i" and "j" location of the node point
// handled by this thread
int i = blockIdx.x * blockDim.x + threadIdx.x ;
int j = blockIdx.y * blockDim.y + threadIdx.y ;
(*(_utemp + (ny+2)*i + j)) = (*(_u + (ny+2)*i + j));
}
void write_array(double *u)
{
FILE *fp;
fp = fopen("Temperature.txt","wb");
for(int i=0;i<nx+2;i++) {
for(int j=0;j<ny+2;j++) {
double value = (*(u + (ny+2)*i + j));
fprintf(fp,"%f ",value);
}
fprintf(fp,"\n");
}
} | .text
.file "cuda_heat.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x406fc00000000000 # double 254
.LCPI0_1:
.quad 0x400921fb54411744 # double 3.1415926535000001
.LCPI0_2:
.quad 0x3f240d21199b749a # double 1.529791741664885E-4
.LCPI0_3:
.quad 0x3ff0000000000000 # double 1
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $524288, %edi # imm = 0x80000
callq _Znam
movq %rax, %r13
movl $8, %edi
callq _Znam
movq %rax, %rbx
movq %r13, %r14
addq $2056, %r14 # imm = 0x808
movl $1, %r15d
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
leal -1(%r15), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
addsd 104(%rsp), %xmm0 # 8-byte Folded Reload
callq sin
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq $254, %r12
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r15
addq $2048, %r14 # imm = 0x800
cmpq $255, %r15
jne .LBB0_1
# %bb.4: # %_Z16initialize_arrayPd.exit
movabsq $68719476752, %r14 # imm = 0x1000000010
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4596373779694328218, %rax # imm = 0x3FC999999999999A
movq %rax, (%rbx)
movq 120(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, 128(%rsp) # 8-byte Spill
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq %r13, 136(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 72(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
xorpd %xmm0, %xmm0
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 16(%rsp), %r15
movq %rsp, %rbx
leaq 80(%rsp), %r12
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd .LCPI0_2(%rip), %xmm1
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movapd %xmm1, %xmm0
jbe .LBB0_16
.LBB0_9: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq 72(%rsp), %rcx
movq 120(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 16(%rsp)
movq %r13, 80(%rsp)
movq %rbp, 88(%rsp)
movq %r15, 96(%rsp)
movq %rbx, %rdi
leaq 40(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z15update_solutionPdS_S_, %edi
movq %r12, %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_11: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, %rdi
movq %rbx, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z26update_periodic_boundariesPd, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r13, 80(%rsp)
movq %rbp, 88(%rsp)
movq %rbx, %rdi
leaq 40(%rsp), %rsi
movq %r15, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z11copy_arraysPdS_, %edi
movq %r12, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_15
.LBB0_16:
movq 32(%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq 136(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
subq 128(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_4(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
movq %r13, %r15
.p2align 4, 0x90
.LBB0_17: # %.preheader.i83
# =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_18: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB0_18
# %bb.19: # in Loop: Header=BB0_17 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $2048, %r15 # imm = 0x800
cmpq $256, %r14 # imm = 0x100
jne .LBB0_17
# %bb.20: # %_Z11write_arrayPd.exit
movq %r13, %rdi
callq _ZdlPv
movq 32(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialize_arrayPd
.LCPI1_0:
.quad 0x406fc00000000000 # double 254
.LCPI1_1:
.quad 0x400921fb54411744 # double 3.1415926535000001
.text
.globl _Z16initialize_arrayPd
.p2align 4, 0x90
.type _Z16initialize_arrayPd,@function
_Z16initialize_arrayPd: # @_Z16initialize_arrayPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
addq $2056, %rbx # imm = 0x808
movl $1, %r14d
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal -1(%r14), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
callq sin
movsd .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $254, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $2048, %rbx # imm = 0x800
cmpq $255, %r14
jne .LBB1_1
# %bb.4:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16initialize_arrayPd, .Lfunc_end1-_Z16initialize_arrayPd
.cfi_endproc
# -- End function
.globl _Z41__device_stub__update_periodic_boundariesPd # -- Begin function _Z41__device_stub__update_periodic_boundariesPd
.p2align 4, 0x90
.type _Z41__device_stub__update_periodic_boundariesPd,@function
_Z41__device_stub__update_periodic_boundariesPd: # @_Z41__device_stub__update_periodic_boundariesPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z41__device_stub__update_periodic_boundariesPd, .Lfunc_end2-_Z41__device_stub__update_periodic_boundariesPd
.cfi_endproc
# -- End function
.globl _Z30__device_stub__update_solutionPdS_S_ # -- Begin function _Z30__device_stub__update_solutionPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__update_solutionPdS_S_,@function
_Z30__device_stub__update_solutionPdS_S_: # @_Z30__device_stub__update_solutionPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15update_solutionPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z30__device_stub__update_solutionPdS_S_, .Lfunc_end3-_Z30__device_stub__update_solutionPdS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__copy_arraysPdS_ # -- Begin function _Z26__device_stub__copy_arraysPdS_
.p2align 4, 0x90
.type _Z26__device_stub__copy_arraysPdS_,@function
_Z26__device_stub__copy_arraysPdS_: # @_Z26__device_stub__copy_arraysPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11copy_arraysPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z26__device_stub__copy_arraysPdS_, .Lfunc_end4-_Z26__device_stub__copy_arraysPdS_
.cfi_endproc
# -- End function
.globl _Z11write_arrayPd # -- Begin function _Z11write_arrayPd
.p2align 4, 0x90
.type _Z11write_arrayPd,@function
_Z11write_arrayPd: # @_Z11write_arrayPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $2048, %rbx # imm = 0x800
cmpq $256, %r15 # imm = 0x100
jne .LBB5_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11write_arrayPd, .Lfunc_end5-_Z11write_arrayPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26update_periodic_boundariesPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15update_solutionPdS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11copy_arraysPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26update_periodic_boundariesPd,@object # @_Z26update_periodic_boundariesPd
.section .rodata,"a",@progbits
.globl _Z26update_periodic_boundariesPd
.p2align 3, 0x0
_Z26update_periodic_boundariesPd:
.quad _Z41__device_stub__update_periodic_boundariesPd
.size _Z26update_periodic_boundariesPd, 8
.type _Z15update_solutionPdS_S_,@object # @_Z15update_solutionPdS_S_
.globl _Z15update_solutionPdS_S_
.p2align 3, 0x0
_Z15update_solutionPdS_S_:
.quad _Z30__device_stub__update_solutionPdS_S_
.size _Z15update_solutionPdS_S_, 8
.type _Z11copy_arraysPdS_,@object # @_Z11copy_arraysPdS_
.globl _Z11copy_arraysPdS_
.p2align 3, 0x0
_Z11copy_arraysPdS_:
.quad _Z26__device_stub__copy_arraysPdS_
.size _Z11copy_arraysPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU time used = %f\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Temperature.txt"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26update_periodic_boundariesPd"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15update_solutionPdS_S_"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11copy_arraysPdS_"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__update_periodic_boundariesPd
.addrsig_sym _Z30__device_stub__update_solutionPdS_S_
.addrsig_sym _Z26__device_stub__copy_arraysPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26update_periodic_boundariesPd
.addrsig_sym _Z15update_solutionPdS_S_
.addrsig_sym _Z11copy_arraysPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11copy_arraysPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.SHL.U32 R3, R0, 0x100, RZ ; /* 0x0000010000037824 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fca00078e0205 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fe40000011402 */
/*00a0*/ IADD3 R2, P0, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R3, R0, 0x1, P0 ; /* 0x0000000003037211 */
/* 0x000fe200000f0eff */
/*00c0*/ IMAD.SHL.U32 R4, R2, 0x8, RZ ; /* 0x0000000802047824 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U64.HI R0, R2, 0x3, R3 ; /* 0x0000000302007819 */
/* 0x000fe40000010203 */
/*00e0*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fcc00007fe4ff */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*0130*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15update_solutionPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*0070*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*0090*/ ISETP.GT.U32.AND P0, PT, R2, 0xfd, PT ; /* 0x000000fd0200780c */
/* 0x000fc80003f04070 */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R4, 0xfd, P0 ; /* 0x000000fd0400780c */
/* 0x000fda0000704470 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LEA R0, R0, R3, 0x8 ; /* 0x0000000300007211 */
/* 0x000fe200078e40ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x040fe200078e0205 */
/*0100*/ IADD3 R12, R0, -0x100, RZ ; /* 0xffffff00000c7810 */
/* 0x000fc80007ffe0ff */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ IMAD.WIDE R12, R12, R5, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc600078e0205 */
/*0140*/ LDG.E.64 R10, [R6.64+-0x8] ; /* 0xfffff804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000f22000c1e1b00 */
/*0160*/ MOV R18, c[0x0][0x170] ; /* 0x00005c0000127a02 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff137624 */
/* 0x000fe400078e00ff */
/*0180*/ LDG.E.64 R16, [R12.64+0x1000] ; /* 0x001000040c107981 */
/* 0x000f68000c1e1b00 */
/*0190*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ DFMA R8, R2, -4, R8 ; /* 0xc01000000208782b */
/* 0x004ecc0000000008 */
/*01b0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008f0c000000000a */
/*01c0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x010f4c000000000e */
/*01d0*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x020e0c0000000010 */
/*01e0*/ DFMA R8, R8, R18, R2 ; /* 0x000000120808722b */
/* 0x0010640000000002 */
/*01f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0205 */
/*0200*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26update_periodic_boundariesPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R2, 0xfd, PT ; /* 0x000000fd0200780c */
/* 0x000fe20003f24070 */
/*00b0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc600078e0209 */
/*00c0*/ ISETP.NE.OR P3, PT, R0, 0xff, P1 ; /* 0x000000ff0000780c */
/* 0x000fda0000f65670 */
/*00d0*/ @!P3 LDG.E.64 R6, [R2.64+0x800] ; /* 0x000800040206b981 */
/* 0x000162000c1e1b00 */
/*00e0*/ ISETP.NE.OR P1, PT, R0.reuse, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x040fe20000f25670 */
/*00f0*/ BSSY B0, 0x180 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe20003f04070 */
/*0110*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fc600078e00ff */
/*0120*/ ISETP.NE.OR P2, PT, R4.reuse, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x040fe40000745670 */
/*0130*/ ISETP.NE.OR P0, PT, R4, 0xff, P0 ; /* 0x000000ff0400780c */
/* 0x000fca0000705670 */
/*0140*/ @P1 BRA 0x170 ; /* 0x0000002000001947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R2.64+0x7f000] ; /* 0x07f0000402047981 */
/* 0x001ea8000c1e1b00 */
/*0160*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041e4000c101b04 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0180*/ @!P3 STG.E.64 [R2.64+0x7f800], R6 ; /* 0x07f800060200b986 */
/* 0x0201e2000c101b04 */
/*0190*/ BSSY B0, 0x1f0 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0209 */
/*01b0*/ @P2 BRA 0x1e0 ; /* 0x0000002000002947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E.64 R2, [R4.64+0x7f0] ; /* 0x0007f00404027981 */
/* 0x001ea8000c1e1b00 */
/*01d0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041e4000c101b04 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x001ea8000c1e1b00 */
/*0210*/ STG.E.64 [R4.64+0x7f8], R2 ; /* 0x0007f80204007986 */
/* 0x004fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26update_periodic_boundariesPd
.globl _Z26update_periodic_boundariesPd
.p2align 8
.type _Z26update_periodic_boundariesPd,@function
_Z26update_periodic_boundariesPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s0, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, -1, v2
v_cmp_gt_u32_e32 vcc_lo, 0xfe, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v0
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
v_add_co_u32 v5, s0, 0x7f000, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v4, s0
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[5:6], v[3:4], off offset:2048
v_add_co_u32 v3, vcc_lo, 0x7f000, v3
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off offset:2048
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
v_cmp_eq_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_b64 v[5:6], v[3:4], off offset:2032
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0xff, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off offset:8
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off offset:2040
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26update_periodic_boundariesPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26update_periodic_boundariesPd, .Lfunc_end0-_Z26update_periodic_boundariesPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15update_solutionPdS_S_
.globl _Z15update_solutionPdS_S_
.p2align 8
.type _Z15update_solutionPdS_S_,@function
_Z15update_solutionPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v2, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, -1, v1
v_max_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xfe, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v4, v0, 8, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v9, 0xffffff00, v4
v_add_nc_u32_e32 v11, 0x100, v4
v_lshlrev_b64 v[5:6], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[7:8], off
global_load_b64 v[7:8], v[7:8], off offset:-8
v_add_co_u32 v11, vcc_lo, s6, v11
global_load_b64 v[9:10], v[9:10], off
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(3)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[9:10]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[11:12]
s_waitcnt lgkmcnt(0)
v_fma_f64 v[0:1], s[0:1], v[2:3], v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15update_solutionPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15update_solutionPdS_S_, .Lfunc_end1-_Z15update_solutionPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11copy_arraysPdS_
.globl _Z11copy_arraysPdS_
.p2align 8
.type _Z11copy_arraysPdS_,@function
_Z11copy_arraysPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s14, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v1, s14, v1, 8
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[3:4]
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11copy_arraysPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11copy_arraysPdS_, .Lfunc_end2-_Z11copy_arraysPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26update_periodic_boundariesPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26update_periodic_boundariesPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15update_solutionPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15update_solutionPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11copy_arraysPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11copy_arraysPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001494a9_00000000-6_cuda_heat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16initialize_arrayPd
.type _Z16initialize_arrayPd, @function
_Z16initialize_arrayPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
leaq 2048(%rdi), %rbp
movl $0, %r12d
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
divsd .LC0(%rip), %xmm0
addsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movl $0, %ebx
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
divsd .LC0(%rip), %xmm0
addsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
addsd 8(%rsp), %xmm0
call sin@PLT
movsd %xmm0, 8(%rbp,%rbx,8)
addq $1, %rbx
cmpq $254, %rbx
jne .L5
addq $1, %r12
addq $2048, %rbp
cmpq $254, %r12
jne .L4
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16initialize_arrayPd, .-_Z16initialize_arrayPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "wb"
.LC3:
.string "Temperature.txt"
.LC4:
.string "%f "
.LC5:
.string "\n"
.text
.globl _Z11write_arrayPd
.type _Z11write_arrayPd, @function
_Z11write_arrayPd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 2048(%r14), %rbp
addq $526336, %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r15
.L10:
leaq -2048(%rbp), %rbx
.L11:
movsd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L11
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $2048, %rbp
cmpq %r14, %rbp
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11write_arrayPd, .-_Z11write_arrayPd
.globl _Z46__device_stub__Z26update_periodic_boundariesPdPd
.type _Z46__device_stub__Z26update_periodic_boundariesPdPd, @function
_Z46__device_stub__Z26update_periodic_boundariesPdPd:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26update_periodic_boundariesPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z26update_periodic_boundariesPdPd, .-_Z46__device_stub__Z26update_periodic_boundariesPdPd
.globl _Z26update_periodic_boundariesPd
.type _Z26update_periodic_boundariesPd, @function
_Z26update_periodic_boundariesPd:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26update_periodic_boundariesPd, .-_Z26update_periodic_boundariesPd
.globl _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
.type _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_, @function
_Z39__device_stub__Z15update_solutionPdS_S_PdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15update_solutionPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_, .-_Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
.globl _Z15update_solutionPdS_S_
.type _Z15update_solutionPdS_S_, @function
_Z15update_solutionPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15update_solutionPdS_S_, .-_Z15update_solutionPdS_S_
.globl _Z33__device_stub__Z11copy_arraysPdS_PdS_
.type _Z33__device_stub__Z11copy_arraysPdS_PdS_, @function
_Z33__device_stub__Z11copy_arraysPdS_PdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11copy_arraysPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z11copy_arraysPdS_PdS_, .-_Z33__device_stub__Z11copy_arraysPdS_PdS_
.globl _Z11copy_arraysPdS_
.type _Z11copy_arraysPdS_, @function
_Z11copy_arraysPdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11copy_arraysPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11copy_arraysPdS_, .-_Z11copy_arraysPdS_
.section .rodata.str1.1
.LC11:
.string "CPU time used = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $524288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rbx, %rdi
call _Z16initialize_arrayPd
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $524288, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movq .LC7(%rip), %rax
movq %rax, 0(%rbp)
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbp
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L40:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L41:
call cudaThreadSynchronize@PLT
movq $0x000000000, 8(%rsp)
jmp .L45
.L49:
movq 24(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L40
.L50:
movq 32(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L41
.L52:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z15update_solutionPdS_S_PdS_S_
jmp .L42
.L53:
movq 24(%rsp), %rdi
call _Z46__device_stub__Z26update_periodic_boundariesPdPd
jmp .L43
.L44:
call cudaThreadSynchronize@PLT
movsd .LC8(%rip), %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 8(%rsp)
movsd .LC9(%rip), %xmm3
comisd %xmm1, %xmm3
jbe .L51
.L45:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L42:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L43:
call cudaThreadSynchronize@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L44
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11copy_arraysPdS_PdS_
jmp .L44
.L51:
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _Z11write_arrayPd
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11copy_arraysPdS_"
.LC13:
.string "_Z15update_solutionPdS_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "_Z26update_periodic_boundariesPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11copy_arraysPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z15update_solutionPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z26update_periodic_boundariesPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081065472
.align 8
.LC1:
.long 1413551940
.long 1074340347
.align 8
.LC7:
.long -1717986918
.long 1070176665
.align 8
.LC8:
.long 429618330
.long 1059327265
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_heat.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x406fc00000000000 # double 254
.LCPI0_1:
.quad 0x400921fb54411744 # double 3.1415926535000001
.LCPI0_2:
.quad 0x3f240d21199b749a # double 1.529791741664885E-4
.LCPI0_3:
.quad 0x3ff0000000000000 # double 1
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $524288, %edi # imm = 0x80000
callq _Znam
movq %rax, %r13
movl $8, %edi
callq _Znam
movq %rax, %rbx
movq %r13, %r14
addq $2056, %r14 # imm = 0x808
movl $1, %r15d
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
leal -1(%r15), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
addsd 104(%rsp), %xmm0 # 8-byte Folded Reload
callq sin
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq $254, %r12
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r15
addq $2048, %r14 # imm = 0x800
cmpq $255, %r15
jne .LBB0_1
# %bb.4: # %_Z16initialize_arrayPd.exit
movabsq $68719476752, %r14 # imm = 0x1000000010
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4596373779694328218, %rax # imm = 0x3FC999999999999A
movq %rax, (%rbx)
movq 120(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, 128(%rsp) # 8-byte Spill
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq %r13, 136(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 72(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
xorpd %xmm0, %xmm0
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 16(%rsp), %r15
movq %rsp, %rbx
leaq 80(%rsp), %r12
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd .LCPI0_2(%rip), %xmm1
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movapd %xmm1, %xmm0
jbe .LBB0_16
.LBB0_9: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq 72(%rsp), %rcx
movq 120(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 16(%rsp)
movq %r13, 80(%rsp)
movq %rbp, 88(%rsp)
movq %r15, 96(%rsp)
movq %rbx, %rdi
leaq 40(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z15update_solutionPdS_S_, %edi
movq %r12, %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_11: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, %rdi
movq %rbx, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z26update_periodic_boundariesPd, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14: # in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r13, 80(%rsp)
movq %rbp, 88(%rsp)
movq %rbx, %rdi
leaq 40(%rsp), %rsi
movq %r15, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z11copy_arraysPdS_, %edi
movq %r12, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_15
.LBB0_16:
movq 32(%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq 136(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
subq 128(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_4(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
movq %r13, %r15
.p2align 4, 0x90
.LBB0_17: # %.preheader.i83
# =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_18: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB0_18
# %bb.19: # in Loop: Header=BB0_17 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $2048, %r15 # imm = 0x800
cmpq $256, %r14 # imm = 0x100
jne .LBB0_17
# %bb.20: # %_Z11write_arrayPd.exit
movq %r13, %rdi
callq _ZdlPv
movq 32(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialize_arrayPd
.LCPI1_0:
.quad 0x406fc00000000000 # double 254
.LCPI1_1:
.quad 0x400921fb54411744 # double 3.1415926535000001
.text
.globl _Z16initialize_arrayPd
.p2align 4, 0x90
.type _Z16initialize_arrayPd,@function
_Z16initialize_arrayPd: # @_Z16initialize_arrayPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
addq $2056, %rbx # imm = 0x808
movl $1, %r14d
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal -1(%r14), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
mulsd %xmm2, %xmm0
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
callq sin
movsd .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $254, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $2048, %rbx # imm = 0x800
cmpq $255, %r14
jne .LBB1_1
# %bb.4:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16initialize_arrayPd, .Lfunc_end1-_Z16initialize_arrayPd
.cfi_endproc
# -- End function
.globl _Z41__device_stub__update_periodic_boundariesPd # -- Begin function _Z41__device_stub__update_periodic_boundariesPd
.p2align 4, 0x90
.type _Z41__device_stub__update_periodic_boundariesPd,@function
_Z41__device_stub__update_periodic_boundariesPd: # @_Z41__device_stub__update_periodic_boundariesPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z26update_periodic_boundariesPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z41__device_stub__update_periodic_boundariesPd, .Lfunc_end2-_Z41__device_stub__update_periodic_boundariesPd
.cfi_endproc
# -- End function
.globl _Z30__device_stub__update_solutionPdS_S_ # -- Begin function _Z30__device_stub__update_solutionPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__update_solutionPdS_S_,@function
_Z30__device_stub__update_solutionPdS_S_: # @_Z30__device_stub__update_solutionPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15update_solutionPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z30__device_stub__update_solutionPdS_S_, .Lfunc_end3-_Z30__device_stub__update_solutionPdS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__copy_arraysPdS_ # -- Begin function _Z26__device_stub__copy_arraysPdS_
.p2align 4, 0x90
.type _Z26__device_stub__copy_arraysPdS_,@function
_Z26__device_stub__copy_arraysPdS_: # @_Z26__device_stub__copy_arraysPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11copy_arraysPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z26__device_stub__copy_arraysPdS_, .Lfunc_end4-_Z26__device_stub__copy_arraysPdS_
.cfi_endproc
# -- End function
.globl _Z11write_arrayPd # -- Begin function _Z11write_arrayPd
.p2align 4, 0x90
.type _Z11write_arrayPd,@function
_Z11write_arrayPd: # @_Z11write_arrayPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $2048, %rbx # imm = 0x800
cmpq $256, %r15 # imm = 0x100
jne .LBB5_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11write_arrayPd, .Lfunc_end5-_Z11write_arrayPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26update_periodic_boundariesPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15update_solutionPdS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11copy_arraysPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26update_periodic_boundariesPd,@object # @_Z26update_periodic_boundariesPd
.section .rodata,"a",@progbits
.globl _Z26update_periodic_boundariesPd
.p2align 3, 0x0
_Z26update_periodic_boundariesPd:
.quad _Z41__device_stub__update_periodic_boundariesPd
.size _Z26update_periodic_boundariesPd, 8
.type _Z15update_solutionPdS_S_,@object # @_Z15update_solutionPdS_S_
.globl _Z15update_solutionPdS_S_
.p2align 3, 0x0
_Z15update_solutionPdS_S_:
.quad _Z30__device_stub__update_solutionPdS_S_
.size _Z15update_solutionPdS_S_, 8
.type _Z11copy_arraysPdS_,@object # @_Z11copy_arraysPdS_
.globl _Z11copy_arraysPdS_
.p2align 3, 0x0
_Z11copy_arraysPdS_:
.quad _Z26__device_stub__copy_arraysPdS_
.size _Z11copy_arraysPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU time used = %f\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Temperature.txt"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26update_periodic_boundariesPd"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15update_solutionPdS_S_"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11copy_arraysPdS_"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__update_periodic_boundariesPd
.addrsig_sym _Z30__device_stub__update_solutionPdS_S_
.addrsig_sym _Z26__device_stub__copy_arraysPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26update_periodic_boundariesPd
.addrsig_sym _Z15update_solutionPdS_S_
.addrsig_sym _Z11copy_arraysPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMalloc((void **)&d_g, a_size);
cudaMemcpy(d_g, h_graph, a_size, cudaMemcpyHostToDevice);
cudaMalloc(&d_d, n*sizeof(int));
cudaMemcpy(d_d, h_d,n*sizeof(int),cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
cudaMemcpyFromSymbol(&answer, d_change, sizeof(int), 0, cudaMemcpyDeviceToHost);
if (answer == 0)
break;
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMemcpy(h_d, d_d,n*sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} | code for sm_80
Function : _Z12bellman_fordPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0003e2000c101904 */
/*00a0*/ IMAD R11, R9, c[0x0][0x0], R8 ; /* 0x00000000090b7a24 */
/* 0x001fc800078e0208 */
/*00b0*/ IMAD.WIDE R4, R11, R17, c[0x0][0x168] ; /* 0x00005a000b047625 */
/* 0x000fca00078e0211 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000368000c1e1900 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @!P0 BRA 0x6b0 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R0.reuse, -0x2, RZ ; /* 0xfffffffe00067810 */
/* 0x042fe40007ffe0ff */
/*0100*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd600078ec0ff */
/*0140*/ @!P0 BRA 0x530 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, R8, c[0x0][0x174], RZ ; /* 0x00005d0008067a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ MOV R8, c[0x0][0x168] ; /* 0x00005a0000087a02 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R10, -R0, c[0x0][0x174], RZ ; /* 0x00005d00000a7a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD R16, R9, c[0x0][0x0], R6 ; /* 0x0000000009107a24 */
/* 0x000fe400078e0206 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fca00078e0211 */
/*01c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B0, 0x290 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01f0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fc40003f05270 */
/*0200*/ IMAD.WIDE R12, R15, 0x4, R16 ; /* 0x000000040f0c7825 */
/* 0x000fd600078e0210 */
/*0210*/ @P0 BRA 0x280 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GT.AND P0, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f04270 */
/*0250*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff110424 */
/* 0x000fe200078e00ff */
/*0260*/ @P0 MOV R7, R14 ; /* 0x0000000e00070202 */
/* 0x000fc80000000f00 */
/*0270*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e6000c101904 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ BSSY B0, 0x350 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.WIDE R16, R15, 0x4, R12 ; /* 0x000000040f107825 */
/* 0x001fe200078e020c */
/*02c0*/ ISETP.NE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fda0003f05270 */
/*02d0*/ @P0 BRA 0x340 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x004fc80007ffe0ff */
/*0300*/ ISETP.GT.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x020fda0003f04270 */
/*0310*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d0424 */
/* 0x000fe400078e00ff */
/*0320*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff070224 */
/* 0x000fc600078e000c */
/*0330*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e8000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ BSSY B0, 0x410 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fe20003f05270 */
/*0380*/ IMAD.WIDE R12, R15, 0x4, R16 ; /* 0x000000040f0c7825 */
/* 0x001fd800078e0210 */
/*0390*/ @P0 BRA 0x400 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R14, [R8.64+0xc] ; /* 0x00000c04080e7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*03c0*/ ISETP.GT.AND P0, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f04270 */
/*03d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff110424 */
/* 0x000fe400078e00ff */
/*03e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fc600078e000e */
/*03f0*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e8000c101904 */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0420*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ BSSY B0, 0x4e0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0440*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f05270 */
/*0450*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fda0003f25270 */
/*0460*/ @P1 BRA 0x4d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f24270 */
/*04a0*/ @P1 MOV R17, 0x1 ; /* 0x0000000100111802 */
/* 0x001fe20000000f00 */
/*04b0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff071224 */
/* 0x000fc800078e000e */
/*04c0*/ @P1 STG.E [R2.64], R17 ; /* 0x0000001102001986 */
/* 0x0001e6000c101904 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007f3e0ff */
/*04f0*/ IMAD.WIDE R16, R15, 0x4, R12 ; /* 0x000000040f107825 */
/* 0x001fe200078e020c */
/*0500*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*0520*/ @P0 BRA 0x1c0 ; /* 0xfffffc9000000947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0540*/ @!P0 BRA 0x6b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD R11, R6.reuse, c[0x0][0x174], R11 ; /* 0x00005d00060b7a24 */
/* 0x040fe400078e020b */
/*0570*/ IMAD.WIDE R8, R6, R10, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fc800078e020a */
/*0580*/ IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fca00078e020a */
/*0590*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ BSSY B0, 0x670 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*05c0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe400078e00ff */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*05e0*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f25270 */
/*05f0*/ @P1 BRA 0x660 ; /* 0x0000006000001947 */
/* 0x001fea0003800000 */
/*0600*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea4000c1e1900 */
/*0610*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x004fc80007ffe0ff */
/*0620*/ ISETP.GT.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x020fda0003f24270 */
/*0630*/ @P1 MOV R13, 0x1 ; /* 0x00000001000d1802 */
/* 0x000fe20000000f00 */
/*0640*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff071224 */
/* 0x000fc800078e0006 */
/*0650*/ @P1 STG.E [R2.64], R13 ; /* 0x0000000d02001986 */
/* 0x0001e6000c101904 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f3e0ff */
/*0680*/ IMAD.WIDE R10, R15, 0x4, R10 ; /* 0x000000040f0a7825 */
/* 0x000fc800078e020a */
/*0690*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*06a0*/ @P0 BRA 0x590 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fec0000010000 */
/*06c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x020fe2000c101904 */
/*06d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06e0*/ BRA 0x6e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMalloc((void **)&d_g, a_size);
cudaMemcpy(d_g, h_graph, a_size, cudaMemcpyHostToDevice);
cudaMalloc(&d_d, n*sizeof(int));
cudaMemcpy(d_d, h_d,n*sizeof(int),cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
cudaMemcpyFromSymbol(&answer, d_change, sizeof(int), 0, cudaMemcpyDeviceToHost);
if (answer == 0)
break;
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMemcpy(h_d, d_d,n*sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} | .file "tmpxft_000aa007_00000000-6_sssp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
.type _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii, @function
_Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12bellman_fordPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii, .-_Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
.globl _Z12bellman_fordPiS_ii
.type _Z12bellman_fordPiS_ii, @function
_Z12bellman_fordPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12bellman_fordPiS_ii, .-_Z12bellman_fordPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "wiki-Vote.txt"
.LC2:
.string "%d"
.LC3:
.string "w %f\n"
.LC4:
.string "e %f\n"
.LC5:
.string "w"
.LC6:
.string "bellman.txt"
.LC7:
.string "%d: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32824
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3336, %rsp
.cfi_def_cfa_offset 36160
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 36088(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 12(%rsp), %r14
leaq .LC2(%rip), %rbp
leaq 16(%rsp), %r13
leaq h_graph(%rip), %r12
jmp .L12
.L13:
movq %r14, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq 16(%rsp), %rdx
movslq 12(%rsp), %rax
imulq $9000, %rax, %rax
addq %rdx, %rax
movl $1, (%r12,%rax,4)
.L12:
movq %rbx, %rdi
call feof@PLT
testl %eax, %eax
je .L13
movq %rbx, %rdi
call fclose@PLT
movq 8(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl $9000, %eax
movl $0, %edx
idivl %ebp
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %r12d
leaq 80(%rsp), %rdx
leaq 36080(%rsp), %rcx
.L14:
movl $100000, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L14
movl $0, 92(%rsp)
leaq 40(%rsp), %r13
movq %r13, %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rbx
movq %rbx, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $324000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $324000000, %edx
leaq h_graph(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $36000, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $36000, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call cudaEventCreate@PLT
movq %rbx, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
leaq _ZL8d_change(%rip), %r13
jmp .L17
.L15:
leaq 68(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
movq %r13, %rsi
call cudaMemcpyFromSymbol@PLT
cmpl $0, 68(%rsp)
je .L18
addl $1, %ebx
cmpl $8999, %ebx
je .L18
.L17:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $9000, %ecx
movl %ebx, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
jmp .L15
.L18:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rbx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $36000, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC7(%rip), %r12
.L19:
movl 80(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $9000, %rbx
jne .L19
movq %rbp, %rdi
call fclose@PLT
movq 36088(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $36104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12bellman_fordPiS_ii"
.LC9:
.string "d_change"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bellman_fordPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8d_change(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_graph
.bss
.align 32
.type h_graph, @object
.size h_graph, 324000000
h_graph:
.zero 324000000
.local _ZL8d_change
.comm _ZL8d_change,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMalloc((void **)&d_g, a_size);
cudaMemcpy(d_g, h_graph, a_size, cudaMemcpyHostToDevice);
cudaMalloc(&d_d, n*sizeof(int));
cudaMemcpy(d_d, h_d,n*sizeof(int),cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
cudaMemcpyFromSymbol(&answer, d_change, sizeof(int), 0, cudaMemcpyDeviceToHost);
if (answer == 0)
break;
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
cudaMemcpy(h_d, d_d,n*sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
hipEvent_t start, stop;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMalloc((void **)&d_g, a_size);
hipMemcpy(d_g, h_graph, a_size, hipMemcpyHostToDevice);
hipMalloc(&d_d, n*sizeof(int));
hipMemcpy(d_d, h_d,n*sizeof(int),hipMemcpyHostToDevice);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
hipMemcpyFromSymbol(&answer, HIP_SYMBOL(d_change), sizeof(int), 0, hipMemcpyDeviceToHost);
if (answer == 0)
break;
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMemcpy(h_d, d_d,n*sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
hipEvent_t start, stop;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMalloc((void **)&d_g, a_size);
hipMemcpy(d_g, h_graph, a_size, hipMemcpyHostToDevice);
hipMalloc(&d_d, n*sizeof(int));
hipMemcpy(d_d, h_d,n*sizeof(int),hipMemcpyHostToDevice);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
hipMemcpyFromSymbol(&answer, HIP_SYMBOL(d_change), sizeof(int), 0, hipMemcpyDeviceToHost);
if (answer == 0)
break;
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMemcpy(h_d, d_d,n*sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12bellman_fordPiS_ii
.globl _Z12bellman_fordPiS_ii
.p2align 8
.type _Z12bellman_fordPiS_ii,@function
_Z12bellman_fordPiS_ii:
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s15, s15, s4
s_load_b32 s4, s[0:1], 0x14
v_add_nc_u32_e32 v1, s15, v0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_change@rel32@lo+4
s_addc_u32 s7, s7, d_change@rel32@hi+12
global_store_b32 v6, v6, s[6:7]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_cmp_lt_i32 s4, 2
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_add3_u32 v3, s15, s4, v0
v_mov_b32_e32 v0, 1
s_add_i32 s5, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, -1
v_add_nc_u32_e32 v3, s4, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s5, 0
s_cbranch_scc0 .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v4
s_cbranch_execz .LBB0_3
global_load_b32 v4, v6, s[2:3]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v5, v4
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v5, v4
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_change@rel32@lo+4
s_addc_u32 s9, s9, d_change@rel32@hi+12
global_store_b32 v6, v0, s[8:9]
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_store_b32 v[1:2], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12bellman_fordPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12bellman_fordPiS_ii, .Lfunc_end0-_Z12bellman_fordPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_change
.type d_change,@object
.section .bss,"aw",@nobits
.globl d_change
.p2align 2, 0x0
d_change:
.long 0
.size d_change, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_change
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12bellman_fordPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12bellman_fordPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__device__ int d_change;
__global__ void bellman_ford(int *d_g, int *d_d, int k, int n)
{
d_change = 0;
int i = blockIdx.x*blockDim.x+threadIdx.x;
int cur_dis = d_d[i];
__syncthreads();
int j;
for (j=1; j<n;j++)
{
if (d_g[j*n+i]==1 && cur_dis > d_d[j] + d_g[j*n+i])
{
cur_dis = d_d[j] + d_g[j*n+i];
d_change = 1;
}
}
__syncthreads();
d_d[i] = cur_dis;
}
int h_graph[9000][9000];
int main( int argc, char* argv[] )
{
FILE *fp = fopen("wiki-Vote.txt","r");
int source =0,dest=0, n =9000,i;
srand(time(NULL));
while(!feof(fp))
{
fscanf(fp,"%d",&source);
fscanf(fp,"%d",&dest);
h_graph[source][dest] = 1;
}
fclose(fp);
int *d_g;
const size_t a_size = sizeof(int) * size_t(n*n);
int block_size = atoi(argv[1]);
int n_blocks = n/block_size + (n%block_size==0?0:1);
int h_s = 3;
int h_d[9000], *d_d, k;
for(i=0; i<n; i++)
h_d[i] = (int)1e5;
h_d[h_s] = 0;
float time;
hipEvent_t start, stop;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMalloc((void **)&d_g, a_size);
hipMemcpy(d_g, h_graph, a_size, hipMemcpyHostToDevice);
hipMalloc(&d_d, n*sizeof(int));
hipMemcpy(d_d, h_d,n*sizeof(int),hipMemcpyHostToDevice);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (k=0;k<n-1;k++)
{
bellman_ford<<<n_blocks,block_size>>>(d_g, d_d, k, n);
int answer;
hipMemcpyFromSymbol(&answer, HIP_SYMBOL(d_change), sizeof(int), 0, hipMemcpyDeviceToHost);
if (answer == 0)
break;
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("e %f\n", time);
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
hipMemcpy(h_d, d_d,n*sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("w %f\n", time);
FILE *op = fopen("bellman.txt","w");
for (i=0;i<n;i++)
{
fprintf(op,"%d: %d\n",i,h_d[i]);
}
fclose(op);
return 0;
} | .text
.file "sssp.hip"
.globl _Z27__device_stub__bellman_fordPiS_ii # -- Begin function _Z27__device_stub__bellman_fordPiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__bellman_fordPiS_ii,@function
_Z27__device_stub__bellman_fordPiS_ii: # @_Z27__device_stub__bellman_fordPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12bellman_fordPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__bellman_fordPiS_ii, .Lfunc_end0-_Z27__device_stub__bellman_fordPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $36168, %rsp # imm = 0x8D48
.cfi_def_cfa_offset 36224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $0, 36(%rsp)
movl $0, 32(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 36(%rsp), %r15
leaq 32(%rsp), %r12
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 36(%rsp), %rax
movslq 32(%rsp), %rcx
imulq $36000, %rax, %rax # imm = 0x8CA0
movl $1, h_graph(%rax,%rcx,4)
movq %r14, %rdi
callq feof
testl %eax, %eax
je .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rbx), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $9000, %eax # imm = 0x2328
xorl %edx, %edx
idivl %r14d
movl %eax, %ebx
xorl %eax, %eax
testl %edx, %edx
setne %al
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl $100000, 160(%rsp,%r15,4) # imm = 0x186A0
incq %r15
cmpq $9000, %r15 # imm = 0x2328
jne .LBB1_4
# %bb.5:
addl %eax, %ebx
movl $0, 172(%rsp)
leaq 24(%rsp), %r15
movq %r15, %rdi
callq hipEventCreate
leaq 8(%rsp), %r13
movq %r13, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
leaq 56(%rsp), %rdi
movl $324000000, %esi # imm = 0x134FD900
callq hipMalloc
movq 56(%rsp), %rdi
movl $h_graph, %esi
movl $324000000, %edx # imm = 0x134FD900
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movl $36000, %esi # imm = 0x8CA0
callq hipMalloc
movq 40(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $36000, %edx # imm = 0x8CA0
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r14d, %r14d
orq %rax, %r14
leaq 72(%rsp), %r13
leaq 64(%rsp), %rbp
leaq 128(%rsp), %r15
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r12d, 52(%rsp)
movl $9000, 48(%rsp) # imm = 0x2328
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z12bellman_fordPiS_ii, %edi
movq %r15, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
movl $d_change, %esi
movl $4, %edx
movq %r15, %rdi
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
cmpl $0, 128(%rsp)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_6 Depth=1
leal 1(%r12), %eax
cmpl $8998, %r12d # imm = 0x2326
movl %eax, %r12d
jne .LBB1_6
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $36000, %edx # imm = 0x8CA0
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl 160(%rsp,%r14,4), %ecx
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $9000, %r14 # imm = 0x2328
jne .LBB1_11
# %bb.12:
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $36168, %rsp # imm = 0x8D48
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bellman_fordPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_change, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_change,@object # @d_change
.local d_change
.comm d_change,4,4
.type _Z12bellman_fordPiS_ii,@object # @_Z12bellman_fordPiS_ii
.section .rodata,"a",@progbits
.globl _Z12bellman_fordPiS_ii
.p2align 3, 0x0
_Z12bellman_fordPiS_ii:
.quad _Z27__device_stub__bellman_fordPiS_ii
.size _Z12bellman_fordPiS_ii, 8
.type h_graph,@object # @h_graph
.bss
.globl h_graph
.p2align 4, 0x0
h_graph:
.zero 324000000
.size h_graph, 324000000
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wiki-Vote.txt"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w %f\n"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "e %f\n"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "bellman.txt"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d: %d\n"
.size .L.str.7, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12bellman_fordPiS_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_change"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__bellman_fordPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_change
.addrsig_sym _Z12bellman_fordPiS_ii
.addrsig_sym h_graph
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12bellman_fordPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0003e2000c101904 */
/*00a0*/ IMAD R11, R9, c[0x0][0x0], R8 ; /* 0x00000000090b7a24 */
/* 0x001fc800078e0208 */
/*00b0*/ IMAD.WIDE R4, R11, R17, c[0x0][0x168] ; /* 0x00005a000b047625 */
/* 0x000fca00078e0211 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000368000c1e1900 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @!P0 BRA 0x6b0 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R0.reuse, -0x2, RZ ; /* 0xfffffffe00067810 */
/* 0x042fe40007ffe0ff */
/*0100*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd600078ec0ff */
/*0140*/ @!P0 BRA 0x530 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, R8, c[0x0][0x174], RZ ; /* 0x00005d0008067a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ MOV R8, c[0x0][0x168] ; /* 0x00005a0000087a02 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R10, -R0, c[0x0][0x174], RZ ; /* 0x00005d00000a7a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD R16, R9, c[0x0][0x0], R6 ; /* 0x0000000009107a24 */
/* 0x000fe400078e0206 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fca00078e0211 */
/*01c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B0, 0x290 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01f0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fc40003f05270 */
/*0200*/ IMAD.WIDE R12, R15, 0x4, R16 ; /* 0x000000040f0c7825 */
/* 0x000fd600078e0210 */
/*0210*/ @P0 BRA 0x280 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GT.AND P0, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f04270 */
/*0250*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff110424 */
/* 0x000fe200078e00ff */
/*0260*/ @P0 MOV R7, R14 ; /* 0x0000000e00070202 */
/* 0x000fc80000000f00 */
/*0270*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e6000c101904 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ BSSY B0, 0x350 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.WIDE R16, R15, 0x4, R12 ; /* 0x000000040f107825 */
/* 0x001fe200078e020c */
/*02c0*/ ISETP.NE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fda0003f05270 */
/*02d0*/ @P0 BRA 0x340 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x004fc80007ffe0ff */
/*0300*/ ISETP.GT.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x020fda0003f04270 */
/*0310*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d0424 */
/* 0x000fe400078e00ff */
/*0320*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff070224 */
/* 0x000fc600078e000c */
/*0330*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e8000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ BSSY B0, 0x410 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fe20003f05270 */
/*0380*/ IMAD.WIDE R12, R15, 0x4, R16 ; /* 0x000000040f0c7825 */
/* 0x001fd800078e0210 */
/*0390*/ @P0 BRA 0x400 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R14, [R8.64+0xc] ; /* 0x00000c04080e7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*03c0*/ ISETP.GT.AND P0, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f04270 */
/*03d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff110424 */
/* 0x000fe400078e00ff */
/*03e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fc600078e000e */
/*03f0*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e8000c101904 */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0420*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ BSSY B0, 0x4e0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0440*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f05270 */
/*0450*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fda0003f25270 */
/*0460*/ @P1 BRA 0x4d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x004fc80007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x020fda0003f24270 */
/*04a0*/ @P1 MOV R17, 0x1 ; /* 0x0000000100111802 */
/* 0x001fe20000000f00 */
/*04b0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff071224 */
/* 0x000fc800078e000e */
/*04c0*/ @P1 STG.E [R2.64], R17 ; /* 0x0000001102001986 */
/* 0x0001e6000c101904 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007f3e0ff */
/*04f0*/ IMAD.WIDE R16, R15, 0x4, R12 ; /* 0x000000040f107825 */
/* 0x001fe200078e020c */
/*0500*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*0520*/ @P0 BRA 0x1c0 ; /* 0xfffffc9000000947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0540*/ @!P0 BRA 0x6b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD R11, R6.reuse, c[0x0][0x174], R11 ; /* 0x00005d00060b7a24 */
/* 0x040fe400078e020b */
/*0570*/ IMAD.WIDE R8, R6, R10, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fc800078e020a */
/*0580*/ IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fca00078e020a */
/*0590*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ BSSY B0, 0x670 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*05c0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe400078e00ff */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*05e0*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f25270 */
/*05f0*/ @P1 BRA 0x660 ; /* 0x0000006000001947 */
/* 0x001fea0003800000 */
/*0600*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea4000c1e1900 */
/*0610*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x004fc80007ffe0ff */
/*0620*/ ISETP.GT.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x020fda0003f24270 */
/*0630*/ @P1 MOV R13, 0x1 ; /* 0x00000001000d1802 */
/* 0x000fe20000000f00 */
/*0640*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff071224 */
/* 0x000fc800078e0006 */
/*0650*/ @P1 STG.E [R2.64], R13 ; /* 0x0000000d02001986 */
/* 0x0001e6000c101904 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f3e0ff */
/*0680*/ IMAD.WIDE R10, R15, 0x4, R10 ; /* 0x000000040f0a7825 */
/* 0x000fc800078e020a */
/*0690*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*06a0*/ @P0 BRA 0x590 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fec0000010000 */
/*06c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x020fe2000c101904 */
/*06d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06e0*/ BRA 0x6e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12bellman_fordPiS_ii
.globl _Z12bellman_fordPiS_ii
.p2align 8
.type _Z12bellman_fordPiS_ii,@function
_Z12bellman_fordPiS_ii:
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s15, s15, s4
s_load_b32 s4, s[0:1], 0x14
v_add_nc_u32_e32 v1, s15, v0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_change@rel32@lo+4
s_addc_u32 s7, s7, d_change@rel32@hi+12
global_store_b32 v6, v6, s[6:7]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_cmp_lt_i32 s4, 2
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_add3_u32 v3, s15, s4, v0
v_mov_b32_e32 v0, 1
s_add_i32 s5, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, -1
v_add_nc_u32_e32 v3, s4, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s5, 0
s_cbranch_scc0 .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v4
s_cbranch_execz .LBB0_3
global_load_b32 v4, v6, s[2:3]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v5, v4
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v5, v4
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_change@rel32@lo+4
s_addc_u32 s9, s9, d_change@rel32@hi+12
global_store_b32 v6, v0, s[8:9]
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_store_b32 v[1:2], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12bellman_fordPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12bellman_fordPiS_ii, .Lfunc_end0-_Z12bellman_fordPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_change
.type d_change,@object
.section .bss,"aw",@nobits
.globl d_change
.p2align 2, 0x0
d_change:
.long 0
.size d_change, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_change
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12bellman_fordPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12bellman_fordPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa007_00000000-6_sssp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
.type _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii, @function
_Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12bellman_fordPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii, .-_Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
.globl _Z12bellman_fordPiS_ii
.type _Z12bellman_fordPiS_ii, @function
_Z12bellman_fordPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12bellman_fordPiS_ii, .-_Z12bellman_fordPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "wiki-Vote.txt"
.LC2:
.string "%d"
.LC3:
.string "w %f\n"
.LC4:
.string "e %f\n"
.LC5:
.string "w"
.LC6:
.string "bellman.txt"
.LC7:
.string "%d: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32824
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3336, %rsp
.cfi_def_cfa_offset 36160
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 36088(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 12(%rsp), %r14
leaq .LC2(%rip), %rbp
leaq 16(%rsp), %r13
leaq h_graph(%rip), %r12
jmp .L12
.L13:
movq %r14, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq 16(%rsp), %rdx
movslq 12(%rsp), %rax
imulq $9000, %rax, %rax
addq %rdx, %rax
movl $1, (%r12,%rax,4)
.L12:
movq %rbx, %rdi
call feof@PLT
testl %eax, %eax
je .L13
movq %rbx, %rdi
call fclose@PLT
movq 8(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl $9000, %eax
movl $0, %edx
idivl %ebp
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %r12d
leaq 80(%rsp), %rdx
leaq 36080(%rsp), %rcx
.L14:
movl $100000, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L14
movl $0, 92(%rsp)
leaq 40(%rsp), %r13
movq %r13, %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rbx
movq %rbx, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $324000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $324000000, %edx
leaq h_graph(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $36000, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $36000, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call cudaEventCreate@PLT
movq %rbx, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
leaq _ZL8d_change(%rip), %r13
jmp .L17
.L15:
leaq 68(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
movq %r13, %rsi
call cudaMemcpyFromSymbol@PLT
cmpl $0, 68(%rsp)
je .L18
addl $1, %ebx
cmpl $8999, %ebx
je .L18
.L17:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $9000, %ecx
movl %ebx, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12bellman_fordPiS_iiPiS_ii
jmp .L15
.L18:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rbx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $36000, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC7(%rip), %r12
.L19:
movl 80(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $9000, %rbx
jne .L19
movq %rbp, %rdi
call fclose@PLT
movq 36088(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $36104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12bellman_fordPiS_ii"
.LC9:
.string "d_change"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bellman_fordPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8d_change(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_graph
.bss
.align 32
.type h_graph, @object
.size h_graph, 324000000
h_graph:
.zero 324000000
.local _ZL8d_change
.comm _ZL8d_change,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sssp.hip"
.globl _Z27__device_stub__bellman_fordPiS_ii # -- Begin function _Z27__device_stub__bellman_fordPiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__bellman_fordPiS_ii,@function
_Z27__device_stub__bellman_fordPiS_ii: # @_Z27__device_stub__bellman_fordPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12bellman_fordPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__bellman_fordPiS_ii, .Lfunc_end0-_Z27__device_stub__bellman_fordPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $36168, %rsp # imm = 0x8D48
.cfi_def_cfa_offset 36224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $0, 36(%rsp)
movl $0, 32(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 36(%rsp), %r15
leaq 32(%rsp), %r12
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 36(%rsp), %rax
movslq 32(%rsp), %rcx
imulq $36000, %rax, %rax # imm = 0x8CA0
movl $1, h_graph(%rax,%rcx,4)
movq %r14, %rdi
callq feof
testl %eax, %eax
je .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rbx), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $9000, %eax # imm = 0x2328
xorl %edx, %edx
idivl %r14d
movl %eax, %ebx
xorl %eax, %eax
testl %edx, %edx
setne %al
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl $100000, 160(%rsp,%r15,4) # imm = 0x186A0
incq %r15
cmpq $9000, %r15 # imm = 0x2328
jne .LBB1_4
# %bb.5:
addl %eax, %ebx
movl $0, 172(%rsp)
leaq 24(%rsp), %r15
movq %r15, %rdi
callq hipEventCreate
leaq 8(%rsp), %r13
movq %r13, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
leaq 56(%rsp), %rdi
movl $324000000, %esi # imm = 0x134FD900
callq hipMalloc
movq 56(%rsp), %rdi
movl $h_graph, %esi
movl $324000000, %edx # imm = 0x134FD900
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movl $36000, %esi # imm = 0x8CA0
callq hipMalloc
movq 40(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $36000, %edx # imm = 0x8CA0
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r14d, %r14d
orq %rax, %r14
leaq 72(%rsp), %r13
leaq 64(%rsp), %rbp
leaq 128(%rsp), %r15
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r12d, 52(%rsp)
movl $9000, 48(%rsp) # imm = 0x2328
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z12bellman_fordPiS_ii, %edi
movq %r15, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
movl $d_change, %esi
movl $4, %edx
movq %r15, %rdi
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
cmpl $0, 128(%rsp)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_6 Depth=1
leal 1(%r12), %eax
cmpl $8998, %r12d # imm = 0x2326
movl %eax, %r12d
jne .LBB1_6
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $36000, %edx # imm = 0x8CA0
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl 160(%rsp,%r14,4), %ecx
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $9000, %r14 # imm = 0x2328
jne .LBB1_11
# %bb.12:
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $36168, %rsp # imm = 0x8D48
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bellman_fordPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_change, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_change,@object # @d_change
.local d_change
.comm d_change,4,4
.type _Z12bellman_fordPiS_ii,@object # @_Z12bellman_fordPiS_ii
.section .rodata,"a",@progbits
.globl _Z12bellman_fordPiS_ii
.p2align 3, 0x0
_Z12bellman_fordPiS_ii:
.quad _Z27__device_stub__bellman_fordPiS_ii
.size _Z12bellman_fordPiS_ii, 8
.type h_graph,@object # @h_graph
.bss
.globl h_graph
.p2align 4, 0x0
h_graph:
.zero 324000000
.size h_graph, 324000000
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wiki-Vote.txt"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w %f\n"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "e %f\n"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "bellman.txt"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d: %d\n"
.size .L.str.7, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12bellman_fordPiS_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_change"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__bellman_fordPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_change
.addrsig_sym _Z12bellman_fordPiS_ii
.addrsig_sym h_graph
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} | code for sm_80
Function : _Z17bitonic_sort_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} | .file "tmpxft_0016b46b_00000000-6_bitonic_sort_step.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.type _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, @function
_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17bitonic_sort_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, .-_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.globl _Z17bitonic_sort_stepPiii
.type _Z17bitonic_sort_stepPiii, @function
_Z17bitonic_sort_stepPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17bitonic_sort_stepPiii, .-_Z17bitonic_sort_stepPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17bitonic_sort_stepPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonic_sort_stepPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonic_sort_stepPiii
.globl _Z17bitonic_sort_stepPiii
.p2align 8
.type _Z17bitonic_sort_stepPiii,@function
_Z17bitonic_sort_stepPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonic_sort_stepPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonic_sort_stepPiii, .Lfunc_end0-_Z17bitonic_sort_stepPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonic_sort_stepPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonic_sort_stepPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
} | .text
.file "bitonic_sort_step.hip"
.globl _Z32__device_stub__bitonic_sort_stepPiii # -- Begin function _Z32__device_stub__bitonic_sort_stepPiii
.p2align 4, 0x90
.type _Z32__device_stub__bitonic_sort_stepPiii,@function
_Z32__device_stub__bitonic_sort_stepPiii: # @_Z32__device_stub__bitonic_sort_stepPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17bitonic_sort_stepPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__bitonic_sort_stepPiii, .Lfunc_end0-_Z32__device_stub__bitonic_sort_stepPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonic_sort_stepPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17bitonic_sort_stepPiii,@object # @_Z17bitonic_sort_stepPiii
.section .rodata,"a",@progbits
.globl _Z17bitonic_sort_stepPiii
.p2align 3, 0x0
_Z17bitonic_sort_stepPiii:
.quad _Z32__device_stub__bitonic_sort_stepPiii
.size _Z17bitonic_sort_stepPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17bitonic_sort_stepPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonic_sort_stepPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonic_sort_stepPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17bitonic_sort_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonic_sort_stepPiii
.globl _Z17bitonic_sort_stepPiii
.p2align 8
.type _Z17bitonic_sort_stepPiii,@function
_Z17bitonic_sort_stepPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonic_sort_stepPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonic_sort_stepPiii, .Lfunc_end0-_Z17bitonic_sort_stepPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonic_sort_stepPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonic_sort_stepPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b46b_00000000-6_bitonic_sort_step.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.type _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, @function
_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17bitonic_sort_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, .-_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.globl _Z17bitonic_sort_stepPiii
.type _Z17bitonic_sort_stepPiii, @function
_Z17bitonic_sort_stepPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17bitonic_sort_stepPiii, .-_Z17bitonic_sort_stepPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17bitonic_sort_stepPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonic_sort_stepPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonic_sort_step.hip"
.globl _Z32__device_stub__bitonic_sort_stepPiii # -- Begin function _Z32__device_stub__bitonic_sort_stepPiii
.p2align 4, 0x90
.type _Z32__device_stub__bitonic_sort_stepPiii,@function
_Z32__device_stub__bitonic_sort_stepPiii: # @_Z32__device_stub__bitonic_sort_stepPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17bitonic_sort_stepPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__bitonic_sort_stepPiii, .Lfunc_end0-_Z32__device_stub__bitonic_sort_stepPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonic_sort_stepPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17bitonic_sort_stepPiii,@object # @_Z17bitonic_sort_stepPiii
.section .rodata,"a",@progbits
.globl _Z17bitonic_sort_stepPiii
.p2align 3, 0x0
_Z17bitonic_sort_stepPiii:
.quad _Z32__device_stub__bitonic_sort_stepPiii
.size _Z17bitonic_sort_stepPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17bitonic_sort_stepPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonic_sort_stepPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonic_sort_stepPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This exercise is for student to learn about data sharing and synchronization between threads
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, sizeof(int)*N);
cudaMalloc((void**)&d_b, sizeof(int)*N);
cudaMalloc((void**)&d_c, sizeof(int));
cudaMemcpy(d_a, a, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(int)*N, cudaMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} | code for sm_80
Function : _Z10vector_macPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x040fe400078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R7, R4, R3, RZ ; /* 0x0000000304077224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0x520 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd800078e00ff */
/*0180*/ @!P0 BRA 0x490 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01c0*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x330 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDS.128 R16, [UR5] ; /* 0x00000005ff107984 */
/* 0x000e220008000c00 */
/*0230*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe20007ffe0ff */
/*0240*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0250*/ LDS.128 R12, [UR5+0x10] ; /* 0x00001005ff0c7984 */
/* 0x000e620008000c00 */
/*0260*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fc60003f24270 */
/*0270*/ LDS.128 R8, [UR5+0x20] ; /* 0x00002005ff087984 */
/* 0x000ea80008000c00 */
/*0280*/ LDS.128 R4, [UR5+0x30] ; /* 0x00003005ff047984 */
/* 0x000ee20008000c00 */
/*0290*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*02a0*/ IADD3 R16, R17, R16, R2 ; /* 0x0000001011107210 */
/* 0x001fc80007ffe002 */
/*02b0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*02c0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x002fc80007ffe010 */
/*02d0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*02e0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x004fc80007ffe00c */
/*02f0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0300*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x008fc80007ffe008 */
/*0310*/ IADD3 R2, R7, R6, R4 ; /* 0x0000000607027210 */
/* 0x000fe20007ffe004 */
/*0320*/ @P1 BRA 0x220 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0330*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0340*/ @!P1 BRA 0x3f0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0350*/ LDS.128 R8, [UR5] ; /* 0x00000005ff087984 */
/* 0x000e220008000c00 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0370*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0380*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe20007ffe0ff */
/*0390*/ LDS.128 R4, [UR5+0x10] ; /* 0x00001005ff047984 */
/* 0x000e620008000c00 */
/*03a0*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*03b0*/ IADD3 R8, R9, R8, R2 ; /* 0x0000000809087210 */
/* 0x001fc80007ffe002 */
/*03c0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*03d0*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x002fc80007ffe008 */
/*03e0*/ IADD3 R2, R7, R6, R4 ; /* 0x0000000607027210 */
/* 0x000fe40007ffe004 */
/*03f0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0400*/ @!P0 BRA 0x490 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0410*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*0420*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe20007ffe0ff */
/*0430*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0440*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*0450*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0460*/ IADD3 R2, R5, R4, R2 ; /* 0x0000000405027210 */
/* 0x001fc80007ffe002 */
/*0470*/ IADD3 R2, R7, R6, R2 ; /* 0x0000000607027210 */
/* 0x000fce0007ffe002 */
/*0480*/ @P0 BRA 0x410 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0490*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*04a0*/ @!P0 BRA 0x520 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*04b0*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fd2000800063f */
/*04c0*/ LDS R3, [UR4] ; /* 0x00000004ff037984 */
/* 0x000e220008000800 */
/*04d0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*04f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0500*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x001fd800078e0202 */
/*0510*/ @P0 BRA 0x4c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0540*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101906 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This exercise is for student to learn about data sharing and synchronization between threads
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, sizeof(int)*N);
cudaMalloc((void**)&d_b, sizeof(int)*N);
cudaMalloc((void**)&d_c, sizeof(int));
cudaMemcpy(d_a, a, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(int)*N, cudaMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} | .file "tmpxft_000a3e85_00000000-6_Lab5-3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_macPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
.globl _Z10vector_macPiS_S_i
.type _Z10vector_macPiS_S_i, @function
_Z10vector_macPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_macPiS_S_i, .-_Z10vector_macPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A = [%2d %2d %2d %2d]\n"
.LC1:
.string "B = [%2d %2d %2d %2d]\n"
.LC2:
.string "Answer = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $22, 64(%rsp)
movl $13, 68(%rsp)
movl $16, 72(%rsp)
movl $5, 76(%rsp)
movl $5, 80(%rsp)
movl $22, 84(%rsp)
movl $17, 88(%rsp)
movl $37, 92(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %r9d
movl 88(%rsp), %r8d
movl 84(%rsp), %ecx
movl 80(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 60(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $4, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_macPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_macPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This exercise is for student to learn about data sharing and synchronization between threads
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, sizeof(int)*N);
cudaMalloc((void**)&d_b, sizeof(int)*N);
cudaMalloc((void**)&d_c, sizeof(int));
cudaMemcpy(d_a, a, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(int)*N, cudaMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} | // This exercise is for student to learn about data sharing and synchronization between threads
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, sizeof(int)*N);
hipMalloc((void**)&d_b, sizeof(int)*N);
hipMalloc((void**)&d_c, sizeof(int));
hipMemcpy(d_a, a, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeof(int)*N, hipMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // This exercise is for student to learn about data sharing and synchronization between threads
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, sizeof(int)*N);
hipMalloc((void**)&d_b, sizeof(int)*N);
hipMalloc((void**)&d_c, sizeof(int));
hipMemcpy(d_a, a, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeof(int)*N, hipMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_macPiS_S_i
.globl _Z10vector_macPiS_S_i
.p2align 8
.type _Z10vector_macPiS_S_i,@function
_Z10vector_macPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v2, v0
v_lshlrev_b32_e32 v2, 2, v1
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_mov_b32 s3, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_add_i32 s2, s2, -1
s_add_i32 s3, s3, 4
s_cmp_eq_u32 s2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_macPiS_S_i
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_macPiS_S_i, .Lfunc_end0-_Z10vector_macPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_macPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_macPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This exercise is for student to learn about data sharing and synchronization between threads
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 4 // number of elements in vector
__global__
void vector_mac(int *d_c, int *d_a, int *d_b, int n){
__shared__ int tmp[N]; // shared memory
int i = blockIdx.x * blockDim.x + threadIdx.x;
tmp[i] = d_a[i] * d_b[i];
__syncthreads(); // not really necessary for this simple program
if (i==0){ // use thread 0 to perform the summation
int sum = 0;
for (int j = 0; j < n; j++)
sum = sum + tmp[j];
*d_c = sum;
}
}
int main(void){
int a[N] = {22, 13, 16, 5};
int b[N] = { 5, 22, 17, 37};
int c[1];
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, sizeof(int)*N);
hipMalloc((void**)&d_b, sizeof(int)*N);
hipMalloc((void**)&d_c, sizeof(int));
hipMemcpy(d_a, a, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeof(int)*N, hipMemcpyHostToDevice);
vector_mac<<<1,N>>>(d_c, d_a, d_b, N); // 1 thread block with N (4) threads
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("A = [%2d %2d %2d %2d]\n", a[0], a[1], a[2], a[3]);
printf("B = [%2d %2d %2d %2d]\n", b[0], b[1], b[2], b[3]);
printf("Answer = %d\n", c[0]);
return 0;
} | .text
.file "Lab5-3.hip"
.globl _Z25__device_stub__vector_macPiS_S_i # -- Begin function _Z25__device_stub__vector_macPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_macPiS_S_i,@function
_Z25__device_stub__vector_macPiS_S_i: # @_Z25__device_stub__vector_macPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_macPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_macPiS_S_i, .Lfunc_end0-_Z25__device_stub__vector_macPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 22 # 0x16
.long 13 # 0xd
.long 16 # 0x10
.long 5 # 0x5
.LCPI1_1:
.long 5 # 0x5
.long 22 # 0x16
.long 17 # 0x11
.long 37 # 0x25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [22,13,16,5]
movaps %xmm0, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,22,17,37]
movaps %xmm0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $4, 28(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z10vector_macPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 144(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 48(%rsp), %esi
movl 52(%rsp), %edx
movl 56(%rsp), %ecx
movl 60(%rsp), %r8d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 144(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_macPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_macPiS_S_i,@object # @_Z10vector_macPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_macPiS_S_i
.p2align 3, 0x0
_Z10vector_macPiS_S_i:
.quad _Z25__device_stub__vector_macPiS_S_i
.size _Z10vector_macPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A = [%2d %2d %2d %2d]\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "B = [%2d %2d %2d %2d]\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Answer = %d\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_macPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_macPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_macPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_macPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x040fe400078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R7, R4, R3, RZ ; /* 0x0000000304077224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0x520 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd800078e00ff */
/*0180*/ @!P0 BRA 0x490 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01c0*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x330 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDS.128 R16, [UR5] ; /* 0x00000005ff107984 */
/* 0x000e220008000c00 */
/*0230*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe20007ffe0ff */
/*0240*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0250*/ LDS.128 R12, [UR5+0x10] ; /* 0x00001005ff0c7984 */
/* 0x000e620008000c00 */
/*0260*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fc60003f24270 */
/*0270*/ LDS.128 R8, [UR5+0x20] ; /* 0x00002005ff087984 */
/* 0x000ea80008000c00 */
/*0280*/ LDS.128 R4, [UR5+0x30] ; /* 0x00003005ff047984 */
/* 0x000ee20008000c00 */
/*0290*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*02a0*/ IADD3 R16, R17, R16, R2 ; /* 0x0000001011107210 */
/* 0x001fc80007ffe002 */
/*02b0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*02c0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x002fc80007ffe010 */
/*02d0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*02e0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x004fc80007ffe00c */
/*02f0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0300*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x008fc80007ffe008 */
/*0310*/ IADD3 R2, R7, R6, R4 ; /* 0x0000000607027210 */
/* 0x000fe20007ffe004 */
/*0320*/ @P1 BRA 0x220 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0330*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0340*/ @!P1 BRA 0x3f0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0350*/ LDS.128 R8, [UR5] ; /* 0x00000005ff087984 */
/* 0x000e220008000c00 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0370*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0380*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe20007ffe0ff */
/*0390*/ LDS.128 R4, [UR5+0x10] ; /* 0x00001005ff047984 */
/* 0x000e620008000c00 */
/*03a0*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*03b0*/ IADD3 R8, R9, R8, R2 ; /* 0x0000000809087210 */
/* 0x001fc80007ffe002 */
/*03c0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*03d0*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x002fc80007ffe008 */
/*03e0*/ IADD3 R2, R7, R6, R4 ; /* 0x0000000607027210 */
/* 0x000fe40007ffe004 */
/*03f0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0400*/ @!P0 BRA 0x490 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0410*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*0420*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe20007ffe0ff */
/*0430*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0440*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*0450*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0460*/ IADD3 R2, R5, R4, R2 ; /* 0x0000000405027210 */
/* 0x001fc80007ffe002 */
/*0470*/ IADD3 R2, R7, R6, R2 ; /* 0x0000000607027210 */
/* 0x000fce0007ffe002 */
/*0480*/ @P0 BRA 0x410 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0490*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*04a0*/ @!P0 BRA 0x520 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*04b0*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fd2000800063f */
/*04c0*/ LDS R3, [UR4] ; /* 0x00000004ff037984 */
/* 0x000e220008000800 */
/*04d0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*04f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0500*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x001fd800078e0202 */
/*0510*/ @P0 BRA 0x4c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0540*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101906 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_macPiS_S_i
.globl _Z10vector_macPiS_S_i
.p2align 8
.type _Z10vector_macPiS_S_i,@function
_Z10vector_macPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v2, v0
v_lshlrev_b32_e32 v2, 2, v1
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_mov_b32 s3, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_add_i32 s2, s2, -1
s_add_i32 s3, s3, 4
s_cmp_eq_u32 s2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_macPiS_S_i
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_macPiS_S_i, .Lfunc_end0-_Z10vector_macPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_macPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_macPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a3e85_00000000-6_Lab5-3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_macPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
.globl _Z10vector_macPiS_S_i
.type _Z10vector_macPiS_S_i, @function
_Z10vector_macPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_macPiS_S_i, .-_Z10vector_macPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A = [%2d %2d %2d %2d]\n"
.LC1:
.string "B = [%2d %2d %2d %2d]\n"
.LC2:
.string "Answer = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $22, 64(%rsp)
movl $13, 68(%rsp)
movl $16, 72(%rsp)
movl $5, 76(%rsp)
movl $5, 80(%rsp)
movl $22, 84(%rsp)
movl $17, 88(%rsp)
movl $37, 92(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %r9d
movl 88(%rsp), %r8d
movl 84(%rsp), %ecx
movl 80(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 60(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $4, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_macPiS_S_iPiS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_macPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_macPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Lab5-3.hip"
.globl _Z25__device_stub__vector_macPiS_S_i # -- Begin function _Z25__device_stub__vector_macPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_macPiS_S_i,@function
_Z25__device_stub__vector_macPiS_S_i: # @_Z25__device_stub__vector_macPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_macPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_macPiS_S_i, .Lfunc_end0-_Z25__device_stub__vector_macPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 22 # 0x16
.long 13 # 0xd
.long 16 # 0x10
.long 5 # 0x5
.LCPI1_1:
.long 5 # 0x5
.long 22 # 0x16
.long 17 # 0x11
.long 37 # 0x25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [22,13,16,5]
movaps %xmm0, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,22,17,37]
movaps %xmm0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $4, 28(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z10vector_macPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 144(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 48(%rsp), %esi
movl 52(%rsp), %edx
movl 56(%rsp), %ecx
movl 60(%rsp), %r8d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 144(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_macPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_macPiS_S_i,@object # @_Z10vector_macPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_macPiS_S_i
.p2align 3, 0x0
_Z10vector_macPiS_S_i:
.quad _Z25__device_stub__vector_macPiS_S_i
.size _Z10vector_macPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A = [%2d %2d %2d %2d]\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "B = [%2d %2d %2d %2d]\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Answer = %d\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_macPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_macPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_macPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fm_order2_dgrad_kernel(const float* in, const float* top_grad, float* dgrad, int batch_size, int slot_num, int emb_vec_size) {
int tid = threadIdx.x;
int bid = blockIdx.x;
if (tid < emb_vec_size && bid < batch_size) {
float emb_sum = 0.0f;
int offset = bid * slot_num * emb_vec_size + tid;
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
emb_sum += in[index];
}
float tgrad = top_grad[bid * emb_vec_size + tid];
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
dgrad[index] = tgrad * (emb_sum - in[index]);
}
}
} | .file "tmpxft_0004e39f_00000000-6_fm_order2_dgrad_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22fm_order2_dgrad_kernelPKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
.globl _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.type _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, @function
_Z22fm_order2_dgrad_kernelPKfS0_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, .-_Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22fm_order2_dgrad_kernelPKfS0_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22fm_order2_dgrad_kernelPKfS0_Pfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fm_order2_dgrad_kernel(const float* in, const float* top_grad, float* dgrad, int batch_size, int slot_num, int emb_vec_size) {
int tid = threadIdx.x;
int bid = blockIdx.x;
if (tid < emb_vec_size && bid < batch_size) {
float emb_sum = 0.0f;
int offset = bid * slot_num * emb_vec_size + tid;
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
emb_sum += in[index];
}
float tgrad = top_grad[bid * emb_vec_size + tid];
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
dgrad[index] = tgrad * (emb_sum - in[index]);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fm_order2_dgrad_kernel(const float* in, const float* top_grad, float* dgrad, int batch_size, int slot_num, int emb_vec_size) {
int tid = threadIdx.x;
int bid = blockIdx.x;
if (tid < emb_vec_size && bid < batch_size) {
float emb_sum = 0.0f;
int offset = bid * slot_num * emb_vec_size + tid;
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
emb_sum += in[index];
}
float tgrad = top_grad[bid * emb_vec_size + tid];
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
dgrad[index] = tgrad * (emb_sum - in[index]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fm_order2_dgrad_kernel(const float* in, const float* top_grad, float* dgrad, int batch_size, int slot_num, int emb_vec_size) {
int tid = threadIdx.x;
int bid = blockIdx.x;
if (tid < emb_vec_size && bid < batch_size) {
float emb_sum = 0.0f;
int offset = bid * slot_num * emb_vec_size + tid;
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
emb_sum += in[index];
}
float tgrad = top_grad[bid * emb_vec_size + tid];
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
dgrad[index] = tgrad * (emb_sum - in[index]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.globl _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.p2align 8
.type _Z22fm_order2_dgrad_kernelPKfS0_Pfiii,@function
_Z22fm_order2_dgrad_kernelPKfS0_Pfiii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
s_cmp_lt_i32 s15, s2
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s7, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mul_i32 s2, s15, s6
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s7, v[0:1]
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
s_mov_b32 s2, s7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_7
s_load_b128 s[0:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
.p2align 6
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s7, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v5, v0, v5
global_store_b32 v[2:3], v5, off
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, .Lfunc_end0-_Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22fm_order2_dgrad_kernelPKfS0_Pfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fm_order2_dgrad_kernel(const float* in, const float* top_grad, float* dgrad, int batch_size, int slot_num, int emb_vec_size) {
int tid = threadIdx.x;
int bid = blockIdx.x;
if (tid < emb_vec_size && bid < batch_size) {
float emb_sum = 0.0f;
int offset = bid * slot_num * emb_vec_size + tid;
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
emb_sum += in[index];
}
float tgrad = top_grad[bid * emb_vec_size + tid];
for (int i = 0; i < slot_num; i++) {
int index = offset + i * emb_vec_size;
dgrad[index] = tgrad * (emb_sum - in[index]);
}
}
} | .text
.file "fm_order2_dgrad_kernel.hip"
.globl _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii # -- Begin function _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.p2align 4, 0x90
.type _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii,@function
_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii: # @_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22fm_order2_dgrad_kernelPKfS0_Pfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii, .Lfunc_end0-_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22fm_order2_dgrad_kernelPKfS0_Pfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22fm_order2_dgrad_kernelPKfS0_Pfiii,@object # @_Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.section .rodata,"a",@progbits
.globl _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.p2align 3, 0x0
_Z22fm_order2_dgrad_kernelPKfS0_Pfiii:
.quad _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.size _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22fm_order2_dgrad_kernelPKfS0_Pfiii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004e39f_00000000-6_fm_order2_dgrad_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22fm_order2_dgrad_kernelPKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
.globl _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.type _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, @function
_Z22fm_order2_dgrad_kernelPKfS0_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22fm_order2_dgrad_kernelPKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, .-_Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22fm_order2_dgrad_kernelPKfS0_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22fm_order2_dgrad_kernelPKfS0_Pfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fm_order2_dgrad_kernel.hip"
.globl _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii # -- Begin function _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.p2align 4, 0x90
.type _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii,@function
_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii: # @_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22fm_order2_dgrad_kernelPKfS0_Pfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii, .Lfunc_end0-_Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22fm_order2_dgrad_kernelPKfS0_Pfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22fm_order2_dgrad_kernelPKfS0_Pfiii,@object # @_Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.section .rodata,"a",@progbits
.globl _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.p2align 3, 0x0
_Z22fm_order2_dgrad_kernelPKfS0_Pfiii:
.quad _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.size _Z22fm_order2_dgrad_kernelPKfS0_Pfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22fm_order2_dgrad_kernelPKfS0_Pfiii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__fm_order2_dgrad_kernelPKfS0_Pfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22fm_order2_dgrad_kernelPKfS0_Pfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} | code for sm_80
Function : _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD R6, R0, 0x3, RZ ; /* 0x0000000300067824 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R6.reuse, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe400078e0207 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f62000c1e1900 */
/*0110*/ IADD3 R6, R6, c[0x0][0x188], RZ ; /* 0x0000620006067a10 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0140*/ FSEL R9, R0, c[0x0][0x170], P0 ; /* 0x00005c0000097a08 */
/* 0x008fe40000000000 */
/*0150*/ FSEL R11, R8, c[0x0][0x174], P0 ; /* 0x00005d00080b7a08 */
/* 0x010fc60000000000 */
/*0160*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0170*/ FSEL R13, R10, c[0x0][0x178], P0 ; /* 0x00005e000a0d7a08 */
/* 0x020fc60000000000 */
/*0180*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} | .file "tmpxft_0011f3e8_00000000-6_CopyPointsCoordinatesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
.type _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii, @function
_Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27CopyPointsCoordinatesKernelPfPifffS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii, .-_Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii, @function
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, .-_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27CopyPointsCoordinatesKernelPfPifffS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27CopyPointsCoordinatesKernelPfPifffS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 8
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii,@function
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v3, v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[0:1], off
global_load_b96 v[0:2], v[4:5], off
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v0, v0, s2, vcc_lo
v_cndmask_b32_e64 v1, v1, s3, vcc_lo
v_cndmask_b32_e64 v2, v2, s5, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b96 v[3:4], v[0:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, .Lfunc_end0-_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27CopyPointsCoordinatesKernelPfPifffS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyPointsCoordinatesKernel( float *pointsCoordinates, int *activityFlag, float xNonValid, float yNonValid, float zNonValid, float *dataVertex, int dataVertexOffset, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
float xToCopy = pointsCoordinates[threadId * 3];
float yToCopy = pointsCoordinates[threadId * 3 + 1];
float zToCopy = pointsCoordinates[threadId * 3 + 2];
if(activityFlag[threadId] == 0)
{
xToCopy = xNonValid;
yToCopy = yNonValid;
zToCopy = zNonValid;
}
dataVertex[dataVertexOffset + threadId * 3] = xToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 1] = yToCopy;
dataVertex[dataVertexOffset + threadId * 3 + 2] = zToCopy;
}
} | .text
.file "CopyPointsCoordinatesKernel.hip"
.globl _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii # -- Begin function _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 4, 0x90
.type _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii,@function
_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii: # @_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27CopyPointsCoordinatesKernelPfPifffS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii, .Lfunc_end0-_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27CopyPointsCoordinatesKernelPfPifffS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii,@object # @_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .rodata,"a",@progbits
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 3, 0x0
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
.quad _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27CopyPointsCoordinatesKernelPfPifffS_ii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD R6, R0, 0x3, RZ ; /* 0x0000000300067824 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R6.reuse, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe400078e0207 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f62000c1e1900 */
/*0110*/ IADD3 R6, R6, c[0x0][0x188], RZ ; /* 0x0000620006067a10 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0140*/ FSEL R9, R0, c[0x0][0x170], P0 ; /* 0x00005c0000097a08 */
/* 0x008fe40000000000 */
/*0150*/ FSEL R11, R8, c[0x0][0x174], P0 ; /* 0x00005d00080b7a08 */
/* 0x010fc60000000000 */
/*0160*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0170*/ FSEL R13, R10, c[0x0][0x178], P0 ; /* 0x00005e000a0d7a08 */
/* 0x020fc60000000000 */
/*0180*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 8
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii,@function
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v3, v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[0:1], off
global_load_b96 v[0:2], v[4:5], off
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v0, v0, s2, vcc_lo
v_cndmask_b32_e64 v1, v1, s3, vcc_lo
v_cndmask_b32_e64 v2, v2, s5, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b96 v[3:4], v[0:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, .Lfunc_end0-_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27CopyPointsCoordinatesKernelPfPifffS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f3e8_00000000-6_CopyPointsCoordinatesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
.type _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii, @function
_Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27CopyPointsCoordinatesKernelPfPifffS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii, .-_Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii, @function
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z27CopyPointsCoordinatesKernelPfPifffS_iiPfPifffS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, .-_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27CopyPointsCoordinatesKernelPfPifffS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27CopyPointsCoordinatesKernelPfPifffS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CopyPointsCoordinatesKernel.hip"
.globl _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii # -- Begin function _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 4, 0x90
.type _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii,@function
_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii: # @_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27CopyPointsCoordinatesKernelPfPifffS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii, .Lfunc_end0-_Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27CopyPointsCoordinatesKernelPfPifffS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27CopyPointsCoordinatesKernelPfPifffS_ii,@object # @_Z27CopyPointsCoordinatesKernelPfPifffS_ii
.section .rodata,"a",@progbits
.globl _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.p2align 3, 0x0
_Z27CopyPointsCoordinatesKernelPfPifffS_ii:
.quad _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.size _Z27CopyPointsCoordinatesKernelPfPifffS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27CopyPointsCoordinatesKernelPfPifffS_ii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__CopyPointsCoordinatesKernelPfPifffS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27CopyPointsCoordinatesKernelPfPifffS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* MAC0431 - Introducao a Programacao Paralela e Distribuida
*
* Fisica Alternativa
*
* Bruno Endo - 7990982
* Danilo Aleixo - 7972370
* Gustavo Caparica - 7991020
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__constant__ int WIDTH, HEIGHT;
int WIDTHH, HEIGHTH;
#define SIZE (WIDTH*HEIGHT)
#define SIZEH (WIDTHH*HEIGHTH)
#define BORDERW (WIDTH+2)
#define BORDERH (HEIGHT+2)
#define FAKE_SIZE (BORDERW*BORDERH)
#define FAKE_SIZEH ((WIDTHH+2)*(HEIGHTH+2))
#define MAXLINE 128
#define PI acosf(-1)
__device__ void get_components(int x, int y, float theta, float *V, float *outx, float *outy) {
*outx = V[y*BORDERW + x]*sinf(theta);
*outy = V[y*BORDERW + x]*cosf(theta);
}
__device__ float get_theta(int x, int y, float *V) {
return V[y*BORDERW + x]*2*PI;
}
__global__ void calc_contributions(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float theta = get_theta(x, y, G);
float contribRx, contribRy;
get_components(x, y, theta, R, &contribRx, &contribRy);
float contribBx, contribBy;
get_components(x, y, theta, B, &contribBx, &contribBy);
contribBx *= -1;
contribBy *= -1;
int xx = 0;
int yy = 0;
if (contribRx > 0) {
xx = 1;
} else {
xx = -1;
}
if (contribRy > 0) {
yy = 1;
} else {
yy = -1;
}
float deltaRx = (1 - R[y*BORDERW + (x + xx)])*contribRx/4.0;
float deltaRy = (1 - R[(y + yy)*BORDERW + x])*contribRy/4.0;
float deltaBx = (1 - B[y*BORDERW + (x - xx)])*contribBx/4.0;
float deltaBy = (1 - B[(y - yy)*BORDERW + x])*contribBy/4.0;
if (xx != 0) {
atomicAdd(&Rx[y*BORDERW + (x + xx)], deltaRx);
atomicAdd(&Rx[y*BORDERW + x], -deltaRx);
atomicAdd(&Bx[y*BORDERW + (x - xx)], deltaBx);
atomicAdd(&Bx[y*BORDERW + x], -deltaBx);
}
if (yy != 0) {
atomicAdd(&Ry[(y + yy)*BORDERW + x], deltaRy);
atomicAdd(&Ry[y*BORDERW + x], -deltaRy);
atomicAdd(&By[(y - yy)*BORDERW + x], deltaBy);
atomicAdd(&By[y*BORDERW + x], -deltaBy);
}
}
__global__ void calc_components(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
get_components(x, y, get_theta(x, y, R), R, &Rx[y*BORDERW + x], &Ry[y*BORDERW + x]);
get_components(x, y, get_theta(x, y, B), B, &Bx[y*BORDERW + x], &By[y*BORDERW + x]);
Bx[y*BORDERW + x] *= -1;
By[y*BORDERW + x] *= -1;
}
__global__ void recalc_magnitudes(float *Rx, float *Ry, float *Bx, float *By, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float rx = Rx[y*BORDERW + x];
float ry = Ry[y*BORDERW + x];
float r = sqrtf((rx*rx)+(ry*ry));
R[y*BORDERW + x] = r;
float bx = Bx[y*BORDERW + x];
float by = By[y*BORDERW + x];
float b = sqrtf((bx*bx)+(by*by));
B[y*BORDERW + x] = b;
Rx[y*BORDERW + x] = r;
Bx[y*BORDERW + x] = b;
}
__global__ void redist(float *nR, float *nB, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) {
float tmp = 1 - R[y*BORDERW + x];
nR[y*BORDERW + x] = 1;
atomicAdd(&nR[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nR[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nR[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nR[(y-1)*BORDERW + x], tmp/4);
}
if (B[y*BORDERW + x] > 1) {
float tmp = 1 - B[y*BORDERW + x];
nB[y*BORDERW + x] = 1;
atomicAdd(&nB[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nB[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nB[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nB[(y-1)*BORDERW + x], tmp/4);
}
}
__global__ void re_redist_w(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x + BORDERW], R[x]);
atomicAdd(&R[FAKE_SIZE - 1 - x - BORDERW], R[FAKE_SIZE - 1 - x]);
atomicAdd(&B[x + BORDERW], B[x]);
atomicAdd(&B[FAKE_SIZE - 1 - x - BORDERW], B[FAKE_SIZE - 1 - x]);
R[x] = 0;
R[FAKE_SIZE - 1 - x] = 0;
B[x] = 0;
B[FAKE_SIZE - 1 - x] = 0;
}
__global__ void re_redist_h(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x * BORDERW + 1], R[x * BORDERW]);
atomicAdd(&R[x * BORDERW + BORDERW - 2], R[x * BORDERW + BORDERW - 1]);
atomicAdd(&B[x * BORDERW + 1], B[x * BORDERW]);
atomicAdd(&B[x * BORDERW + BORDERW - 2], B[x * BORDERW + BORDERW - 1]);
R[x * BORDERW] = 0;
R[x * BORDERW + BORDERW - 1] = 0;
B[x * BORDERW] = 0;
B[x * BORDERW + BORDERW - 1] = 0;
}
__global__ void finalize(float *R, float *G, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) R[y*BORDERW + x] = 1;
if (B[y*BORDERW + x] > 1) B[y*BORDERW + x] = 1;
if (R[y*BORDERW + x] < 0) R[y*BORDERW + x] = 0;
if (B[y*BORDERW + x] < 0) B[y*BORDERW + x] = 0;
atomicAdd(&G[y*BORDERW + x], atan2f(B[y*BORDERW + x], R[y*BORDERW + x])/(2*PI));
if (G[y*BORDERW + x] > 1) G[y*BORDERW + x] = 0;
if (G[y*BORDERW + x] < 0) G[y*BORDERW + x] = 0;
}
// the wrapper around the kernel call for main program to call.
extern "C" void kernel_wrapper(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
dim3 image_size(WIDTHH, HEIGHTH);
calc_components<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(cudaGetLastError() == cudaSuccess);
calc_contributions<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(cudaGetLastError() == cudaSuccess);
recalc_magnitudes<<<image_size, 1>>>(Rx, Ry, Bx, By, R, B);
assert(cudaGetLastError() == cudaSuccess);
redist<<<image_size, 1>>>(R, B, Rx, Bx);
assert(cudaGetLastError() == cudaSuccess);
re_redist_w<<<WIDTHH, 1>>>(R, B);
assert(cudaGetLastError() == cudaSuccess);
re_redist_h<<<HEIGHTH, 1>>>(R, B);
assert(cudaGetLastError() == cudaSuccess);
finalize<<<image_size, 1>>>(R, G, B);
assert(cudaGetLastError() == cudaSuccess);
}
void writePPM(const char* file, float *R, float *G, float *B) {
FILE *fp = fopen(file, "w");
if (fp == NULL) {
fprintf(stderr, "Erro ao escrever %s\n", file);
return;
}
fprintf(fp, "P3\n%d %d\n255\n", WIDTHH, HEIGHTH);
for (int i = 1; i <= HEIGHTH; i++) {
for (int j = 1; j <= WIDTHH; j++) {
int idx = i*(WIDTHH+2) + j;
fprintf(fp, "%d %d %d ", (int)(R[idx]*255), (int)(G[idx]*255), (int)(B[idx]*255));
}
fprintf(fp, "\n");
}
fclose(fp);
}
int readPPM(const char* file, float **R, float **G, float **B) {
FILE *fp = fopen(file, "rb");
if (fp == NULL) {
fprintf(stderr, "Erro ao abrir %s\n", file);
return 0;
}
int w, h, k;
int red, green, blue;
int *gw, *gh;
char c;
char tmp[MAXLINE];
c = getc(fp);
if (c == 'P' || c == 'p') {
c = getc(fp);
}
if (c != '3') {
fprintf(stderr, "Erro: formato do PPM (P%c) nao suportado\n", c);
return 0;
}
c = getc(fp);
if (c == '\n' || c == '\r') {
c = getc(fp);
while(c == '#') {
fscanf(fp, "%[^\n\r] ", tmp);
c = getc(fp);
}
ungetc(c,fp);
}
fscanf(fp, "%d %d %d", &w, &h, &k);
WIDTHH = w;
HEIGHTH = h;
cudaGetSymbolAddress((void**)&gw, WIDTH);
assert(cudaGetLastError() == cudaSuccess);
cudaGetSymbolAddress((void**)&gh, HEIGHT);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gw, &w, sizeof(int), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gh, &h, sizeof(int), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
*R = (float*)malloc(FAKE_SIZEH*sizeof(float));
*G = (float*)malloc(FAKE_SIZEH*sizeof(float));
*B = (float*)malloc(FAKE_SIZEH*sizeof(float));
for (int i = 1; i <= h; i++) {
for (int j = 1; j <= w; j++) {
fscanf(fp, "%d %d %d", &red, &green, &blue );
(*R)[i*(w+2) + j] = (float)red/(float)k;
(*G)[i*(w+2) + j] = (float)green/(float)k;
(*B)[i*(w+2) + j] = (float)blue/(float)k;
}
}
for (int i = 0; i < w + 2; i++) {
(*R)[i] = (*G)[i] = (*B)[i] = 0;
(*R)[(h+1)*(w+2) + i] = (*G)[(h+1)*(w+2) + i] = (*B)[(h+1)*(w+2) + i] = 0;
}
for (int i = 0; i < h + 2; i++) {
(*R)[i*(w+2)] = (*G)[i*(w+2)] = (*B)[i*(w+2)] = 0;
(*R)[i*(w+2) + w + 1] = (*G)[i*(w+2) + w + 1] = (*B)[i*(w+2) + w + 1] = 0;
}
return 1;
}
int main(int argc, char const *argv[]) {
if (argc < 4) {
printf("Uso:\n");
printf("%s entrada saida num_iters [num_procs]\n", argv[0]);
printf("Nota: num_procs é ignorado pois usamos CUDA\n");
return 0;
}
int iters = atoi(argv[3]);
srand(time(NULL));
float *R, *G, *B, *gR, *gG, *gB, *nR, *nG, *nB, *nN;
if (!readPPM(argv[1], &R, &G, &B)) {
fprintf(stderr, "Erro durante a leitura\n");
return 1;
}
cudaMalloc((void**)&gR, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&gG, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&gB, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nR, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nG, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nB, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nN, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gR, R, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gG, G, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gB, B, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
clock_t start, stop;
start = clock();
for(int i = 0; i < iters; i++) {
kernel_wrapper(gR, gG, gB, nR, nG, nB, nN);
}
cudaDeviceSynchronize();
stop = clock();
cudaMemcpy(R, gR, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(G, gG, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(B, gB, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
float tempo = (float)(stop - start) / CLOCKS_PER_SEC;
printf("Tempo total: %fs (tempo medio por iteracao: %fs)\n", tempo, tempo/iters);
printf("Nota: tempo nao inclui tempo de copia de/para a GPU\n");
writePPM(argv[2], R, G, B);
return 0;
} | .file "tmpxft_000f1887_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14get_componentsiifPfS_S_
.type _Z14get_componentsiifPfS_S_, @function
_Z14get_componentsiifPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14get_componentsiifPfS_S_, .-_Z14get_componentsiifPfS_S_
.globl _Z9get_thetaiiPf
.type _Z9get_thetaiiPf, @function
_Z9get_thetaiiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z9get_thetaiiPf, .-_Z9get_thetaiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "Erro ao escrever %s\n"
.LC2:
.string "P3\n%d %d\n255\n"
.LC4:
.string "%d %d %d "
.LC5:
.string "\n"
.text
.globl _Z8writePPMPKcPfS1_S1_
.type _Z8writePPMPKcPfS1_S1_, @function
_Z8writePPMPKcPfS1_S1_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %r15
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %r12
movl HEIGHTH(%rip), %r8d
movl WIDTHH(%rip), %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %ebp
cmpl $0, HEIGHTH(%rip)
jg .L10
.L11:
movq %r12, %rdi
call fclose@PLT
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L7
.L12:
addl $2, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movss (%r15,%rax,4), %xmm1
mulss .LC3(%rip), %xmm1
movss (%r14,%rax,4), %xmm0
mulss .LC3(%rip), %xmm0
movss 0(%r13,%rax,4), %xmm2
mulss .LC3(%rip), %xmm2
cvttss2sil %xmm2, %ecx
cvttss2sil %xmm1, %r9d
cvttss2sil %xmm0, %r8d
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl WIDTHH(%rip), %eax
cmpl %ebx, %eax
jge .L12
.L13:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, HEIGHTH(%rip)
jl .L11
.L10:
movl WIDTHH(%rip), %eax
movl $1, %ebx
testl %eax, %eax
jg .L12
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z8writePPMPKcPfS1_S1_, .-_Z8writePPMPKcPfS1_S1_
.section .rodata.str1.1
.LC6:
.string "rb"
.LC7:
.string "Erro ao abrir %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Erro: formato do PPM (P%c) nao suportado\n"
.section .rodata.str1.1
.LC9:
.string "%[^\n\r] "
.LC10:
.string "%d %d %d"
.text
.globl _Z7readPPMPKcPPfS2_S2_
.type _Z7readPPMPKcPPfS2_S2_, @function
_Z7readPPMPKcPPfS2_S2_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq .LC6(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L49
movq %rax, %r15
movq %rax, %rdi
call getc@PLT
movl %eax, %edx
andl $-33, %eax
cmpb $80, %al
je .L50
.L24:
cmpb $51, %dl
je .L25
movsbl %dl, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
.L21:
movq 184(%rsp), %rdx
subq %fs:40, %rdx
jne .L51
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L21
.L50:
movq %r15, %rdi
call getc@PLT
movl %eax, %edx
jmp .L24
.L25:
movq %r15, %rdi
call getc@PLT
cmpb $10, %al
je .L41
cmpb $13, %al
je .L41
.L26:
leaq 12(%rsp), %rbx
leaq 8(%rsp), %rbp
leaq 16(%rsp), %r8
movq %rbx, %rcx
movq %rbp, %rdx
leaq .LC10(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 8(%rsp), %eax
movl %eax, WIDTHH(%rip)
movl 12(%rsp), %eax
movl %eax, HEIGHTH(%rip)
leaq 32(%rsp), %rdi
leaq _ZL5WIDTH(%rip), %rsi
call cudaGetSymbolAddress@PLT
leaq 40(%rsp), %rdi
leaq _ZL6HEIGHT(%rip), %rsi
call cudaGetSymbolAddress@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %ebx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r12)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 0(%r13)
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r14)
movl $1, %ebp
cmpl $0, 12(%rsp)
jg .L30
.L31:
cmpl $-1, 8(%rsp)
jl .L34
movl $0, %edx
.L35:
movq (%r14), %rax
movl $0x00000000, (%rax,%rdx,4)
movq 0(%r13), %rax
movl $0x00000000, (%rax,%rdx,4)
movq (%r12), %rax
movl $0x00000000, (%rax,%rdx,4)
movl 12(%rsp), %eax
addl $1, %eax
movl 8(%rsp), %esi
leal 2(%rsi), %ecx
imull %ecx, %eax
addl %edx, %eax
cltq
movq (%r14), %rcx
movl $0x00000000, (%rcx,%rax,4)
movl 12(%rsp), %eax
addl $1, %eax
movl 8(%rsp), %edi
leal 2(%rdi), %ecx
imull %ecx, %eax
addl %edx, %eax
cltq
movq 0(%r13), %rcx
movl $0x00000000, (%rcx,%rax,4)
movl 12(%rsp), %eax
addl $1, %eax
movl 8(%rsp), %esi
leal 2(%rsi), %ecx
imull %ecx, %eax
addl %edx, %eax
cltq
movq (%r12), %rcx
movl $0x00000000, (%rcx,%rax,4)
addq $1, %rdx
leal -1(%rdx), %eax
cmpl %eax, 8(%rsp)
jge .L35
.L34:
cmpl $-1, 12(%rsp)
jl .L40
movl $0, %eax
.L36:
movl 8(%rsp), %edi
leal 2(%rdi), %edx
imull %eax, %edx
movslq %edx, %rdx
movq (%r14), %rcx
movl $0x00000000, (%rcx,%rdx,4)
movl 8(%rsp), %esi
leal 2(%rsi), %edx
imull %eax, %edx
movslq %edx, %rdx
movq 0(%r13), %rcx
movl $0x00000000, (%rcx,%rdx,4)
movl 8(%rsp), %edi
leal 2(%rdi), %edx
imull %eax, %edx
movslq %edx, %rdx
movq (%r12), %rcx
movl $0x00000000, (%rcx,%rdx,4)
movl 8(%rsp), %ecx
leal 2(%rcx), %edx
imull %eax, %edx
addl %ecx, %edx
movslq %edx, %rdx
movq (%r14), %rcx
movl $0x00000000, 4(%rcx,%rdx,4)
movl 8(%rsp), %ecx
leal 2(%rcx), %edx
imull %eax, %edx
addl %ecx, %edx
movslq %edx, %rdx
movq 0(%r13), %rcx
movl $0x00000000, 4(%rcx,%rdx,4)
movl 8(%rsp), %ecx
leal 2(%rcx), %edx
imull %eax, %edx
addl %ecx, %edx
movslq %edx, %rdx
movq (%r12), %rcx
movl $0x00000000, 4(%rcx,%rdx,4)
movl %eax, %edx
addl $1, %eax
cmpl %edx, 12(%rsp)
jge .L36
movl $1, %eax
jmp .L21
.L41:
movq %r15, %rdi
call getc@PLT
movl %eax, %edx
cmpb $35, %al
jne .L28
leaq .LC9(%rip), %rbx
.L29:
leaq 48(%rsp), %rdx
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r15, %rdi
call getc@PLT
movl %eax, %edx
cmpb $35, %al
je .L29
.L28:
movsbl %dl, %edi
movq %r15, %rsi
call ungetc@PLT
jmp .L26
.L32:
leaq 24(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq 28(%rsp), %r8
leaq .LC10(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 8(%rsp), %eax
addl $2, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movq (%r12), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 20(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl 16(%rsp), %xmm1
divss %xmm1, %xmm0
movss %xmm0, (%rdx,%rax,4)
movl 8(%rsp), %eax
addl $2, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movq 0(%r13), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 24(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl 16(%rsp), %xmm1
divss %xmm1, %xmm0
movss %xmm0, (%rdx,%rax,4)
movl 8(%rsp), %eax
addl $2, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movq (%r14), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl 16(%rsp), %xmm1
divss %xmm1, %xmm0
movss %xmm0, (%rdx,%rax,4)
addl $1, %ebx
cmpl %ebx, 8(%rsp)
jge .L32
.L33:
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jl .L31
.L30:
movl $1, %ebx
cmpl $0, 8(%rsp)
jg .L32
jmp .L33
.L40:
movl $1, %eax
jmp .L21
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7readPPMPKcPPfS2_S2_, .-_Z7readPPMPKcPPfS2_S2_
.globl _Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
.type _Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18calc_contributionsPfS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
.globl _Z18calc_contributionsPfS_S_S_S_S_S_
.type _Z18calc_contributionsPfS_S_S_S_S_S_, @function
_Z18calc_contributionsPfS_S_S_S_S_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z18calc_contributionsPfS_S_S_S_S_S_, .-_Z18calc_contributionsPfS_S_S_S_S_S_
.globl _Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
.type _Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15calc_componentsPfS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
.globl _Z15calc_componentsPfS_S_S_S_S_S_
.type _Z15calc_componentsPfS_S_S_S_S_S_, @function
_Z15calc_componentsPfS_S_S_S_S_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z15calc_componentsPfS_S_S_S_S_S_, .-_Z15calc_componentsPfS_S_S_S_S_S_
.globl _Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_
.type _Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_, @function
_Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17recalc_magnitudesPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_, .-_Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_
.globl _Z17recalc_magnitudesPfS_S_S_S_S_
.type _Z17recalc_magnitudesPfS_S_S_S_S_, @function
_Z17recalc_magnitudesPfS_S_S_S_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z17recalc_magnitudesPfS_S_S_S_S_, .-_Z17recalc_magnitudesPfS_S_S_S_S_
.globl _Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_
.type _Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_, @function
_Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L80
.L76:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L81
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6redistPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L76
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_, .-_Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_
.globl _Z6redistPfS_S_S_
.type _Z6redistPfS_S_S_, @function
_Z6redistPfS_S_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z6redistPfS_S_S_, .-_Z6redistPfS_S_S_
.globl _Z33__device_stub__Z11re_redist_wPfS_PfS_
.type _Z33__device_stub__Z11re_redist_wPfS_PfS_, @function
_Z33__device_stub__Z11re_redist_wPfS_PfS_:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L88
.L84:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L89
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L88:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11re_redist_wPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L84
.L89:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z33__device_stub__Z11re_redist_wPfS_PfS_, .-_Z33__device_stub__Z11re_redist_wPfS_PfS_
.globl _Z11re_redist_wPfS_
.type _Z11re_redist_wPfS_, @function
_Z11re_redist_wPfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11re_redist_wPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11re_redist_wPfS_, .-_Z11re_redist_wPfS_
.globl _Z33__device_stub__Z11re_redist_hPfS_PfS_
.type _Z33__device_stub__Z11re_redist_hPfS_PfS_, @function
_Z33__device_stub__Z11re_redist_hPfS_PfS_:
.LFB2097:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L96
.L92:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L97
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11re_redist_hPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L92
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z33__device_stub__Z11re_redist_hPfS_PfS_, .-_Z33__device_stub__Z11re_redist_hPfS_PfS_
.globl _Z11re_redist_hPfS_
.type _Z11re_redist_hPfS_, @function
_Z11re_redist_hPfS_:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11re_redist_hPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z11re_redist_hPfS_, .-_Z11re_redist_hPfS_
.globl _Z31__device_stub__Z8finalizePfS_S_PfS_S_
.type _Z31__device_stub__Z8finalizePfS_S_PfS_S_, @function
_Z31__device_stub__Z8finalizePfS_S_PfS_S_:
.LFB2099:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L104
.L100:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L105
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L104:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8finalizePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L100
.L105:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z31__device_stub__Z8finalizePfS_S_PfS_S_, .-_Z31__device_stub__Z8finalizePfS_S_PfS_S_
.globl _Z8finalizePfS_S_
.type _Z8finalizePfS_S_, @function
_Z8finalizePfS_S_:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8finalizePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z8finalizePfS_S_, .-_Z8finalizePfS_S_
.globl kernel_wrapper
.type kernel_wrapper, @function
kernel_wrapper:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r15
movq %r9, %r13
movl WIDTHH(%rip), %eax
movl %eax, 12(%rsp)
movl HEIGHTH(%rip), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L109:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L110:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L111:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L112:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl WIDTHH(%rip), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L121
.L113:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl HEIGHTH(%rip), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L114:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L123
.L108:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L117:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r13, %r9
movq %r15, %r8
movq %r12, %rcx
movq %rbp, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _Z47__device_stub__Z15calc_componentsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L109
.L118:
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r13, %r9
movq %r15, %r8
movq %r12, %rcx
movq %rbp, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _Z50__device_stub__Z18calc_contributionsPfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L110
.L119:
movq %rbp, %r9
movq %rbx, %r8
movq 112(%rsp), %rcx
movq %r13, %rdx
movq %r15, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z17recalc_magnitudesPfS_S_S_S_S_PfS_S_S_S_S_
jmp .L111
.L120:
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z6redistPfS_S_S_PfS_S_S_
jmp .L112
.L121:
movq %rbp, %rsi
movq %rbx, %rdi
call _Z33__device_stub__Z11re_redist_wPfS_PfS_
jmp .L113
.L122:
movq %rbp, %rsi
movq %rbx, %rdi
call _Z33__device_stub__Z11re_redist_hPfS_PfS_
jmp .L114
.L123:
movq %rbp, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z8finalizePfS_S_PfS_S_
jmp .L108
.cfi_endproc
.LFE2059:
.size kernel_wrapper, .-kernel_wrapper
.section .rodata.str1.1
.LC12:
.string "Uso:\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "%s entrada saida num_iters [num_procs]\n"
.align 8
.LC14:
.string "Nota: num_procs \303\251 ignorado pois usamos CUDA\n"
.section .rodata.str1.1
.LC15:
.string "Erro durante a leitura\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "Tempo total: %fs (tempo medio por iteracao: %fs)\n"
.align 8
.LC18:
.string "Nota: tempo nao inclui tempo de copia de/para a GPU\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L133
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, (%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
movq 8(%rbp), %rdi
call _Z7readPPMPKcPPfS2_S2_
testl %eax, %eax
je .L134
movq (%rsp), %rbx
movl %ebx, %r12d
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %esi
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movq 24(%rsp), %r13
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %r14
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %r15
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L128
movl $0, %ebx
.L129:
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq 104(%rsp)
.cfi_def_cfa_offset 192
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call kernel_wrapper
addl $1, %ebx
addq $16, %rsp
.cfi_def_cfa_offset 176
cmpl %r12d, %ebx
jne .L129
.L128:
call cudaDeviceSynchronize@PLT
call clock@PLT
movq %rax, %rbx
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl WIDTHH(%rip), %eax
leal 2(%rax), %edx
movl HEIGHTH(%rip), %eax
addl $2, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
subq %rax, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC16(%rip), %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl (%rsp), %xmm2
movaps %xmm0, %xmm1
divss %xmm2, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbp), %rdi
movq %r15, %rcx
movq %r14, %rdx
movq %r13, %rsi
call _Z8writePPMPKcPfS1_S1_
movl $0, %eax
.L124:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L135
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq 0(%rbp), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L124
.L134:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L124
.L135:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z8finalizePfS_S_"
.LC20:
.string "_Z11re_redist_hPfS_"
.LC21:
.string "_Z11re_redist_wPfS_"
.LC22:
.string "_Z6redistPfS_S_S_"
.section .rodata.str1.8
.align 8
.LC23:
.string "_Z17recalc_magnitudesPfS_S_S_S_S_"
.align 8
.LC24:
.string "_Z15calc_componentsPfS_S_S_S_S_S_"
.align 8
.LC25:
.string "_Z18calc_contributionsPfS_S_S_S_S_S_"
.section .rodata.str1.1
.LC26:
.string "WIDTH"
.LC27:
.string "HEIGHT"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8finalizePfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z11re_redist_hPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z11re_redist_wPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z6redistPfS_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z17recalc_magnitudesPfS_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calc_componentsPfS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calc_contributionsPfS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5WIDTH(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6HEIGHT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl HEIGHTH
.bss
.align 4
.type HEIGHTH, @object
.size HEIGHTH, 4
HEIGHTH:
.zero 4
.globl WIDTHH
.align 4
.type WIDTHH, @object
.size WIDTHH, 4
WIDTHH:
.zero 4
.local _ZL6HEIGHT
.comm _ZL6HEIGHT,4,4
.local _ZL5WIDTH
.comm _ZL5WIDTH,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1132396544
.align 4
.LC16:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* MAC0431 - Introducao a Programacao Paralela e Distribuida
*
* Fisica Alternativa
*
* Bruno Endo - 7990982
* Danilo Aleixo - 7972370
* Gustavo Caparica - 7991020
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__constant__ int WIDTH, HEIGHT;
int WIDTHH, HEIGHTH;
#define SIZE (WIDTH*HEIGHT)
#define SIZEH (WIDTHH*HEIGHTH)
#define BORDERW (WIDTH+2)
#define BORDERH (HEIGHT+2)
#define FAKE_SIZE (BORDERW*BORDERH)
#define FAKE_SIZEH ((WIDTHH+2)*(HEIGHTH+2))
#define MAXLINE 128
#define PI acosf(-1)
__device__ void get_components(int x, int y, float theta, float *V, float *outx, float *outy) {
*outx = V[y*BORDERW + x]*sinf(theta);
*outy = V[y*BORDERW + x]*cosf(theta);
}
__device__ float get_theta(int x, int y, float *V) {
return V[y*BORDERW + x]*2*PI;
}
__global__ void calc_contributions(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float theta = get_theta(x, y, G);
float contribRx, contribRy;
get_components(x, y, theta, R, &contribRx, &contribRy);
float contribBx, contribBy;
get_components(x, y, theta, B, &contribBx, &contribBy);
contribBx *= -1;
contribBy *= -1;
int xx = 0;
int yy = 0;
if (contribRx > 0) {
xx = 1;
} else {
xx = -1;
}
if (contribRy > 0) {
yy = 1;
} else {
yy = -1;
}
float deltaRx = (1 - R[y*BORDERW + (x + xx)])*contribRx/4.0;
float deltaRy = (1 - R[(y + yy)*BORDERW + x])*contribRy/4.0;
float deltaBx = (1 - B[y*BORDERW + (x - xx)])*contribBx/4.0;
float deltaBy = (1 - B[(y - yy)*BORDERW + x])*contribBy/4.0;
if (xx != 0) {
atomicAdd(&Rx[y*BORDERW + (x + xx)], deltaRx);
atomicAdd(&Rx[y*BORDERW + x], -deltaRx);
atomicAdd(&Bx[y*BORDERW + (x - xx)], deltaBx);
atomicAdd(&Bx[y*BORDERW + x], -deltaBx);
}
if (yy != 0) {
atomicAdd(&Ry[(y + yy)*BORDERW + x], deltaRy);
atomicAdd(&Ry[y*BORDERW + x], -deltaRy);
atomicAdd(&By[(y - yy)*BORDERW + x], deltaBy);
atomicAdd(&By[y*BORDERW + x], -deltaBy);
}
}
__global__ void calc_components(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
get_components(x, y, get_theta(x, y, R), R, &Rx[y*BORDERW + x], &Ry[y*BORDERW + x]);
get_components(x, y, get_theta(x, y, B), B, &Bx[y*BORDERW + x], &By[y*BORDERW + x]);
Bx[y*BORDERW + x] *= -1;
By[y*BORDERW + x] *= -1;
}
__global__ void recalc_magnitudes(float *Rx, float *Ry, float *Bx, float *By, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float rx = Rx[y*BORDERW + x];
float ry = Ry[y*BORDERW + x];
float r = sqrtf((rx*rx)+(ry*ry));
R[y*BORDERW + x] = r;
float bx = Bx[y*BORDERW + x];
float by = By[y*BORDERW + x];
float b = sqrtf((bx*bx)+(by*by));
B[y*BORDERW + x] = b;
Rx[y*BORDERW + x] = r;
Bx[y*BORDERW + x] = b;
}
__global__ void redist(float *nR, float *nB, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) {
float tmp = 1 - R[y*BORDERW + x];
nR[y*BORDERW + x] = 1;
atomicAdd(&nR[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nR[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nR[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nR[(y-1)*BORDERW + x], tmp/4);
}
if (B[y*BORDERW + x] > 1) {
float tmp = 1 - B[y*BORDERW + x];
nB[y*BORDERW + x] = 1;
atomicAdd(&nB[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nB[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nB[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nB[(y-1)*BORDERW + x], tmp/4);
}
}
__global__ void re_redist_w(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x + BORDERW], R[x]);
atomicAdd(&R[FAKE_SIZE - 1 - x - BORDERW], R[FAKE_SIZE - 1 - x]);
atomicAdd(&B[x + BORDERW], B[x]);
atomicAdd(&B[FAKE_SIZE - 1 - x - BORDERW], B[FAKE_SIZE - 1 - x]);
R[x] = 0;
R[FAKE_SIZE - 1 - x] = 0;
B[x] = 0;
B[FAKE_SIZE - 1 - x] = 0;
}
__global__ void re_redist_h(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x * BORDERW + 1], R[x * BORDERW]);
atomicAdd(&R[x * BORDERW + BORDERW - 2], R[x * BORDERW + BORDERW - 1]);
atomicAdd(&B[x * BORDERW + 1], B[x * BORDERW]);
atomicAdd(&B[x * BORDERW + BORDERW - 2], B[x * BORDERW + BORDERW - 1]);
R[x * BORDERW] = 0;
R[x * BORDERW + BORDERW - 1] = 0;
B[x * BORDERW] = 0;
B[x * BORDERW + BORDERW - 1] = 0;
}
__global__ void finalize(float *R, float *G, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) R[y*BORDERW + x] = 1;
if (B[y*BORDERW + x] > 1) B[y*BORDERW + x] = 1;
if (R[y*BORDERW + x] < 0) R[y*BORDERW + x] = 0;
if (B[y*BORDERW + x] < 0) B[y*BORDERW + x] = 0;
atomicAdd(&G[y*BORDERW + x], atan2f(B[y*BORDERW + x], R[y*BORDERW + x])/(2*PI));
if (G[y*BORDERW + x] > 1) G[y*BORDERW + x] = 0;
if (G[y*BORDERW + x] < 0) G[y*BORDERW + x] = 0;
}
// the wrapper around the kernel call for main program to call.
extern "C" void kernel_wrapper(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
dim3 image_size(WIDTHH, HEIGHTH);
calc_components<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(cudaGetLastError() == cudaSuccess);
calc_contributions<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(cudaGetLastError() == cudaSuccess);
recalc_magnitudes<<<image_size, 1>>>(Rx, Ry, Bx, By, R, B);
assert(cudaGetLastError() == cudaSuccess);
redist<<<image_size, 1>>>(R, B, Rx, Bx);
assert(cudaGetLastError() == cudaSuccess);
re_redist_w<<<WIDTHH, 1>>>(R, B);
assert(cudaGetLastError() == cudaSuccess);
re_redist_h<<<HEIGHTH, 1>>>(R, B);
assert(cudaGetLastError() == cudaSuccess);
finalize<<<image_size, 1>>>(R, G, B);
assert(cudaGetLastError() == cudaSuccess);
}
void writePPM(const char* file, float *R, float *G, float *B) {
FILE *fp = fopen(file, "w");
if (fp == NULL) {
fprintf(stderr, "Erro ao escrever %s\n", file);
return;
}
fprintf(fp, "P3\n%d %d\n255\n", WIDTHH, HEIGHTH);
for (int i = 1; i <= HEIGHTH; i++) {
for (int j = 1; j <= WIDTHH; j++) {
int idx = i*(WIDTHH+2) + j;
fprintf(fp, "%d %d %d ", (int)(R[idx]*255), (int)(G[idx]*255), (int)(B[idx]*255));
}
fprintf(fp, "\n");
}
fclose(fp);
}
int readPPM(const char* file, float **R, float **G, float **B) {
FILE *fp = fopen(file, "rb");
if (fp == NULL) {
fprintf(stderr, "Erro ao abrir %s\n", file);
return 0;
}
int w, h, k;
int red, green, blue;
int *gw, *gh;
char c;
char tmp[MAXLINE];
c = getc(fp);
if (c == 'P' || c == 'p') {
c = getc(fp);
}
if (c != '3') {
fprintf(stderr, "Erro: formato do PPM (P%c) nao suportado\n", c);
return 0;
}
c = getc(fp);
if (c == '\n' || c == '\r') {
c = getc(fp);
while(c == '#') {
fscanf(fp, "%[^\n\r] ", tmp);
c = getc(fp);
}
ungetc(c,fp);
}
fscanf(fp, "%d %d %d", &w, &h, &k);
WIDTHH = w;
HEIGHTH = h;
cudaGetSymbolAddress((void**)&gw, WIDTH);
assert(cudaGetLastError() == cudaSuccess);
cudaGetSymbolAddress((void**)&gh, HEIGHT);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gw, &w, sizeof(int), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gh, &h, sizeof(int), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
*R = (float*)malloc(FAKE_SIZEH*sizeof(float));
*G = (float*)malloc(FAKE_SIZEH*sizeof(float));
*B = (float*)malloc(FAKE_SIZEH*sizeof(float));
for (int i = 1; i <= h; i++) {
for (int j = 1; j <= w; j++) {
fscanf(fp, "%d %d %d", &red, &green, &blue );
(*R)[i*(w+2) + j] = (float)red/(float)k;
(*G)[i*(w+2) + j] = (float)green/(float)k;
(*B)[i*(w+2) + j] = (float)blue/(float)k;
}
}
for (int i = 0; i < w + 2; i++) {
(*R)[i] = (*G)[i] = (*B)[i] = 0;
(*R)[(h+1)*(w+2) + i] = (*G)[(h+1)*(w+2) + i] = (*B)[(h+1)*(w+2) + i] = 0;
}
for (int i = 0; i < h + 2; i++) {
(*R)[i*(w+2)] = (*G)[i*(w+2)] = (*B)[i*(w+2)] = 0;
(*R)[i*(w+2) + w + 1] = (*G)[i*(w+2) + w + 1] = (*B)[i*(w+2) + w + 1] = 0;
}
return 1;
}
int main(int argc, char const *argv[]) {
if (argc < 4) {
printf("Uso:\n");
printf("%s entrada saida num_iters [num_procs]\n", argv[0]);
printf("Nota: num_procs é ignorado pois usamos CUDA\n");
return 0;
}
int iters = atoi(argv[3]);
srand(time(NULL));
float *R, *G, *B, *gR, *gG, *gB, *nR, *nG, *nB, *nN;
if (!readPPM(argv[1], &R, &G, &B)) {
fprintf(stderr, "Erro durante a leitura\n");
return 1;
}
cudaMalloc((void**)&gR, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&gG, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&gB, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nR, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nG, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nB, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMalloc((void**)&nN, FAKE_SIZEH*sizeof(float));
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gR, R, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gG, G, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(gB, B, FAKE_SIZEH*sizeof(float), cudaMemcpyHostToDevice);
assert(cudaGetLastError() == cudaSuccess);
clock_t start, stop;
start = clock();
for(int i = 0; i < iters; i++) {
kernel_wrapper(gR, gG, gB, nR, nG, nB, nN);
}
cudaDeviceSynchronize();
stop = clock();
cudaMemcpy(R, gR, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(G, gG, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
cudaMemcpy(B, gB, FAKE_SIZEH*sizeof(float), cudaMemcpyDeviceToHost);
assert(cudaGetLastError() == cudaSuccess);
float tempo = (float)(stop - start) / CLOCKS_PER_SEC;
printf("Tempo total: %fs (tempo medio por iteracao: %fs)\n", tempo, tempo/iters);
printf("Nota: tempo nao inclui tempo de copia de/para a GPU\n");
writePPM(argv[2], R, G, B);
return 0;
} | /*
* MAC0431 - Introducao a Programacao Paralela e Distribuida
*
* Fisica Alternativa
*
* Bruno Endo - 7990982
* Danilo Aleixo - 7972370
* Gustavo Caparica - 7991020
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <hip/hip_runtime.h>
__constant__ int WIDTH, HEIGHT;
int WIDTHH, HEIGHTH;
#define SIZE (WIDTH*HEIGHT)
#define SIZEH (WIDTHH*HEIGHTH)
#define BORDERW (WIDTH+2)
#define BORDERH (HEIGHT+2)
#define FAKE_SIZE (BORDERW*BORDERH)
#define FAKE_SIZEH ((WIDTHH+2)*(HEIGHTH+2))
#define MAXLINE 128
#define PI acosf(-1)
__device__ void get_components(int x, int y, float theta, float *V, float *outx, float *outy) {
*outx = V[y*BORDERW + x]*sinf(theta);
*outy = V[y*BORDERW + x]*cosf(theta);
}
__device__ float get_theta(int x, int y, float *V) {
return V[y*BORDERW + x]*2*PI;
}
__global__ void calc_contributions(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float theta = get_theta(x, y, G);
float contribRx, contribRy;
get_components(x, y, theta, R, &contribRx, &contribRy);
float contribBx, contribBy;
get_components(x, y, theta, B, &contribBx, &contribBy);
contribBx *= -1;
contribBy *= -1;
int xx = 0;
int yy = 0;
if (contribRx > 0) {
xx = 1;
} else {
xx = -1;
}
if (contribRy > 0) {
yy = 1;
} else {
yy = -1;
}
float deltaRx = (1 - R[y*BORDERW + (x + xx)])*contribRx/4.0;
float deltaRy = (1 - R[(y + yy)*BORDERW + x])*contribRy/4.0;
float deltaBx = (1 - B[y*BORDERW + (x - xx)])*contribBx/4.0;
float deltaBy = (1 - B[(y - yy)*BORDERW + x])*contribBy/4.0;
if (xx != 0) {
atomicAdd(&Rx[y*BORDERW + (x + xx)], deltaRx);
atomicAdd(&Rx[y*BORDERW + x], -deltaRx);
atomicAdd(&Bx[y*BORDERW + (x - xx)], deltaBx);
atomicAdd(&Bx[y*BORDERW + x], -deltaBx);
}
if (yy != 0) {
atomicAdd(&Ry[(y + yy)*BORDERW + x], deltaRy);
atomicAdd(&Ry[y*BORDERW + x], -deltaRy);
atomicAdd(&By[(y - yy)*BORDERW + x], deltaBy);
atomicAdd(&By[y*BORDERW + x], -deltaBy);
}
}
__global__ void calc_components(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
get_components(x, y, get_theta(x, y, R), R, &Rx[y*BORDERW + x], &Ry[y*BORDERW + x]);
get_components(x, y, get_theta(x, y, B), B, &Bx[y*BORDERW + x], &By[y*BORDERW + x]);
Bx[y*BORDERW + x] *= -1;
By[y*BORDERW + x] *= -1;
}
__global__ void recalc_magnitudes(float *Rx, float *Ry, float *Bx, float *By, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
float rx = Rx[y*BORDERW + x];
float ry = Ry[y*BORDERW + x];
float r = sqrtf((rx*rx)+(ry*ry));
R[y*BORDERW + x] = r;
float bx = Bx[y*BORDERW + x];
float by = By[y*BORDERW + x];
float b = sqrtf((bx*bx)+(by*by));
B[y*BORDERW + x] = b;
Rx[y*BORDERW + x] = r;
Bx[y*BORDERW + x] = b;
}
__global__ void redist(float *nR, float *nB, float *R, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) {
float tmp = 1 - R[y*BORDERW + x];
nR[y*BORDERW + x] = 1;
atomicAdd(&nR[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nR[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nR[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nR[(y-1)*BORDERW + x], tmp/4);
}
if (B[y*BORDERW + x] > 1) {
float tmp = 1 - B[y*BORDERW + x];
nB[y*BORDERW + x] = 1;
atomicAdd(&nB[y*BORDERW + x + 1], tmp/4);
atomicAdd(&nB[y*BORDERW + x - 1], tmp/4);
atomicAdd(&nB[(y+1)*BORDERW + x], tmp/4);
atomicAdd(&nB[(y-1)*BORDERW + x], tmp/4);
}
}
__global__ void re_redist_w(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x + BORDERW], R[x]);
atomicAdd(&R[FAKE_SIZE - 1 - x - BORDERW], R[FAKE_SIZE - 1 - x]);
atomicAdd(&B[x + BORDERW], B[x]);
atomicAdd(&B[FAKE_SIZE - 1 - x - BORDERW], B[FAKE_SIZE - 1 - x]);
R[x] = 0;
R[FAKE_SIZE - 1 - x] = 0;
B[x] = 0;
B[FAKE_SIZE - 1 - x] = 0;
}
__global__ void re_redist_h(float *R, float *B) {
int x = blockIdx.x + 1;
atomicAdd(&R[x * BORDERW + 1], R[x * BORDERW]);
atomicAdd(&R[x * BORDERW + BORDERW - 2], R[x * BORDERW + BORDERW - 1]);
atomicAdd(&B[x * BORDERW + 1], B[x * BORDERW]);
atomicAdd(&B[x * BORDERW + BORDERW - 2], B[x * BORDERW + BORDERW - 1]);
R[x * BORDERW] = 0;
R[x * BORDERW + BORDERW - 1] = 0;
B[x * BORDERW] = 0;
B[x * BORDERW + BORDERW - 1] = 0;
}
__global__ void finalize(float *R, float *G, float *B) {
int x = blockIdx.x + 1;
int y = blockIdx.y + 1;
if (R[y*BORDERW + x] > 1) R[y*BORDERW + x] = 1;
if (B[y*BORDERW + x] > 1) B[y*BORDERW + x] = 1;
if (R[y*BORDERW + x] < 0) R[y*BORDERW + x] = 0;
if (B[y*BORDERW + x] < 0) B[y*BORDERW + x] = 0;
atomicAdd(&G[y*BORDERW + x], atan2f(B[y*BORDERW + x], R[y*BORDERW + x])/(2*PI));
if (G[y*BORDERW + x] > 1) G[y*BORDERW + x] = 0;
if (G[y*BORDERW + x] < 0) G[y*BORDERW + x] = 0;
}
// the wrapper around the kernel call for main program to call.
extern "C" void kernel_wrapper(float *R, float *G, float *B, float *Rx, float *Ry, float *Bx, float *By) {
dim3 image_size(WIDTHH, HEIGHTH);
calc_components<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(hipGetLastError() == hipSuccess);
calc_contributions<<<image_size, 1>>>(R, G, B, Rx, Ry, Bx, By);
assert(hipGetLastError() == hipSuccess);
recalc_magnitudes<<<image_size, 1>>>(Rx, Ry, Bx, By, R, B);
assert(hipGetLastError() == hipSuccess);
redist<<<image_size, 1>>>(R, B, Rx, Bx);
assert(hipGetLastError() == hipSuccess);
re_redist_w<<<WIDTHH, 1>>>(R, B);
assert(hipGetLastError() == hipSuccess);
re_redist_h<<<HEIGHTH, 1>>>(R, B);
assert(hipGetLastError() == hipSuccess);
finalize<<<image_size, 1>>>(R, G, B);
assert(hipGetLastError() == hipSuccess);
}
void writePPM(const char* file, float *R, float *G, float *B) {
FILE *fp = fopen(file, "w");
if (fp == NULL) {
fprintf(stderr, "Erro ao escrever %s\n", file);
return;
}
fprintf(fp, "P3\n%d %d\n255\n", WIDTHH, HEIGHTH);
for (int i = 1; i <= HEIGHTH; i++) {
for (int j = 1; j <= WIDTHH; j++) {
int idx = i*(WIDTHH+2) + j;
fprintf(fp, "%d %d %d ", (int)(R[idx]*255), (int)(G[idx]*255), (int)(B[idx]*255));
}
fprintf(fp, "\n");
}
fclose(fp);
}
int readPPM(const char* file, float **R, float **G, float **B) {
FILE *fp = fopen(file, "rb");
if (fp == NULL) {
fprintf(stderr, "Erro ao abrir %s\n", file);
return 0;
}
int w, h, k;
int red, green, blue;
int *gw, *gh;
char c;
char tmp[MAXLINE];
c = getc(fp);
if (c == 'P' || c == 'p') {
c = getc(fp);
}
if (c != '3') {
fprintf(stderr, "Erro: formato do PPM (P%c) nao suportado\n", c);
return 0;
}
c = getc(fp);
if (c == '\n' || c == '\r') {
c = getc(fp);
while(c == '#') {
fscanf(fp, "%[^\n\r] ", tmp);
c = getc(fp);
}
ungetc(c,fp);
}
fscanf(fp, "%d %d %d", &w, &h, &k);
WIDTHH = w;
HEIGHTH = h;
hipGetSymbolAddress((void**)&gw, HIP_SYMBOL(WIDTH));
assert(hipGetLastError() == hipSuccess);
hipGetSymbolAddress((void**)&gh, HIP_SYMBOL(HEIGHT));
assert(hipGetLastError() == hipSuccess);
hipMemcpy(gw, &w, sizeof(int), hipMemcpyHostToDevice);
assert(hipGetLastError() == hipSuccess);
hipMemcpy(gh, &h, sizeof(int), hipMemcpyHostToDevice);
assert(hipGetLastError() == hipSuccess);
*R = (float*)malloc(FAKE_SIZEH*sizeof(float));
*G = (float*)malloc(FAKE_SIZEH*sizeof(float));
*B = (float*)malloc(FAKE_SIZEH*sizeof(float));
for (int i = 1; i <= h; i++) {
for (int j = 1; j <= w; j++) {
fscanf(fp, "%d %d %d", &red, &green, &blue );
(*R)[i*(w+2) + j] = (float)red/(float)k;
(*G)[i*(w+2) + j] = (float)green/(float)k;
(*B)[i*(w+2) + j] = (float)blue/(float)k;
}
}
for (int i = 0; i < w + 2; i++) {
(*R)[i] = (*G)[i] = (*B)[i] = 0;
(*R)[(h+1)*(w+2) + i] = (*G)[(h+1)*(w+2) + i] = (*B)[(h+1)*(w+2) + i] = 0;
}
for (int i = 0; i < h + 2; i++) {
(*R)[i*(w+2)] = (*G)[i*(w+2)] = (*B)[i*(w+2)] = 0;
(*R)[i*(w+2) + w + 1] = (*G)[i*(w+2) + w + 1] = (*B)[i*(w+2) + w + 1] = 0;
}
return 1;
}
int main(int argc, char const *argv[]) {
if (argc < 4) {
printf("Uso:\n");
printf("%s entrada saida num_iters [num_procs]\n", argv[0]);
printf("Nota: num_procs é ignorado pois usamos CUDA\n");
return 0;
}
int iters = atoi(argv[3]);
srand(time(NULL));
float *R, *G, *B, *gR, *gG, *gB, *nR, *nG, *nB, *nN;
if (!readPPM(argv[1], &R, &G, &B)) {
fprintf(stderr, "Erro durante a leitura\n");
return 1;
}
hipMalloc((void**)&gR, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&gG, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&gB, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&nR, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&nG, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&nB, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMalloc((void**)&nN, FAKE_SIZEH*sizeof(float));
assert(hipGetLastError() == hipSuccess);
hipMemcpy(gR, R, FAKE_SIZEH*sizeof(float), hipMemcpyHostToDevice);
assert(hipGetLastError() == hipSuccess);
hipMemcpy(gG, G, FAKE_SIZEH*sizeof(float), hipMemcpyHostToDevice);
assert(hipGetLastError() == hipSuccess);
hipMemcpy(gB, B, FAKE_SIZEH*sizeof(float), hipMemcpyHostToDevice);
assert(hipGetLastError() == hipSuccess);
clock_t start, stop;
start = clock();
for(int i = 0; i < iters; i++) {
kernel_wrapper(gR, gG, gB, nR, nG, nB, nN);
}
hipDeviceSynchronize();
stop = clock();
hipMemcpy(R, gR, FAKE_SIZEH*sizeof(float), hipMemcpyDeviceToHost);
assert(hipGetLastError() == hipSuccess);
hipMemcpy(G, gG, FAKE_SIZEH*sizeof(float), hipMemcpyDeviceToHost);
assert(hipGetLastError() == hipSuccess);
hipMemcpy(B, gB, FAKE_SIZEH*sizeof(float), hipMemcpyDeviceToHost);
assert(hipGetLastError() == hipSuccess);
float tempo = (float)(stop - start) / CLOCKS_PER_SEC;
printf("Tempo total: %fs (tempo medio por iteracao: %fs)\n", tempo, tempo/iters);
printf("Nota: tempo nao inclui tempo de copia de/para a GPU\n");
writePPM(argv[2], R, G, B);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "max_reduction.cuh"
int* arr;
static void generate_integers(const int ARR_SIZE);
static int sequential(const int ARR_SIZE);
int main(int argc, char* argv[]) {
if (argc != 2 && argc != 3) {
fprintf(stderr, "Usage: %s BLOCK_SIZE [ARRAY_SIZE]\n", argv[0]);
return 1;
}
const int BLOCK_SIZE = atoi(argv[1]);
const int ARR_SIZE = (argc == 3 ? atoi(argv[2]) : DEF_ARR_SIZE);
generate_integers(ARR_SIZE);
sequential(ARR_SIZE);
reduction_divergent(arr, ARR_SIZE);
reduction_opt_1(arr, ARR_SIZE);
reduction_opt_2(arr, ARR_SIZE, BLOCK_SIZE);
free(arr);
return 0;
}
static void generate_integers(const int ARR_SIZE) {
if ((arr = (int*) malloc(sizeof(int) * ARR_SIZE)) == NULL) {
fprintf(stderr, "Error while allocating memory\n");
exit(1);
}
srand(time(NULL));
for (int i = 0; i < ARR_SIZE; i++) {
arr[i] = rand();
}
}
static int sequential(const int ARR_SIZE) {
double start, end;
GET_TIME(start);
int mx = arr[0];
for (int i = 1; i < ARR_SIZE; i++) {
mx = max(mx, arr[i]);
}
GET_TIME(end);
printf("[reduction_sequential]\tMaximum: %d\tTime: %fs\n", mx, end - start);
return mx;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "max_reduction.cuh"
int* arr;
static void generate_integers(const int ARR_SIZE);
static int sequential(const int ARR_SIZE);
int main(int argc, char* argv[]) {
if (argc != 2 && argc != 3) {
fprintf(stderr, "Usage: %s BLOCK_SIZE [ARRAY_SIZE]\n", argv[0]);
return 1;
}
const int BLOCK_SIZE = atoi(argv[1]);
const int ARR_SIZE = (argc == 3 ? atoi(argv[2]) : DEF_ARR_SIZE);
generate_integers(ARR_SIZE);
sequential(ARR_SIZE);
reduction_divergent(arr, ARR_SIZE);
reduction_opt_1(arr, ARR_SIZE);
reduction_opt_2(arr, ARR_SIZE, BLOCK_SIZE);
free(arr);
return 0;
}
static void generate_integers(const int ARR_SIZE) {
if ((arr = (int*) malloc(sizeof(int) * ARR_SIZE)) == NULL) {
fprintf(stderr, "Error while allocating memory\n");
exit(1);
}
srand(time(NULL));
for (int i = 0; i < ARR_SIZE; i++) {
arr[i] = rand();
}
}
static int sequential(const int ARR_SIZE) {
double start, end;
GET_TIME(start);
int mx = arr[0];
for (int i = 1; i < ARR_SIZE; i++) {
mx = max(mx, arr[i]);
}
GET_TIME(end);
printf("[reduction_sequential]\tMaximum: %d\tTime: %fs\n", mx, end - start);
return mx;
} | .file "tmpxft_00171398_00000000-6_max_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s BLOCK_SIZE [ARRAY_SIZE]\n"
.align 8
.LC1:
.string "Error while allocating memory\n"
.align 8
.LC3:
.string "[reduction_sequential]\tMaximum: %d\tTime: %fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal -2(%rdi), %eax
cmpl $1, %eax
ja .L20
movl %edi, %ebx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
cmpl $3, %ebx
je .L21
movl $40000, %edi
call malloc@PLT
movq %rax, arr(%rip)
testq %rax, %rax
je .L13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %r14d
movl $10000, %ebp
.L12:
movl $0, %ebx
.L9:
movq %rbx, %r13
addq arr(%rip), %r13
call rand@PLT
movl %eax, 0(%r13)
addq $4, %rbx
cmpq %r14, %rbx
jne .L9
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movq arr(%rip), %rdx
movl (%rdx), %ebx
cmpl $1, %ebp
jle .L10
leaq 4(%rdx), %rax
leal -2(%rbp), %ecx
leaq 8(%rdx,%rcx,4), %rcx
.L11:
movl (%rax), %edx
cmpl %edx, %ebx
cmovl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L11
.L10:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z19reduction_divergentPKii@PLT
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z15reduction_opt_1PKii@PLT
movl %r12d, %edx
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z15reduction_opt_2PKiii@PLT
movq arr(%rip), %rdi
call free@PLT
movl $0, %eax
.L3:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L22
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L21:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movslq %eax, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, arr(%rip)
testq %rax, %rax
je .L13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jg .L12
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movq arr(%rip), %rax
movl (%rax), %ebx
jmp .L10
.L13:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl arr
.bss
.align 8
.type arr, @object
.size arr, 8
arr:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "max_reduction.cuh"
int* arr;
static void generate_integers(const int ARR_SIZE);
static int sequential(const int ARR_SIZE);
int main(int argc, char* argv[]) {
if (argc != 2 && argc != 3) {
fprintf(stderr, "Usage: %s BLOCK_SIZE [ARRAY_SIZE]\n", argv[0]);
return 1;
}
const int BLOCK_SIZE = atoi(argv[1]);
const int ARR_SIZE = (argc == 3 ? atoi(argv[2]) : DEF_ARR_SIZE);
generate_integers(ARR_SIZE);
sequential(ARR_SIZE);
reduction_divergent(arr, ARR_SIZE);
reduction_opt_1(arr, ARR_SIZE);
reduction_opt_2(arr, ARR_SIZE, BLOCK_SIZE);
free(arr);
return 0;
}
static void generate_integers(const int ARR_SIZE) {
if ((arr = (int*) malloc(sizeof(int) * ARR_SIZE)) == NULL) {
fprintf(stderr, "Error while allocating memory\n");
exit(1);
}
srand(time(NULL));
for (int i = 0; i < ARR_SIZE; i++) {
arr[i] = rand();
}
}
static int sequential(const int ARR_SIZE) {
double start, end;
GET_TIME(start);
int mx = arr[0];
for (int i = 1; i < ARR_SIZE; i++) {
mx = max(mx, arr[i]);
}
GET_TIME(end);
printf("[reduction_sequential]\tMaximum: %d\tTime: %fs\n", mx, end - start);
return mx;
} | #ifndef _MAX_REDUCTION_CUH_INCLUDED_
#define _MAX_REDUCTION_CUH_INCLUDED_
#include <sys/time.h>
#define GET_TIME(now) \
{ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec + t.tv_usec / 1000000.0; \
}
#define DEF_ARR_SIZE 10000
#define DEF_BLOCK_SIZE 512
__host__ void reduction_divergent(const int* arr, const int n);
__host__ void reduction_opt_1(const int* arr, const int n);
__host__ void reduction_opt_2(const int* arr, const int n,
const int BLOCK_SIZE);
#endif /* _MAX_REDUCTION_CUH_INCLUDED_ */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef _MAX_REDUCTION_CUH_INCLUDED_
#define _MAX_REDUCTION_CUH_INCLUDED_
#include <sys/time.h>
#define GET_TIME(now) \
{ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec + t.tv_usec / 1000000.0; \
}
#define DEF_ARR_SIZE 10000
#define DEF_BLOCK_SIZE 512
__host__ void reduction_divergent(const int* arr, const int n);
__host__ void reduction_opt_1(const int* arr, const int n);
__host__ void reduction_opt_2(const int* arr, const int n,
const int BLOCK_SIZE);
#endif /* _MAX_REDUCTION_CUH_INCLUDED_ */ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef _MAX_REDUCTION_CUH_INCLUDED_
#define _MAX_REDUCTION_CUH_INCLUDED_
#include <sys/time.h>
#define GET_TIME(now) \
{ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec + t.tv_usec / 1000000.0; \
}
#define DEF_ARR_SIZE 10000
#define DEF_BLOCK_SIZE 512
__host__ void reduction_divergent(const int* arr, const int n);
__host__ void reduction_opt_1(const int* arr, const int n);
__host__ void reduction_opt_2(const int* arr, const int n,
const int BLOCK_SIZE);
#endif /* _MAX_REDUCTION_CUH_INCLUDED_ */ | .text
.file "max_reduction.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00171398_00000000-6_max_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s BLOCK_SIZE [ARRAY_SIZE]\n"
.align 8
.LC1:
.string "Error while allocating memory\n"
.align 8
.LC3:
.string "[reduction_sequential]\tMaximum: %d\tTime: %fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal -2(%rdi), %eax
cmpl $1, %eax
ja .L20
movl %edi, %ebx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
cmpl $3, %ebx
je .L21
movl $40000, %edi
call malloc@PLT
movq %rax, arr(%rip)
testq %rax, %rax
je .L13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %r14d
movl $10000, %ebp
.L12:
movl $0, %ebx
.L9:
movq %rbx, %r13
addq arr(%rip), %r13
call rand@PLT
movl %eax, 0(%r13)
addq $4, %rbx
cmpq %r14, %rbx
jne .L9
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movq arr(%rip), %rdx
movl (%rdx), %ebx
cmpl $1, %ebp
jle .L10
leaq 4(%rdx), %rax
leal -2(%rbp), %ecx
leaq 8(%rdx,%rcx,4), %rcx
.L11:
movl (%rax), %edx
cmpl %edx, %ebx
cmovl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L11
.L10:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z19reduction_divergentPKii@PLT
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z15reduction_opt_1PKii@PLT
movl %r12d, %edx
movl %ebp, %esi
movq arr(%rip), %rdi
call _Z15reduction_opt_2PKiii@PLT
movq arr(%rip), %rdi
call free@PLT
movl $0, %eax
.L3:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L22
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L21:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movslq %eax, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, arr(%rip)
testq %rax, %rax
je .L13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jg .L12
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movq arr(%rip), %rax
movl (%rax), %ebx
jmp .L10
.L13:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl arr
.bss
.align 8
.type arr, @object
.size arr, 8
arr:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_reduction.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sum_optimization(float* in, int inStr0, int inStr1, int inStr2, int inStr3, float* out, int outStr0, int outStr1, int outStr2, int dim, int nElementOut, int dimSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = tid; i < nElementOut; i += stride) {
int outOff0 = i / outStr0;
int outOff1temp = i - outOff0 * outStr0;
int outOff1 = outOff1temp / outStr1;
int outOff2 = outOff1temp - outOff1 * outStr1;
for (int j = 0; j < dimSize; j++) {
int inOff;
if (dim == 0) inOff = j * inStr0 + outOff0 * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 1) inOff = outOff0 * inStr0 + j * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 2) inOff = outOff0 * inStr0 + outOff1 * inStr1 + j * inStr2 + outOff2 * inStr3;
if (dim == 3) inOff = outOff0 * inStr0 + outOff1 * inStr1 + outOff2 * inStr2 + j * inStr3;
out[i] += in[inOff];
}
}
} | .file "tmpxft_00032e17_00000000-6_sum_optimization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
.type _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii, @function
_Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 232
pushq 40(%rsp)
.cfi_def_cfa_offset 240
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sum_optimizationPfiiiiS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii, .-_Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
.globl _Z16sum_optimizationPfiiiiS_iiiiii
.type _Z16sum_optimizationPfiiiiS_iiiiii, @function
_Z16sum_optimizationPfiiiiS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z16sum_optimizationPfiiiiS_iiiiiiPfiiiiS_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sum_optimizationPfiiiiS_iiiiii, .-_Z16sum_optimizationPfiiiiS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16sum_optimizationPfiiiiS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sum_optimizationPfiiiiS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sum_optimization(float* in, int inStr0, int inStr1, int inStr2, int inStr3, float* out, int outStr0, int outStr1, int outStr2, int dim, int nElementOut, int dimSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = tid; i < nElementOut; i += stride) {
int outOff0 = i / outStr0;
int outOff1temp = i - outOff0 * outStr0;
int outOff1 = outOff1temp / outStr1;
int outOff2 = outOff1temp - outOff1 * outStr1;
for (int j = 0; j < dimSize; j++) {
int inOff;
if (dim == 0) inOff = j * inStr0 + outOff0 * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 1) inOff = outOff0 * inStr0 + j * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 2) inOff = outOff0 * inStr0 + outOff1 * inStr1 + j * inStr2 + outOff2 * inStr3;
if (dim == 3) inOff = outOff0 * inStr0 + outOff1 * inStr1 + outOff2 * inStr2 + j * inStr3;
out[i] += in[inOff];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_optimization(float* in, int inStr0, int inStr1, int inStr2, int inStr3, float* out, int outStr0, int outStr1, int outStr2, int dim, int nElementOut, int dimSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = tid; i < nElementOut; i += stride) {
int outOff0 = i / outStr0;
int outOff1temp = i - outOff0 * outStr0;
int outOff1 = outOff1temp / outStr1;
int outOff2 = outOff1temp - outOff1 * outStr1;
for (int j = 0; j < dimSize; j++) {
int inOff;
if (dim == 0) inOff = j * inStr0 + outOff0 * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 1) inOff = outOff0 * inStr0 + j * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 2) inOff = outOff0 * inStr0 + outOff1 * inStr1 + j * inStr2 + outOff2 * inStr3;
if (dim == 3) inOff = outOff0 * inStr0 + outOff1 * inStr1 + outOff2 * inStr2 + j * inStr3;
out[i] += in[inOff];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_optimization(float* in, int inStr0, int inStr1, int inStr2, int inStr3, float* out, int outStr0, int outStr1, int outStr2, int dim, int nElementOut, int dimSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = tid; i < nElementOut; i += stride) {
int outOff0 = i / outStr0;
int outOff1temp = i - outOff0 * outStr0;
int outOff1 = outOff1temp / outStr1;
int outOff2 = outOff1temp - outOff1 * outStr1;
for (int j = 0; j < dimSize; j++) {
int inOff;
if (dim == 0) inOff = j * inStr0 + outOff0 * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 1) inOff = outOff0 * inStr0 + j * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 2) inOff = outOff0 * inStr0 + outOff1 * inStr1 + j * inStr2 + outOff2 * inStr3;
if (dim == 3) inOff = outOff0 * inStr0 + outOff1 * inStr1 + outOff2 * inStr2 + j * inStr3;
out[i] += in[inOff];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sum_optimizationPfiiiiS_iiiiii
.globl _Z16sum_optimizationPfiiiiS_iiiiii
.p2align 8
.type _Z16sum_optimizationPfiiiiS_iiiiii,@function
_Z16sum_optimizationPfiiiiS_iiiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s10, s[0:1], 0x30
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s21, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s21, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_14
s_clause 0x2
s_load_b32 s11, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b32 s22, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s11, 0
s_cselect_b32 s12, -1, 0
s_cmp_eq_u32 s4, 0
s_mul_i32 s21, s22, s21
s_cselect_b32 s13, -1, 0
s_cmp_eq_u32 s4, 1
s_mov_b32 s22, 0
s_cselect_b32 s14, -1, 0
s_cmp_eq_u32 s4, 2
s_cselect_b32 s15, -1, 0
s_cmp_eq_u32 s4, 3
s_cselect_b32 s16, -1, 0
s_ashr_i32 s17, s8, 31
s_ashr_i32 s18, s9, 31
s_add_i32 s4, s8, s17
s_add_i32 s5, s9, s18
s_xor_b32 s19, s4, s17
s_xor_b32 s20, s5, s18
v_cvt_f32_u32_e32 v0, s19
v_cvt_f32_u32_e32 v2, s20
s_sub_i32 s2, 0, s19
s_sub_i32 s3, 0, s20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s2, v0
v_mul_lo_u32 v4, s3, v2
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v9, v2, v4
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s21, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s22, vcc_lo, s22
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_14
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v1
s_mov_b32 s23, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v7, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_mul_hi_u32 v8, v7, v0
v_xor_b32_e32 v4, s17, v4
global_load_b32 v2, v[5:6], off
v_mul_lo_u32 v10, v8, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v7, v10
v_subrev_nc_u32_e32 v11, s19, v7
v_cmp_le_u32_e32 vcc_lo, s19, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v7, v11 :: v_dual_add_nc_u32 v10, 1, v8
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s19, v7
v_add_nc_u32_e32 v10, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v8, v10, vcc_lo
v_xor_b32_e32 v7, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v7, v4
v_mul_lo_u32 v4, v10, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v1, v4
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v8
v_xor_b32_e32 v7, v7, v8
v_xor_b32_e32 v8, s18, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v7, v9
v_mul_lo_u32 v12, v11, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v12
v_add_nc_u32_e32 v12, 1, v11
v_subrev_nc_u32_e32 v13, s20, v7
v_cmp_le_u32_e32 vcc_lo, s20, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cndmask_b32_e32 v7, v7, v13, vcc_lo
v_mul_lo_u32 v13, v10, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v12, 1, v11
v_cmp_le_u32_e32 vcc_lo, s20, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v11, v12, vcc_lo
v_xor_b32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, v7, s9
v_mul_lo_u32 v14, v7, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v1, v8
v_sub_nc_u32_e32 v8, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s5, v8
v_mad_u64_u32 v[11:12], null, v7, s4, v[4:5]
v_mul_lo_u32 v12, s4, v8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v10, s3, v[11:12]
v_add3_u32 v8, v12, v14, v13
v_add3_u32 v10, v4, v14, v13
v_add_nc_u32_e32 v11, v11, v13
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, s5, v8
v_add_nc_u32_e32 v10, s4, v10
v_add_nc_u32_e32 v7, s2, v7
s_add_i32 s23, s23, -1
v_lshlrev_b64 v[12:13], 2, v[3:4]
s_cmp_eq_u32 s23, 0
v_add_nc_u32_e32 v11, s3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
global_load_b32 v4, v[12:13], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[5:6], v2, off
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccz .LBB0_10
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccz .LBB0_11
.LBB0_8:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccz .LBB0_12
.LBB0_9:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_5
s_branch .LBB0_13
.p2align 6
.LBB0_10:
v_mov_b32_e32 v3, v7
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_8
.LBB0_11:
v_mov_b32_e32 v3, v11
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_9
.LBB0_12:
v_mov_b32_e32 v3, v10
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_5
.LBB0_13:
v_mov_b32_e32 v3, v8
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sum_optimizationPfiiiiS_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sum_optimizationPfiiiiS_iiiiii, .Lfunc_end0-_Z16sum_optimizationPfiiiiS_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sum_optimizationPfiiiiS_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z16sum_optimizationPfiiiiS_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_optimization(float* in, int inStr0, int inStr1, int inStr2, int inStr3, float* out, int outStr0, int outStr1, int outStr2, int dim, int nElementOut, int dimSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = tid; i < nElementOut; i += stride) {
int outOff0 = i / outStr0;
int outOff1temp = i - outOff0 * outStr0;
int outOff1 = outOff1temp / outStr1;
int outOff2 = outOff1temp - outOff1 * outStr1;
for (int j = 0; j < dimSize; j++) {
int inOff;
if (dim == 0) inOff = j * inStr0 + outOff0 * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 1) inOff = outOff0 * inStr0 + j * inStr1 + outOff1 * inStr2 + outOff2 * inStr3;
if (dim == 2) inOff = outOff0 * inStr0 + outOff1 * inStr1 + j * inStr2 + outOff2 * inStr3;
if (dim == 3) inOff = outOff0 * inStr0 + outOff1 * inStr1 + outOff2 * inStr2 + j * inStr3;
out[i] += in[inOff];
}
}
} | .text
.file "sum_optimization.hip"
.globl _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii # -- Begin function _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.p2align 4, 0x90
.type _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii,@function
_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii: # @_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sum_optimizationPfiiiiS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii, .Lfunc_end0-_Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sum_optimizationPfiiiiS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sum_optimizationPfiiiiS_iiiiii,@object # @_Z16sum_optimizationPfiiiiS_iiiiii
.section .rodata,"a",@progbits
.globl _Z16sum_optimizationPfiiiiS_iiiiii
.p2align 3, 0x0
_Z16sum_optimizationPfiiiiS_iiiiii:
.quad _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.size _Z16sum_optimizationPfiiiiS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sum_optimizationPfiiiiS_iiiiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sum_optimizationPfiiiiS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sum_optimizationPfiiiiS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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