system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
hipMallocManaged (&a, size);
hipMallocManaged (&b, size);
hipMallocManaged (&c_cpu, size);
hipMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
hipEvent_t start, end;
// Cria os eventos
hipEventCreate(&start);
hipEventCreate(&end);
// Registra o primeiro evento
hipEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
hipEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
hipDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
hipEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
hipFree(a);
hipFree(b);
hipFree( c_cpu );
hipFree( c_gpu );
} | .text
.file "exemplo3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPiS_S_ # -- Begin function _Z12matrixMulCPUPiS_S_
.p2align 4, 0x90
.type _Z12matrixMulCPUPiS_S_,@function
_Z12matrixMulCPUPiS_S_: # @_Z12matrixMulCPUPiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
imulq $3024, %rax, %rcx # imm = 0xBD0
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %ebp
imull (%rdi,%r10,4), %ebp
addl %ebp, %ebx
incq %r10
addq $3024, %r11 # imm = 0xBD0
cmpq $756, %r10 # imm = 0x2F4
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
movl %ebx, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $756, %r9 # imm = 0x2F4
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $3024, %rdi # imm = 0xBD0
cmpq $756, %rax # imm = 0x2F4
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matrixMulCPUPiS_S_, .Lfunc_end1-_Z12matrixMulCPUPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
xorl %esi, %esi
movq (%rsp), %rdi
.p2align 4, 0x90
.LBB2_1: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, (%rax,%r8,4)
leal 2(%r8), %r9d
movl %r9d, (%rcx,%r8,4)
movl $0, (%rdx,%r8,4)
movl $0, (%rdi,%r8,4)
incq %r8
cmpq $756, %r8 # imm = 0x2F4
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rsi
addq $3024, %rdi # imm = 0xBD0
addq $3024, %rdx # imm = 0xBD0
addq $3024, %rcx # imm = 0xBD0
addq $3024, %rax # imm = 0xBD0
cmpq $756, %rsi # imm = 0x2F4
jne .LBB2_1
# %bb.4:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $206158430256, %rdi # imm = 0x3000000030
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 48(%rsp)
leaq 144(%rsp), %rax
movq %rax, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $40, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_30
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %rbx
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB2_11: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
# Child Loop BB2_13 Depth 3
imulq $3024, %rdx, %rdi # imm = 0xBD0
addq %rsi, %rdi
movq %rcx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_12: # %.preheader.i
# Parent Loop BB2_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_13 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_11 Depth=1
# Parent Loop BB2_12 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %r14d
imull (%rax,%r10,4), %r14d
addl %r14d, %ebp
incq %r10
addq $3024, %r11 # imm = 0xBD0
cmpq $756, %r10 # imm = 0x2F4
jne .LBB2_13
# %bb.14: # in Loop: Header=BB2_12 Depth=2
movl %ebp, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq $756, %r9 # imm = 0x2F4
jne .LBB2_12
# %bb.15: # in Loop: Header=BB2_11 Depth=1
incq %rdx
addq $3024, %rax # imm = 0xBD0
cmpq $756, %rdx # imm = 0x2F4
jne .LBB2_11
# %bb.16: # %_Z12matrixMulCPUPiS_S_.exit
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_30
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_19
# %bb.18:
movzbl 67(%r14), %eax
jmp .LBB2_20
.LBB2_19:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
xorl %r14d, %r14d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
movq (%rsp), %rcx
addq %r14, %rcx
movq 8(%rsp), %rsi
addq %r14, %rsi
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdx,4), %edi
cmpl (%rcx,%rdx,4), %edi
jne .LBB2_23
# %bb.24: # in Loop: Header=BB2_22 Depth=2
incq %rdx
cmpq $756, %rdx # imm = 0x2F4
jne .LBB2_22
# %bb.25: # %.loopexit
# in Loop: Header=BB2_21 Depth=1
cmpq $754, %rbx # imm = 0x2F2
jbe .LBB2_26
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_23: # in Loop: Header=BB2_21 Depth=1
movl $.L.str.4, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movb $1, %al
cmpq $754, %rbx # imm = 0x2F2
ja .LBB2_27
.LBB2_26: # %.loopexit
# in Loop: Header=BB2_21 Depth=1
incq %rbx
movl %eax, %ecx
andb $1, %cl
addq $3024, %r14 # imm = 0xBD0
testb %cl, %cl
je .LBB2_21
.LBB2_27:
testb $1, %al
jne .LBB2_29
# %bb.28:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_29:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_30:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tempo de processamento na GPU igual a "
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " msec (aproximadamente 0.01108 segundos)"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tempo de processamento na CPU igual a "
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " sec"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "FOUND ERROR at c[%d][%d]\n"
.size .L.str.4, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successo! As duas matrizes s\303\243o iguais, sendo executadas na CPU e na GPU!"
.size .Lstr, 74
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x2f3, PT ; /* 0x000002f30000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R6, 0x2f3, P0 ; /* 0x000002f30600780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R6, R6, 0x2f4, RZ ; /* 0x000002f406067824 */
/* 0x000fe200078e02ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fe200078e0207 */
/*00f0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R15, [R4.64+0xbd0] ; /* 0x000bd004040f7981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R17, [R4.64+0x17a0] ; /* 0x0017a00404117981 */
/* 0x000128000c1e1900 */
/*0140*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000328000c1e1900 */
/*0150*/ LDG.E R19, [R4.64+0x2370] ; /* 0x0023700404137981 */
/* 0x000168000c1e1900 */
/*0160*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R21, [R4.64+0x2f40] ; /* 0x002f400404157981 */
/* 0x000168000c1e1900 */
/*0180*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000368000c1e1900 */
/*0190*/ LDG.E R23, [R4.64+0x3b10] ; /* 0x003b100404177981 */
/* 0x000168000c1e1900 */
/*01a0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000368000c1e1900 */
/*01b0*/ LDG.E R10, [R4.64+0x46e0] ; /* 0x0046e004040a7981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000368000c1e1900 */
/*01d0*/ LDG.E R8, [R4.64+0x52b0] ; /* 0x0052b00404087981 */
/* 0x000168000c1e1900 */
/*01e0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x000362000c1e1900 */
/*01f0*/ IMAD R12, R12, R13, RZ ; /* 0x0000000d0c0c7224 */
/* 0x004fc800078e02ff */
/*0200*/ IMAD R12, R15, R14, R12 ; /* 0x0000000e0f0c7224 */
/* 0x008fe200078e020c */
/*0210*/ IADD3 R15, P0, R4, 0x5e80, RZ ; /* 0x00005e80040f7810 */
/* 0x000fe40007f1e0ff */
/*0220*/ IADD3 R14, P1, R2, 0x28, RZ ; /* 0x00000028020e7810 */
/* 0x000fe40007f3e0ff */
/*0230*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400007fe4ff */
/*0240*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe20000ffe4ff */
/*0250*/ IMAD R12, R17, R16, R12 ; /* 0x00000010110c7224 */
/* 0x010fc800078e020c */
/*0260*/ IMAD R12, R19, R18, R12 ; /* 0x00000012130c7224 */
/* 0x020fc800078e020c */
/*0270*/ IMAD R12, R21, R20, R12 ; /* 0x00000014150c7224 */
/* 0x000fc800078e020c */
/*0280*/ IMAD R12, R23, R22, R12 ; /* 0x00000016170c7224 */
/* 0x000fc800078e020c */
/*0290*/ IMAD R10, R10, R11, R12 ; /* 0x0000000b0a0a7224 */
/* 0x000fc800078e020c */
/*02a0*/ IMAD R13, R8, R9, R10 ; /* 0x00000009080d7224 */
/* 0x000fe200078e020a */
/*02b0*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe400000001ff */
/*02c0*/ MOV R4, R15 ; /* 0x0000000f00047202 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R2, R14 ; /* 0x0000000e00027202 */
/* 0x000fc60000000f00 */
/*02e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R19, [R2.64+-0x8] ; /* 0xfffff80402137981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R20, [R4.64+0xbd0] ; /* 0x000bd00404147981 */
/* 0x000ee8000c1e1900 */
/*0310*/ LDG.E R25, [R2.64+-0x4] ; /* 0xfffffc0402197981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R23, [R4.64+0x17a0] ; /* 0x0017a00404177981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R22, [R4.64+0x2370] ; /* 0x0023700404167981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x000f68000c1e1900 */
/*0360*/ LDG.E R17, [R4.64+0x2f40] ; /* 0x002f400404117981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R8, [R4.64+0x3b10] ; /* 0x003b100404087981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0402097981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R11, [R4.64+0x46e0] ; /* 0x0046e004040b7981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R15, [R4.64+0x52b0] ; /* 0x0052b004040f7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R19, R14, R19, R13 ; /* 0x000000130e137224 */
/* 0x004fc600078e020d */
/*03f0*/ LDG.E R13, [R4.64+0x5e80] ; /* 0x005e8004040d7981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD R25, R20, R25, R19 ; /* 0x0000001914197224 */
/* 0x008fc600078e0213 */
/*0420*/ LDG.E R19, [R4.64+0x6a50] ; /* 0x006a500404137981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000ee2000c1e1900 */
/*0440*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*0450*/ LDG.E R23, [R4.64+0x7620] ; /* 0x0076200404177981 */
/* 0x000f28000c1e1900 */
/*0460*/ LDG.E R24, [R2.64+0x20] ; /* 0x0000200402187981 */
/* 0x000f22000c1e1900 */
/*0470*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0480*/ LDG.E R21, [R4.64+0x81f0] ; /* 0x0081f00404157981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000f62000c1e1900 */
/*04a0*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*04b0*/ LDG.E R17, [R4.64+0x8dc0] ; /* 0x008dc00404117981 */
/* 0x000f68000c1e1900 */
/*04c0*/ LDG.E R18, [R2.64+0x28] ; /* 0x0000280402127981 */
/* 0x000f62000c1e1900 */
/*04d0*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*04e0*/ LDG.E R8, [R4.64+0x9990] ; /* 0x0099900404087981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f62000c1e1900 */
/*0500*/ IMAD R25, R11, R12, R25 ; /* 0x0000000c0b197224 */
/* 0x000fc600078e0219 */
/*0510*/ LDG.E R11, [R4.64+0xa560] ; /* 0x00a56004040b7981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R2.64+0x30] ; /* 0x00003004020c7981 */
/* 0x000f62000c1e1900 */
/*0530*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*0540*/ LDG.E R15, [R4.64+0xb130] ; /* 0x00b13004040f7981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R16, [R2.64+0x34] ; /* 0x0000340402107981 */
/* 0x000f62000c1e1900 */
/*0560*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*0570*/ LDG.E R13, [R4.64+0xbd00] ; /* 0x00bd0004040d7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*05a0*/ LDG.E R19, [R4.64+0xc8d0] ; /* 0x00c8d00404137981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R20, [R2.64+0x3c] ; /* 0x00003c0402147981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*05d0*/ LDG.E R23, [R4.64+0xd4a0] ; /* 0x00d4a00404177981 */
/* 0x000f28000c1e1900 */
/*05e0*/ LDG.E R24, [R2.64+0x40] ; /* 0x0000400402187981 */
/* 0x000f22000c1e1900 */
/*05f0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0600*/ LDG.E R21, [R4.64+0xe070] ; /* 0x00e0700404157981 */
/* 0x000f68000c1e1900 */
/*0610*/ LDG.E R22, [R2.64+0x44] ; /* 0x0000440402167981 */
/* 0x000f62000c1e1900 */
/*0620*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*0630*/ LDG.E R17, [R4.64+0xec40] ; /* 0x00ec400404117981 */
/* 0x000f68000c1e1900 */
/*0640*/ LDG.E R18, [R2.64+0x48] ; /* 0x0000480402127981 */
/* 0x000f62000c1e1900 */
/*0650*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*0660*/ LDG.E R8, [R4.64+0xf810] ; /* 0x00f8100404087981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R9, [R2.64+0x4c] ; /* 0x00004c0402097981 */
/* 0x000f62000c1e1900 */
/*0680*/ IMAD R25, R11, R12, R25 ; /* 0x0000000c0b197224 */
/* 0x000fc600078e0219 */
/*0690*/ LDG.E R12, [R4.64+0x103e0] ; /* 0x0103e004040c7981 */
/* 0x000f68000c1e1900 */
/*06a0*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000f62000c1e1900 */
/*06b0*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*06c0*/ LDG.E R15, [R4.64+0x10fb0] ; /* 0x010fb004040f7981 */
/* 0x000f68000c1e1900 */
/*06d0*/ LDG.E R16, [R2.64+0x54] ; /* 0x0000540402107981 */
/* 0x000f62000c1e1900 */
/*06e0*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*06f0*/ LDG.E R13, [R4.64+0x11b80] ; /* 0x011b8004040d7981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R14, [R2.64+0x58] ; /* 0x00005804020e7981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*0720*/ LDG.E R19, [R4.64+0x12750] ; /* 0x0127500404137981 */
/* 0x000ee8000c1e1900 */
/*0730*/ LDG.E R20, [R2.64+0x5c] ; /* 0x00005c0402147981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*0750*/ LDG.E R23, [R4.64+0x13320] ; /* 0x0133200404177981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R24, [R2.64+0x60] ; /* 0x0000600402187981 */
/* 0x000f22000c1e1900 */
/*0770*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0780*/ LDG.E R21, [R4.64+0x13ef0] ; /* 0x013ef00404157981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R22, [R2.64+0x64] ; /* 0x0000640402167981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*07b0*/ LDG.E R18, [R4.64+0x14ac0] ; /* 0x014ac00404127981 */
/* 0x000f68000c1e1900 */
/*07c0*/ LDG.E R17, [R2.64+0x68] ; /* 0x0000680402117981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*07e0*/ LDG.E R8, [R4.64+0x15690] ; /* 0x0156900404087981 */
/* 0x000f68000c1e1900 */
/*07f0*/ LDG.E R9, [R2.64+0x6c] ; /* 0x00006c0402097981 */
/* 0x000f62000c1e1900 */
/*0800*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0810*/ LDG.E R12, [R4.64+0x16260] ; /* 0x01626004040c7981 */
/* 0x000f68000c1e1900 */
/*0820*/ LDG.E R11, [R2.64+0x70] ; /* 0x00007004020b7981 */
/* 0x000f62000c1e1900 */
/*0830*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*0840*/ LDG.E R16, [R4.64+0x16e30] ; /* 0x016e300404107981 */
/* 0x000f68000c1e1900 */
/*0850*/ LDG.E R15, [R2.64+0x74] ; /* 0x00007404020f7981 */
/* 0x000f62000c1e1900 */
/*0860*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*0870*/ LDG.E R14, [R4.64+0x17a00] ; /* 0x017a0004040e7981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R13, [R2.64+0x78] ; /* 0x00007804020d7981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*08a0*/ LDG.E R20, [R4.64+0x185d0] ; /* 0x0185d00404147981 */
/* 0x000ee8000c1e1900 */
/*08b0*/ LDG.E R19, [R2.64+0x7c] ; /* 0x00007c0402137981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*08d0*/ LDG.E R24, [R4.64+0x191a0] ; /* 0x0191a00404187981 */
/* 0x000f28000c1e1900 */
/*08e0*/ LDG.E R23, [R2.64+0x80] ; /* 0x0000800402177981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0900*/ LDG.E R21, [R4.64+0x19d70] ; /* 0x019d700404157981 */
/* 0x000f68000c1e1900 */
/*0910*/ LDG.E R22, [R2.64+0x84] ; /* 0x0000840402167981 */
/* 0x000f62000c1e1900 */
/*0920*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x000fc600078e0219 */
/*0930*/ LDG.E R18, [R4.64+0x1a940] ; /* 0x01a9400404127981 */
/* 0x000f68000c1e1900 */
/*0940*/ LDG.E R17, [R2.64+0x88] ; /* 0x0000880402117981 */
/* 0x000f62000c1e1900 */
/*0950*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*0960*/ LDG.E R8, [R4.64+0x1b510] ; /* 0x01b5100404087981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R9, [R2.64+0x8c] ; /* 0x00008c0402097981 */
/* 0x000f62000c1e1900 */
/*0980*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0990*/ LDG.E R11, [R4.64+0x1c0e0] ; /* 0x01c0e004040b7981 */
/* 0x000f68000c1e1900 */
/*09a0*/ LDG.E R12, [R2.64+0x90] ; /* 0x00009004020c7981 */
/* 0x000f62000c1e1900 */
/*09b0*/ IMAD R25, R16, R15, R25 ; /* 0x0000000f10197224 */
/* 0x000fc600078e0219 */
/*09c0*/ LDG.E R15, [R4.64+0x1ccb0] ; /* 0x01ccb004040f7981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R16, [R2.64+0x94] ; /* 0x0000940402107981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IMAD R25, R14, R13, R25 ; /* 0x0000000d0e197224 */
/* 0x004fc600078e0219 */
/*09f0*/ LDG.E R13, [R4.64+0x1d880] ; /* 0x01d88004040d7981 */
/* 0x0000a8000c1e1900 */
/*0a00*/ LDG.E R14, [R2.64+0x98] ; /* 0x00009804020e7981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x008fc600078e0219 */
/*0a20*/ LDG.E R19, [R4.64+0x1e450] ; /* 0x01e4500404137981 */
/* 0x0000e8000c1e1900 */
/*0a30*/ LDG.E R20, [R2.64+0x9c] ; /* 0x00009c0402147981 */
/* 0x0002e2000c1e1900 */
/*0a40*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x010fc600078e0219 */
/*0a50*/ LDG.E R24, [R4.64+0x1f020] ; /* 0x01f0200404187981 */
/* 0x000128000c1e1900 */
/*0a60*/ LDG.E R23, [R2.64+0xa0] ; /* 0x0000a00402177981 */
/* 0x000322000c1e1900 */
/*0a70*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0a80*/ LDG.E R21, [R4.64+0x1fbf0] ; /* 0x01fbf00404157981 */
/* 0x000168000c1e1900 */
/*0a90*/ LDG.E R22, [R2.64+0xa4] ; /* 0x0000a40402167981 */
/* 0x000362000c1e1900 */
/*0aa0*/ IADD3 R10, R10, 0x2c, RZ ; /* 0x0000002c0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD R17, R18, R17, R25 ; /* 0x0000001112117224 */
/* 0x000fc600078e0219 */
/*0ac0*/ ISETP.NE.AND P0, PT, R10, 0x2f4, PT ; /* 0x000002f40a00780c */
/* 0x000fe20003f05270 */
/*0ad0*/ IMAD R8, R8, R9, R17 ; /* 0x0000000908087224 */
/* 0x000fc800078e0211 */
/*0ae0*/ IMAD R8, R11, R12, R8 ; /* 0x0000000c0b087224 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD R8, R15, R16, R8 ; /* 0x000000100f087224 */
/* 0x000fe200078e0208 */
/*0b00*/ IADD3 R15, P1, R4, 0x207c0, RZ ; /* 0x000207c0040f7810 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x001fe20000ffe4ff */
/*0b20*/ IMAD R13, R13, R14, R8 ; /* 0x0000000e0d0d7224 */
/* 0x004fe200078e0208 */
/*0b30*/ IADD3 R14, P2, R2, 0xb0, RZ ; /* 0x000000b0020e7810 */
/* 0x000fc80007f5e0ff */
/*0b40*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x002fe200017fe4ff */
/*0b50*/ IMAD R13, R19, R20, R13 ; /* 0x00000014130d7224 */
/* 0x008fc800078e020d */
/*0b60*/ IMAD R13, R24, R23, R13 ; /* 0x00000017180d7224 */
/* 0x010fc800078e020d */
/*0b70*/ IMAD R13, R21, R22, R13 ; /* 0x00000016150d7224 */
/* 0x020fe200078e020d */
/*0b80*/ @P0 BRA 0x2c0 ; /* 0xfffff73000000947 */
/* 0x000fea000383ffff */
/*0b90*/ IADD3 R2, R0, R6, RZ ; /* 0x0000000600027210 */
/* 0x000fca0007ffe0ff */
/*0ba0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0bb0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2f4, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, 0x2f4
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v5, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x2f4, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0xbd0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, 0x2f4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ccca_00000000-6_exemplo3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12matrixMulCPUPiS_S_
.type _Z12matrixMulCPUPiS_S_, @function
_Z12matrixMulCPUPiS_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %rbx
movl $0, %r11d
.L4:
leaq 2286144(%rbp), %rdi
imulq $3024, %r11, %r9
leaq (%r12,%r9), %r10
addq %rbx, %r9
movl $0, %r8d
.L8:
leaq -2286144(%rdi), %rax
movq %r10, %rcx
movl $0, %esi
.L5:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $3024, %rax
cmpq %rdi, %rax
jne .L5
movl %esi, (%r9,%r8,4)
addq $1, %r8
addq $4, %rdi
cmpq $756, %r8
jne .L8
addq $1, %r11
cmpq $756, %r11
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z12matrixMulCPUPiS_S_, .-_Z12matrixMulCPUPiS_S_
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Tempo de processamento na GPU igual a "
.align 8
.LC1:
.string " msec (aproximadamente 0.01108 segundos)"
.align 8
.LC3:
.string "Tempo de processamento na CPU igual a "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string " sec"
.LC5:
.string "FOUND ERROR at c[%d][%d]\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Successo! As duas matrizes s\303\243o iguais, sendo executadas na CPU e na GPU!\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
movl $3024, %edi
movl $0, %esi
.L20:
leaq -3024(%rdi), %rax
movl $2, %edx
.L21:
movq 32(%rsp), %rcx
movl %esi, (%rcx,%rax)
movq 40(%rsp), %rcx
movl %edx, (%rcx,%rax)
movq 48(%rsp), %rcx
movl $0, (%rcx,%rax)
movq 56(%rsp), %rcx
movl $0, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq %rdi, %rax
jne .L21
addl $1, %esi
addq $3024, %rdi
cmpl $756, %esi
jne .L20
movl $1, 88(%rsp)
movl $48, 92(%rsp)
movl $48, 96(%rsp)
movl $1, 100(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L23:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z12matrixMulCPUPiS_S_
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movl $0, %esi
jmp .L24
.L34:
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
jmp .L23
.L36:
movl %eax, %ecx
movl %esi, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
addl $1, %esi
addq $3024, %rcx
addq $3024, %rdx
cmpl $756, %esi
je .L28
.L24:
movl $0, %eax
.L27:
movl (%rdx,%rax,4), %ebx
cmpl %ebx, (%rcx,%rax,4)
jne .L36
addq $1, %rax
cmpq $756, %rax
jne .L27
jmp .L37
.L28:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exemplo3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPiS_S_ # -- Begin function _Z12matrixMulCPUPiS_S_
.p2align 4, 0x90
.type _Z12matrixMulCPUPiS_S_,@function
_Z12matrixMulCPUPiS_S_: # @_Z12matrixMulCPUPiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
imulq $3024, %rax, %rcx # imm = 0xBD0
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %ebp
imull (%rdi,%r10,4), %ebp
addl %ebp, %ebx
incq %r10
addq $3024, %r11 # imm = 0xBD0
cmpq $756, %r10 # imm = 0x2F4
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
movl %ebx, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $756, %r9 # imm = 0x2F4
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $3024, %rdi # imm = 0xBD0
cmpq $756, %rax # imm = 0x2F4
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matrixMulCPUPiS_S_, .Lfunc_end1-_Z12matrixMulCPUPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $2286144, %esi # imm = 0x22E240
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
xorl %esi, %esi
movq (%rsp), %rdi
.p2align 4, 0x90
.LBB2_1: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, (%rax,%r8,4)
leal 2(%r8), %r9d
movl %r9d, (%rcx,%r8,4)
movl $0, (%rdx,%r8,4)
movl $0, (%rdi,%r8,4)
incq %r8
cmpq $756, %r8 # imm = 0x2F4
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rsi
addq $3024, %rdi # imm = 0xBD0
addq $3024, %rdx # imm = 0xBD0
addq $3024, %rcx # imm = 0xBD0
addq $3024, %rax # imm = 0xBD0
cmpq $756, %rsi # imm = 0x2F4
jne .LBB2_1
# %bb.4:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $206158430256, %rdi # imm = 0x3000000030
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 48(%rsp)
leaq 144(%rsp), %rax
movq %rax, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $40, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_30
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %rbx
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB2_11: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
# Child Loop BB2_13 Depth 3
imulq $3024, %rdx, %rdi # imm = 0xBD0
addq %rsi, %rdi
movq %rcx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_12: # %.preheader.i
# Parent Loop BB2_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_13 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_11 Depth=1
# Parent Loop BB2_12 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %r14d
imull (%rax,%r10,4), %r14d
addl %r14d, %ebp
incq %r10
addq $3024, %r11 # imm = 0xBD0
cmpq $756, %r10 # imm = 0x2F4
jne .LBB2_13
# %bb.14: # in Loop: Header=BB2_12 Depth=2
movl %ebp, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq $756, %r9 # imm = 0x2F4
jne .LBB2_12
# %bb.15: # in Loop: Header=BB2_11 Depth=1
incq %rdx
addq $3024, %rax # imm = 0xBD0
cmpq $756, %rdx # imm = 0x2F4
jne .LBB2_11
# %bb.16: # %_Z12matrixMulCPUPiS_S_.exit
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_30
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_19
# %bb.18:
movzbl 67(%r14), %eax
jmp .LBB2_20
.LBB2_19:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
xorl %r14d, %r14d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
movq (%rsp), %rcx
addq %r14, %rcx
movq 8(%rsp), %rsi
addq %r14, %rsi
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdx,4), %edi
cmpl (%rcx,%rdx,4), %edi
jne .LBB2_23
# %bb.24: # in Loop: Header=BB2_22 Depth=2
incq %rdx
cmpq $756, %rdx # imm = 0x2F4
jne .LBB2_22
# %bb.25: # %.loopexit
# in Loop: Header=BB2_21 Depth=1
cmpq $754, %rbx # imm = 0x2F2
jbe .LBB2_26
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_23: # in Loop: Header=BB2_21 Depth=1
movl $.L.str.4, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movb $1, %al
cmpq $754, %rbx # imm = 0x2F2
ja .LBB2_27
.LBB2_26: # %.loopexit
# in Loop: Header=BB2_21 Depth=1
incq %rbx
movl %eax, %ecx
andb $1, %cl
addq $3024, %r14 # imm = 0xBD0
testb %cl, %cl
je .LBB2_21
.LBB2_27:
testb $1, %al
jne .LBB2_29
# %bb.28:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_29:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_30:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tempo de processamento na GPU igual a "
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " msec (aproximadamente 0.01108 segundos)"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tempo de processamento na CPU igual a "
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " sec"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "FOUND ERROR at c[%d][%d]\n"
.size .L.str.4, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successo! As duas matrizes s\303\243o iguais, sendo executadas na CPU e na GPU!"
.size .Lstr, 74
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | .file "tmpxft_000b1215_00000000-6__upfirdn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5978:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
.type _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi:
.LFB6000:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_float32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6000:
.size _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
.globl _cupy_upfirdn1D_float32
.type _cupy_upfirdn1D_float32, @function
_cupy_upfirdn1D_float32:
.LFB6001:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6001:
.size _cupy_upfirdn1D_float32, .-_cupy_upfirdn1D_float32
.globl _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
.type _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi:
.LFB6002:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_float64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6002:
.size _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
.globl _cupy_upfirdn1D_float64
.type _cupy_upfirdn1D_float64, @function
_cupy_upfirdn1D_float64:
.LFB6003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6003:
.size _cupy_upfirdn1D_float64, .-_cupy_upfirdn1D_float64
.globl _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
.type _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i, @function
_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i:
.LFB6004:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_complex64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6004:
.size _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i, .-_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
.globl _cupy_upfirdn1D_complex64
.type _cupy_upfirdn1D_complex64, @function
_cupy_upfirdn1D_complex64:
.LFB6005:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6005:
.size _cupy_upfirdn1D_complex64, .-_cupy_upfirdn1D_complex64
.globl _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
.type _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i, @function
_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i:
.LFB6006:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_complex128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6006:
.size _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i, .-_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
.globl _cupy_upfirdn1D_complex128
.type _cupy_upfirdn1D_complex128, @function
_cupy_upfirdn1D_complex128:
.LFB6007:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6007:
.size _cupy_upfirdn1D_complex128, .-_cupy_upfirdn1D_complex128
.globl _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
.type _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii:
.LFB6008:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_float32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6008:
.size _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
.globl _cupy_upfirdn2D_float32
.type _cupy_upfirdn2D_float32, @function
_cupy_upfirdn2D_float32:
.LFB6009:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6009:
.size _cupy_upfirdn2D_float32, .-_cupy_upfirdn2D_float32
.globl _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
.type _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii:
.LFB6010:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_float64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6010:
.size _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
.globl _cupy_upfirdn2D_float64
.type _cupy_upfirdn2D_float64, @function
_cupy_upfirdn2D_float64:
.LFB6011:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6011:
.size _cupy_upfirdn2D_float64, .-_cupy_upfirdn2D_float64
.globl _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
.type _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii, @function
_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii:
.LFB6012:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_complex64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6012:
.size _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii, .-_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
.globl _cupy_upfirdn2D_complex64
.type _cupy_upfirdn2D_complex64, @function
_cupy_upfirdn2D_complex64:
.LFB6013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6013:
.size _cupy_upfirdn2D_complex64, .-_cupy_upfirdn2D_complex64
.globl _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
.type _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii, @function
_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii:
.LFB6014:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_complex128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6014:
.size _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii, .-_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
.globl _cupy_upfirdn2D_complex128
.type _cupy_upfirdn2D_complex128, @function
_cupy_upfirdn2D_complex128:
.LFB6015:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6015:
.size _cupy_upfirdn2D_complex128, .-_cupy_upfirdn2D_complex128
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_cupy_upfirdn2D_complex128"
.LC1:
.string "_cupy_upfirdn2D_complex64"
.LC2:
.string "_cupy_upfirdn2D_float64"
.LC3:
.string "_cupy_upfirdn2D_float32"
.LC4:
.string "_cupy_upfirdn1D_complex128"
.LC5:
.string "_cupy_upfirdn1D_complex64"
.LC6:
.string "_cupy_upfirdn1D_float64"
.LC7:
.string "_cupy_upfirdn1D_float32"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo5beginE"
.align 8
.LC9:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo3endE"
.align 8
.LC10:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo6cbeginE"
.align 8
.LC11:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo4cendE"
.align 8
.LC12:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE"
.align 8
.LC13:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__419piecewise_constructE"
.align 8
.LC14:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__48in_placeE"
.align 8
.LC15:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC16:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC17:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC18:
.string "_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955906thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6017:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_complex128(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_complex64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_float64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_float32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_complex128(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_complex64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_float64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_float32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6017:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE
.weak _ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE
.section .rodata._ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE,"aG",@progbits,_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE,comdat
.type _ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE, 1
_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <hip/hip_runtime.h>
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <hip/hip_runtime.h>
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | .text
.file "_upfirdn.hip"
.globl __device_stub___cupy_upfirdn1D_float32 # -- Begin function __device_stub___cupy_upfirdn1D_float32
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_float32,@function
__device_stub___cupy_upfirdn1D_float32: # @__device_stub___cupy_upfirdn1D_float32
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_float32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub___cupy_upfirdn1D_float32, .Lfunc_end0-__device_stub___cupy_upfirdn1D_float32
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_float64 # -- Begin function __device_stub___cupy_upfirdn1D_float64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_float64,@function
__device_stub___cupy_upfirdn1D_float64: # @__device_stub___cupy_upfirdn1D_float64
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_float64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub___cupy_upfirdn1D_float64, .Lfunc_end1-__device_stub___cupy_upfirdn1D_float64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_complex64 # -- Begin function __device_stub___cupy_upfirdn1D_complex64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_complex64,@function
__device_stub___cupy_upfirdn1D_complex64: # @__device_stub___cupy_upfirdn1D_complex64
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_complex64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size __device_stub___cupy_upfirdn1D_complex64, .Lfunc_end2-__device_stub___cupy_upfirdn1D_complex64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_complex128 # -- Begin function __device_stub___cupy_upfirdn1D_complex128
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_complex128,@function
__device_stub___cupy_upfirdn1D_complex128: # @__device_stub___cupy_upfirdn1D_complex128
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_complex128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size __device_stub___cupy_upfirdn1D_complex128, .Lfunc_end3-__device_stub___cupy_upfirdn1D_complex128
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_float32 # -- Begin function __device_stub___cupy_upfirdn2D_float32
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_float32,@function
__device_stub___cupy_upfirdn2D_float32: # @__device_stub___cupy_upfirdn2D_float32
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_float32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end4:
.size __device_stub___cupy_upfirdn2D_float32, .Lfunc_end4-__device_stub___cupy_upfirdn2D_float32
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_float64 # -- Begin function __device_stub___cupy_upfirdn2D_float64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_float64,@function
__device_stub___cupy_upfirdn2D_float64: # @__device_stub___cupy_upfirdn2D_float64
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_float64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end5:
.size __device_stub___cupy_upfirdn2D_float64, .Lfunc_end5-__device_stub___cupy_upfirdn2D_float64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_complex64 # -- Begin function __device_stub___cupy_upfirdn2D_complex64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_complex64,@function
__device_stub___cupy_upfirdn2D_complex64: # @__device_stub___cupy_upfirdn2D_complex64
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_complex64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end6:
.size __device_stub___cupy_upfirdn2D_complex64, .Lfunc_end6-__device_stub___cupy_upfirdn2D_complex64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_complex128 # -- Begin function __device_stub___cupy_upfirdn2D_complex128
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_complex128,@function
__device_stub___cupy_upfirdn2D_complex128: # @__device_stub___cupy_upfirdn2D_complex128
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_complex128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end7:
.size __device_stub___cupy_upfirdn2D_complex128, .Lfunc_end7-__device_stub___cupy_upfirdn2D_complex128
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_float32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_float64, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_complex64, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_complex128, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_float32, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_float64, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_complex64, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_complex128, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _cupy_upfirdn1D_float32,@object # @_cupy_upfirdn1D_float32
.section .rodata,"a",@progbits
.globl _cupy_upfirdn1D_float32
.p2align 3, 0x0
_cupy_upfirdn1D_float32:
.quad __device_stub___cupy_upfirdn1D_float32
.size _cupy_upfirdn1D_float32, 8
.type _cupy_upfirdn1D_float64,@object # @_cupy_upfirdn1D_float64
.globl _cupy_upfirdn1D_float64
.p2align 3, 0x0
_cupy_upfirdn1D_float64:
.quad __device_stub___cupy_upfirdn1D_float64
.size _cupy_upfirdn1D_float64, 8
.type _cupy_upfirdn1D_complex64,@object # @_cupy_upfirdn1D_complex64
.globl _cupy_upfirdn1D_complex64
.p2align 3, 0x0
_cupy_upfirdn1D_complex64:
.quad __device_stub___cupy_upfirdn1D_complex64
.size _cupy_upfirdn1D_complex64, 8
.type _cupy_upfirdn1D_complex128,@object # @_cupy_upfirdn1D_complex128
.globl _cupy_upfirdn1D_complex128
.p2align 3, 0x0
_cupy_upfirdn1D_complex128:
.quad __device_stub___cupy_upfirdn1D_complex128
.size _cupy_upfirdn1D_complex128, 8
.type _cupy_upfirdn2D_float32,@object # @_cupy_upfirdn2D_float32
.globl _cupy_upfirdn2D_float32
.p2align 3, 0x0
_cupy_upfirdn2D_float32:
.quad __device_stub___cupy_upfirdn2D_float32
.size _cupy_upfirdn2D_float32, 8
.type _cupy_upfirdn2D_float64,@object # @_cupy_upfirdn2D_float64
.globl _cupy_upfirdn2D_float64
.p2align 3, 0x0
_cupy_upfirdn2D_float64:
.quad __device_stub___cupy_upfirdn2D_float64
.size _cupy_upfirdn2D_float64, 8
.type _cupy_upfirdn2D_complex64,@object # @_cupy_upfirdn2D_complex64
.globl _cupy_upfirdn2D_complex64
.p2align 3, 0x0
_cupy_upfirdn2D_complex64:
.quad __device_stub___cupy_upfirdn2D_complex64
.size _cupy_upfirdn2D_complex64, 8
.type _cupy_upfirdn2D_complex128,@object # @_cupy_upfirdn2D_complex128
.globl _cupy_upfirdn2D_complex128
.p2align 3, 0x0
_cupy_upfirdn2D_complex128:
.quad __device_stub___cupy_upfirdn2D_complex128
.size _cupy_upfirdn2D_complex128, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_cupy_upfirdn1D_float32"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_cupy_upfirdn1D_float64"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_cupy_upfirdn1D_complex64"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_cupy_upfirdn1D_complex128"
.size .L__unnamed_4, 27
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_cupy_upfirdn2D_float32"
.size .L__unnamed_5, 24
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_cupy_upfirdn2D_float64"
.size .L__unnamed_6, 24
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_cupy_upfirdn2D_complex64"
.size .L__unnamed_7, 26
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_cupy_upfirdn2D_complex128"
.size .L__unnamed_8, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub___cupy_upfirdn1D_float32
.addrsig_sym __device_stub___cupy_upfirdn1D_float64
.addrsig_sym __device_stub___cupy_upfirdn1D_complex64
.addrsig_sym __device_stub___cupy_upfirdn1D_complex128
.addrsig_sym __device_stub___cupy_upfirdn2D_float32
.addrsig_sym __device_stub___cupy_upfirdn2D_float64
.addrsig_sym __device_stub___cupy_upfirdn2D_complex64
.addrsig_sym __device_stub___cupy_upfirdn2D_complex128
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _cupy_upfirdn1D_float32
.addrsig_sym _cupy_upfirdn1D_float64
.addrsig_sym _cupy_upfirdn1D_complex64
.addrsig_sym _cupy_upfirdn1D_complex128
.addrsig_sym _cupy_upfirdn2D_float32
.addrsig_sym _cupy_upfirdn2D_float64
.addrsig_sym _cupy_upfirdn2D_complex64
.addrsig_sym _cupy_upfirdn2D_complex128
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include <device_functions.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char* file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define GRAPH_SIZE 6144
#define WORK_SIZE 256
#define NTHREADS 1024
#define BLOCKS 16
#define EDGE_COST(graph, GRAPH_SIZE, a, b) graph[a * GRAPH_SIZE + b]
#define D(a, b) EDGE_COST(output, GRAPH_SIZE, a, b)
#define INF 0x1fffffff
//createGraph
void generate_random_graph(int* output) {
int i, j;
srand(0xdadadada);
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (i == j) {
D(i, j) = 0;
}
else {
int r;
r = rand() % 40;
if (r > 20) {
r = INF;
}
D(i, j) = r;
}
}
}
}
//sequencial GPU
__global__ void calculateSequencialGPU(int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
__global__ void calcWithoutAtomic1D(int* output, int k) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i = totalID / GRAPH_SIZE;
int j = totalID % GRAPH_SIZE;
int counter = 0;
while (counter < WORK_SIZE)
{
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
if ((j + 1) < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
}
__global__ void calcWithAtomic1D(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (D(i,k) + D(k, j) < D(i, j)) {
D(i, j) = D(i,k) + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
__global__ void calcWithAtomic1DMem(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
Dik = D(i,k);
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (Dik + D(k, j) < D(i, j)) {
D(i, j) = Dik + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i += ((i+1)< GRAPH_SIZE);
j = 0;
Dik = D(i,k);
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
void floyd_warshall_gpu(const int* graph, int* output) {
int* dev_a;
cudaMalloc(&dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
cudaMemcpy(dev_a, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, cudaMemcpyHostToDevice);
//calculateSequencialGPU << <1, 1 >> > (dev_a, GRAPH_SIZE);
int blocks;
int threads;
cudaOccupancyMaxPotentialBlockSize (&blocks, &threads, calcWithoutAtomic1D, 0, GRAPH_SIZE*GRAPH_SIZE);
//blocks = sqrt(blocks);
//threads = sqrt(threads);
int workPerThread = ((GRAPH_SIZE*GRAPH_SIZE) / (threads*blocks));// + 1;
printf("workPerThread= %d, blocks= %d threadsPerBlocks = %d\n", workPerThread, blocks, threads);
int* syncGrid;
cudaMalloc(&syncGrid, sizeof(int) * blocks);
for (int k = 0; k < GRAPH_SIZE; k++) {
calcWithoutAtomic1D <<<blocks, threads>>> (dev_a, k);
}
//calcWithAtomic1D<<<blocks, threads>>> (dev_a, syncGrid);
//calcWithAtomic1DShared<<<blocks, threads>>> (dev_a, syncGrid);
cudaError_t err = cudaMemcpy(output, dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, cudaMemcpyDeviceToHost);
gpuErrchk(err);
cudaFree(dev_a);
cudaFree(syncGrid);//teste
}
void floyd_warshall_cpu(const int* graph, int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
int main(int argc, char** argv) {
/*
LARGE_INTEGER frequency;
LARGE_INTEGER start;
LARGE_INTEGER end;
double interval;*/
#define TIMER_START() gettimeofday(&tv1, NULL)
#define TIMER_STOP() \
gettimeofday(&tv2, NULL); \
timersub(&tv2, &tv1, &tv); \
time_delta = (float)tv.tv_sec + tv.tv_usec / 1000000.0
struct timeval tv1, tv2, tv;
float time_delta;
int* graph, * output_cpu, * output_gpu;
int size;
size = sizeof(int) * GRAPH_SIZE * GRAPH_SIZE;
graph = (int*)malloc(size);
assert(graph);
output_cpu = (int*)malloc(size);
assert(output_cpu);
memset(output_cpu, 0, size);
output_gpu = (int*)malloc(size);
assert(output_gpu);
generate_random_graph(graph);
fprintf(stderr, "running on cpu...\n");
TIMER_START();
memcpy(output_cpu, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_cpu(graph, output_cpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
fprintf(stderr, "running on gpu...\n");
TIMER_START();
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_gpu(graph, output_gpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
if (memcmp(output_cpu, output_gpu, size) != 0) {
fprintf(stderr, "FAIL!\n");
}
else {
fprintf(stderr, "Verified!\n");
}
return 0;
} | .file "tmpxft_0010d211_00000000-6_cuda_FW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21generate_random_graphPi
.type _Z21generate_random_graphPi, @function
_Z21generate_random_graphPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movl $-623191334, %edi
call srand@PLT
movl $0, %r13d
movl $6144, %r12d
movl $0, %ebp
movl $536870911, %r15d
jmp .L4
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
sall $3, %ecx
subl %ecx, %eax
movl %eax, %edx
cmpl $21, %eax
cmovge %r15d, %edx
movslq %ebx, %rax
movl %edx, (%r14,%rax,4)
.L6:
addl $1, %ebx
cmpl %r12d, %ebx
je .L13
.L8:
leal (%rbx,%r13), %eax
cmpl %eax, %ebp
jne .L5
movslq %ebx, %rax
movl $0, (%r14,%rax,4)
jmp .L6
.L13:
addl $1, %ebp
addl $6144, %r12d
subl $6144, %r13d
cmpl $6144, %ebp
je .L3
.L4:
leal -6144(%r12), %ebx
jmp .L8
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21generate_random_graphPi, .-_Z21generate_random_graphPi
.globl _Z18floyd_warshall_cpuPKiPi
.type _Z18floyd_warshall_cpuPKiPi, @function
_Z18floyd_warshall_cpuPKiPi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r11
movq %rsi, %rbp
movl $0, %r9d
movl $0, %ebx
leaq 151019520(%rsi), %r10
jmp .L15
.L16:
addq $4, %rax
cmpq %rsi, %rax
je .L23
.L17:
leaq (%rax,%rdi), %rcx
movl (%r8), %edx
addl (%rcx,%r9), %edx
cmpl (%rax), %edx
jge .L16
movl %edx, (%rax)
jmp .L16
.L23:
addq $24576, %rsi
addq $24576, %r8
subq $24576, %rdi
cmpq %r10, %rsi
je .L18
.L20:
leaq -24576(%rsi), %rax
jmp .L17
.L18:
addl $1, %ebx
addq $24576, %r9
addq $4, %rbp
cmpl $6144, %ebx
je .L14
.L15:
leaq 24576(%r11), %rsi
movq %rbp, %r8
movl $0, %edi
jmp .L20
.L14:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z18floyd_warshall_cpuPKiPi, .-_Z18floyd_warshall_cpuPKiPi
.globl _Z42__device_stub__Z22calculateSequencialGPUPiPi
.type _Z42__device_stub__Z22calculateSequencialGPUPiPi, @function
_Z42__device_stub__Z22calculateSequencialGPUPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22calculateSequencialGPUPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z22calculateSequencialGPUPiPi, .-_Z42__device_stub__Z22calculateSequencialGPUPiPi
.globl _Z22calculateSequencialGPUPi
.type _Z22calculateSequencialGPUPi, @function
_Z22calculateSequencialGPUPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z22calculateSequencialGPUPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22calculateSequencialGPUPi, .-_Z22calculateSequencialGPUPi
.globl _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
.type _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii, @function
_Z40__device_stub__Z19calcWithoutAtomic1DPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii, .-_Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
.globl _Z19calcWithoutAtomic1DPii
.type _Z19calcWithoutAtomic1DPii, @function
_Z19calcWithoutAtomic1DPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19calcWithoutAtomic1DPii, .-_Z19calcWithoutAtomic1DPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "workPerThread= %d, blocks= %d threadsPerBlocks = %d\n"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/pedrocarrega/projectPCM/master/project/cuda_FW.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z18floyd_warshall_gpuPKiPi
.type _Z18floyd_warshall_gpuPKiPi, @function
_Z18floyd_warshall_gpuPKiPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rdi, %r13
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rdi
movl $150994944, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $150994944, %edx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 44(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L56
.L41:
movl %ebx, %ecx
imull %ebp, %ecx
movl $37748736, %eax
movl $0, %edx
idivl %ecx
movl %ebp, %r8d
movl %ebx, %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %r13d
jmp .L46
.L56:
leaq 48(%rsp), %rdi
movl 44(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 52(%rsp), %rdi
movl 44(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 64(%rsp), %rdi
movl 44(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 72(%rsp), %rdi
movl 44(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 96(%rsp), %rdi
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L41
movl 48(%rsp), %eax
movl %eax, 24(%rsp)
movl 52(%rsp), %r15d
movl 120(%rsp), %r14d
movl 64(%rsp), %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
movl $37748736, %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
leal -1(%r15,%r14), %eax
cltd
idivl %r15d
imull %r15d, %eax
movl %eax, %r13d
testl %eax, %eax
jle .L49
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movl %ebx, 28(%rsp)
jmp .L44
.L43:
movl 12(%rsp), %edx
cmpl %edx, 24(%rsp)
je .L42
subl %r15d, %r13d
testl %r13d, %r13d
jle .L42
.L44:
cmpl %r14d, %r13d
movl %r14d, %ebx
cmovle %r13d, %ebx
leaq 84(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L53
movl 84(%rsp), %eax
movl %ebx, %edx
imull %eax, %edx
cmpl %edx, 12(%rsp)
jge .L43
movl %edx, 12(%rsp)
movl %eax, 20(%rsp)
movl %ebx, 16(%rsp)
jmp .L43
.L49:
movl $0, 20(%rsp)
movl $0, 16(%rsp)
.L42:
movl 20(%rsp), %ebx
imull 72(%rsp), %ebx
movl 16(%rsp), %ebp
jmp .L41
.L53:
movl 28(%rsp), %ebx
jmp .L41
.L45:
addl $1, %r13d
cmpl $6144, %r13d
je .L57
.L46:
movl %ebp, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl %ebx, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movl %r13d, %esi
movq 56(%rsp), %rdi
call _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
jmp .L45
.L57:
movl $2, %ecx
movl $150994944, %edx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $207, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18floyd_warshall_gpuPKiPi, .-_Z18floyd_warshall_gpuPKiPi
.section .rodata.str1.1
.LC3:
.string "running on cpu...\n"
.LC5:
.string "%f seconds\n"
.LC6:
.string "running on gpu...\n"
.LC7:
.string "FAIL!\n"
.LC8:
.string "Verified!\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $150994944, %edi
call malloc@PLT
movq %rax, %r12
movl $150994944, %edi
call malloc@PLT
movq %rax, %rbx
movl $150994944, %edi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Z21generate_random_graphPi
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $150994944, %edx
movq %r12, %rsi
movq %rbx, %rdi
call memcpy@PLT
movq %rbx, %rsi
movq %r12, %rdi
call _Z18floyd_warshall_cpuPKiPi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rdx
subq (%rsp), %rdx
movq 24(%rsp), %rax
subq 8(%rsp), %rax
js .L67
.L61:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z18floyd_warshall_gpuPKiPi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rdx
subq (%rsp), %rdx
movq 24(%rsp), %rax
subq 8(%rsp), %rax
js .L68
.L62:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $150994944, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call memcmp@PLT
testl %eax, %eax
je .L63
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L64:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
subq $1, %rdx
addq $1000000, %rax
jmp .L61
.L68:
subq $1, %rdx
addq $1000000, %rax
jmp .L62
.L63:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.globl _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
.type _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_, @function
_Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L74
.L70:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16calcWithAtomic1DPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L70
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_, .-_Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
.globl _Z16calcWithAtomic1DPiS_
.type _Z16calcWithAtomic1DPiS_, @function
_Z16calcWithAtomic1DPiS_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z16calcWithAtomic1DPiS_, .-_Z16calcWithAtomic1DPiS_
.globl _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
.type _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_, @function
_Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L82
.L78:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L83
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19calcWithAtomic1DMemPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L78
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_, .-_Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
.globl _Z19calcWithAtomic1DMemPiS_
.type _Z19calcWithAtomic1DMemPiS_, @function
_Z19calcWithAtomic1DMemPiS_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19calcWithAtomic1DMemPiS_, .-_Z19calcWithAtomic1DMemPiS_
.section .rodata.str1.1
.LC9:
.string "_Z19calcWithAtomic1DMemPiS_"
.LC10:
.string "_Z16calcWithAtomic1DPiS_"
.LC11:
.string "_Z19calcWithoutAtomic1DPii"
.LC12:
.string "_Z22calculateSequencialGPUPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcWithAtomic1DMemPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16calcWithAtomic1DPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z22calculateSequencialGPUPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include <device_functions.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char* file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define GRAPH_SIZE 6144
#define WORK_SIZE 256
#define NTHREADS 1024
#define BLOCKS 16
#define EDGE_COST(graph, GRAPH_SIZE, a, b) graph[a * GRAPH_SIZE + b]
#define D(a, b) EDGE_COST(output, GRAPH_SIZE, a, b)
#define INF 0x1fffffff
//createGraph
void generate_random_graph(int* output) {
int i, j;
srand(0xdadadada);
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (i == j) {
D(i, j) = 0;
}
else {
int r;
r = rand() % 40;
if (r > 20) {
r = INF;
}
D(i, j) = r;
}
}
}
}
//sequencial GPU
__global__ void calculateSequencialGPU(int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
__global__ void calcWithoutAtomic1D(int* output, int k) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i = totalID / GRAPH_SIZE;
int j = totalID % GRAPH_SIZE;
int counter = 0;
while (counter < WORK_SIZE)
{
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
if ((j + 1) < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
}
__global__ void calcWithAtomic1D(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (D(i,k) + D(k, j) < D(i, j)) {
D(i, j) = D(i,k) + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
__global__ void calcWithAtomic1DMem(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
Dik = D(i,k);
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (Dik + D(k, j) < D(i, j)) {
D(i, j) = Dik + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i += ((i+1)< GRAPH_SIZE);
j = 0;
Dik = D(i,k);
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
void floyd_warshall_gpu(const int* graph, int* output) {
int* dev_a;
cudaMalloc(&dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
cudaMemcpy(dev_a, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, cudaMemcpyHostToDevice);
//calculateSequencialGPU << <1, 1 >> > (dev_a, GRAPH_SIZE);
int blocks;
int threads;
cudaOccupancyMaxPotentialBlockSize (&blocks, &threads, calcWithoutAtomic1D, 0, GRAPH_SIZE*GRAPH_SIZE);
//blocks = sqrt(blocks);
//threads = sqrt(threads);
int workPerThread = ((GRAPH_SIZE*GRAPH_SIZE) / (threads*blocks));// + 1;
printf("workPerThread= %d, blocks= %d threadsPerBlocks = %d\n", workPerThread, blocks, threads);
int* syncGrid;
cudaMalloc(&syncGrid, sizeof(int) * blocks);
for (int k = 0; k < GRAPH_SIZE; k++) {
calcWithoutAtomic1D <<<blocks, threads>>> (dev_a, k);
}
//calcWithAtomic1D<<<blocks, threads>>> (dev_a, syncGrid);
//calcWithAtomic1DShared<<<blocks, threads>>> (dev_a, syncGrid);
cudaError_t err = cudaMemcpy(output, dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, cudaMemcpyDeviceToHost);
gpuErrchk(err);
cudaFree(dev_a);
cudaFree(syncGrid);//teste
}
void floyd_warshall_cpu(const int* graph, int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
int main(int argc, char** argv) {
/*
LARGE_INTEGER frequency;
LARGE_INTEGER start;
LARGE_INTEGER end;
double interval;*/
#define TIMER_START() gettimeofday(&tv1, NULL)
#define TIMER_STOP() \
gettimeofday(&tv2, NULL); \
timersub(&tv2, &tv1, &tv); \
time_delta = (float)tv.tv_sec + tv.tv_usec / 1000000.0
struct timeval tv1, tv2, tv;
float time_delta;
int* graph, * output_cpu, * output_gpu;
int size;
size = sizeof(int) * GRAPH_SIZE * GRAPH_SIZE;
graph = (int*)malloc(size);
assert(graph);
output_cpu = (int*)malloc(size);
assert(output_cpu);
memset(output_cpu, 0, size);
output_gpu = (int*)malloc(size);
assert(output_gpu);
generate_random_graph(graph);
fprintf(stderr, "running on cpu...\n");
TIMER_START();
memcpy(output_cpu, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_cpu(graph, output_cpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
fprintf(stderr, "running on gpu...\n");
TIMER_START();
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_gpu(graph, output_gpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
if (memcmp(output_cpu, output_gpu, size) != 0) {
fprintf(stderr, "FAIL!\n");
}
else {
fprintf(stderr, "Verified!\n");
}
return 0;
} | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char* file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define GRAPH_SIZE 6144
#define WORK_SIZE 256
#define NTHREADS 1024
#define BLOCKS 16
#define EDGE_COST(graph, GRAPH_SIZE, a, b) graph[a * GRAPH_SIZE + b]
#define D(a, b) EDGE_COST(output, GRAPH_SIZE, a, b)
#define INF 0x1fffffff
//createGraph
void generate_random_graph(int* output) {
int i, j;
srand(0xdadadada);
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (i == j) {
D(i, j) = 0;
}
else {
int r;
r = rand() % 40;
if (r > 20) {
r = INF;
}
D(i, j) = r;
}
}
}
}
//sequencial GPU
__global__ void calculateSequencialGPU(int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
__global__ void calcWithoutAtomic1D(int* output, int k) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i = totalID / GRAPH_SIZE;
int j = totalID % GRAPH_SIZE;
int counter = 0;
while (counter < WORK_SIZE)
{
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
if ((j + 1) < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
}
__global__ void calcWithAtomic1D(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (D(i,k) + D(k, j) < D(i, j)) {
D(i, j) = D(i,k) + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
__global__ void calcWithAtomic1DMem(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
Dik = D(i,k);
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (Dik + D(k, j) < D(i, j)) {
D(i, j) = Dik + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i += ((i+1)< GRAPH_SIZE);
j = 0;
Dik = D(i,k);
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
void floyd_warshall_gpu(const int* graph, int* output) {
int* dev_a;
hipMalloc(&dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
hipMemcpy(dev_a, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyHostToDevice);
//calculateSequencialGPU << <1, 1 >> > (dev_a, GRAPH_SIZE);
int blocks;
int threads;
hipOccupancyMaxPotentialBlockSize (&blocks, &threads, calcWithoutAtomic1D, 0, GRAPH_SIZE*GRAPH_SIZE);
//blocks = sqrt(blocks);
//threads = sqrt(threads);
int workPerThread = ((GRAPH_SIZE*GRAPH_SIZE) / (threads*blocks));// + 1;
printf("workPerThread= %d, blocks= %d threadsPerBlocks = %d\n", workPerThread, blocks, threads);
int* syncGrid;
hipMalloc(&syncGrid, sizeof(int) * blocks);
for (int k = 0; k < GRAPH_SIZE; k++) {
calcWithoutAtomic1D <<<blocks, threads>>> (dev_a, k);
}
//calcWithAtomic1D<<<blocks, threads>>> (dev_a, syncGrid);
//calcWithAtomic1DShared<<<blocks, threads>>> (dev_a, syncGrid);
hipError_t err = hipMemcpy(output, dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyDeviceToHost);
gpuErrchk(err);
hipFree(dev_a);
hipFree(syncGrid);//teste
}
void floyd_warshall_cpu(const int* graph, int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
int main(int argc, char** argv) {
/*
LARGE_INTEGER frequency;
LARGE_INTEGER start;
LARGE_INTEGER end;
double interval;*/
#define TIMER_START() gettimeofday(&tv1, NULL)
#define TIMER_STOP() \
gettimeofday(&tv2, NULL); \
timersub(&tv2, &tv1, &tv); \
time_delta = (float)tv.tv_sec + tv.tv_usec / 1000000.0
struct timeval tv1, tv2, tv;
float time_delta;
int* graph, * output_cpu, * output_gpu;
int size;
size = sizeof(int) * GRAPH_SIZE * GRAPH_SIZE;
graph = (int*)malloc(size);
assert(graph);
output_cpu = (int*)malloc(size);
assert(output_cpu);
memset(output_cpu, 0, size);
output_gpu = (int*)malloc(size);
assert(output_gpu);
generate_random_graph(graph);
fprintf(stderr, "running on cpu...\n");
TIMER_START();
memcpy(output_cpu, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_cpu(graph, output_cpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
fprintf(stderr, "running on gpu...\n");
TIMER_START();
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_gpu(graph, output_gpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
if (memcmp(output_cpu, output_gpu, size) != 0) {
fprintf(stderr, "FAIL!\n");
}
else {
fprintf(stderr, "Verified!\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char* file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define GRAPH_SIZE 6144
#define WORK_SIZE 256
#define NTHREADS 1024
#define BLOCKS 16
#define EDGE_COST(graph, GRAPH_SIZE, a, b) graph[a * GRAPH_SIZE + b]
#define D(a, b) EDGE_COST(output, GRAPH_SIZE, a, b)
#define INF 0x1fffffff
//createGraph
void generate_random_graph(int* output) {
int i, j;
srand(0xdadadada);
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (i == j) {
D(i, j) = 0;
}
else {
int r;
r = rand() % 40;
if (r > 20) {
r = INF;
}
D(i, j) = r;
}
}
}
}
//sequencial GPU
__global__ void calculateSequencialGPU(int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
__global__ void calcWithoutAtomic1D(int* output, int k) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i = totalID / GRAPH_SIZE;
int j = totalID % GRAPH_SIZE;
int counter = 0;
while (counter < WORK_SIZE)
{
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
if ((j + 1) < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
}
__global__ void calcWithAtomic1D(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (D(i,k) + D(k, j) < D(i, j)) {
D(i, j) = D(i,k) + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
__global__ void calcWithAtomic1DMem(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
Dik = D(i,k);
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (Dik + D(k, j) < D(i, j)) {
D(i, j) = Dik + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i += ((i+1)< GRAPH_SIZE);
j = 0;
Dik = D(i,k);
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
void floyd_warshall_gpu(const int* graph, int* output) {
int* dev_a;
hipMalloc(&dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
hipMemcpy(dev_a, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyHostToDevice);
//calculateSequencialGPU << <1, 1 >> > (dev_a, GRAPH_SIZE);
int blocks;
int threads;
hipOccupancyMaxPotentialBlockSize (&blocks, &threads, calcWithoutAtomic1D, 0, GRAPH_SIZE*GRAPH_SIZE);
//blocks = sqrt(blocks);
//threads = sqrt(threads);
int workPerThread = ((GRAPH_SIZE*GRAPH_SIZE) / (threads*blocks));// + 1;
printf("workPerThread= %d, blocks= %d threadsPerBlocks = %d\n", workPerThread, blocks, threads);
int* syncGrid;
hipMalloc(&syncGrid, sizeof(int) * blocks);
for (int k = 0; k < GRAPH_SIZE; k++) {
calcWithoutAtomic1D <<<blocks, threads>>> (dev_a, k);
}
//calcWithAtomic1D<<<blocks, threads>>> (dev_a, syncGrid);
//calcWithAtomic1DShared<<<blocks, threads>>> (dev_a, syncGrid);
hipError_t err = hipMemcpy(output, dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyDeviceToHost);
gpuErrchk(err);
hipFree(dev_a);
hipFree(syncGrid);//teste
}
void floyd_warshall_cpu(const int* graph, int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
int main(int argc, char** argv) {
/*
LARGE_INTEGER frequency;
LARGE_INTEGER start;
LARGE_INTEGER end;
double interval;*/
#define TIMER_START() gettimeofday(&tv1, NULL)
#define TIMER_STOP() \
gettimeofday(&tv2, NULL); \
timersub(&tv2, &tv1, &tv); \
time_delta = (float)tv.tv_sec + tv.tv_usec / 1000000.0
struct timeval tv1, tv2, tv;
float time_delta;
int* graph, * output_cpu, * output_gpu;
int size;
size = sizeof(int) * GRAPH_SIZE * GRAPH_SIZE;
graph = (int*)malloc(size);
assert(graph);
output_cpu = (int*)malloc(size);
assert(output_cpu);
memset(output_cpu, 0, size);
output_gpu = (int*)malloc(size);
assert(output_gpu);
generate_random_graph(graph);
fprintf(stderr, "running on cpu...\n");
TIMER_START();
memcpy(output_cpu, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_cpu(graph, output_cpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
fprintf(stderr, "running on gpu...\n");
TIMER_START();
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_gpu(graph, output_gpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
if (memcmp(output_cpu, output_gpu, size) != 0) {
fprintf(stderr, "FAIL!\n");
}
else {
fprintf(stderr, "Verified!\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22calculateSequencialGPUPi
.globl _Z22calculateSequencialGPUPi
.p2align 8
.type _Z22calculateSequencialGPUPi,@function
_Z22calculateSequencialGPUPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_add_i32 s14, s14, 1
s_add_u32 s4, s4, 0x6000
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s14, 0x1800
s_cbranch_scc0 .LBB0_8
.LBB0_2:
s_mov_b64 s[6:7], s[0:1]
s_mov_b32 s15, s3
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_add_i32 s15, s15, 1
s_add_u32 s6, s6, 0x6000
s_addc_u32 s7, s7, 0
s_cmpk_lg_i32 s15, 0x1800
s_cbranch_scc0 .LBB0_1
.LBB0_4:
s_mul_i32 s2, s15, 0x1800
s_mov_b64 s[10:11], 0
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmpk_lg_i32 s10, 0x6000
s_cbranch_scc0 .LBB0_3
.LBB0_6:
s_add_u32 s12, s4, s10
s_addc_u32 s13, s5, s11
s_clause 0x1
global_load_b32 v1, v0, s[8:9]
global_load_b32 v2, v0, s[12:13]
s_add_u32 s12, s6, s10
s_addc_u32 s13, s7, s11
global_load_b32 v3, v0, s[12:13]
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v2, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v3
s_cbranch_vccnz .LBB0_5
global_store_b32 v0, v1, s[12:13]
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22calculateSequencialGPUPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22calculateSequencialGPUPi, .Lfunc_end0-_Z22calculateSequencialGPUPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19calcWithoutAtomic1DPii
.globl _Z19calcWithoutAtomic1DPii
.p2align 8
.type _Z19calcWithoutAtomic1DPii,@function
_Z19calcWithoutAtomic1DPii:
s_load_b32 s2, s[0:1], 0x1c
s_movk_i32 s5, 0x100
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_hi_i32 v1, v0, 0x2aaaaaab
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s4, 0x1800
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v2
v_mul_i32_i24_e32 v1, 0x1800, v2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v1
s_branch .LBB1_2
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v3
v_cmp_lt_i32_e32 vcc_lo, 0x17fe, v3
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
v_add_co_ci_u32_e64 v2, s0, 0, v2, vcc_lo
v_cndmask_b32_e64 v3, v0, 0, vcc_lo
s_cbranch_scc0 .LBB1_4
.LBB1_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v2, 0x1800
v_add_nc_u32_e32 v0, s1, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, s4, v5
v_add_nc_u32_e32 v6, v5, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v8, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_load_b32 v6, v[8:9], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v4, v6, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB1_1
global_store_b32 v[0:1], v4, off
s_branch .LBB1_1
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcWithoutAtomic1DPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19calcWithoutAtomic1DPii, .Lfunc_end1-_Z19calcWithoutAtomic1DPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16calcWithAtomic1DPiS_
.globl _Z16calcWithAtomic1DPiS_
.p2align 8
.type _Z16calcWithAtomic1DPiS_,@function
_Z16calcWithAtomic1DPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_mov_b32_e32 v5, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
v_lshlrev_b32_e32 v1, 8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v2, v1, 0x2aaaaaab
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, v2, v3
v_mul_i32_i24_e32 v4, 0x1800, v2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v1, v4
s_branch .LBB2_2
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s3, s3, 1
s_waitcnt_vscnt null, 0x0
s_cmpk_lg_i32 s3, 0x1800
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_8
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v4
s_mul_i32 s1, s3, 0x1800
s_movk_i32 s2, 0x100
global_store_b32 v3, v3, s[6:7]
s_branch .LBB2_4
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, 1, v7
v_cmp_lt_i32_e64 s0, 0x17fe, v7
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_cndmask_b32_e64 v7, v0, 0, s0
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_cbranch_scc0 .LBB2_6
.LBB2_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v6, 0x1800
v_add_nc_u32_e32 v0, s1, v7
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v8, s3, v9
v_add_nc_u32_e32 v10, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v12, s0, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_ci_u32_e64 v13, s0, s5, v1, s0
v_lshlrev_b64 v[0:1], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
s_clause 0x2
global_load_b32 v10, v[12:13], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v8, v10, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v8, v9
s_cbranch_execz .LBB2_3
global_store_b32 v[0:1], v8, off
s_branch .LBB2_3
.LBB2_6:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB2_1
global_store_b32 v3, v5, s[6:7]
s_branch .LBB2_1
.LBB2_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16calcWithAtomic1DPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16calcWithAtomic1DPiS_, .Lfunc_end2-_Z16calcWithAtomic1DPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19calcWithAtomic1DMemPiS_
.globl _Z19calcWithAtomic1DMemPiS_
.p2align 8
.type _Z19calcWithAtomic1DMemPiS_,@function
_Z19calcWithAtomic1DMemPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s8, s15
s_mov_b32 s9, 0
v_mov_b32_e32 v5, 0
s_lshl_b64 s[0:1], s[8:9], 2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_mov_b32_e32 v7, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s8, s2, v[0:1]
s_add_u32 s2, s6, s0
s_addc_u32 s3, s7, s1
s_mov_b32 s6, s9
v_lshlrev_b32_e32 v1, 8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v2, v1, 0x2aaaaaab
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v2, v3
v_mul_i32_i24_e32 v4, 0x1800, v3
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v1, v4
s_branch .LBB3_2
.LBB3_1:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s6, s6, 1
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_cmpk_lg_i32 s6, 0x1800
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB3_12
.LBB3_2:
v_add_nc_u32_e32 v0, s6, v4
v_mov_b32_e32 v8, v3
s_mul_i32 s1, s6, 0x1800
s_movk_i32 s7, 0x100
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
global_load_b32 v9, v[0:1], off
v_mov_b32_e32 v0, v6
global_store_b32 v5, v5, s[2:3]
s_branch .LBB3_4
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v0, v1
s_add_i32 s7, s7, -1
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB3_10
.LBB3_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s1, v0
s_mov_b32 s8, exec_lo
v_mad_u64_u32 v[10:11], null, v8, 0x1800, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, s0, s4, v1
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v13, s0, s5, v2, s0
v_add_co_u32 v1, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s5, v11, s0
s_clause 0x1
global_load_b32 v10, v[12:13], off
global_load_b32 v11, v[1:2], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v10, v10, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v10, v11
s_cbranch_execz .LBB3_6
global_store_b32 v[1:2], v10, off
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s8, exec_lo
v_cmpx_lt_i32_e32 0x17fe, v0
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB3_8
v_cmp_gt_i32_e64 s0, 0x17ff, v8
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
v_mad_u64_u32 v[0:1], null, v8, 0x1800, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
global_load_b32 v9, v[0:1], off
.LBB3_8:
s_or_saveexec_b32 s0, s8
v_mov_b32_e32 v1, s9
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB3_3
v_add_nc_u32_e32 v1, 1, v0
s_branch .LBB3_3
.LBB3_10:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB3_1
global_store_b32 v5, v7, s[2:3]
s_branch .LBB3_1
.LBB3_12:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcWithAtomic1DMemPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z19calcWithAtomic1DMemPiS_, .Lfunc_end3-_Z19calcWithAtomic1DMemPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22calculateSequencialGPUPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22calculateSequencialGPUPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcWithoutAtomic1DPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcWithoutAtomic1DPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16calcWithAtomic1DPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16calcWithAtomic1DPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcWithAtomic1DMemPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcWithAtomic1DMemPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char* file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define GRAPH_SIZE 6144
#define WORK_SIZE 256
#define NTHREADS 1024
#define BLOCKS 16
#define EDGE_COST(graph, GRAPH_SIZE, a, b) graph[a * GRAPH_SIZE + b]
#define D(a, b) EDGE_COST(output, GRAPH_SIZE, a, b)
#define INF 0x1fffffff
//createGraph
void generate_random_graph(int* output) {
int i, j;
srand(0xdadadada);
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (i == j) {
D(i, j) = 0;
}
else {
int r;
r = rand() % 40;
if (r > 20) {
r = INF;
}
D(i, j) = r;
}
}
}
}
//sequencial GPU
__global__ void calculateSequencialGPU(int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
__global__ void calcWithoutAtomic1D(int* output, int k) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i = totalID / GRAPH_SIZE;
int j = totalID % GRAPH_SIZE;
int counter = 0;
while (counter < WORK_SIZE)
{
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
if ((j + 1) < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
}
__global__ void calcWithAtomic1D(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (D(i,k) + D(k, j) < D(i, j)) {
D(i, j) = D(i,k) + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i++;
j = 0;
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
__global__ void calcWithAtomic1DMem(int* output, int* syncGrid) {
int totalID = blockIdx.x * blockDim.x * WORK_SIZE + threadIdx.x * WORK_SIZE;
int i, j, counter, k = 0, avaliador = 0, Dik;
while(k < GRAPH_SIZE){
i = totalID / GRAPH_SIZE;
j = totalID % GRAPH_SIZE;
counter = 0;
Dik = D(i,k);
syncGrid[blockIdx.x] = 0;
while (counter < WORK_SIZE)
{
if (Dik + D(k, j) < D(i, j)) {
D(i, j) = Dik + D(k, j);
}
if (j + 1 < GRAPH_SIZE) {
j++;
}else {
i += ((i+1)< GRAPH_SIZE);
j = 0;
Dik = D(i,k);
}
counter++;
}
k++;
if (threadIdx.x == 0) {
syncGrid[blockIdx.x] = 1;
do{
avaliador = 0;
for(int i = 0; i < gridDim.x; i++){
avaliador += syncGrid[i];
}
}while(avaliador != gridDim.x);
}
__syncthreads();
}
}
void floyd_warshall_gpu(const int* graph, int* output) {
int* dev_a;
hipMalloc(&dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
hipMemcpy(dev_a, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyHostToDevice);
//calculateSequencialGPU << <1, 1 >> > (dev_a, GRAPH_SIZE);
int blocks;
int threads;
hipOccupancyMaxPotentialBlockSize (&blocks, &threads, calcWithoutAtomic1D, 0, GRAPH_SIZE*GRAPH_SIZE);
//blocks = sqrt(blocks);
//threads = sqrt(threads);
int workPerThread = ((GRAPH_SIZE*GRAPH_SIZE) / (threads*blocks));// + 1;
printf("workPerThread= %d, blocks= %d threadsPerBlocks = %d\n", workPerThread, blocks, threads);
int* syncGrid;
hipMalloc(&syncGrid, sizeof(int) * blocks);
for (int k = 0; k < GRAPH_SIZE; k++) {
calcWithoutAtomic1D <<<blocks, threads>>> (dev_a, k);
}
//calcWithAtomic1D<<<blocks, threads>>> (dev_a, syncGrid);
//calcWithAtomic1DShared<<<blocks, threads>>> (dev_a, syncGrid);
hipError_t err = hipMemcpy(output, dev_a, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE, hipMemcpyDeviceToHost);
gpuErrchk(err);
hipFree(dev_a);
hipFree(syncGrid);//teste
}
void floyd_warshall_cpu(const int* graph, int* output) {
int i, j, k;
for (k = 0; k < GRAPH_SIZE; k++) {
for (i = 0; i < GRAPH_SIZE; i++) {
for (j = 0; j < GRAPH_SIZE; j++) {
if (D(i, k) + D(k, j) < D(i, j)) {
D(i, j) = D(i, k) + D(k, j);
}
}
}
}
}
int main(int argc, char** argv) {
/*
LARGE_INTEGER frequency;
LARGE_INTEGER start;
LARGE_INTEGER end;
double interval;*/
#define TIMER_START() gettimeofday(&tv1, NULL)
#define TIMER_STOP() \
gettimeofday(&tv2, NULL); \
timersub(&tv2, &tv1, &tv); \
time_delta = (float)tv.tv_sec + tv.tv_usec / 1000000.0
struct timeval tv1, tv2, tv;
float time_delta;
int* graph, * output_cpu, * output_gpu;
int size;
size = sizeof(int) * GRAPH_SIZE * GRAPH_SIZE;
graph = (int*)malloc(size);
assert(graph);
output_cpu = (int*)malloc(size);
assert(output_cpu);
memset(output_cpu, 0, size);
output_gpu = (int*)malloc(size);
assert(output_gpu);
generate_random_graph(graph);
fprintf(stderr, "running on cpu...\n");
TIMER_START();
memcpy(output_cpu, graph, sizeof(int) * GRAPH_SIZE * GRAPH_SIZE);
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_cpu(graph, output_cpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
fprintf(stderr, "running on gpu...\n");
TIMER_START();
//QueryPerformanceFrequency(&frequency);
//QueryPerformanceCounter(&start);
floyd_warshall_gpu(graph, output_gpu);
TIMER_STOP();
fprintf(stderr, "%f seconds\n", time_delta);
//QueryPerformanceCounter(&end);
//interval = (double)(end.QuadPart - start.QuadPart) / frequency.QuadPart;
//fprintf(stderr, "%f seconds\n", interval);
if (memcmp(output_cpu, output_gpu, size) != 0) {
fprintf(stderr, "FAIL!\n");
}
else {
fprintf(stderr, "Verified!\n");
}
return 0;
} | .text
.file "cuda_FW.hip"
.globl _Z21generate_random_graphPi # -- Begin function _Z21generate_random_graphPi
.p2align 4, 0x90
.type _Z21generate_random_graphPi,@function
_Z21generate_random_graphPi: # @_Z21generate_random_graphPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $-623191334, %edi # imm = 0xDADADADA
callq srand
xorl %r14d, %r14d
movl $536870911, %ebp # imm = 0x1FFFFFFF
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24576, %rbx # imm = 0x6000
cmpq $6144, %r14 # imm = 0x1800
je .LBB0_6
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=2
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $6144, %r15 # imm = 0x1800
je .LBB0_5
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpq %r15, %r14
je .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
shll $3, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
cmpl $21, %eax
cmovgel %ebp, %eax
jmp .LBB0_4
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21generate_random_graphPi, .Lfunc_end0-_Z21generate_random_graphPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__calculateSequencialGPUPi # -- Begin function _Z37__device_stub__calculateSequencialGPUPi
.p2align 4, 0x90
.type _Z37__device_stub__calculateSequencialGPUPi,@function
_Z37__device_stub__calculateSequencialGPUPi: # @_Z37__device_stub__calculateSequencialGPUPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z22calculateSequencialGPUPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z37__device_stub__calculateSequencialGPUPi, .Lfunc_end1-_Z37__device_stub__calculateSequencialGPUPi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcWithoutAtomic1DPii # -- Begin function _Z34__device_stub__calcWithoutAtomic1DPii
.p2align 4, 0x90
.type _Z34__device_stub__calcWithoutAtomic1DPii,@function
_Z34__device_stub__calcWithoutAtomic1DPii: # @_Z34__device_stub__calcWithoutAtomic1DPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19calcWithoutAtomic1DPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z34__device_stub__calcWithoutAtomic1DPii, .Lfunc_end2-_Z34__device_stub__calcWithoutAtomic1DPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__calcWithAtomic1DPiS_ # -- Begin function _Z31__device_stub__calcWithAtomic1DPiS_
.p2align 4, 0x90
.type _Z31__device_stub__calcWithAtomic1DPiS_,@function
_Z31__device_stub__calcWithAtomic1DPiS_: # @_Z31__device_stub__calcWithAtomic1DPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16calcWithAtomic1DPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z31__device_stub__calcWithAtomic1DPiS_, .Lfunc_end3-_Z31__device_stub__calcWithAtomic1DPiS_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcWithAtomic1DMemPiS_ # -- Begin function _Z34__device_stub__calcWithAtomic1DMemPiS_
.p2align 4, 0x90
.type _Z34__device_stub__calcWithAtomic1DMemPiS_,@function
_Z34__device_stub__calcWithAtomic1DMemPiS_: # @_Z34__device_stub__calcWithAtomic1DMemPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19calcWithAtomic1DMemPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z34__device_stub__calcWithAtomic1DMemPiS_, .Lfunc_end4-_Z34__device_stub__calcWithAtomic1DMemPiS_
.cfi_endproc
# -- End function
.globl _Z18floyd_warshall_gpuPKiPi # -- Begin function _Z18floyd_warshall_gpuPKiPi
.p2align 4, 0x90
.type _Z18floyd_warshall_gpuPKiPi,@function
_Z18floyd_warshall_gpuPKiPi: # @_Z18floyd_warshall_gpuPKiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, %r14
movabsq $4294967296, %rbx # imm = 0x100000000
leaq 8(%rsp), %rdi
movl $150994944, %esi # imm = 0x9000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $150994944, %edx # imm = 0x9000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rsp, %rdi
leaq 4(%rsp), %rsi
movl $_Z19calcWithoutAtomic1DPii, %edx
xorl %ecx, %ecx
movl $37748736, %r8d # imm = 0x2400000
callq hipOccupancyMaxPotentialBlockSize
movl 4(%rsp), %ecx
movl (%rsp), %r8d
movl %r8d, %esi
imull %ecx, %esi
movl $37748736, %eax # imm = 0x2400000
xorl %edx, %edx
idivl %esi
movl $.L.str, %edi
movl %eax, %esi
movl %r8d, %edx
xorl %eax, %eax
callq printf
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
leaq 56(%rsp), %r15
leaq 48(%rsp), %r12
leaq 40(%rsp), %r13
leaq 96(%rsp), %rbp
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_3: # in Loop: Header=BB5_1 Depth=1
incl %r14d
cmpl $6144, %r14d # imm = 0x1800
je .LBB5_4
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl (%rsp), %edi
movl 4(%rsp), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_3
# %bb.2: # in Loop: Header=BB5_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19calcWithoutAtomic1DPii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_3
.LBB5_4:
movq 8(%rsp), %rsi
movl $150994944, %edx # imm = 0x9000000
movq 24(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_6
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_6:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $207, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end5:
.size _Z18floyd_warshall_gpuPKiPi, .Lfunc_end5-_Z18floyd_warshall_gpuPKiPi
.cfi_endproc
# -- End function
.globl _Z18floyd_warshall_cpuPKiPi # -- Begin function _Z18floyd_warshall_cpuPKiPi
.p2align 4, 0x90
.type _Z18floyd_warshall_cpuPKiPi,@function
_Z18floyd_warshall_cpuPKiPi: # @_Z18floyd_warshall_cpuPKiPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movq %rsi, %rcx
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
incq %rax
addq $24576, %rcx # imm = 0x6000
cmpq $6144, %rax # imm = 0x1800
je .LBB6_8
.LBB6_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
leaq (%rsi,%rax,4), %rdx
movq %rsi, %rdi
xorl %r8d, %r8d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_2 Depth=2
incq %r8
addq $24576, %rdi # imm = 0x6000
cmpq $6144, %r8 # imm = 0x1800
je .LBB6_7
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
movq %r8, %r9
shlq $11, %r9
leaq (%r9,%r9,2), %r9
xorl %r10d, %r10d
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_5: # in Loop: Header=BB6_3 Depth=3
incq %r10
cmpq $6144, %r10 # imm = 0x1800
je .LBB6_6
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rcx,%r10,4), %r11d
addl (%rdx,%r9,4), %r11d
cmpl (%rdi,%r10,4), %r11d
jge .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=3
movl %r11d, (%rdi,%r10,4)
jmp .LBB6_5
.LBB6_8:
retq
.Lfunc_end6:
.size _Z18floyd_warshall_cpuPKiPi, .Lfunc_end6-_Z18floyd_warshall_cpuPKiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, %r15
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
movl $150994944, %edx # imm = 0x9000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movl $-623191334, %edi # imm = 0xDADADADA
callq srand
movl $536870911, %ebp # imm = 0x1FFFFFFF
movq %r15, %r13
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_1 Depth=1
incq %r12
addq $24576, %r13 # imm = 0x6000
cmpq $6144, %r12 # imm = 0x1800
je .LBB7_6
.LBB7_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
xorl %r14d, %r14d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_4: # in Loop: Header=BB7_2 Depth=2
movl %eax, (%r13,%r14,4)
incq %r14
cmpq $6144, %r14 # imm = 0x1800
je .LBB7_5
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpq %r14, %r12
je .LBB7_4
# %bb.3: # in Loop: Header=BB7_2 Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
shll $3, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
cmpl $21, %eax
cmovgel %ebp, %eax
jmp .LBB7_4
.LBB7_6: # %_Z21generate_random_graphPi.exit
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $150994944, %edx # imm = 0x9000000
movq %rbx, %rdi
movq %r15, %rsi
callq memcpy@PLT
movq %rbx, %rax
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_13: # in Loop: Header=BB7_7 Depth=1
incq %r12
addq $24576, %rax # imm = 0x6000
cmpq $6144, %r12 # imm = 0x1800
je .LBB7_14
.LBB7_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB7_8 Depth 2
# Child Loop BB7_9 Depth 3
leaq (%rbx,%r12,4), %rcx
movq %rbx, %rdx
xorl %esi, %esi
jmp .LBB7_8
.p2align 4, 0x90
.LBB7_12: # in Loop: Header=BB7_8 Depth=2
incq %rsi
addq $24576, %rdx # imm = 0x6000
cmpq $6144, %rsi # imm = 0x1800
je .LBB7_13
.LBB7_8: # %.preheader.i26
# Parent Loop BB7_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_9 Depth 3
movq %rsi, %rdi
shlq $11, %rdi
leaq (%rdi,%rdi,2), %rdi
xorl %r8d, %r8d
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_11: # in Loop: Header=BB7_9 Depth=3
incq %r8
cmpq $6144, %r8 # imm = 0x1800
je .LBB7_12
.LBB7_9: # Parent Loop BB7_7 Depth=1
# Parent Loop BB7_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rax,%r8,4), %r9d
addl (%rcx,%rdi,4), %r9d
cmpl (%rdx,%r8,4), %r9d
jge .LBB7_11
# %bb.10: # in Loop: Header=BB7_9 Depth=3
movl %r9d, (%rdx,%r8,4)
jmp .LBB7_11
.LBB7_14: # %_Z18floyd_warshall_cpuPKiPi.exit
leaq 16(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq (%rsp), %rax
subq 8(%rsp), %rcx
leaq 1000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cvtsi2ss %rsi, %xmm0
cmovnsq %rcx, %rdx
cvtsi2sd %rdx, %xmm1
cvtss2sd %xmm0, %xmm0
divsd .LCPI7_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stderr(%rip), %rdi
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq %r15, %rdi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq _Z18floyd_warshall_gpuPKiPi
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq (%rsp), %rax
subq 8(%rsp), %rcx
leaq 1000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rsi, %xmm0
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rdx, %xmm1
divsd .LCPI7_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stderr(%rip), %rdi
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movl $150994944, %edx # imm = 0x9000000
movq %rbx, %rdi
movq %r14, %rsi
callq bcmp@PLT
movq stderr(%rip), %rcx
testl %eax, %eax
jne .LBB7_15
# %bb.16:
movl $.L.str.6, %edi
movl $10, %esi
jmp .LBB7_17
.LBB7_15:
movl $.L.str.5, %edi
movl $6, %esi
.LBB7_17:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22calculateSequencialGPUPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcWithoutAtomic1DPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16calcWithAtomic1DPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcWithAtomic1DMemPiS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22calculateSequencialGPUPi,@object # @_Z22calculateSequencialGPUPi
.section .rodata,"a",@progbits
.globl _Z22calculateSequencialGPUPi
.p2align 3, 0x0
_Z22calculateSequencialGPUPi:
.quad _Z37__device_stub__calculateSequencialGPUPi
.size _Z22calculateSequencialGPUPi, 8
.type _Z19calcWithoutAtomic1DPii,@object # @_Z19calcWithoutAtomic1DPii
.globl _Z19calcWithoutAtomic1DPii
.p2align 3, 0x0
_Z19calcWithoutAtomic1DPii:
.quad _Z34__device_stub__calcWithoutAtomic1DPii
.size _Z19calcWithoutAtomic1DPii, 8
.type _Z16calcWithAtomic1DPiS_,@object # @_Z16calcWithAtomic1DPiS_
.globl _Z16calcWithAtomic1DPiS_
.p2align 3, 0x0
_Z16calcWithAtomic1DPiS_:
.quad _Z31__device_stub__calcWithAtomic1DPiS_
.size _Z16calcWithAtomic1DPiS_, 8
.type _Z19calcWithAtomic1DMemPiS_,@object # @_Z19calcWithAtomic1DMemPiS_
.globl _Z19calcWithAtomic1DMemPiS_
.p2align 3, 0x0
_Z19calcWithAtomic1DMemPiS_:
.quad _Z34__device_stub__calcWithAtomic1DMemPiS_
.size _Z19calcWithAtomic1DMemPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "workPerThread= %d, blocks= %d threadsPerBlocks = %d\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/pedrocarrega/projectPCM/master/project/cuda_FW.hip"
.size .L.str.1, 108
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "running on cpu...\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f seconds\n"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "running on gpu...\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "FAIL!\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Verified!\n"
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22calculateSequencialGPUPi"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcWithoutAtomic1DPii"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16calcWithAtomic1DPiS_"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z19calcWithAtomic1DMemPiS_"
.size .L__unnamed_4, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__calculateSequencialGPUPi
.addrsig_sym _Z34__device_stub__calcWithoutAtomic1DPii
.addrsig_sym _Z31__device_stub__calcWithAtomic1DPiS_
.addrsig_sym _Z34__device_stub__calcWithAtomic1DMemPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22calculateSequencialGPUPi
.addrsig_sym _Z19calcWithoutAtomic1DPii
.addrsig_sym _Z16calcWithAtomic1DPiS_
.addrsig_sym _Z19calcWithAtomic1DMemPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010d211_00000000-6_cuda_FW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21generate_random_graphPi
.type _Z21generate_random_graphPi, @function
_Z21generate_random_graphPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movl $-623191334, %edi
call srand@PLT
movl $0, %r13d
movl $6144, %r12d
movl $0, %ebp
movl $536870911, %r15d
jmp .L4
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
sall $3, %ecx
subl %ecx, %eax
movl %eax, %edx
cmpl $21, %eax
cmovge %r15d, %edx
movslq %ebx, %rax
movl %edx, (%r14,%rax,4)
.L6:
addl $1, %ebx
cmpl %r12d, %ebx
je .L13
.L8:
leal (%rbx,%r13), %eax
cmpl %eax, %ebp
jne .L5
movslq %ebx, %rax
movl $0, (%r14,%rax,4)
jmp .L6
.L13:
addl $1, %ebp
addl $6144, %r12d
subl $6144, %r13d
cmpl $6144, %ebp
je .L3
.L4:
leal -6144(%r12), %ebx
jmp .L8
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21generate_random_graphPi, .-_Z21generate_random_graphPi
.globl _Z18floyd_warshall_cpuPKiPi
.type _Z18floyd_warshall_cpuPKiPi, @function
_Z18floyd_warshall_cpuPKiPi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r11
movq %rsi, %rbp
movl $0, %r9d
movl $0, %ebx
leaq 151019520(%rsi), %r10
jmp .L15
.L16:
addq $4, %rax
cmpq %rsi, %rax
je .L23
.L17:
leaq (%rax,%rdi), %rcx
movl (%r8), %edx
addl (%rcx,%r9), %edx
cmpl (%rax), %edx
jge .L16
movl %edx, (%rax)
jmp .L16
.L23:
addq $24576, %rsi
addq $24576, %r8
subq $24576, %rdi
cmpq %r10, %rsi
je .L18
.L20:
leaq -24576(%rsi), %rax
jmp .L17
.L18:
addl $1, %ebx
addq $24576, %r9
addq $4, %rbp
cmpl $6144, %ebx
je .L14
.L15:
leaq 24576(%r11), %rsi
movq %rbp, %r8
movl $0, %edi
jmp .L20
.L14:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z18floyd_warshall_cpuPKiPi, .-_Z18floyd_warshall_cpuPKiPi
.globl _Z42__device_stub__Z22calculateSequencialGPUPiPi
.type _Z42__device_stub__Z22calculateSequencialGPUPiPi, @function
_Z42__device_stub__Z22calculateSequencialGPUPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22calculateSequencialGPUPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z22calculateSequencialGPUPiPi, .-_Z42__device_stub__Z22calculateSequencialGPUPiPi
.globl _Z22calculateSequencialGPUPi
.type _Z22calculateSequencialGPUPi, @function
_Z22calculateSequencialGPUPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z22calculateSequencialGPUPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22calculateSequencialGPUPi, .-_Z22calculateSequencialGPUPi
.globl _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
.type _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii, @function
_Z40__device_stub__Z19calcWithoutAtomic1DPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii, .-_Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
.globl _Z19calcWithoutAtomic1DPii
.type _Z19calcWithoutAtomic1DPii, @function
_Z19calcWithoutAtomic1DPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19calcWithoutAtomic1DPii, .-_Z19calcWithoutAtomic1DPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "workPerThread= %d, blocks= %d threadsPerBlocks = %d\n"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/pedrocarrega/projectPCM/master/project/cuda_FW.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z18floyd_warshall_gpuPKiPi
.type _Z18floyd_warshall_gpuPKiPi, @function
_Z18floyd_warshall_gpuPKiPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rdi, %r13
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rdi
movl $150994944, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $150994944, %edx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 44(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L56
.L41:
movl %ebx, %ecx
imull %ebp, %ecx
movl $37748736, %eax
movl $0, %edx
idivl %ecx
movl %ebp, %r8d
movl %ebx, %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %r13d
jmp .L46
.L56:
leaq 48(%rsp), %rdi
movl 44(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 52(%rsp), %rdi
movl 44(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 64(%rsp), %rdi
movl 44(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 72(%rsp), %rdi
movl 44(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L41
leaq 96(%rsp), %rdi
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L41
movl 48(%rsp), %eax
movl %eax, 24(%rsp)
movl 52(%rsp), %r15d
movl 120(%rsp), %r14d
movl 64(%rsp), %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
movl $37748736, %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
leal -1(%r15,%r14), %eax
cltd
idivl %r15d
imull %r15d, %eax
movl %eax, %r13d
testl %eax, %eax
jle .L49
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movl %ebx, 28(%rsp)
jmp .L44
.L43:
movl 12(%rsp), %edx
cmpl %edx, 24(%rsp)
je .L42
subl %r15d, %r13d
testl %r13d, %r13d
jle .L42
.L44:
cmpl %r14d, %r13d
movl %r14d, %ebx
cmovle %r13d, %ebx
leaq 84(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L53
movl 84(%rsp), %eax
movl %ebx, %edx
imull %eax, %edx
cmpl %edx, 12(%rsp)
jge .L43
movl %edx, 12(%rsp)
movl %eax, 20(%rsp)
movl %ebx, 16(%rsp)
jmp .L43
.L49:
movl $0, 20(%rsp)
movl $0, 16(%rsp)
.L42:
movl 20(%rsp), %ebx
imull 72(%rsp), %ebx
movl 16(%rsp), %ebp
jmp .L41
.L53:
movl 28(%rsp), %ebx
jmp .L41
.L45:
addl $1, %r13d
cmpl $6144, %r13d
je .L57
.L46:
movl %ebp, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl %ebx, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movl %r13d, %esi
movq 56(%rsp), %rdi
call _Z40__device_stub__Z19calcWithoutAtomic1DPiiPii
jmp .L45
.L57:
movl $2, %ecx
movl $150994944, %edx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $207, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18floyd_warshall_gpuPKiPi, .-_Z18floyd_warshall_gpuPKiPi
.section .rodata.str1.1
.LC3:
.string "running on cpu...\n"
.LC5:
.string "%f seconds\n"
.LC6:
.string "running on gpu...\n"
.LC7:
.string "FAIL!\n"
.LC8:
.string "Verified!\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $150994944, %edi
call malloc@PLT
movq %rax, %r12
movl $150994944, %edi
call malloc@PLT
movq %rax, %rbx
movl $150994944, %edi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Z21generate_random_graphPi
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $150994944, %edx
movq %r12, %rsi
movq %rbx, %rdi
call memcpy@PLT
movq %rbx, %rsi
movq %r12, %rdi
call _Z18floyd_warshall_cpuPKiPi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rdx
subq (%rsp), %rdx
movq 24(%rsp), %rax
subq 8(%rsp), %rax
js .L67
.L61:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z18floyd_warshall_gpuPKiPi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rdx
subq (%rsp), %rdx
movq 24(%rsp), %rax
subq 8(%rsp), %rax
js .L68
.L62:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $150994944, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call memcmp@PLT
testl %eax, %eax
je .L63
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L64:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
subq $1, %rdx
addq $1000000, %rax
jmp .L61
.L68:
subq $1, %rdx
addq $1000000, %rax
jmp .L62
.L63:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.globl _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
.type _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_, @function
_Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L74
.L70:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16calcWithAtomic1DPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L70
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_, .-_Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
.globl _Z16calcWithAtomic1DPiS_
.type _Z16calcWithAtomic1DPiS_, @function
_Z16calcWithAtomic1DPiS_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16calcWithAtomic1DPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z16calcWithAtomic1DPiS_, .-_Z16calcWithAtomic1DPiS_
.globl _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
.type _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_, @function
_Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L82
.L78:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L83
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19calcWithAtomic1DMemPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L78
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_, .-_Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
.globl _Z19calcWithAtomic1DMemPiS_
.type _Z19calcWithAtomic1DMemPiS_, @function
_Z19calcWithAtomic1DMemPiS_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19calcWithAtomic1DMemPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19calcWithAtomic1DMemPiS_, .-_Z19calcWithAtomic1DMemPiS_
.section .rodata.str1.1
.LC9:
.string "_Z19calcWithAtomic1DMemPiS_"
.LC10:
.string "_Z16calcWithAtomic1DPiS_"
.LC11:
.string "_Z19calcWithoutAtomic1DPii"
.LC12:
.string "_Z22calculateSequencialGPUPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcWithAtomic1DMemPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16calcWithAtomic1DPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcWithoutAtomic1DPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z22calculateSequencialGPUPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_FW.hip"
.globl _Z21generate_random_graphPi # -- Begin function _Z21generate_random_graphPi
.p2align 4, 0x90
.type _Z21generate_random_graphPi,@function
_Z21generate_random_graphPi: # @_Z21generate_random_graphPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $-623191334, %edi # imm = 0xDADADADA
callq srand
xorl %r14d, %r14d
movl $536870911, %ebp # imm = 0x1FFFFFFF
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24576, %rbx # imm = 0x6000
cmpq $6144, %r14 # imm = 0x1800
je .LBB0_6
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=2
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $6144, %r15 # imm = 0x1800
je .LBB0_5
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpq %r15, %r14
je .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
shll $3, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
cmpl $21, %eax
cmovgel %ebp, %eax
jmp .LBB0_4
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21generate_random_graphPi, .Lfunc_end0-_Z21generate_random_graphPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__calculateSequencialGPUPi # -- Begin function _Z37__device_stub__calculateSequencialGPUPi
.p2align 4, 0x90
.type _Z37__device_stub__calculateSequencialGPUPi,@function
_Z37__device_stub__calculateSequencialGPUPi: # @_Z37__device_stub__calculateSequencialGPUPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z22calculateSequencialGPUPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z37__device_stub__calculateSequencialGPUPi, .Lfunc_end1-_Z37__device_stub__calculateSequencialGPUPi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcWithoutAtomic1DPii # -- Begin function _Z34__device_stub__calcWithoutAtomic1DPii
.p2align 4, 0x90
.type _Z34__device_stub__calcWithoutAtomic1DPii,@function
_Z34__device_stub__calcWithoutAtomic1DPii: # @_Z34__device_stub__calcWithoutAtomic1DPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19calcWithoutAtomic1DPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z34__device_stub__calcWithoutAtomic1DPii, .Lfunc_end2-_Z34__device_stub__calcWithoutAtomic1DPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__calcWithAtomic1DPiS_ # -- Begin function _Z31__device_stub__calcWithAtomic1DPiS_
.p2align 4, 0x90
.type _Z31__device_stub__calcWithAtomic1DPiS_,@function
_Z31__device_stub__calcWithAtomic1DPiS_: # @_Z31__device_stub__calcWithAtomic1DPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16calcWithAtomic1DPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z31__device_stub__calcWithAtomic1DPiS_, .Lfunc_end3-_Z31__device_stub__calcWithAtomic1DPiS_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcWithAtomic1DMemPiS_ # -- Begin function _Z34__device_stub__calcWithAtomic1DMemPiS_
.p2align 4, 0x90
.type _Z34__device_stub__calcWithAtomic1DMemPiS_,@function
_Z34__device_stub__calcWithAtomic1DMemPiS_: # @_Z34__device_stub__calcWithAtomic1DMemPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19calcWithAtomic1DMemPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z34__device_stub__calcWithAtomic1DMemPiS_, .Lfunc_end4-_Z34__device_stub__calcWithAtomic1DMemPiS_
.cfi_endproc
# -- End function
.globl _Z18floyd_warshall_gpuPKiPi # -- Begin function _Z18floyd_warshall_gpuPKiPi
.p2align 4, 0x90
.type _Z18floyd_warshall_gpuPKiPi,@function
_Z18floyd_warshall_gpuPKiPi: # @_Z18floyd_warshall_gpuPKiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, %r14
movabsq $4294967296, %rbx # imm = 0x100000000
leaq 8(%rsp), %rdi
movl $150994944, %esi # imm = 0x9000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $150994944, %edx # imm = 0x9000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rsp, %rdi
leaq 4(%rsp), %rsi
movl $_Z19calcWithoutAtomic1DPii, %edx
xorl %ecx, %ecx
movl $37748736, %r8d # imm = 0x2400000
callq hipOccupancyMaxPotentialBlockSize
movl 4(%rsp), %ecx
movl (%rsp), %r8d
movl %r8d, %esi
imull %ecx, %esi
movl $37748736, %eax # imm = 0x2400000
xorl %edx, %edx
idivl %esi
movl $.L.str, %edi
movl %eax, %esi
movl %r8d, %edx
xorl %eax, %eax
callq printf
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
leaq 56(%rsp), %r15
leaq 48(%rsp), %r12
leaq 40(%rsp), %r13
leaq 96(%rsp), %rbp
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_3: # in Loop: Header=BB5_1 Depth=1
incl %r14d
cmpl $6144, %r14d # imm = 0x1800
je .LBB5_4
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl (%rsp), %edi
movl 4(%rsp), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_3
# %bb.2: # in Loop: Header=BB5_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19calcWithoutAtomic1DPii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_3
.LBB5_4:
movq 8(%rsp), %rsi
movl $150994944, %edx # imm = 0x9000000
movq 24(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_6
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_6:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $207, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end5:
.size _Z18floyd_warshall_gpuPKiPi, .Lfunc_end5-_Z18floyd_warshall_gpuPKiPi
.cfi_endproc
# -- End function
.globl _Z18floyd_warshall_cpuPKiPi # -- Begin function _Z18floyd_warshall_cpuPKiPi
.p2align 4, 0x90
.type _Z18floyd_warshall_cpuPKiPi,@function
_Z18floyd_warshall_cpuPKiPi: # @_Z18floyd_warshall_cpuPKiPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movq %rsi, %rcx
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
incq %rax
addq $24576, %rcx # imm = 0x6000
cmpq $6144, %rax # imm = 0x1800
je .LBB6_8
.LBB6_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
leaq (%rsi,%rax,4), %rdx
movq %rsi, %rdi
xorl %r8d, %r8d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_2 Depth=2
incq %r8
addq $24576, %rdi # imm = 0x6000
cmpq $6144, %r8 # imm = 0x1800
je .LBB6_7
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
movq %r8, %r9
shlq $11, %r9
leaq (%r9,%r9,2), %r9
xorl %r10d, %r10d
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_5: # in Loop: Header=BB6_3 Depth=3
incq %r10
cmpq $6144, %r10 # imm = 0x1800
je .LBB6_6
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rcx,%r10,4), %r11d
addl (%rdx,%r9,4), %r11d
cmpl (%rdi,%r10,4), %r11d
jge .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=3
movl %r11d, (%rdi,%r10,4)
jmp .LBB6_5
.LBB6_8:
retq
.Lfunc_end6:
.size _Z18floyd_warshall_cpuPKiPi, .Lfunc_end6-_Z18floyd_warshall_cpuPKiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, %r15
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
movl $150994944, %edx # imm = 0x9000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $150994944, %edi # imm = 0x9000000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movl $-623191334, %edi # imm = 0xDADADADA
callq srand
movl $536870911, %ebp # imm = 0x1FFFFFFF
movq %r15, %r13
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_1 Depth=1
incq %r12
addq $24576, %r13 # imm = 0x6000
cmpq $6144, %r12 # imm = 0x1800
je .LBB7_6
.LBB7_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
xorl %r14d, %r14d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_4: # in Loop: Header=BB7_2 Depth=2
movl %eax, (%r13,%r14,4)
incq %r14
cmpq $6144, %r14 # imm = 0x1800
je .LBB7_5
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpq %r14, %r12
je .LBB7_4
# %bb.3: # in Loop: Header=BB7_2 Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
shll $3, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
cmpl $21, %eax
cmovgel %ebp, %eax
jmp .LBB7_4
.LBB7_6: # %_Z21generate_random_graphPi.exit
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $150994944, %edx # imm = 0x9000000
movq %rbx, %rdi
movq %r15, %rsi
callq memcpy@PLT
movq %rbx, %rax
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_13: # in Loop: Header=BB7_7 Depth=1
incq %r12
addq $24576, %rax # imm = 0x6000
cmpq $6144, %r12 # imm = 0x1800
je .LBB7_14
.LBB7_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB7_8 Depth 2
# Child Loop BB7_9 Depth 3
leaq (%rbx,%r12,4), %rcx
movq %rbx, %rdx
xorl %esi, %esi
jmp .LBB7_8
.p2align 4, 0x90
.LBB7_12: # in Loop: Header=BB7_8 Depth=2
incq %rsi
addq $24576, %rdx # imm = 0x6000
cmpq $6144, %rsi # imm = 0x1800
je .LBB7_13
.LBB7_8: # %.preheader.i26
# Parent Loop BB7_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_9 Depth 3
movq %rsi, %rdi
shlq $11, %rdi
leaq (%rdi,%rdi,2), %rdi
xorl %r8d, %r8d
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_11: # in Loop: Header=BB7_9 Depth=3
incq %r8
cmpq $6144, %r8 # imm = 0x1800
je .LBB7_12
.LBB7_9: # Parent Loop BB7_7 Depth=1
# Parent Loop BB7_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rax,%r8,4), %r9d
addl (%rcx,%rdi,4), %r9d
cmpl (%rdx,%r8,4), %r9d
jge .LBB7_11
# %bb.10: # in Loop: Header=BB7_9 Depth=3
movl %r9d, (%rdx,%r8,4)
jmp .LBB7_11
.LBB7_14: # %_Z18floyd_warshall_cpuPKiPi.exit
leaq 16(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq (%rsp), %rax
subq 8(%rsp), %rcx
leaq 1000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cvtsi2ss %rsi, %xmm0
cmovnsq %rcx, %rdx
cvtsi2sd %rdx, %xmm1
cvtss2sd %xmm0, %xmm0
divsd .LCPI7_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stderr(%rip), %rdi
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq %r15, %rdi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq _Z18floyd_warshall_gpuPKiPi
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq (%rsp), %rax
subq 8(%rsp), %rcx
leaq 1000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rsi, %xmm0
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rdx, %xmm1
divsd .LCPI7_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stderr(%rip), %rdi
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movl $150994944, %edx # imm = 0x9000000
movq %rbx, %rdi
movq %r14, %rsi
callq bcmp@PLT
movq stderr(%rip), %rcx
testl %eax, %eax
jne .LBB7_15
# %bb.16:
movl $.L.str.6, %edi
movl $10, %esi
jmp .LBB7_17
.LBB7_15:
movl $.L.str.5, %edi
movl $6, %esi
.LBB7_17:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22calculateSequencialGPUPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcWithoutAtomic1DPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16calcWithAtomic1DPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcWithAtomic1DMemPiS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22calculateSequencialGPUPi,@object # @_Z22calculateSequencialGPUPi
.section .rodata,"a",@progbits
.globl _Z22calculateSequencialGPUPi
.p2align 3, 0x0
_Z22calculateSequencialGPUPi:
.quad _Z37__device_stub__calculateSequencialGPUPi
.size _Z22calculateSequencialGPUPi, 8
.type _Z19calcWithoutAtomic1DPii,@object # @_Z19calcWithoutAtomic1DPii
.globl _Z19calcWithoutAtomic1DPii
.p2align 3, 0x0
_Z19calcWithoutAtomic1DPii:
.quad _Z34__device_stub__calcWithoutAtomic1DPii
.size _Z19calcWithoutAtomic1DPii, 8
.type _Z16calcWithAtomic1DPiS_,@object # @_Z16calcWithAtomic1DPiS_
.globl _Z16calcWithAtomic1DPiS_
.p2align 3, 0x0
_Z16calcWithAtomic1DPiS_:
.quad _Z31__device_stub__calcWithAtomic1DPiS_
.size _Z16calcWithAtomic1DPiS_, 8
.type _Z19calcWithAtomic1DMemPiS_,@object # @_Z19calcWithAtomic1DMemPiS_
.globl _Z19calcWithAtomic1DMemPiS_
.p2align 3, 0x0
_Z19calcWithAtomic1DMemPiS_:
.quad _Z34__device_stub__calcWithAtomic1DMemPiS_
.size _Z19calcWithAtomic1DMemPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "workPerThread= %d, blocks= %d threadsPerBlocks = %d\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/pedrocarrega/projectPCM/master/project/cuda_FW.hip"
.size .L.str.1, 108
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "running on cpu...\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f seconds\n"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "running on gpu...\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "FAIL!\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Verified!\n"
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22calculateSequencialGPUPi"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcWithoutAtomic1DPii"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16calcWithAtomic1DPiS_"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z19calcWithAtomic1DMemPiS_"
.size .L__unnamed_4, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__calculateSequencialGPUPi
.addrsig_sym _Z34__device_stub__calcWithoutAtomic1DPii
.addrsig_sym _Z31__device_stub__calcWithAtomic1DPiS_
.addrsig_sym _Z34__device_stub__calcWithAtomic1DMemPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22calculateSequencialGPUPi
.addrsig_sym _Z19calcWithoutAtomic1DPii
.addrsig_sym _Z16calcWithAtomic1DPiS_
.addrsig_sym _Z19calcWithAtomic1DMemPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe | .file "tmpxft_001054af_00000000-6_clusters_triplet_loss_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype margin, const Dtype* pos_data,const Dtype* neg_data,
// Dtype* vec_loss) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int ind_a = index / (batch_size * batch_size);
// const int ind_p = (index % (batch_size * batch_size)) / batch_size;
// const int ind_n = index % batch_size;
//
// Dtype dpa(0.0), dna(0.0), t;
// for (int i = 0; i < dim; i++)
// {
// t = pos_data[ind_p * dim + i] - pos_data[ind_a * dim + i];
// dpa += t * t;
// t = neg_data[ind_n * dim + i] - pos_data[ind_a * dim + i];
// dna += t * t;
// }
// vec_loss[index] = max(Dtype(0), dpa + margin - dna);
// }
// }
//
// template <typename Dtype>
// __global__ void ClustersTripletBackward(const int nthreads, const int batch_size,
// const int dim, const Dtype* pos_data, const Dtype* neg_data, const Dtype* vec_loss,
// Dtype* pos_diff, Dtype* neg_diff) {
//
// CUDA_KERNEL_LOOP(index, nthreads) {
// const int item = index / dim;
// const int k = index % dim;
//
// Dtype diff;
// for (int i = 0; i < batch_size; i++)
// {
// for (int j = 0; j < batch_size; j++)
// {
// if (vec_loss[(item * batch_size + i) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += neg_data[j * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + item) * batch_size + j] > 0)
// {
// pos_diff[item * dim + k] += pos_data[item * dim + k] - pos_data[i * dim + k];
// }
//
// if (vec_loss[(i * batch_size + j) * batch_size + item] > 0)
// {
// neg_diff[item * dim + k] += pos_data[i * dim + k] - neg_data[item * dim + k];
// }
// }
// }
// }
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Forward_gpu(
// const vector<Blob<Dtype>*>& bottom,
// const vector<Blob<Dtype>*>& top) {
//
// //ClustersTripletLossLayer<Dtype>::Forward_cpu(bottom, top);
//
// Dtype margin = this->layer_param_.contrastive_loss_param().margin();
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// Dtype* vec_loss = vec_loss_.mutable_gpu_data();
// Dtype nthreads = batch_size * batch_size * batch_size;
// caffe_gpu_set(vec_loss_.count(), Dtype(0), vec_loss);
// ClustersTripletForward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, margin, pos_data, neg_data, vec_loss);
//
// Dtype loss(0.0);
// for (int i = 0; i < vec_loss_.count(); i++)
// {
// loss += vec_loss_.cpu_data()[i];
// }
// top[0]->mutable_cpu_data()[0] = loss / batch_size / 2;
// }
//
// template <typename Dtype>
// void ClustersTripletLossLayer<Dtype>::Backward_gpu(const vector<Blob<Dtype>*>& top,
// const vector<bool>& propagate_down, const vector<Blob<Dtype>*>& bottom) {
//
// //ClustersTripletLossLayer<Dtype>::Backward_cpu(top, propagate_down, bottom);
//
// int batch_size = bottom[0]->num() / 2;
// int dim = bottom[0]->channels();
// const Dtype* pos_data = bottom[0]->gpu_data();
// const Dtype* neg_data = bottom[0]->gpu_data() + batch_size * dim;
// const Dtype* vec_loss = vec_loss_.gpu_data();
// Dtype* pos_diff = bottom[0]->mutable_gpu_diff();
// Dtype* neg_diff = bottom[0]->mutable_gpu_diff() + batch_size * dim;
// Dtype nthreads = batch_size * dim;
//
// if (propagate_down[0]) {
// caffe_gpu_set(bottom[0]->count(), Dtype(0), bottom[0]->mutable_gpu_diff());
// ClustersTripletBackward<Dtype> << <CAFFE_GET_BLOCKS(nthreads), CAFFE_CUDA_NUM_THREADS >> >(
// nthreads, batch_size, dim, pos_data, neg_data, vec_loss, pos_diff, neg_diff);
// const Dtype alpha = top[0]->cpu_diff()[0] / batch_size;
// caffe_gpu_scal(bottom[0]->count(), alpha, bottom[0]->mutable_gpu_diff());
// }
//
// }
//
//INSTANTIATE_LAYER_GPU_FUNCS(ClustersTripletLossLayer);
//
//} // namespace caffe | .text
.file "clusters_triplet_loss_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001054af_00000000-6_clusters_triplet_loss_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "clusters_triplet_loss_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .file "tmpxft_001a29b6_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "La la\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .text
.file "simple_hello.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "La la"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a29b6_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "La la\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_hello.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "La la"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} | code for sm_80
Function : _Z13cuda_add_impllPfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fc80003f06070 */
/*0030*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06300 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0060*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IADD3 R4, P0, R6.reuse, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x040fe40007f1e0ff */
/*0090*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fe40007f3e0ff */
/*00a0*/ IADD3.X R5, R0.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x040fe400007fe4ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fc80000ffe4ff */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000077a10 */
/* 0x000fe200007fe4ff */
/*0100*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} | .file "tmpxft_0011ecce_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
.type _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_, @function
_Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cuda_add_impllPfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_, .-_Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.type _Z13cuda_add_impllPfPKfS1_, @function
_Z13cuda_add_impllPfPKfS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13cuda_add_impllPfPKfS1_, .-_Z13cuda_add_impllPfPKfS1_
.globl _Z8cuda_addlPfPKfS1_
.type _Z8cuda_addlPfPKfS1_, @function
_Z8cuda_addlPfPKfS1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z8cuda_addlPfPKfS1_, .-_Z8cuda_addlPfPKfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13cuda_add_impllPfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuda_add_impllPfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cuda_add_impllPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 8
.type _Z13cuda_add_impllPfPKfS1_,@function
_Z13cuda_add_impllPfPKfS1_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cuda_add_impllPfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cuda_add_impllPfPKfS1_, .Lfunc_end0-_Z13cuda_add_impllPfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cuda_add_impllPfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z13cuda_add_impllPfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X[offset];
}
}
void cuda_add(int64_t N, float* O, const float* X, const float* Y) {
cuda_add_impl<<<1, 256>>>(N, O, X, Y);
} | .text
.file "cuda_add.hip"
.globl _Z28__device_stub__cuda_add_impllPfPKfS1_ # -- Begin function _Z28__device_stub__cuda_add_impllPfPKfS1_
.p2align 4, 0x90
.type _Z28__device_stub__cuda_add_impllPfPKfS1_,@function
_Z28__device_stub__cuda_add_impllPfPKfS1_: # @_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cuda_add_impllPfPKfS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__cuda_add_impllPfPKfS1_, .Lfunc_end0-_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_endproc
# -- End function
.globl _Z8cuda_addlPfPKfS1_ # -- Begin function _Z8cuda_addlPfPKfS1_
.p2align 4, 0x90
.type _Z8cuda_addlPfPKfS1_,@function
_Z8cuda_addlPfPKfS1_: # @_Z8cuda_addlPfPKfS1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cuda_add_impllPfPKfS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8cuda_addlPfPKfS1_, .Lfunc_end1-_Z8cuda_addlPfPKfS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cuda_add_impllPfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cuda_add_impllPfPKfS1_,@object # @_Z13cuda_add_impllPfPKfS1_
.section .rodata,"a",@progbits
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 3, 0x0
_Z13cuda_add_impllPfPKfS1_:
.quad _Z28__device_stub__cuda_add_impllPfPKfS1_
.size _Z13cuda_add_impllPfPKfS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13cuda_add_impllPfPKfS1_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cuda_add_impllPfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cuda_add_impllPfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cuda_add_impllPfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fc80003f06070 */
/*0030*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06300 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0060*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IADD3 R4, P0, R6.reuse, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x040fe40007f1e0ff */
/*0090*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fe40007f3e0ff */
/*00a0*/ IADD3.X R5, R0.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x040fe400007fe4ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fc80000ffe4ff */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000077a10 */
/* 0x000fe200007fe4ff */
/*0100*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cuda_add_impllPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 8
.type _Z13cuda_add_impllPfPKfS1_,@function
_Z13cuda_add_impllPfPKfS1_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cuda_add_impllPfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cuda_add_impllPfPKfS1_, .Lfunc_end0-_Z13cuda_add_impllPfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cuda_add_impllPfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z13cuda_add_impllPfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ecce_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
.type _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_, @function
_Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cuda_add_impllPfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_, .-_Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.type _Z13cuda_add_impllPfPKfS1_, @function
_Z13cuda_add_impllPfPKfS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13cuda_add_impllPfPKfS1_, .-_Z13cuda_add_impllPfPKfS1_
.globl _Z8cuda_addlPfPKfS1_
.type _Z8cuda_addlPfPKfS1_, @function
_Z8cuda_addlPfPKfS1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z40__device_stub__Z13cuda_add_impllPfPKfS1_lPfPKfS1_
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z8cuda_addlPfPKfS1_, .-_Z8cuda_addlPfPKfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13cuda_add_impllPfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuda_add_impllPfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_add.hip"
.globl _Z28__device_stub__cuda_add_impllPfPKfS1_ # -- Begin function _Z28__device_stub__cuda_add_impllPfPKfS1_
.p2align 4, 0x90
.type _Z28__device_stub__cuda_add_impllPfPKfS1_,@function
_Z28__device_stub__cuda_add_impllPfPKfS1_: # @_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cuda_add_impllPfPKfS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__cuda_add_impllPfPKfS1_, .Lfunc_end0-_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_endproc
# -- End function
.globl _Z8cuda_addlPfPKfS1_ # -- Begin function _Z8cuda_addlPfPKfS1_
.p2align 4, 0x90
.type _Z8cuda_addlPfPKfS1_,@function
_Z8cuda_addlPfPKfS1_: # @_Z8cuda_addlPfPKfS1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cuda_add_impllPfPKfS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8cuda_addlPfPKfS1_, .Lfunc_end1-_Z8cuda_addlPfPKfS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cuda_add_impllPfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cuda_add_impllPfPKfS1_,@object # @_Z13cuda_add_impllPfPKfS1_
.section .rodata,"a",@progbits
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 3, 0x0
_Z13cuda_add_impllPfPKfS1_:
.quad _Z28__device_stub__cuda_add_impllPfPKfS1_
.size _Z13cuda_add_impllPfPKfS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13cuda_add_impllPfPKfS1_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cuda_add_impllPfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cuda_add_impllPfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
cudaError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
cudaMemcpyKind dir = cudaMemcpyHostToDevice;
if(rw == 'R')
{
dir = cudaMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - cudaMemcpyHostToDevice;
}
if(test == 'B')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = cudaFree(d_mem_pointer);
CHECK_ERR(err);
} | code for sm_80
Function : _Z8gpu_iopsm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
cudaError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
cudaMemcpyKind dir = cudaMemcpyHostToDevice;
if(rw == 'R')
{
dir = cudaMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - cudaMemcpyHostToDevice;
}
if(test == 'B')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = cudaFree(d_mem_pointer);
CHECK_ERR(err);
} | .file "tmpxft_000fd003_00000000-6_gpu_mem_bench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./benchCPU -n [number of threads]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r:t:"
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/abirylo/cs451/master/Project1/gpu_mem_bench.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC6:
.string "%c\t%c\t%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $82, %ebx
movl $66, %r14d
leaq .LC1(%rip), %r13
.L4:
movq %r13, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call getopt@PLT
cmpb $-1, %al
je .L38
cmpb $114, %al
je .L5
cmpb $116, %al
je .L6
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
.L3:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
movq optarg(%rip), %rax
movzbl (%rax), %ebx
jmp .L4
.L6:
movq optarg(%rip), %rax
movzbl (%rax), %r14d
jmp .L4
.L38:
cmpb $82, %bl
sete %r12b
movzbl %r12b, %r12d
addl $1, %r12d
cmpb $66, %r14b
je .L40
cmpb $75, %r14b
je .L41
cmpb $77, %r14b
je .L42
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $0, %eax
testl %edi, %edi
je .L3
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $133, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
movl $1, %edi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r14
addq 24(%rsp), %r14
movl $0, %ebp
jmp .L17
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movq %rbp, %rdi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
.L15:
testl %eax, %eax
jne .L44
.L16:
addq $1, %rbp
cmpq $1048576, %rbp
je .L45
.L17:
cmpb $87, %bl
je .L46
cmpb $82, %bl
jne .L16
movq %rbp, %rsi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L15
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r14, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $66, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L41:
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r14
addq 24(%rsp), %r14
movl $0, %ebp
jmp .L24
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $91, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movq %rbp, %rdi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1024, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
.L22:
testl %eax, %eax
jne .L48
.L23:
addq $1024, %rbp
cmpq $268435456, %rbp
je .L49
.L24:
cmpb $87, %bl
je .L50
cmpb $82, %bl
jne .L23
movq %rbp, %rsi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1024, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L22
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $102, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r14, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC7(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $75, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L42:
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L51
movl $1048576, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r15
addq 24(%rsp), %r15
movl $0, %ebp
movabsq $5368709120, %r13
jmp .L29
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $113, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movq %rbp, %rdi
andl $535822336, %edi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1048576, %edx
movq %r14, %rsi
call cudaMemcpy@PLT
.L27:
testl %eax, %eax
jne .L52
.L28:
addq $1048576, %rbp
cmpq %r13, %rbp
je .L53
.L29:
cmpb $87, %bl
je .L54
cmpb $82, %bl
jne .L28
movq %rbp, %rsi
andl $535822336, %esi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1048576, %edx
movq %r14, %rdi
call cudaMemcpy@PLT
jmp .L27
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $124, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC8(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $77, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.globl _Z26__device_stub__Z8gpu_iopsmm
.type _Z26__device_stub__Z8gpu_iopsmm, @function
_Z26__device_stub__Z8gpu_iopsmm:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_iopsm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z26__device_stub__Z8gpu_iopsmm, .-_Z26__device_stub__Z8gpu_iopsmm
.globl _Z8gpu_iopsm
.type _Z8gpu_iopsm, @function
_Z8gpu_iopsm:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8gpu_iopsmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z8gpu_iopsm, .-_Z8gpu_iopsm
.section .rodata.str1.1
.LC9:
.string "_Z8gpu_iopsm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_iopsm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MAX_OPS
.data
.align 8
.type MAX_OPS, @object
.size MAX_OPS, 8
MAX_OPS:
.quad 20000000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1070596096
.align 8
.LC8:
.long 0
.long 1085538304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
cudaError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
cudaMemcpyKind dir = cudaMemcpyHostToDevice;
if(rw == 'R')
{
dir = cudaMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - cudaMemcpyHostToDevice;
}
if(test == 'B')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = cudaMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = cudaMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = cudaMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = cudaFree(d_mem_pointer);
CHECK_ERR(err);
} | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
hipError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
hipMemcpyKind dir = hipMemcpyHostToDevice;
if(rw == 'R')
{
dir = hipMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - hipMemcpyHostToDevice;
}
if(test == 'B')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = hipFree(d_mem_pointer);
CHECK_ERR(err);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
hipError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
hipMemcpyKind dir = hipMemcpyHostToDevice;
if(rw == 'R')
{
dir = hipMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - hipMemcpyHostToDevice;
}
if(test == 'B')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = hipFree(d_mem_pointer);
CHECK_ERR(err);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_iopsm
.globl _Z8gpu_iopsm
.p2align 8
.type _Z8gpu_iopsm,@function
_Z8gpu_iopsm:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_iopsm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_iopsm, .Lfunc_end0-_Z8gpu_iopsm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_iopsm
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8gpu_iopsm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__global__ void gpu_iops(unsigned long max_ops) {
// int a = blockDim.x * blockIdx.x + threadIdx.x;
}
int main(int argc, char *argv[]) {
char c;
char test = 'B';
char rw = 'R';
while ( (c = getopt(argc, argv, "r:t:") ) != -1)
{
switch (c)
{
case 'r':
rw = optarg[0];
break;
case 't':
test = optarg[0];
break;
default:
printf("Usage: ./benchCPU -n [number of threads]\n");
return -1;
}
}
struct timeval tv;
long long start, stop;
double secs;
hipError_t err;
unsigned char *d_mem_pointer;
unsigned char *mem_pointer;
hipMemcpyKind dir = hipMemcpyHostToDevice;
if(rw == 'R')
{
dir = hipMemcpyDeviceToHost;
}
else if(rw == 'W')
{
dir - hipMemcpyHostToDevice;
}
if(test == 'B')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<MEGABYTE; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i], (void *)mem_pointer, 1, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i], 1, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, 1.0/(secs));
}
else if(test == 'K')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*256*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*1024);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<256*MEGABYTE/1024; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[i*1024], (void *)mem_pointer, 1024, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[i*1024], 1024, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (256.0/1024.0)/(secs));
}
else if(test == 'M')
{
err = hipMalloc((void **) &d_mem_pointer, sizeof(unsigned char)*512*MEGABYTE);
CHECK_ERR(err);
mem_pointer = (unsigned char *)malloc(sizeof(unsigned char)*MEGABYTE);
gettimeofday(&tv, NULL);
start = tv.tv_sec*1000000LL + tv.tv_usec;
for(unsigned long i = 0; i<512*10; i++)
{
if(rw == 'W')
err = hipMemcpy((void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], (void *)mem_pointer, MEGABYTE, dir);
else if(rw == 'R')
err = hipMemcpy((void *)mem_pointer, (void *)&d_mem_pointer[(i*MEGABYTE)%(512*MEGABYTE)], MEGABYTE, dir);
CHECK_ERR(err);
}
gettimeofday(&tv, NULL);
stop = tv.tv_sec*1000000LL + tv.tv_usec;
secs = (stop-start)/1000000.0;
printf("%c\t%c\t%lf\n", rw, test, (512*10)/(secs));
}
err = hipFree(d_mem_pointer);
CHECK_ERR(err);
} | .text
.file "gpu_mem_bench.hip"
.globl _Z23__device_stub__gpu_iopsm # -- Begin function _Z23__device_stub__gpu_iopsm
.p2align 4, 0x90
.type _Z23__device_stub__gpu_iopsm,@function
_Z23__device_stub__gpu_iopsm: # @_Z23__device_stub__gpu_iopsm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8gpu_iopsm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_iopsm, .Lfunc_end0-_Z23__device_stub__gpu_iopsm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x40b4000000000000 # double 5120
.LCPI1_1:
.quad 0x3fd0000000000000 # double 0.25
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.L.str, %edx
callq getopt
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
jne .LBB1_2
# %bb.1:
movb $82, %r15b
movb $66, %r14b
.LBB1_9: # %._crit_edge
xorl %ebx, %ebx
cmpb $82, %r15b
sete %bl
incl %ebx
cmpb $77, %r14b
je .LBB1_37
# %bb.10: # %._crit_edge
movzbl %r14b, %eax
cmpl $75, %eax
je .LBB1_25
# %bb.11: # %._crit_edge
cmpl $66, %eax
jne .LBB1_42
# %bb.12:
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.17:
movl $1, %edi
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %r12
.p2align 4, 0x90
.LBB1_18: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq %r14, %rsi
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_18 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_23
# %bb.21: # in Loop: Header=BB1_18 Depth=1
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq %r14, %rdi
.LBB1_22: # %.sink.split
# in Loop: Header=BB1_18 Depth=1
movl $1, %edx
movl %ebx, %ecx
callq hipMemcpy
.LBB1_23: # in Loop: Header=BB1_18 Depth=1
testl %eax, %eax
jne .LBB1_24
# %bb.15: # in Loop: Header=BB1_18 Depth=1
incq %rbp
cmpq $1048576, %rbp # imm = 0x100000
jne .LBB1_18
# %bb.16:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq %r12, %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $66, %edx
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB1_41
.LBB1_2: # %.lr.ph.preheader
movb $66, %r14b
movb $82, %r15b
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq optarg(%rip), %rax
movzbl (%rax), %r14d
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
je .LBB1_9
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl $24, %eax
cmpl $116, %eax
je .LBB1_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
cmpl $114, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movq optarg(%rip), %rax
movzbl (%rax), %r15d
jmp .LBB1_8
.LBB1_25:
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_26
# %bb.29:
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %r12
.p2align 4, 0x90
.LBB1_30: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_32
# %bb.31: # in Loop: Header=BB1_30 Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq %r14, %rsi
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_30 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_35
# %bb.33: # in Loop: Header=BB1_30 Depth=1
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq %r14, %rdi
.LBB1_34: # %.sink.split127
# in Loop: Header=BB1_30 Depth=1
movl $1024, %edx # imm = 0x400
movl %ebx, %ecx
callq hipMemcpy
.LBB1_35: # in Loop: Header=BB1_30 Depth=1
testl %eax, %eax
jne .LBB1_36
# %bb.27: # in Loop: Header=BB1_30 Depth=1
addq $1024, %rbp # imm = 0x400
cmpq $268435456, %rbp # imm = 0x10000000
jne .LBB1_30
# %bb.28:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq %r12, %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $75, %edx
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB1_41
.LBB1_37:
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.44:
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl $5120, %r12d # imm = 0x1400
.p2align 4, 0x90
.LBB1_45: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_47
# %bb.46: # in Loop: Header=BB1_45 Depth=1
movl %ebp, %edi
andl $535822336, %edi # imm = 0x1FF00000
addq 8(%rsp), %rdi
movq %r14, %rsi
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_47: # in Loop: Header=BB1_45 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_50
# %bb.48: # in Loop: Header=BB1_45 Depth=1
movl %ebp, %esi
andl $535822336, %esi # imm = 0x1FF00000
addq 8(%rsp), %rsi
movq %r14, %rdi
.LBB1_49: # %.sink.split130
# in Loop: Header=BB1_45 Depth=1
movl $1048576, %edx # imm = 0x100000
movl %ebx, %ecx
callq hipMemcpy
.LBB1_50: # in Loop: Header=BB1_45 Depth=1
testl %eax, %eax
jne .LBB1_51
# %bb.39: # in Loop: Header=BB1_45 Depth=1
addq $1048576, %rbp # imm = 0x100000
decq %r12
jne .LBB1_45
# %bb.40:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq 32(%rsp), %rcx # 8-byte Folded Reload
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $77, %edx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB1_41: # %.sink.split133
cvtsi2sd %rax, %xmm1
movsbl %r15b, %esi
divsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB1_42:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.52:
xorl %eax, %eax
.LBB1_53:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 96
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB1_53
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB1_14
.LBB1_51:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_14
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
.LBB1_14:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $135, %r8d
jmp .LBB1_14
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_14
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
jmp .LBB1_14
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_14
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_iopsm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type MAX_OPS,@object # @MAX_OPS
.data
.globl MAX_OPS
.p2align 3, 0x0
MAX_OPS:
.quad 20000000 # 0x1312d00
.size MAX_OPS, 8
.type _Z8gpu_iopsm,@object # @_Z8gpu_iopsm
.section .rodata,"a",@progbits
.globl _Z8gpu_iopsm
.p2align 3, 0x0
_Z8gpu_iopsm:
.quad _Z23__device_stub__gpu_iopsm
.size _Z8gpu_iopsm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r:t:"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/abirylo/cs451/master/Project1/gpu_mem_bench.hip"
.size .L.str.3, 105
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%c\t%c\t%lf\n"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_iopsm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./benchCPU -n [number of threads]"
.size .Lstr, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_iopsm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_iopsm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpu_iopsm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_iopsm
.globl _Z8gpu_iopsm
.p2align 8
.type _Z8gpu_iopsm,@function
_Z8gpu_iopsm:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_iopsm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_iopsm, .Lfunc_end0-_Z8gpu_iopsm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_iopsm
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8gpu_iopsm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fd003_00000000-6_gpu_mem_bench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./benchCPU -n [number of threads]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r:t:"
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/abirylo/cs451/master/Project1/gpu_mem_bench.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC6:
.string "%c\t%c\t%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $82, %ebx
movl $66, %r14d
leaq .LC1(%rip), %r13
.L4:
movq %r13, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call getopt@PLT
cmpb $-1, %al
je .L38
cmpb $114, %al
je .L5
cmpb $116, %al
je .L6
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
.L3:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
movq optarg(%rip), %rax
movzbl (%rax), %ebx
jmp .L4
.L6:
movq optarg(%rip), %rax
movzbl (%rax), %r14d
jmp .L4
.L38:
cmpb $82, %bl
sete %r12b
movzbl %r12b, %r12d
addl $1, %r12d
cmpb $66, %r14b
je .L40
cmpb $75, %r14b
je .L41
cmpb $77, %r14b
je .L42
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $0, %eax
testl %edi, %edi
je .L3
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $133, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
movl $1, %edi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r14
addq 24(%rsp), %r14
movl $0, %ebp
jmp .L17
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movq %rbp, %rdi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
.L15:
testl %eax, %eax
jne .L44
.L16:
addq $1, %rbp
cmpq $1048576, %rbp
je .L45
.L17:
cmpb $87, %bl
je .L46
cmpb $82, %bl
jne .L16
movq %rbp, %rsi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L15
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r14, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $66, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L41:
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r14
addq 24(%rsp), %r14
movl $0, %ebp
jmp .L24
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $91, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movq %rbp, %rdi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1024, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
.L22:
testl %eax, %eax
jne .L48
.L23:
addq $1024, %rbp
cmpq $268435456, %rbp
je .L49
.L24:
cmpb $87, %bl
je .L50
cmpb $82, %bl
jne .L23
movq %rbp, %rsi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1024, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L22
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $102, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r14, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC7(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $75, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L42:
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L51
movl $1048576, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %r15
addq 24(%rsp), %r15
movl $0, %ebp
movabsq $5368709120, %r13
jmp .L29
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $113, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movq %rbp, %rdi
andl $535822336, %edi
addq 8(%rsp), %rdi
movl %r12d, %ecx
movl $1048576, %edx
movq %r14, %rsi
call cudaMemcpy@PLT
.L27:
testl %eax, %eax
jne .L52
.L28:
addq $1048576, %rbp
cmpq %r13, %rbp
je .L53
.L29:
cmpb $87, %bl
je .L54
cmpb $82, %bl
jne .L28
movq %rbp, %rsi
andl $535822336, %esi
addq 8(%rsp), %rsi
movl %r12d, %ecx
movl $1048576, %edx
movq %r14, %rdi
call cudaMemcpy@PLT
jmp .L27
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $124, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rax
addq 24(%rsp), %rax
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd .LC8(%rip), %xmm0
divsd %xmm1, %xmm0
movsbl %bl, %edx
movl $77, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.globl _Z26__device_stub__Z8gpu_iopsmm
.type _Z26__device_stub__Z8gpu_iopsmm, @function
_Z26__device_stub__Z8gpu_iopsmm:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_iopsm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z26__device_stub__Z8gpu_iopsmm, .-_Z26__device_stub__Z8gpu_iopsmm
.globl _Z8gpu_iopsm
.type _Z8gpu_iopsm, @function
_Z8gpu_iopsm:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8gpu_iopsmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z8gpu_iopsm, .-_Z8gpu_iopsm
.section .rodata.str1.1
.LC9:
.string "_Z8gpu_iopsm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_iopsm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MAX_OPS
.data
.align 8
.type MAX_OPS, @object
.size MAX_OPS, 8
MAX_OPS:
.quad 20000000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1070596096
.align 8
.LC8:
.long 0
.long 1085538304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_mem_bench.hip"
.globl _Z23__device_stub__gpu_iopsm # -- Begin function _Z23__device_stub__gpu_iopsm
.p2align 4, 0x90
.type _Z23__device_stub__gpu_iopsm,@function
_Z23__device_stub__gpu_iopsm: # @_Z23__device_stub__gpu_iopsm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8gpu_iopsm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_iopsm, .Lfunc_end0-_Z23__device_stub__gpu_iopsm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x40b4000000000000 # double 5120
.LCPI1_1:
.quad 0x3fd0000000000000 # double 0.25
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.L.str, %edx
callq getopt
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
jne .LBB1_2
# %bb.1:
movb $82, %r15b
movb $66, %r14b
.LBB1_9: # %._crit_edge
xorl %ebx, %ebx
cmpb $82, %r15b
sete %bl
incl %ebx
cmpb $77, %r14b
je .LBB1_37
# %bb.10: # %._crit_edge
movzbl %r14b, %eax
cmpl $75, %eax
je .LBB1_25
# %bb.11: # %._crit_edge
cmpl $66, %eax
jne .LBB1_42
# %bb.12:
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.17:
movl $1, %edi
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %r12
.p2align 4, 0x90
.LBB1_18: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq %r14, %rsi
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_18 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_23
# %bb.21: # in Loop: Header=BB1_18 Depth=1
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq %r14, %rdi
.LBB1_22: # %.sink.split
# in Loop: Header=BB1_18 Depth=1
movl $1, %edx
movl %ebx, %ecx
callq hipMemcpy
.LBB1_23: # in Loop: Header=BB1_18 Depth=1
testl %eax, %eax
jne .LBB1_24
# %bb.15: # in Loop: Header=BB1_18 Depth=1
incq %rbp
cmpq $1048576, %rbp # imm = 0x100000
jne .LBB1_18
# %bb.16:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq %r12, %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $66, %edx
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB1_41
.LBB1_2: # %.lr.ph.preheader
movb $66, %r14b
movb $82, %r15b
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq optarg(%rip), %rax
movzbl (%rax), %r14d
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
je .LBB1_9
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl $24, %eax
cmpl $116, %eax
je .LBB1_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
cmpl $114, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movq optarg(%rip), %rax
movzbl (%rax), %r15d
jmp .LBB1_8
.LBB1_25:
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_26
# %bb.29:
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %r12
.p2align 4, 0x90
.LBB1_30: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_32
# %bb.31: # in Loop: Header=BB1_30 Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq %r14, %rsi
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_30 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_35
# %bb.33: # in Loop: Header=BB1_30 Depth=1
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq %r14, %rdi
.LBB1_34: # %.sink.split127
# in Loop: Header=BB1_30 Depth=1
movl $1024, %edx # imm = 0x400
movl %ebx, %ecx
callq hipMemcpy
.LBB1_35: # in Loop: Header=BB1_30 Depth=1
testl %eax, %eax
jne .LBB1_36
# %bb.27: # in Loop: Header=BB1_30 Depth=1
addq $1024, %rbp # imm = 0x400
cmpq $268435456, %rbp # imm = 0x10000000
jne .LBB1_30
# %bb.28:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq %r12, %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $75, %edx
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB1_41
.LBB1_37:
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.44:
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
xorl %ebp, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl $5120, %r12d # imm = 0x1400
.p2align 4, 0x90
.LBB1_45: # =>This Inner Loop Header: Depth=1
cmpb $87, %r15b
jne .LBB1_47
# %bb.46: # in Loop: Header=BB1_45 Depth=1
movl %ebp, %edi
andl $535822336, %edi # imm = 0x1FF00000
addq 8(%rsp), %rdi
movq %r14, %rsi
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_47: # in Loop: Header=BB1_45 Depth=1
xorl %eax, %eax
cmpb $82, %r15b
jne .LBB1_50
# %bb.48: # in Loop: Header=BB1_45 Depth=1
movl %ebp, %esi
andl $535822336, %esi # imm = 0x1FF00000
addq 8(%rsp), %rsi
movq %r14, %rdi
.LBB1_49: # %.sink.split130
# in Loop: Header=BB1_45 Depth=1
movl $1048576, %edx # imm = 0x100000
movl %ebx, %ecx
callq hipMemcpy
.LBB1_50: # in Loop: Header=BB1_45 Depth=1
testl %eax, %eax
jne .LBB1_51
# %bb.39: # in Loop: Header=BB1_45 Depth=1
addq $1048576, %rbp # imm = 0x100000
decq %r12
jne .LBB1_45
# %bb.40:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq %r13, %rax
movq 24(%rsp), %rcx
subq 32(%rsp), %rcx # 8-byte Folded Reload
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
movl $77, %edx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB1_41: # %.sink.split133
cvtsi2sd %rax, %xmm1
movsbl %r15b, %esi
divsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB1_42:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.52:
xorl %eax, %eax
.LBB1_53:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 96
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB1_53
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB1_14
.LBB1_51:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_14
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
.LBB1_14:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $135, %r8d
jmp .LBB1_14
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_14
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
jmp .LBB1_14
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_14
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_iopsm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type MAX_OPS,@object # @MAX_OPS
.data
.globl MAX_OPS
.p2align 3, 0x0
MAX_OPS:
.quad 20000000 # 0x1312d00
.size MAX_OPS, 8
.type _Z8gpu_iopsm,@object # @_Z8gpu_iopsm
.section .rodata,"a",@progbits
.globl _Z8gpu_iopsm
.p2align 3, 0x0
_Z8gpu_iopsm:
.quad _Z23__device_stub__gpu_iopsm
.size _Z8gpu_iopsm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r:t:"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/abirylo/cs451/master/Project1/gpu_mem_bench.hip"
.size .L.str.3, 105
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%c\t%c\t%lf\n"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_iopsm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./benchCPU -n [number of threads]"
.size .Lstr, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_iopsm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_iopsm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | code for sm_80
Function : gradalex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R2, R3, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f62000c1e1b00 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fe200078e0203 */
/*00d0*/ DSETP.GT.AND P0, PT, R8, -0.5, PT ; /* 0xbfe000000800742a */
/* 0x004e1c0003f04000 */
/*00e0*/ @P0 BRA 0x280 ; /* 0x0000019000000947 */
/* 0x001fea0003800000 */
/*00f0*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001800 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x240 ; /* 0x0000012000007945 */
/* 0x000fea0003800000 */
/*0120*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0140*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e080000000006 */
/*0150*/ DMUL R6, R4, -0.5 ; /* 0xbfe0000004067828 */
/* 0x020fc80000000000 */
/*0160*/ DFMA R12, -R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010a */
/*0170*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e22000000000a */
/*0180*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0190*/ DMUL R4, R6, R12 ; /* 0x0000000c06047228 */
/* 0x001e0c0000000000 */
/*01a0*/ DFMA R10, -R8, R4, R6 ; /* 0x00000004080a722b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R4, R12, R10, R4 ; /* 0x0000000a0c04722b */
/* 0x001e140000000004 */
/*01c0*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*01d0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01e0*/ @P0 BRA P1, 0x230 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01f0*/ MOV R0, 0x210 ; /* 0x0000021000007802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x2c0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*0250*/ DADD R6, R6, R4 ; /* 0x0000000006067229 */
/* 0x004e0e0000000004 */
/*0260*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*0290*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x024e0e0000000006 */
/*02a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0300*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0320*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0340*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*0350*/ BSSY B1, 0x860 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0360*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*0370*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*0390*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*03a0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*03b0*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*03c0*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*03d0*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*03e0*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*03f0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*0400*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*0410*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0420*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0430*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*0440*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0450*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0460*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0470*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0480*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0490*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*04a0*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*04b0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*04d0*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*04e0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*04f0*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0500*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0510*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0520*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*0560*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*0570*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*0580*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0590*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*05a0*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*05b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0610*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0640*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0670*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*06a0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*07a0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0840*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .file "tmpxft_0006c1b6_00000000-6_gradalex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
.type _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd, @function
_Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gradalex(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd, .-_Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
.globl gradalex
.type gradalex, @function
gradalex:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gradalex, .-gradalex
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gradalex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gradalex(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gradalex
.globl gradalex
.p2align 8
.type gradalex,@function
gradalex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(1)
v_cmpx_nlt_f64_e32 -0.5, v[3:4]
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[7:8], -0.5
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b64 v[11:12], v[5:6], off
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
v_div_scale_f64 v[13:14], vcc_lo, v[0:1], v[3:4], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[13:14], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[15:16]
v_div_fixup_f64 v[0:1], v[7:8], v[3:4], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[11:12], v[0:1]
global_store_b64 v[5:6], v[0:1], off
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[7:8], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gradalex
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gradalex, .Lfunc_end0-gradalex
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gradalex
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gradalex.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .text
.file "gradalex.hip"
.globl __device_stub__gradalex # -- Begin function __device_stub__gradalex
.p2align 4, 0x90
.type __device_stub__gradalex,@function
__device_stub__gradalex: # @__device_stub__gradalex
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gradalex, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gradalex, .Lfunc_end0-__device_stub__gradalex
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gradalex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gradalex,@object # @gradalex
.section .rodata,"a",@progbits
.globl gradalex
.p2align 3, 0x0
gradalex:
.quad __device_stub__gradalex
.size gradalex, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gradalex"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gradalex
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gradalex
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : gradalex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R2, R3, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f62000c1e1b00 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fe200078e0203 */
/*00d0*/ DSETP.GT.AND P0, PT, R8, -0.5, PT ; /* 0xbfe000000800742a */
/* 0x004e1c0003f04000 */
/*00e0*/ @P0 BRA 0x280 ; /* 0x0000019000000947 */
/* 0x001fea0003800000 */
/*00f0*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001800 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x240 ; /* 0x0000012000007945 */
/* 0x000fea0003800000 */
/*0120*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0140*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e080000000006 */
/*0150*/ DMUL R6, R4, -0.5 ; /* 0xbfe0000004067828 */
/* 0x020fc80000000000 */
/*0160*/ DFMA R12, -R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010a */
/*0170*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e22000000000a */
/*0180*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0190*/ DMUL R4, R6, R12 ; /* 0x0000000c06047228 */
/* 0x001e0c0000000000 */
/*01a0*/ DFMA R10, -R8, R4, R6 ; /* 0x00000004080a722b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R4, R12, R10, R4 ; /* 0x0000000a0c04722b */
/* 0x001e140000000004 */
/*01c0*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*01d0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01e0*/ @P0 BRA P1, 0x230 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01f0*/ MOV R0, 0x210 ; /* 0x0000021000007802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x2c0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*0250*/ DADD R6, R6, R4 ; /* 0x0000000006067229 */
/* 0x004e0e0000000004 */
/*0260*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*0290*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x024e0e0000000006 */
/*02a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0300*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0320*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0340*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*0350*/ BSSY B1, 0x860 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0360*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*0370*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*0390*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*03a0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*03b0*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*03c0*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*03d0*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*03e0*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*03f0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*0400*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*0410*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0420*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0430*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*0440*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0450*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0460*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0470*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0480*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0490*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*04a0*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*04b0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*04d0*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*04e0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*04f0*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0500*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0510*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0520*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*0560*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*0570*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*0580*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0590*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*05a0*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*05b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0610*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0640*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0670*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*06a0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*07a0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0840*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gradalex
.globl gradalex
.p2align 8
.type gradalex,@function
gradalex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(1)
v_cmpx_nlt_f64_e32 -0.5, v[3:4]
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[7:8], -0.5
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b64 v[11:12], v[5:6], off
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
v_div_scale_f64 v[13:14], vcc_lo, v[0:1], v[3:4], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[13:14], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[15:16]
v_div_fixup_f64 v[0:1], v[7:8], v[3:4], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[11:12], v[0:1]
global_store_b64 v[5:6], v[0:1], off
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[7:8], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gradalex
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gradalex, .Lfunc_end0-gradalex
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gradalex
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gradalex.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006c1b6_00000000-6_gradalex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
.type _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd, @function
_Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gradalex(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd, .-_Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
.globl gradalex
.type gradalex, @function
gradalex:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8gradalexiPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gradalex, .-gradalex
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gradalex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gradalex(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gradalex.hip"
.globl __device_stub__gradalex # -- Begin function __device_stub__gradalex
.p2align 4, 0x90
.type __device_stub__gradalex,@function
__device_stub__gradalex: # @__device_stub__gradalex
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gradalex, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gradalex, .Lfunc_end0-__device_stub__gradalex
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gradalex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gradalex,@object # @gradalex
.section .rodata,"a",@progbits
.globl gradalex
.p2align 3, 0x0
gradalex:
.quad __device_stub__gradalex
.size gradalex, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gradalex"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gradalex
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gradalex
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} | code for sm_80
Function : _Z9maxKernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e640000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R10, 0x42, PT ; /* 0x000000420a00780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD.SHL.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037824 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fe200078e0202 */
/*0090*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e20000004800 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x040fe40003f24070 */
/*00b0*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45270 */
/*00c0*/ ISETP.GE.U32.AND P3, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f66070 */
/*00d0*/ @P3 BRA 0x1c0 ; /* 0x000000e000003947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R10, R10, c[0x0][0xc], RZ ; /* 0x000003000a0a7a24 */
/* 0x001fe400078e02ff */
/*00f0*/ IADD3 R6, R3, c[0x0][0x0], RZ ; /* 0x0000000003067a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE.U32 R6, R6, R4, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe400078e0004 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD R3, R10, 0x2, R3 ; /* 0x000000020a037824 */
/* 0x000fe200078e0203 */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe80003800000 */
/*0170*/ ISETP.GE.U32.AND P3, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fc40003f66070 */
/*0180*/ FMNMX R9, R6, R5, !PT ; /* 0x0000000506097209 */
/* 0x004fca0007800000 */
/*0190*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @!P3 BRA 0xf0 ; /* 0xffffff300000b947 */
/* 0x001fea000383ffff */
/*01c0*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x001fe200078e00ff */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x1, R8 ; /* 0x00000001ff067819 */
/* 0x000fe20000011608 */
/*01f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, R6, PT ; /* 0x000000060200720c */
/* 0x000fda0003f06070 */
/*0210*/ @!P0 IMAD R5, R6, 0x4, R3 ; /* 0x0000000406058824 */
/* 0x000fe200078e0203 */
/*0220*/ @!P0 LDS R4, [R2.X4] ; /* 0x0000000002048984 */
/* 0x000fea0000004800 */
/*0230*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x001e240000000800 */
/*0240*/ @!P0 FMNMX R7, R4, R5, !PT ; /* 0x0000000504078209 */
/* 0x001fca0007800000 */
/*0250*/ @!P0 STS [R2.X4], R7 ; /* 0x0000000702008388 */
/* 0x0001e40000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P0, PT, R8, 0x83, PT ; /* 0x000000830800780c */
/* 0x000fe20003f04070 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0006 */
/*0290*/ @P0 BRA 0x1e0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*02a0*/ @P1 BRA 0x4a0 ; /* 0x000001f000001947 */
/* 0x000fea0003800000 */
/*02b0*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x000fe20000004800 */
/*02c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*02d0*/ LDS R4, [R2.X4+0x80] ; /* 0x0000800002047984 */
/* 0x000e640000004800 */
/*02e0*/ FMNMX R3, R3, R4, !PT ; /* 0x0000000403037209 */
/* 0x002fca0007800000 */
/*02f0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R4, [R2.X4+0x40] ; /* 0x0000400002047984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e640000004800 */
/*0330*/ FMNMX R5, R4, R5, !PT ; /* 0x0000000504057209 */
/* 0x002fca0007800000 */
/*0340*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDS R4, [R2.X4+0x20] ; /* 0x0000200002047984 */
/* 0x000fe80000004800 */
/*0370*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x001e240000004800 */
/*0380*/ FMNMX R7, R4, R7, !PT ; /* 0x0000000704077209 */
/* 0x001fca0007800000 */
/*0390*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000004800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03b0*/ LDS R3, [R2.X4+0x10] ; /* 0x0000100002037984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000e240000004800 */
/*03d0*/ FMNMX R3, R3, R4, !PT ; /* 0x0000000403037209 */
/* 0x001fca0007800000 */
/*03e0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDS R4, [R2.X4+0x8] ; /* 0x0000080002047984 */
/* 0x000fe80000004800 */
/*0410*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*0420*/ FMNMX R5, R4, R5, !PT ; /* 0x0000000504057209 */
/* 0x001fca0007800000 */
/*0430*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ LDS R4, [R2.X4+0x4] ; /* 0x0000040002047984 */
/* 0x000fe80000004800 */
/*0460*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0470*/ FMNMX R7, R4, R7, !PT ; /* 0x0000000704077209 */
/* 0x001fca0007800000 */
/*0480*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*04b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fca00078e0003 */
/*04e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} | .file "tmpxft_0004b236_00000000-6_maxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9maxKernelPfiS_PfiS_
.type _Z31__device_stub__Z9maxKernelPfiS_PfiS_, @function
_Z31__device_stub__Z9maxKernelPfiS_PfiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9maxKernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9maxKernelPfiS_PfiS_, .-_Z31__device_stub__Z9maxKernelPfiS_PfiS_
.globl _Z9maxKernelPfiS_
.type _Z9maxKernelPfiS_, @function
_Z9maxKernelPfiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9maxKernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9maxKernelPfiS_, .-_Z9maxKernelPfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9maxKernelPfiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9maxKernelPfiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxKernelPfiS_
.globl _Z9maxKernelPfiS_
.p2align 8
.type _Z9maxKernelPfiS_,@function
_Z9maxKernelPfiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_lshl_b32 s10, s15, 1
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s2, s15
s_mov_b32 s8, 0
s_mov_b32 s9, exec_lo
v_mov_b32_e32 v3, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s10, s3
v_add_nc_u32_e32 v2, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v2
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v2, v0
s_add_i32 s12, s10, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s10, s11, 1
s_mul_i32 s11, s12, s3
.p2align 6
.LBB0_2:
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_nc_u32_e32 v3, s11, v2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_dual_max_f32 v5, v5, v5 :: v_dual_add_nc_u32 v2, s10, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_max_f32 v3, v3, v3 :: v_dual_add_nc_u32 v4, s7, v2
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_max_f32_e32 v3, v5, v3
s_or_b32 s8, vcc_lo, s8
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_cmpk_lt_u32 s3, 0x42
s_cbranch_scc0 .LBB0_10
.LBB0_4:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v4, v2 offset:128
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v3, v4
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:64
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:32
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:16
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:8
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2 offset:4
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_10:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
v_max_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_9
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9maxKernelPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9maxKernelPfiS_, .Lfunc_end0-_Z9maxKernelPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9maxKernelPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9maxKernelPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], array[i + blockDim.x]);
i += stride;
__syncthreads();
}
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s)
sdata[tid] = fmaxf(sdata[tid], sdata[tid + s]);
__syncthreads();
}
if (tid < 32) {
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 32]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 16]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 8]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 4]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 2]);
__syncthreads();
sdata[tid] = fmaxf(sdata[tid], sdata[tid + 1]);
__syncthreads();
}
if (tid == 0) {
max[blockIdx.x] = sdata[0];
}
} | .text
.file "maxKernel.hip"
.globl _Z24__device_stub__maxKernelPfiS_ # -- Begin function _Z24__device_stub__maxKernelPfiS_
.p2align 4, 0x90
.type _Z24__device_stub__maxKernelPfiS_,@function
_Z24__device_stub__maxKernelPfiS_: # @_Z24__device_stub__maxKernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9maxKernelPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__maxKernelPfiS_, .Lfunc_end0-_Z24__device_stub__maxKernelPfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9maxKernelPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9maxKernelPfiS_,@object # @_Z9maxKernelPfiS_
.section .rodata,"a",@progbits
.globl _Z9maxKernelPfiS_
.p2align 3, 0x0
_Z9maxKernelPfiS_:
.quad _Z24__device_stub__maxKernelPfiS_
.size _Z9maxKernelPfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9maxKernelPfiS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__maxKernelPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9maxKernelPfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9maxKernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e640000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R10, 0x42, PT ; /* 0x000000420a00780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD.SHL.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037824 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fe200078e0202 */
/*0090*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e20000004800 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x040fe40003f24070 */
/*00b0*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45270 */
/*00c0*/ ISETP.GE.U32.AND P3, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f66070 */
/*00d0*/ @P3 BRA 0x1c0 ; /* 0x000000e000003947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R10, R10, c[0x0][0xc], RZ ; /* 0x000003000a0a7a24 */
/* 0x001fe400078e02ff */
/*00f0*/ IADD3 R6, R3, c[0x0][0x0], RZ ; /* 0x0000000003067a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE.U32 R6, R6, R4, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe400078e0004 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD R3, R10, 0x2, R3 ; /* 0x000000020a037824 */
/* 0x000fe200078e0203 */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe80003800000 */
/*0170*/ ISETP.GE.U32.AND P3, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fc40003f66070 */
/*0180*/ FMNMX R9, R6, R5, !PT ; /* 0x0000000506097209 */
/* 0x004fca0007800000 */
/*0190*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @!P3 BRA 0xf0 ; /* 0xffffff300000b947 */
/* 0x001fea000383ffff */
/*01c0*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x001fe200078e00ff */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x1, R8 ; /* 0x00000001ff067819 */
/* 0x000fe20000011608 */
/*01f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, R6, PT ; /* 0x000000060200720c */
/* 0x000fda0003f06070 */
/*0210*/ @!P0 IMAD R5, R6, 0x4, R3 ; /* 0x0000000406058824 */
/* 0x000fe200078e0203 */
/*0220*/ @!P0 LDS R4, [R2.X4] ; /* 0x0000000002048984 */
/* 0x000fea0000004800 */
/*0230*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x001e240000000800 */
/*0240*/ @!P0 FMNMX R7, R4, R5, !PT ; /* 0x0000000504078209 */
/* 0x001fca0007800000 */
/*0250*/ @!P0 STS [R2.X4], R7 ; /* 0x0000000702008388 */
/* 0x0001e40000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P0, PT, R8, 0x83, PT ; /* 0x000000830800780c */
/* 0x000fe20003f04070 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0006 */
/*0290*/ @P0 BRA 0x1e0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*02a0*/ @P1 BRA 0x4a0 ; /* 0x000001f000001947 */
/* 0x000fea0003800000 */
/*02b0*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x000fe20000004800 */
/*02c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*02d0*/ LDS R4, [R2.X4+0x80] ; /* 0x0000800002047984 */
/* 0x000e640000004800 */
/*02e0*/ FMNMX R3, R3, R4, !PT ; /* 0x0000000403037209 */
/* 0x002fca0007800000 */
/*02f0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R4, [R2.X4+0x40] ; /* 0x0000400002047984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e640000004800 */
/*0330*/ FMNMX R5, R4, R5, !PT ; /* 0x0000000504057209 */
/* 0x002fca0007800000 */
/*0340*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDS R4, [R2.X4+0x20] ; /* 0x0000200002047984 */
/* 0x000fe80000004800 */
/*0370*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x001e240000004800 */
/*0380*/ FMNMX R7, R4, R7, !PT ; /* 0x0000000704077209 */
/* 0x001fca0007800000 */
/*0390*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000004800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03b0*/ LDS R3, [R2.X4+0x10] ; /* 0x0000100002037984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000e240000004800 */
/*03d0*/ FMNMX R3, R3, R4, !PT ; /* 0x0000000403037209 */
/* 0x001fca0007800000 */
/*03e0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDS R4, [R2.X4+0x8] ; /* 0x0000080002047984 */
/* 0x000fe80000004800 */
/*0410*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*0420*/ FMNMX R5, R4, R5, !PT ; /* 0x0000000504057209 */
/* 0x001fca0007800000 */
/*0430*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ LDS R4, [R2.X4+0x4] ; /* 0x0000040002047984 */
/* 0x000fe80000004800 */
/*0460*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0470*/ FMNMX R7, R4, R7, !PT ; /* 0x0000000704077209 */
/* 0x001fca0007800000 */
/*0480*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*04b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fca00078e0003 */
/*04e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxKernelPfiS_
.globl _Z9maxKernelPfiS_
.p2align 8
.type _Z9maxKernelPfiS_,@function
_Z9maxKernelPfiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_lshl_b32 s10, s15, 1
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s2, s15
s_mov_b32 s8, 0
s_mov_b32 s9, exec_lo
v_mov_b32_e32 v3, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s10, s3
v_add_nc_u32_e32 v2, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v2
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v2, v0
s_add_i32 s12, s10, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s10, s11, 1
s_mul_i32 s11, s12, s3
.p2align 6
.LBB0_2:
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_nc_u32_e32 v3, s11, v2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_dual_max_f32 v5, v5, v5 :: v_dual_add_nc_u32 v2, s10, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_max_f32 v3, v3, v3 :: v_dual_add_nc_u32 v4, s7, v2
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_max_f32_e32 v3, v5, v3
s_or_b32 s8, vcc_lo, s8
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_cmpk_lt_u32 s3, 0x42
s_cbranch_scc0 .LBB0_10
.LBB0_4:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v4, v2 offset:128
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v3, v4
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:64
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:32
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:16
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2 offset:8
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2 offset:4
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_10:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
v_max_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_9
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9maxKernelPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9maxKernelPfiS_, .Lfunc_end0-_Z9maxKernelPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9maxKernelPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9maxKernelPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b236_00000000-6_maxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9maxKernelPfiS_PfiS_
.type _Z31__device_stub__Z9maxKernelPfiS_PfiS_, @function
_Z31__device_stub__Z9maxKernelPfiS_PfiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9maxKernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9maxKernelPfiS_PfiS_, .-_Z31__device_stub__Z9maxKernelPfiS_PfiS_
.globl _Z9maxKernelPfiS_
.type _Z9maxKernelPfiS_, @function
_Z9maxKernelPfiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9maxKernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9maxKernelPfiS_, .-_Z9maxKernelPfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9maxKernelPfiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9maxKernelPfiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxKernel.hip"
.globl _Z24__device_stub__maxKernelPfiS_ # -- Begin function _Z24__device_stub__maxKernelPfiS_
.p2align 4, 0x90
.type _Z24__device_stub__maxKernelPfiS_,@function
_Z24__device_stub__maxKernelPfiS_: # @_Z24__device_stub__maxKernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9maxKernelPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__maxKernelPfiS_, .Lfunc_end0-_Z24__device_stub__maxKernelPfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9maxKernelPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9maxKernelPfiS_,@object # @_Z9maxKernelPfiS_
.section .rodata,"a",@progbits
.globl _Z9maxKernelPfiS_
.p2align 3, 0x0
_Z9maxKernelPfiS_:
.quad _Z24__device_stub__maxKernelPfiS_
.size _Z9maxKernelPfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9maxKernelPfiS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__maxKernelPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9maxKernelPfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} | code for sm_80
Function : _Z7mat_dotPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x184], R0 ; /* 0x0000610002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} | .file "tmpxft_0013a2b0_00000000-6_mat_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
.type _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii, @function
_Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7mat_dotPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii, .-_Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.type _Z7mat_dotPfS_S_iiii, @function
_Z7mat_dotPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7mat_dotPfS_S_iiii, .-_Z7mat_dotPfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mat_dotPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_dotPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_dotPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.p2align 8
.type _Z7mat_dotPfS_S_iiii,@function
_Z7mat_dotPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_dotPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_dotPfS_S_iiii, .Lfunc_end0-_Z7mat_dotPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_dotPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_dotPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_columns + k] * b[k * b_columns + j];
c[i * b_columns + j] = c_at_ij;
}
} | .text
.file "mat_dot.hip"
.globl _Z22__device_stub__mat_dotPfS_S_iiii # -- Begin function _Z22__device_stub__mat_dotPfS_S_iiii
.p2align 4, 0x90
.type _Z22__device_stub__mat_dotPfS_S_iiii,@function
_Z22__device_stub__mat_dotPfS_S_iiii: # @_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mat_dotPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mat_dotPfS_S_iiii, .Lfunc_end0-_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_dotPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mat_dotPfS_S_iiii,@object # @_Z7mat_dotPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z7mat_dotPfS_S_iiii
.p2align 3, 0x0
_Z7mat_dotPfS_S_iiii:
.quad _Z22__device_stub__mat_dotPfS_S_iiii
.size _Z7mat_dotPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mat_dotPfS_S_iiii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_dotPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mat_dotPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mat_dotPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x184], R0 ; /* 0x0000610002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_dotPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.p2align 8
.type _Z7mat_dotPfS_S_iiii,@function
_Z7mat_dotPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_dotPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_dotPfS_S_iiii, .Lfunc_end0-_Z7mat_dotPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_dotPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_dotPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a2b0_00000000-6_mat_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
.type _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii, @function
_Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7mat_dotPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii, .-_Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.type _Z7mat_dotPfS_S_iiii, @function
_Z7mat_dotPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z7mat_dotPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7mat_dotPfS_S_iiii, .-_Z7mat_dotPfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mat_dotPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_dotPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_dot.hip"
.globl _Z22__device_stub__mat_dotPfS_S_iiii # -- Begin function _Z22__device_stub__mat_dotPfS_S_iiii
.p2align 4, 0x90
.type _Z22__device_stub__mat_dotPfS_S_iiii,@function
_Z22__device_stub__mat_dotPfS_S_iiii: # @_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mat_dotPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mat_dotPfS_S_iiii, .Lfunc_end0-_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_dotPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mat_dotPfS_S_iiii,@object # @_Z7mat_dotPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z7mat_dotPfS_S_iiii
.p2align 3, 0x0
_Z7mat_dotPfS_S_iiii:
.quad _Z22__device_stub__mat_dotPfS_S_iiii
.size _Z7mat_dotPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mat_dotPfS_S_iiii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_dotPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mat_dotPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
cudaMalloc((void**)&in_dev, sizeof(in));
cudaMemcpy(in_dev, in , sizeof(in), cudaMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
cudaMemcpy(in, in_dev , sizeof(in), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.U32.AND P0, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x001fda0003f04070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0070*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0080*/ LDG.E.STRONG.SYS R5, [R2.64+0x80] ; /* 0x0000800402057981 */
/* 0x000ea4000c1f5900 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c115904 */
/*00b0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*00c0*/ LDG.E.STRONG.SYS R7, [R2.64+0x40] ; /* 0x0000400402077981 */
/* 0x000ea4000c1f5900 */
/*00d0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c115904 */
/*00f0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0100*/ LDG.E.STRONG.SYS R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x000ea4000c1f5900 */
/*0110*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*0120*/ STG.E.STRONG.SYS [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c115904 */
/*0130*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0140*/ LDG.E.STRONG.SYS R11, [R2.64+0x10] ; /* 0x00001004020b7981 */
/* 0x000ea4000c1f5900 */
/*0150*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E.STRONG.SYS [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c115904 */
/*0170*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0180*/ LDG.E.STRONG.SYS R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea4000c1f5900 */
/*0190*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c115904 */
/*01b0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*01c0*/ LDG.E.STRONG.SYS R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x002ea4000c1f5900 */
/*01d0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c115904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
cudaMalloc((void**)&in_dev, sizeof(in));
cudaMemcpy(in_dev, in , sizeof(in), cudaMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
cudaMemcpy(in, in_dev , sizeof(in), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} | .file "tmpxft_00177b62_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4testPfPf
.type _Z23__device_stub__Z4testPfPf, @function
_Z23__device_stub__Z4testPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z4testPfPf, .-_Z23__device_stub__Z4testPfPf
.globl _Z4testPf
.type _Z4testPf, @function
_Z4testPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4testPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testPf, .-_Z4testPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $312, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 288(%rsp), %rbp
movq %rbx, %rax
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L12
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z23__device_stub__Z4testPfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4testPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
cudaMalloc((void**)&in_dev, sizeof(in));
cudaMemcpy(in_dev, in , sizeof(in), cudaMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
cudaMemcpy(in, in_dev , sizeof(in), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
hipMalloc((void**)&in_dev, sizeof(in));
hipMemcpy(in_dev, in , sizeof(in), hipMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
hipMemcpy(in, in_dev , sizeof(in), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
hipMalloc((void**)&in_dev, sizeof(in));
hipMemcpy(in_dev, in , sizeof(in), hipMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
hipMemcpy(in, in_dev , sizeof(in), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v0, 0x80, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s0, v0
v_add_co_u32 v2, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s2
v_add_co_ci_u32_e64 v3, null, s1, 0, s0
flat_load_b32 v0, v[0:1] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:64 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:32 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:16 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:8 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:4 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float in[64];
for(int i = 0;i < 64;++i) {
in[i] = 1;
}
float *in_dev;
hipMalloc((void**)&in_dev, sizeof(in));
hipMemcpy(in_dev, in , sizeof(in), hipMemcpyHostToDevice);
dim3 block(32,1);
dim3 grid(1,1);
test<<<grid, block>>>(in_dev);
hipMemcpy(in, in_dev , sizeof(in), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for(int i = 0;i < 64;++i) {
cout << in[i] <<" ";
}
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _Z19__device_stub__testPf,@function
_Z19__device_stub__testPf: # @_Z19__device_stub__testPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testPf, .Lfunc_end0-_Z19__device_stub__testPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 80(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4testPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $64, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPf,@object # @_Z4testPf
.section .rodata,"a",@progbits
.globl _Z4testPf
.p2align 3, 0x0
_Z4testPf:
.quad _Z19__device_stub__testPf
.size _Z4testPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.U32.AND P0, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x001fda0003f04070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0070*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0080*/ LDG.E.STRONG.SYS R5, [R2.64+0x80] ; /* 0x0000800402057981 */
/* 0x000ea4000c1f5900 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c115904 */
/*00b0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*00c0*/ LDG.E.STRONG.SYS R7, [R2.64+0x40] ; /* 0x0000400402077981 */
/* 0x000ea4000c1f5900 */
/*00d0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c115904 */
/*00f0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0100*/ LDG.E.STRONG.SYS R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x000ea4000c1f5900 */
/*0110*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*0120*/ STG.E.STRONG.SYS [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c115904 */
/*0130*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0140*/ LDG.E.STRONG.SYS R11, [R2.64+0x10] ; /* 0x00001004020b7981 */
/* 0x000ea4000c1f5900 */
/*0150*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E.STRONG.SYS [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c115904 */
/*0170*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*0180*/ LDG.E.STRONG.SYS R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea4000c1f5900 */
/*0190*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c115904 */
/*01b0*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1f5900 */
/*01c0*/ LDG.E.STRONG.SYS R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x002ea4000c1f5900 */
/*01d0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c115904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v0, 0x80, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s0, v0
v_add_co_u32 v2, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s2
v_add_co_ci_u32_e64 v3, null, s1, 0, s0
flat_load_b32 v0, v[0:1] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:64 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:32 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:16 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:8 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] offset:4 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v1, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177b62_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4testPfPf
.type _Z23__device_stub__Z4testPfPf, @function
_Z23__device_stub__Z4testPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z4testPfPf, .-_Z23__device_stub__Z4testPfPf
.globl _Z4testPf
.type _Z4testPf, @function
_Z4testPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4testPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testPf, .-_Z4testPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $312, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 288(%rsp), %rbp
movq %rbx, %rax
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L12
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z23__device_stub__Z4testPfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4testPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _Z19__device_stub__testPf,@function
_Z19__device_stub__testPf: # @_Z19__device_stub__testPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testPf, .Lfunc_end0-_Z19__device_stub__testPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 80(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4testPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $64, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPf,@object # @_Z4testPf
.section .rodata,"a",@progbits
.globl _Z4testPf
.p2align 3, 0x0
_Z4testPf:
.quad _Z19__device_stub__testPf
.size _Z4testPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(sourceImg[id].x!=255 && sourceImg[id].y!=255 && sourceImg[id].z!=255)
{
mask[id]=1;
}
}
}
__global__ void borderMark(unsigned char *border,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
//int size=cols*rows;
int r=id/cols;
int c=id%cols;
int cnt=0;
int x=r*cols+c;
if(r>0 && r<rows && c>0 && c<cols){
if(mask[x-cols]==1)
cnt++;
if(mask[x+cols]==1)
cnt++;
if(mask[x+1]==1)
cnt++;
if(mask[x-1]==1)
cnt++;
}
if(cnt==0)
border[id]=0;
else if(cnt==4)
border[id]=2;
else
border[id]=1;
}
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
redChannel[id]=inputImageRGBA[id].x;
blueChannel[id]=inputImageRGBA[id].z;
greenChannel[id]=inputImageRGBA[id].y;
}
}
__global__ void init_guess(unsigned char *channel,float* buf1,float* buf2,int sz)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
unsigned char x=channel[id];
if(id<sz)
{
buf1[id]=x;
buf2[id]=x;
}
}
__global__ void blender(unsigned char *sourceChannel,
unsigned char* destChannel,
float *pbuf,
float *cbuf,
int numCols,
int numRows,
unsigned char* border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
float sum1=0,sum2=0;
int row=id/numCols;
int col=id%numCols;
if(row<numRows && col<numCols)
{
if(border[id]==2)
{
unsigned char sc=sourceChannel[id];
int n1=(row-1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col-1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col+1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row+1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
float newVal=(sum1+sum2)/4.f;
cbuf[id]=min(255.f, max(0.f, newVal));
}
}
}
__global__ void final_merge(uchar4 *blendedImg,
int numCols,
int numRows,
float *green,
float *blue,
float *red,
unsigned char *border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
if(border[id]==2)
{
blendedImg[id].x=red[id];
blendedImg[id].z=blue[id];
blendedImg[id].y=green[id];
}
}
}
int main()
{
int numRowsSource, numColsSource;
numRowsSource=540;//Hard Coded values
numColsSource=960;
uchar4* h_sourceImg,*h_destImg,*h_blendedImg; //IN
int totalSize=numColsSource*numRowsSource;
freopen("s_im.txt","r",stdin);
h_sourceImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_destImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_blendedImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
int t1;
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_sourceImg[i*numColsSource+j].z=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].y=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].x=t1;
}
}
freopen("d_im.txt","r",stdin);
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_destImg[i*numColsSource+j].z=t1;
cin>>t1;
h_destImg[i*numColsSource+j].y=t1;
cin>>t1;
h_destImg[i*numColsSource+j].x=t1;
}
}
cout<<"input taken"<<endl;
//freopen("d_out.txt","w",stdout);
uchar4 *d_sourceImg,*d_destImg;
bool *d_mask;
cudaStream_t rstream,gstream,bstream;
cudaStreamCreate(&rstream);
cudaStreamCreate(&gstream);
cudaStreamCreate(&bstream);
unsigned char *source_r,*source_g,*source_b,*dest_r,*dest_b,*dest_g,*d_border;
cudaMalloc((uchar4**)&d_sourceImg,sizeof(uchar4)*totalSize);
cudaMalloc((uchar4**)&d_destImg,sizeof(uchar4)*totalSize);
cudaMemcpy(d_destImg,h_destImg,sizeof(uchar4)*totalSize,cudaMemcpyHostToDevice);
cudaMemcpy(d_sourceImg,h_sourceImg,sizeof(uchar4)*totalSize,cudaMemcpyHostToDevice);
cudaMalloc((bool**)&d_mask,sizeof(bool)*totalSize);
cudaMalloc((unsigned char**)&d_border,sizeof(char)*totalSize);
int blocks=(totalSize)/THREADS_PER_BLOCK;
//1
maskCompute<<<blocks,THREADS_PER_BLOCK>>>(d_sourceImg,d_mask,numColsSource,numRowsSource);
//2
borderMark<<<blocks,THREADS_PER_BLOCK>>>(d_border,d_mask,numColsSource,numRowsSource);
//3
//Channels for source image
cudaMalloc((unsigned char**)&source_r,sizeof(char)*totalSize);
cudaMalloc((unsigned char**)&source_b,sizeof(char)*totalSize);
cudaMalloc((unsigned char**)&source_g,sizeof(char)*totalSize);
//channels for destination image
cudaMalloc((unsigned char**)&dest_r,sizeof(char)*totalSize);
cudaMalloc((unsigned char**)&dest_b,sizeof(char)*totalSize);
cudaMalloc((unsigned char**)&dest_g,sizeof(char)*totalSize);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(d_sourceImg,numRowsSource,numColsSource,source_r,source_g,source_b);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(d_destImg,numRowsSource,numColsSource,dest_r,dest_g,dest_b);
//4
float *buf1_r,*buf1_g,*buf1_b,*buf2_r,*buf2_g,*buf2_b;
cudaMalloc((float**)&buf1_r,sizeof(float)*totalSize);
cudaMalloc((float**)&buf1_g,sizeof(float)*totalSize);
cudaMalloc((float**)&buf1_b,sizeof(float)*totalSize);
cudaMalloc((float**)&buf2_r,sizeof(float)*totalSize);
cudaMalloc((float**)&buf2_g,sizeof(float)*totalSize);
cudaMalloc((float**)&buf2_b,sizeof(float)*totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,buf1_r,buf2_r,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,buf1_g,buf2_g,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,buf1_b,buf2_b,totalSize);
//5
//Call the kernel 800 times for each color channel
for(int i=0;i<400;i++)
{
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf1_r,buf2_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf1_b,buf2_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf1_g,buf2_g,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf2_r,buf1_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf2_b,buf1_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf2_g,buf1_g,numColsSource,numRowsSource,d_border);
}
final_merge<<<blocks,THREADS_PER_BLOCK>>>(d_destImg,numColsSource,numRowsSource,buf1_g,buf1_b,buf1_r,d_border);
cudaMemcpy(h_blendedImg,d_destImg,sizeof(uchar4)*totalSize,cudaMemcpyDeviceToHost);
int sz=numColsSource*numRowsSource;
freopen("b_out.txt","w",stdout);
for(int i=0;i<sz;i++)
{
cout<<int(h_blendedImg[i].z)<<" "<<int(h_blendedImg[i].y)<<" "<<int(h_blendedImg[i].x)<<" ";
}
cudaDeviceReset();
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(sourceImg[id].x!=255 && sourceImg[id].y!=255 && sourceImg[id].z!=255)
{
mask[id]=1;
}
}
}
__global__ void borderMark(unsigned char *border,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
//int size=cols*rows;
int r=id/cols;
int c=id%cols;
int cnt=0;
int x=r*cols+c;
if(r>0 && r<rows && c>0 && c<cols){
if(mask[x-cols]==1)
cnt++;
if(mask[x+cols]==1)
cnt++;
if(mask[x+1]==1)
cnt++;
if(mask[x-1]==1)
cnt++;
}
if(cnt==0)
border[id]=0;
else if(cnt==4)
border[id]=2;
else
border[id]=1;
}
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
redChannel[id]=inputImageRGBA[id].x;
blueChannel[id]=inputImageRGBA[id].z;
greenChannel[id]=inputImageRGBA[id].y;
}
}
__global__ void init_guess(unsigned char *channel,float* buf1,float* buf2,int sz)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
unsigned char x=channel[id];
if(id<sz)
{
buf1[id]=x;
buf2[id]=x;
}
}
__global__ void blender(unsigned char *sourceChannel,
unsigned char* destChannel,
float *pbuf,
float *cbuf,
int numCols,
int numRows,
unsigned char* border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
float sum1=0,sum2=0;
int row=id/numCols;
int col=id%numCols;
if(row<numRows && col<numCols)
{
if(border[id]==2)
{
unsigned char sc=sourceChannel[id];
int n1=(row-1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col-1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col+1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row+1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
float newVal=(sum1+sum2)/4.f;
cbuf[id]=min(255.f, max(0.f, newVal));
}
}
}
__global__ void final_merge(uchar4 *blendedImg,
int numCols,
int numRows,
float *green,
float *blue,
float *red,
unsigned char *border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
if(border[id]==2)
{
blendedImg[id].x=red[id];
blendedImg[id].z=blue[id];
blendedImg[id].y=green[id];
}
}
}
int main()
{
int numRowsSource, numColsSource;
numRowsSource=540;//Hard Coded values
numColsSource=960;
uchar4* h_sourceImg,*h_destImg,*h_blendedImg; //IN
int totalSize=numColsSource*numRowsSource;
freopen("s_im.txt","r",stdin);
h_sourceImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_destImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_blendedImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
int t1;
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_sourceImg[i*numColsSource+j].z=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].y=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].x=t1;
}
}
freopen("d_im.txt","r",stdin);
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_destImg[i*numColsSource+j].z=t1;
cin>>t1;
h_destImg[i*numColsSource+j].y=t1;
cin>>t1;
h_destImg[i*numColsSource+j].x=t1;
}
}
cout<<"input taken"<<endl;
//freopen("d_out.txt","w",stdout);
uchar4 *d_sourceImg,*d_destImg;
bool *d_mask;
hipStream_t rstream,gstream,bstream;
hipStreamCreate(&rstream);
hipStreamCreate(&gstream);
hipStreamCreate(&bstream);
unsigned char *source_r,*source_g,*source_b,*dest_r,*dest_b,*dest_g,*d_border;
hipMalloc((uchar4**)&d_sourceImg,sizeof(uchar4)*totalSize);
hipMalloc((uchar4**)&d_destImg,sizeof(uchar4)*totalSize);
hipMemcpy(d_destImg,h_destImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMemcpy(d_sourceImg,h_sourceImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMalloc((bool**)&d_mask,sizeof(bool)*totalSize);
hipMalloc((unsigned char**)&d_border,sizeof(char)*totalSize);
int blocks=(totalSize)/THREADS_PER_BLOCK;
//1
maskCompute<<<blocks,THREADS_PER_BLOCK>>>(d_sourceImg,d_mask,numColsSource,numRowsSource);
//2
borderMark<<<blocks,THREADS_PER_BLOCK>>>(d_border,d_mask,numColsSource,numRowsSource);
//3
//Channels for source image
hipMalloc((unsigned char**)&source_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_g,sizeof(char)*totalSize);
//channels for destination image
hipMalloc((unsigned char**)&dest_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_g,sizeof(char)*totalSize);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(d_sourceImg,numRowsSource,numColsSource,source_r,source_g,source_b);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(d_destImg,numRowsSource,numColsSource,dest_r,dest_g,dest_b);
//4
float *buf1_r,*buf1_g,*buf1_b,*buf2_r,*buf2_g,*buf2_b;
hipMalloc((float**)&buf1_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_b,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_b,sizeof(float)*totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,buf1_r,buf2_r,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,buf1_g,buf2_g,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,buf1_b,buf2_b,totalSize);
//5
//Call the kernel 800 times for each color channel
for(int i=0;i<400;i++)
{
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf1_r,buf2_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf1_b,buf2_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf1_g,buf2_g,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf2_r,buf1_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf2_b,buf1_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf2_g,buf1_g,numColsSource,numRowsSource,d_border);
}
final_merge<<<blocks,THREADS_PER_BLOCK>>>(d_destImg,numColsSource,numRowsSource,buf1_g,buf1_b,buf1_r,d_border);
hipMemcpy(h_blendedImg,d_destImg,sizeof(uchar4)*totalSize,hipMemcpyDeviceToHost);
int sz=numColsSource*numRowsSource;
freopen("b_out.txt","w",stdout);
for(int i=0;i<sz;i++)
{
cout<<int(h_blendedImg[i].z)<<" "<<int(h_blendedImg[i].y)<<" "<<int(h_blendedImg[i].x)<<" ";
}
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(sourceImg[id].x!=255 && sourceImg[id].y!=255 && sourceImg[id].z!=255)
{
mask[id]=1;
}
}
}
__global__ void borderMark(unsigned char *border,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
//int size=cols*rows;
int r=id/cols;
int c=id%cols;
int cnt=0;
int x=r*cols+c;
if(r>0 && r<rows && c>0 && c<cols){
if(mask[x-cols]==1)
cnt++;
if(mask[x+cols]==1)
cnt++;
if(mask[x+1]==1)
cnt++;
if(mask[x-1]==1)
cnt++;
}
if(cnt==0)
border[id]=0;
else if(cnt==4)
border[id]=2;
else
border[id]=1;
}
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
redChannel[id]=inputImageRGBA[id].x;
blueChannel[id]=inputImageRGBA[id].z;
greenChannel[id]=inputImageRGBA[id].y;
}
}
__global__ void init_guess(unsigned char *channel,float* buf1,float* buf2,int sz)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
unsigned char x=channel[id];
if(id<sz)
{
buf1[id]=x;
buf2[id]=x;
}
}
__global__ void blender(unsigned char *sourceChannel,
unsigned char* destChannel,
float *pbuf,
float *cbuf,
int numCols,
int numRows,
unsigned char* border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
float sum1=0,sum2=0;
int row=id/numCols;
int col=id%numCols;
if(row<numRows && col<numCols)
{
if(border[id]==2)
{
unsigned char sc=sourceChannel[id];
int n1=(row-1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col-1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col+1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row+1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
float newVal=(sum1+sum2)/4.f;
cbuf[id]=min(255.f, max(0.f, newVal));
}
}
}
__global__ void final_merge(uchar4 *blendedImg,
int numCols,
int numRows,
float *green,
float *blue,
float *red,
unsigned char *border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
if(border[id]==2)
{
blendedImg[id].x=red[id];
blendedImg[id].z=blue[id];
blendedImg[id].y=green[id];
}
}
}
int main()
{
int numRowsSource, numColsSource;
numRowsSource=540;//Hard Coded values
numColsSource=960;
uchar4* h_sourceImg,*h_destImg,*h_blendedImg; //IN
int totalSize=numColsSource*numRowsSource;
freopen("s_im.txt","r",stdin);
h_sourceImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_destImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_blendedImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
int t1;
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_sourceImg[i*numColsSource+j].z=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].y=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].x=t1;
}
}
freopen("d_im.txt","r",stdin);
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_destImg[i*numColsSource+j].z=t1;
cin>>t1;
h_destImg[i*numColsSource+j].y=t1;
cin>>t1;
h_destImg[i*numColsSource+j].x=t1;
}
}
cout<<"input taken"<<endl;
//freopen("d_out.txt","w",stdout);
uchar4 *d_sourceImg,*d_destImg;
bool *d_mask;
hipStream_t rstream,gstream,bstream;
hipStreamCreate(&rstream);
hipStreamCreate(&gstream);
hipStreamCreate(&bstream);
unsigned char *source_r,*source_g,*source_b,*dest_r,*dest_b,*dest_g,*d_border;
hipMalloc((uchar4**)&d_sourceImg,sizeof(uchar4)*totalSize);
hipMalloc((uchar4**)&d_destImg,sizeof(uchar4)*totalSize);
hipMemcpy(d_destImg,h_destImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMemcpy(d_sourceImg,h_sourceImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMalloc((bool**)&d_mask,sizeof(bool)*totalSize);
hipMalloc((unsigned char**)&d_border,sizeof(char)*totalSize);
int blocks=(totalSize)/THREADS_PER_BLOCK;
//1
maskCompute<<<blocks,THREADS_PER_BLOCK>>>(d_sourceImg,d_mask,numColsSource,numRowsSource);
//2
borderMark<<<blocks,THREADS_PER_BLOCK>>>(d_border,d_mask,numColsSource,numRowsSource);
//3
//Channels for source image
hipMalloc((unsigned char**)&source_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_g,sizeof(char)*totalSize);
//channels for destination image
hipMalloc((unsigned char**)&dest_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_g,sizeof(char)*totalSize);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(d_sourceImg,numRowsSource,numColsSource,source_r,source_g,source_b);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(d_destImg,numRowsSource,numColsSource,dest_r,dest_g,dest_b);
//4
float *buf1_r,*buf1_g,*buf1_b,*buf2_r,*buf2_g,*buf2_b;
hipMalloc((float**)&buf1_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_b,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_b,sizeof(float)*totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,buf1_r,buf2_r,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,buf1_g,buf2_g,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,buf1_b,buf2_b,totalSize);
//5
//Call the kernel 800 times for each color channel
for(int i=0;i<400;i++)
{
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf1_r,buf2_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf1_b,buf2_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf1_g,buf2_g,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf2_r,buf1_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf2_b,buf1_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf2_g,buf1_g,numColsSource,numRowsSource,d_border);
}
final_merge<<<blocks,THREADS_PER_BLOCK>>>(d_destImg,numColsSource,numRowsSource,buf1_g,buf1_b,buf1_r,d_border);
hipMemcpy(h_blendedImg,d_destImg,sizeof(uchar4)*totalSize,hipMemcpyDeviceToHost);
int sz=numColsSource*numRowsSource;
freopen("b_out.txt","w",stdout);
for(int i=0;i<sz;i++)
{
cout<<int(h_blendedImg[i].z)<<" "<<int(h_blendedImg[i].y)<<" "<<int(h_blendedImg[i].x)<<" ";
}
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.globl _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.p2align 8
.type _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii,@function
_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mul_i32 s2, s7, s6
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s2, v2
global_store_b8 v[0:1], v4, off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0xff, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_load_u8 v4, v[2:3], off offset:1
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0xff, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_load_u8 v2, v[2:3], off offset:2
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0xff, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii, .Lfunc_end0-_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10borderMarkPhPbii
.globl _Z10borderMarkPhPbii
.p2align 8
.type _Z10borderMarkPhPbii,@function
_Z10borderMarkPhPbii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s5, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
s_mov_b32 s4, exec_lo
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v0, v2
v_mov_b32_e32 v2, 0
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB1_4
s_load_b32 s2, s[0:1], 0x14
v_mul_lo_u32 v0, v3, s3
s_cmp_gt_i32 s3, -1
v_mov_b32_e32 v2, 0
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 s5, vcc_lo, s5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, s5, s2
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB1_3
s_load_b64 s[6:7], s[0:1], 0x8
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v0, s3, v4
v_add_nc_u32_e32 v5, s3, v4
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_ashrrev_i32_e32 v0, 31, v4
s_clause 0x1
global_load_u8 v7, v[2:3], off
global_load_u8 v5, v[5:6], off
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v0, vcc_lo
s_clause 0x1
global_load_u8 v0, v[2:3], off offset:1
global_load_u8 v2, v[2:3], off offset:-1
s_waitcnt vmcnt(2)
v_add_nc_u16 v3, v5, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v0, v3, v0
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0xff, v0
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_cmp_eq_u32_e32 vcc_lo, 4, v2
v_ashrrev_i32_e32 v3, 31, v1
v_cndmask_b32_e64 v4, 1, 2, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10borderMarkPhPbii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10borderMarkPhPbii, .Lfunc_end1-_Z10borderMarkPhPbii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.globl _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 8
.type _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@function
_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b8 v[5:6], v0, off
global_load_u8 v0, v[3:4], off offset:2
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[5:6], v0, off
global_load_u8 v3, v[3:4], off offset:1
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v3, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, .Lfunc_end2-_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10init_guessPhPfS0_i
.globl _Z10init_guessPhPfS0_i
.p2align 8
.type _Z10init_guessPhPfS0_i,@function
_Z10init_guessPhPfS0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
global_load_u8 v4, v[3:4], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v4, v4
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10init_guessPhPfS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10init_guessPhPfS0_i, .Lfunc_end3-_Z10init_guessPhPfS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7blenderPhS_PfS0_iiS_
.globl _Z7blenderPhS_PfS0_iiS_
.p2align 8
.type _Z7blenderPhS_PfS0_iiS_,@function
_Z7blenderPhS_PfS0_iiS_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s2, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s6, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s6
s_cmp_gt_i32 s2, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s4, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
v_add_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v5, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v5
s_cselect_b32 s3, -1, 0
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB4_19
s_load_b64 s[10:11], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_19
v_mul_lo_u32 v11, v5, s2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_add_nc_u32_e32 v6, -1, v5
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v11
v_mad_u64_u32 v[3:4], null, v6, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v6, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v2, vcc_lo
global_load_u8 v6, v[6:7], off
global_load_u8 v9, v[8:9], off
s_waitcnt vmcnt(1)
v_cmpx_ne_u16_e32 2, v6
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB4_4
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v10, v6
.LBB4_4:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB4_6
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v10, 0, v6
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s3
v_mad_u64_u32 v[7:8], null, v5, s2, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, -1, v7
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v12, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_u8 v8, v[12:13], off
global_load_u8 v12, v[3:4], off
s_waitcnt vmcnt(1)
v_cmpx_ne_u16_e32 2, v8
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB4_8
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v13, v3
.LBB4_8:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB4_10
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v13, v[3:4], off
.LBB4_10:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v7, 1, v7
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v3, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_u8 v3, v[3:4], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cmpx_ne_u16_e32 2, v3
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB4_12
v_add_co_u32 v3, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v3
.LBB4_12:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB4_14
v_lshlrev_b64 v[3:4], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v6, v[3:4], off
.LBB4_14:
s_or_b32 exec_lo, exec_lo, s3
v_add3_u32 v3, v11, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v14, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_u8 v11, v[14:15], off
global_load_u8 v0, v[7:8], off
s_waitcnt vmcnt(1)
v_cmpx_ne_u16_e32 2, v11
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB4_16
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v7, v7
.LBB4_16:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB4_18
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.LBB4_18:
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_and_b32_e32 v8, 0xff, v12
s_load_b64 s[0:1], s[0:1], 0x18
global_load_u8 v3, v[3:4], off
v_and_b32_e32 v4, 0xff, v9
v_add_f32_e32 v9, v10, v13
v_and_b32_e32 v5, 0xff, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v4, v8
v_sub_nc_u32_e32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, v8
v_cvt_f32_i32_e32 v5, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v8, v5 :: v_dual_and_b32 v0, 0xff, v0
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_add_f32_e32 v0, v5, v0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v4, v3
v_add_f32_e32 v4, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v3, v3
v_add_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v3
v_add_f32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x3e800000, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_maxmin_f32 v2, v3, 0, 0x437f0000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB4_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7blenderPhS_PfS0_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z7blenderPhS_PfS0_iiS_, .Lfunc_end4-_Z7blenderPhS_PfS0_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.globl _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.p2align 8
.type _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph,@function
_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB5_3
s_load_b64 s[2:3], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB5_3
s_load_b64 s[2:3], s[0:1], 0x20
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v6, v4
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[2:3], v6, off
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
global_store_b8 v[2:3], v4, off offset:2
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v0
global_store_b8 v[2:3], v0, off offset:1
.LBB5_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, .Lfunc_end5-_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10borderMarkPhPbii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10borderMarkPhPbii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10init_guessPhPfS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10init_guessPhPfS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7blenderPhS_PfS0_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7blenderPhS_PfS0_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(sourceImg[id].x!=255 && sourceImg[id].y!=255 && sourceImg[id].z!=255)
{
mask[id]=1;
}
}
}
__global__ void borderMark(unsigned char *border,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
//int size=cols*rows;
int r=id/cols;
int c=id%cols;
int cnt=0;
int x=r*cols+c;
if(r>0 && r<rows && c>0 && c<cols){
if(mask[x-cols]==1)
cnt++;
if(mask[x+cols]==1)
cnt++;
if(mask[x+1]==1)
cnt++;
if(mask[x-1]==1)
cnt++;
}
if(cnt==0)
border[id]=0;
else if(cnt==4)
border[id]=2;
else
border[id]=1;
}
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
redChannel[id]=inputImageRGBA[id].x;
blueChannel[id]=inputImageRGBA[id].z;
greenChannel[id]=inputImageRGBA[id].y;
}
}
__global__ void init_guess(unsigned char *channel,float* buf1,float* buf2,int sz)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
unsigned char x=channel[id];
if(id<sz)
{
buf1[id]=x;
buf2[id]=x;
}
}
__global__ void blender(unsigned char *sourceChannel,
unsigned char* destChannel,
float *pbuf,
float *cbuf,
int numCols,
int numRows,
unsigned char* border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
float sum1=0,sum2=0;
int row=id/numCols;
int col=id%numCols;
if(row<numRows && col<numCols)
{
if(border[id]==2)
{
unsigned char sc=sourceChannel[id];
int n1=(row-1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col-1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row)*numCols+col+1;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
n1=(row+1)*numCols+col;
if(border[n1]==2)
sum1+=pbuf[n1];
else
sum1+=destChannel[n1];
sum2+=sc-sourceChannel[n1];
float newVal=(sum1+sum2)/4.f;
cbuf[id]=min(255.f, max(0.f, newVal));
}
}
}
__global__ void final_merge(uchar4 *blendedImg,
int numCols,
int numRows,
float *green,
float *blue,
float *red,
unsigned char *border)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<numRows*numCols)
{
if(border[id]==2)
{
blendedImg[id].x=red[id];
blendedImg[id].z=blue[id];
blendedImg[id].y=green[id];
}
}
}
int main()
{
int numRowsSource, numColsSource;
numRowsSource=540;//Hard Coded values
numColsSource=960;
uchar4* h_sourceImg,*h_destImg,*h_blendedImg; //IN
int totalSize=numColsSource*numRowsSource;
freopen("s_im.txt","r",stdin);
h_sourceImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_destImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
h_blendedImg=(uchar4*)malloc(sizeof(uchar4)*totalSize);
int t1;
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_sourceImg[i*numColsSource+j].z=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].y=t1;
cin>>t1;
h_sourceImg[i*numColsSource+j].x=t1;
}
}
freopen("d_im.txt","r",stdin);
for(int i=0;i<numRowsSource;i++)
{
for(int j=0;j<numColsSource;j++)
{
cin>>t1;
h_destImg[i*numColsSource+j].z=t1;
cin>>t1;
h_destImg[i*numColsSource+j].y=t1;
cin>>t1;
h_destImg[i*numColsSource+j].x=t1;
}
}
cout<<"input taken"<<endl;
//freopen("d_out.txt","w",stdout);
uchar4 *d_sourceImg,*d_destImg;
bool *d_mask;
hipStream_t rstream,gstream,bstream;
hipStreamCreate(&rstream);
hipStreamCreate(&gstream);
hipStreamCreate(&bstream);
unsigned char *source_r,*source_g,*source_b,*dest_r,*dest_b,*dest_g,*d_border;
hipMalloc((uchar4**)&d_sourceImg,sizeof(uchar4)*totalSize);
hipMalloc((uchar4**)&d_destImg,sizeof(uchar4)*totalSize);
hipMemcpy(d_destImg,h_destImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMemcpy(d_sourceImg,h_sourceImg,sizeof(uchar4)*totalSize,hipMemcpyHostToDevice);
hipMalloc((bool**)&d_mask,sizeof(bool)*totalSize);
hipMalloc((unsigned char**)&d_border,sizeof(char)*totalSize);
int blocks=(totalSize)/THREADS_PER_BLOCK;
//1
maskCompute<<<blocks,THREADS_PER_BLOCK>>>(d_sourceImg,d_mask,numColsSource,numRowsSource);
//2
borderMark<<<blocks,THREADS_PER_BLOCK>>>(d_border,d_mask,numColsSource,numRowsSource);
//3
//Channels for source image
hipMalloc((unsigned char**)&source_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&source_g,sizeof(char)*totalSize);
//channels for destination image
hipMalloc((unsigned char**)&dest_r,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_b,sizeof(char)*totalSize);
hipMalloc((unsigned char**)&dest_g,sizeof(char)*totalSize);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(d_sourceImg,numRowsSource,numColsSource,source_r,source_g,source_b);
separateChannels<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(d_destImg,numRowsSource,numColsSource,dest_r,dest_g,dest_b);
//4
float *buf1_r,*buf1_g,*buf1_b,*buf2_r,*buf2_g,*buf2_b;
hipMalloc((float**)&buf1_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf1_b,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_r,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_g,sizeof(float)*totalSize);
hipMalloc((float**)&buf2_b,sizeof(float)*totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,buf1_r,buf2_r,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,buf1_g,buf2_g,totalSize);
init_guess<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,buf1_b,buf2_b,totalSize);
//5
//Call the kernel 800 times for each color channel
for(int i=0;i<400;i++)
{
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf1_r,buf2_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf1_b,buf2_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf1_g,buf2_g,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,rstream>>>(source_r,dest_r,buf2_r,buf1_r,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,bstream>>>(source_b,dest_b,buf2_b,buf1_b,numColsSource,numRowsSource,d_border);
blender<<<blocks,THREADS_PER_BLOCK,0,gstream>>>(source_g,dest_g,buf2_g,buf1_g,numColsSource,numRowsSource,d_border);
}
final_merge<<<blocks,THREADS_PER_BLOCK>>>(d_destImg,numColsSource,numRowsSource,buf1_g,buf1_b,buf1_r,d_border);
hipMemcpy(h_blendedImg,d_destImg,sizeof(uchar4)*totalSize,hipMemcpyDeviceToHost);
int sz=numColsSource*numRowsSource;
freopen("b_out.txt","w",stdout);
for(int i=0;i<sz;i++)
{
cout<<int(h_blendedImg[i].z)<<" "<<int(h_blendedImg[i].y)<<" "<<int(h_blendedImg[i].x)<<" ";
}
hipDeviceReset();
return 0;
} | .text
.file "blend.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii # -- Begin function _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii
.p2align 4, 0x90
.type _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii,@function
_Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii: # @_Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii, .Lfunc_end0-_Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__borderMarkPhPbii # -- Begin function _Z25__device_stub__borderMarkPhPbii
.p2align 4, 0x90
.type _Z25__device_stub__borderMarkPhPbii,@function
_Z25__device_stub__borderMarkPhPbii: # @_Z25__device_stub__borderMarkPhPbii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10borderMarkPhPbii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__borderMarkPhPbii, .Lfunc_end1-_Z25__device_stub__borderMarkPhPbii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_ # -- Begin function _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 4, 0x90
.type _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@function
_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_: # @_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, .Lfunc_end2-_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__init_guessPhPfS0_i # -- Begin function _Z25__device_stub__init_guessPhPfS0_i
.p2align 4, 0x90
.type _Z25__device_stub__init_guessPhPfS0_i,@function
_Z25__device_stub__init_guessPhPfS0_i: # @_Z25__device_stub__init_guessPhPfS0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10init_guessPhPfS0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__init_guessPhPfS0_i, .Lfunc_end3-_Z25__device_stub__init_guessPhPfS0_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__blenderPhS_PfS0_iiS_ # -- Begin function _Z22__device_stub__blenderPhS_PfS0_iiS_
.p2align 4, 0x90
.type _Z22__device_stub__blenderPhS_PfS0_iiS_,@function
_Z22__device_stub__blenderPhS_PfS0_iiS_: # @_Z22__device_stub__blenderPhS_PfS0_iiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7blenderPhS_PfS0_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z22__device_stub__blenderPhS_PfS0_iiS_, .Lfunc_end4-_Z22__device_stub__blenderPhS_PfS0_iiS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph # -- Begin function _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.p2align 4, 0x90
.type _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph,@function
_Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph: # @_Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, .Lfunc_end5-_Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rdx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq freopen
movl $2073600, %edi # imm = 0x1FA400
callq malloc
movq %rax, %rbx
movl $2073600, %edi # imm = 0x1FA400
callq malloc
movq %rax, %r15
movl $2073600, %edi # imm = 0x1FA400
callq malloc
movq %rax, 320(%rsp) # 8-byte Spill
movq %rbx, %r12
addq $2, %r12
xorl %r13d, %r13d
leaq 100(%rsp), %r14
.p2align 4, 0x90
.LBB6_1: # %.preheader347
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, (%r12,%rbp,4)
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, -1(%r12,%rbp,4)
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, -2(%r12,%rbp,4)
incq %rbp
cmpq $960, %rbp # imm = 0x3C0
jne .LBB6_2
# %bb.3: # in Loop: Header=BB6_1 Depth=1
incq %r13
addq $3840, %r12 # imm = 0xF00
cmpq $540, %r13 # imm = 0x21C
jne .LBB6_1
# %bb.4:
movq stdin(%rip), %rdx
movl $.L.str.2, %edi
movl $.L.str.1, %esi
callq freopen
movq %r15, %r12
addq $2, %r12
xorl %r13d, %r13d
leaq 100(%rsp), %r14
.p2align 4, 0x90
.LBB6_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_6: # Parent Loop BB6_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, (%r12,%rbp,4)
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, -1(%r12,%rbp,4)
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
movzbl 100(%rsp), %eax
movb %al, -2(%r12,%rbp,4)
incq %rbp
cmpq $960, %rbp # imm = 0x3C0
jne .LBB6_6
# %bb.7: # in Loop: Header=BB6_5 Depth=1
incq %r13
addq $3840, %r12 # imm = 0xF00
cmpq $540, %r13 # imm = 0x21C
jne .LBB6_5
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB6_45
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB6_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB6_12
.LBB6_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967552, %r14 # imm = 0x100000100
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 232(%rsp), %rdi
callq hipStreamCreate
leaq 224(%rsp), %rdi
callq hipStreamCreate
leaq 296(%rsp), %rdi
callq hipStreamCreate
leaq 304(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 240(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
movq 240(%rsp), %rdi
movl $2073600, %edx # imm = 0x1FA400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 304(%rsp), %rdi
movl $2073600, %edx # imm = 0x1FA400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 312(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 176(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 1769(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
movq 304(%rsp), %rax
movq 312(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $960, 40(%rsp) # imm = 0x3C0
movl $540, 88(%rsp) # imm = 0x21C
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
leaq 1769(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_16
# %bb.15:
movq 176(%rsp), %rax
movq 312(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $960, 40(%rsp) # imm = 0x3C0
movl $540, 88(%rsp) # imm = 0x21C
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10borderMarkPhPbii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_16:
leaq 216(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 200(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 208(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 288(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 280(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
leaq 272(%rsp), %rdi
movl $518400, %esi # imm = 0x7E900
callq hipMalloc
movq 232(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_18
# %bb.17:
movq 304(%rsp), %rax
movq 216(%rsp), %rcx
movq 208(%rsp), %rdx
movq 200(%rsp), %rsi
movq %rax, 72(%rsp)
movl $540, 104(%rsp) # imm = 0x21C
movl $960, 168(%rsp) # imm = 0x3C0
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_18:
movq 224(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_20
# %bb.19:
movq 240(%rsp), %rax
movq 288(%rsp), %rcx
movq 272(%rsp), %rdx
movq 280(%rsp), %rsi
movq %rax, 72(%rsp)
movl $540, 104(%rsp) # imm = 0x21C
movl $960, 168(%rsp) # imm = 0x3C0
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_20:
leaq 168(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 192(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 184(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 264(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 256(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 248(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
movq 232(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_22
# %bb.21:
movq 216(%rsp), %rax
movq 168(%rsp), %rcx
movq 264(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $518400, 88(%rsp) # imm = 0x7E900
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_guessPhPfS0_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_22:
movq 224(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_24
# %bb.23:
movq 208(%rsp), %rax
movq 192(%rsp), %rcx
movq 256(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $518400, 88(%rsp) # imm = 0x7E900
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_guessPhPfS0_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_24:
movq 296(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_26
# %bb.25:
movq 200(%rsp), %rax
movq 184(%rsp), %rcx
movq 248(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $518400, 88(%rsp) # imm = 0x7E900
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_guessPhPfS0_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_26:
movl $400, %r13d # imm = 0x190
leaq 88(%rsp), %rbp
leaq 104(%rsp), %rbx
leaq 112(%rsp), %r12
jmp .LBB6_27
.p2align 4, 0x90
.LBB6_39: # in Loop: Header=BB6_27 Depth=1
decl %r13d
je .LBB6_40
.LBB6_27: # =>This Inner Loop Header: Depth=1
movq 232(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_29
# %bb.28: # in Loop: Header=BB6_27 Depth=1
movq 216(%rsp), %rax
movq 288(%rsp), %rcx
movq 168(%rsp), %rdx
movq 264(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_29: # in Loop: Header=BB6_27 Depth=1
movq 296(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_31
# %bb.30: # in Loop: Header=BB6_27 Depth=1
movq 200(%rsp), %rax
movq 280(%rsp), %rcx
movq 184(%rsp), %rdx
movq 248(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_31: # in Loop: Header=BB6_27 Depth=1
movq 224(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_33
# %bb.32: # in Loop: Header=BB6_27 Depth=1
movq 208(%rsp), %rax
movq 272(%rsp), %rcx
movq 192(%rsp), %rdx
movq 256(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_33: # in Loop: Header=BB6_27 Depth=1
movq 232(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_35
# %bb.34: # in Loop: Header=BB6_27 Depth=1
movq 216(%rsp), %rax
movq 288(%rsp), %rcx
movq 264(%rsp), %rdx
movq 168(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_35: # in Loop: Header=BB6_27 Depth=1
movq 296(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_37
# %bb.36: # in Loop: Header=BB6_27 Depth=1
movq 200(%rsp), %rax
movq 280(%rsp), %rcx
movq 248(%rsp), %rdx
movq 184(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_37: # in Loop: Header=BB6_27 Depth=1
movq 224(%rsp), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_39
# %bb.38: # in Loop: Header=BB6_27 Depth=1
movq 208(%rsp), %rax
movq 272(%rsp), %rcx
movq 256(%rsp), %rdx
movq 192(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 84(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z7blenderPhS_PfS0_iiS_, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_39
.LBB6_40:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_42
# %bb.41:
movq 240(%rsp), %rax
movq 192(%rsp), %rcx
movq 184(%rsp), %rdx
movq 168(%rsp), %rsi
movq 176(%rsp), %rdi
movq %rax, 72(%rsp)
movl $960, 84(%rsp) # imm = 0x3C0
movl $540, 80(%rsp) # imm = 0x21C
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdi, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 84(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_42:
movq 240(%rsp), %rsi
movl $2073600, %edx # imm = 0x1FA400
movq 320(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq stdout(%rip), %rdx
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq freopen
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_43: # =>This Inner Loop Header: Depth=1
movzbl 2(%r15,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl 1(%r15,%r14,4), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl (%r15,%r14,4), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $518400, %r14 # imm = 0x7E900
jne .LBB6_43
# %bb.44:
callq hipDeviceReset
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_45:
.cfi_def_cfa_offset 384
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10borderMarkPhPbii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_guessPhPfS0_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7blenderPhS_PfS0_iiS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii,@object # @_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.section .rodata,"a",@progbits
.globl _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.p2align 3, 0x0
_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii:
.quad _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii
.size _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii, 8
.type _Z10borderMarkPhPbii,@object # @_Z10borderMarkPhPbii
.globl _Z10borderMarkPhPbii
.p2align 3, 0x0
_Z10borderMarkPhPbii:
.quad _Z25__device_stub__borderMarkPhPbii
.size _Z10borderMarkPhPbii, 8
.type _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@object # @_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.globl _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 3, 0x0
_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_:
.quad _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.size _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, 8
.type _Z10init_guessPhPfS0_i,@object # @_Z10init_guessPhPfS0_i
.globl _Z10init_guessPhPfS0_i
.p2align 3, 0x0
_Z10init_guessPhPfS0_i:
.quad _Z25__device_stub__init_guessPhPfS0_i
.size _Z10init_guessPhPfS0_i, 8
.type _Z7blenderPhS_PfS0_iiS_,@object # @_Z7blenderPhS_PfS0_iiS_
.globl _Z7blenderPhS_PfS0_iiS_
.p2align 3, 0x0
_Z7blenderPhS_PfS0_iiS_:
.quad _Z22__device_stub__blenderPhS_PfS0_iiS_
.size _Z7blenderPhS_PfS0_iiS_, 8
.type _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph,@object # @_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.globl _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.p2align 3, 0x0
_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph:
.quad _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.size _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "s_im.txt"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "d_im.txt"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "input taken"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "b_out.txt"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10borderMarkPhPbii"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_"
.size .L__unnamed_3, 57
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10init_guessPhPfS0_i"
.size .L__unnamed_4, 23
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z7blenderPhS_PfS0_iiS_"
.size .L__unnamed_5, 24
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph"
.size .L__unnamed_6, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii
.addrsig_sym _Z25__device_stub__borderMarkPhPbii
.addrsig_sym _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.addrsig_sym _Z25__device_stub__init_guessPhPfS0_i
.addrsig_sym _Z22__device_stub__blenderPhS_PfS0_iiS_
.addrsig_sym _Z26__device_stub__final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.addrsig_sym _Z10borderMarkPhPbii
.addrsig_sym _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.addrsig_sym _Z10init_guessPhPfS0_i
.addrsig_sym _Z7blenderPhS_PfS0_iiS_
.addrsig_sym _Z11final_mergeP15HIP_vector_typeIhLj4EEiiPfS2_S2_Ph
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
cudaMemcpy(a_d, a_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, bytes, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
cudaMemcpy(c_h, c_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
cudaFree(a_d);
free(b_h);
cudaFree(b_d);
free(c_h);
cudaFree(c_d);
} | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
cudaMemcpy(a_d, a_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, bytes, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
cudaMemcpy(c_h, c_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
cudaFree(a_d);
free(b_h);
cudaFree(b_d);
free(c_h);
cudaFree(c_d);
} | .file "tmpxft_0013a90b_00000000-6_vec-add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
divss %xmm1, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $11, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $10, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
cudaMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
cudaMemcpy(a_d, a_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, bytes, cudaMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
cudaMemcpy(c_h, c_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
cudaFree(a_d);
free(b_h);
cudaFree(b_d);
free(c_h);
cudaFree(c_d);
} | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
hipMemcpy(a_d, a_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, bytes, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
hipMemcpy(c_h, c_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
hipFree(a_d);
free(b_h);
hipFree(b_d);
free(c_h);
hipFree(c_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
hipMemcpy(a_d, a_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, bytes, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
hipMemcpy(c_h, c_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
hipFree(a_d);
free(b_h);
hipFree(b_d);
free(c_h);
hipFree(c_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
float *a_h;
float *a_d; // Pointer to host & device arrays
float *b_h;
float *b_d;
float *c_h;
float *c_d;
const int N = 10; // Number of elements in arrays
size_t bytes = N * sizeof(float);
a_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &a_d, bytes); // Allocate array on device
b_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &b_d, bytes); // Allocate array on device
c_h = (float *)malloc(bytes); // Allocate array on host
hipMalloc((void **) &c_d, bytes); // Allocate array on device
// Initialize host array and copy it to CUDA device
for (int i = 0; i < N; i++) {
a_h[i] = (float)i;
b_h[i] = (float)i/10;
}
hipMemcpy(a_d, a_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, bytes, hipMemcpyHostToDevice);
// Do calculation on device:
int block_size = 256;
int n_blocks = N-1/block_size + 1;
vector_add <<< n_blocks, block_size >>> (c_d, a_d, b_d, N);
// Retrieve result from device and store it in host array
hipMemcpy(c_h, c_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// Print results
for (int i=0; i<N; i++) {
printf("%d %f\n", i, c_h[i]);
}
// Cleanup
free(a_h);
hipFree(a_d);
free(b_h);
hipFree(b_d);
free(c_h);
hipFree(c_d);
} | .text
.file "vec-add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%rbx,%rax,4)
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967307, %rdi # imm = 0x10000000B
leaq 245(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r12d, %esi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a90b_00000000-6_vec-add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
divss %xmm1, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $11, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $10, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec-add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%rbx,%rax,4)
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967307, %rdi # imm = 0x10000000B
leaq 245(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r12d, %esi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} | code for sm_80
Function : kernel3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x003fc800078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*00b0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R5.reuse, 0x2, PT ; /* 0x000000020500780c */
/* 0x040fe40003f05270 */
/*0100*/ IADD3 R4, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fe40007ffe1ff */
/*0110*/ SEL R7, R0, RZ, P0 ; /* 0x000000ff00077207 */
/* 0x001fc40000000000 */
/*0120*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f46270 */
/*0140*/ @!P1 BRA 0x350 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0004 */
/*0170*/ @!P0 BRA 0x300 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P3 BRA 0x270 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*01d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x100fe40007ffe000 */
/*01f0*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0200*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0210*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0220*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0230*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0240*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0250*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fe20007ffe000 */
/*0260*/ @P3 BRA 0x1c0 ; /* 0xffffff5000003947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.GT.AND P3, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f64270 */
/*0280*/ @P3 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40003f0e170 */
/*0290*/ @P3 IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808083810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @P3 IADD3 R11, R0, R9, R0 ; /* 0x00000009000b3210 */
/* 0x020fc80007ffe000 */
/*02b0*/ @P3 IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b3210 */
/* 0x000fc80007ffe000 */
/*02c0*/ @P3 IADD3 R11, R0, R11, R0.reuse ; /* 0x0000000b000b3210 */
/* 0x100fe40007ffe000 */
/*02d0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000705670 */
/*02e0*/ @P3 IADD3 R9, R0, R11, R0 ; /* 0x0000000b00093210 */
/* 0x000fd60007ffe000 */
/*02f0*/ @!P0 BRA 0x350 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0330*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fd60007ffe000 */
/*0340*/ @P0 BRA 0x300 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0350*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0360*/ @!P0 BRA 0x3a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x020fd800078e0209 */
/*0390*/ @P0 IADD3 R9, R7, R9, R0 ; /* 0x0000000907090210 */
/* 0x000fe40007ffe000 */
/*03a0*/ @!P2 BRA 0x120 ; /* 0xfffffd700000a947 */
/* 0x000fea000383ffff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : kernel2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x003fc800078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*00b0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R5.reuse, 0x2, PT ; /* 0x000000020500780c */
/* 0x040fe40003f05270 */
/*0100*/ IADD3 R4, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fe40007ffe1ff */
/*0110*/ SEL R7, R0, RZ, P0 ; /* 0x000000ff00077207 */
/* 0x001fc40000000000 */
/*0120*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f46270 */
/*0140*/ @!P1 BRA 0x350 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0004 */
/*0170*/ @!P0 BRA 0x300 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P3 BRA 0x270 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*01d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x100fe40007ffe000 */
/*01f0*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0200*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0210*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0220*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0230*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0240*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0250*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fe20007ffe000 */
/*0260*/ @P3 BRA 0x1c0 ; /* 0xffffff5000003947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.GT.AND P3, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f64270 */
/*0280*/ @P3 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40003f0e170 */
/*0290*/ @P3 IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808083810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @P3 IADD3 R11, R0, R9, R0 ; /* 0x00000009000b3210 */
/* 0x020fc80007ffe000 */
/*02b0*/ @P3 IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b3210 */
/* 0x000fc80007ffe000 */
/*02c0*/ @P3 IADD3 R11, R0, R11, R0.reuse ; /* 0x0000000b000b3210 */
/* 0x100fe40007ffe000 */
/*02d0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000705670 */
/*02e0*/ @P3 IADD3 R9, R0, R11, R0 ; /* 0x0000000b00093210 */
/* 0x000fd60007ffe000 */
/*02f0*/ @!P0 BRA 0x350 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0330*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fd60007ffe000 */
/*0340*/ @P0 BRA 0x300 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0350*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0360*/ @!P0 BRA 0x3a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x020fd800078e0209 */
/*0390*/ @P0 IADD3 R9, R7, R9, R0 ; /* 0x0000000907090210 */
/* 0x000fe40007ffe000 */
/*03a0*/ @!P2 BRA 0x120 ; /* 0xfffffd700000a947 */
/* 0x000fea000383ffff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : kernel1
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x003fc800078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*00b0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R5.reuse, 0x2, PT ; /* 0x000000020500780c */
/* 0x040fe40003f05270 */
/*0100*/ IADD3 R4, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fe40007ffe1ff */
/*0110*/ SEL R7, R0, RZ, P0 ; /* 0x000000ff00077207 */
/* 0x001fc40000000000 */
/*0120*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f46270 */
/*0140*/ @!P1 BRA 0x350 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0004 */
/*0170*/ @!P0 BRA 0x300 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P3 BRA 0x270 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*01d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x100fe40007ffe000 */
/*01f0*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0200*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0210*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0220*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0230*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0240*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0250*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fe20007ffe000 */
/*0260*/ @P3 BRA 0x1c0 ; /* 0xffffff5000003947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.GT.AND P3, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f64270 */
/*0280*/ @P3 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40003f0e170 */
/*0290*/ @P3 IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808083810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @P3 IADD3 R11, R0, R9, R0 ; /* 0x00000009000b3210 */
/* 0x020fc80007ffe000 */
/*02b0*/ @P3 IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b3210 */
/* 0x000fc80007ffe000 */
/*02c0*/ @P3 IADD3 R11, R0, R11, R0.reuse ; /* 0x0000000b000b3210 */
/* 0x100fe40007ffe000 */
/*02d0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000705670 */
/*02e0*/ @P3 IADD3 R9, R0, R11, R0 ; /* 0x0000000b00093210 */
/* 0x000fd60007ffe000 */
/*02f0*/ @!P0 BRA 0x350 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0330*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fd60007ffe000 */
/*0340*/ @P0 BRA 0x300 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0350*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0360*/ @!P0 BRA 0x3a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x020fd800078e0209 */
/*0390*/ @P0 IADD3 R9, R7, R9, R0 ; /* 0x0000000907090210 */
/* 0x000fe40007ffe000 */
/*03a0*/ @!P2 BRA 0x120 ; /* 0xfffffd700000a947 */
/* 0x000fea000383ffff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : kernel0
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x003fc800078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*00b0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R5.reuse, 0x2, PT ; /* 0x000000020500780c */
/* 0x040fe40003f05270 */
/*0100*/ IADD3 R4, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fe40007ffe1ff */
/*0110*/ SEL R7, R0, RZ, P0 ; /* 0x000000ff00077207 */
/* 0x001fc40000000000 */
/*0120*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f46270 */
/*0140*/ @!P1 BRA 0x350 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd800078e0004 */
/*0170*/ @!P0 BRA 0x300 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P3 BRA 0x270 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*01d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x100fe40007ffe000 */
/*01f0*/ ISETP.GT.AND P3, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f64270 */
/*0200*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0210*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0220*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0230*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0240*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fc80007ffe000 */
/*0250*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fe20007ffe000 */
/*0260*/ @P3 BRA 0x1c0 ; /* 0xffffff5000003947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.GT.AND P3, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f64270 */
/*0280*/ @P3 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40003f0e170 */
/*0290*/ @P3 IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808083810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @P3 IADD3 R11, R0, R9, R0 ; /* 0x00000009000b3210 */
/* 0x020fc80007ffe000 */
/*02b0*/ @P3 IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b3210 */
/* 0x000fc80007ffe000 */
/*02c0*/ @P3 IADD3 R11, R0, R11, R0.reuse ; /* 0x0000000b000b3210 */
/* 0x100fe40007ffe000 */
/*02d0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000705670 */
/*02e0*/ @P3 IADD3 R9, R0, R11, R0 ; /* 0x0000000b00093210 */
/* 0x000fd60007ffe000 */
/*02f0*/ @!P0 BRA 0x350 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R9, R0, R9, R0.reuse ; /* 0x0000000900097210 */
/* 0x120fe40007ffe000 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0330*/ IADD3 R9, R0, R9, R0 ; /* 0x0000000900097210 */
/* 0x000fd60007ffe000 */
/*0340*/ @P0 BRA 0x300 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0350*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0360*/ @!P0 BRA 0x3a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x020fd800078e0209 */
/*0390*/ @P0 IADD3 R9, R7, R9, R0 ; /* 0x0000000907090210 */
/* 0x000fe40007ffe000 */
/*03a0*/ @!P2 BRA 0x120 ; /* 0xfffffd700000a947 */
/* 0x000fea000383ffff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} | .file "tmpxft_00185501_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7kernel0PiiPii
.type _Z27__device_stub__Z7kernel0PiiPii, @function
_Z27__device_stub__Z7kernel0PiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7kernel0PiiPii, .-_Z27__device_stub__Z7kernel0PiiPii
.globl kernel0
.type kernel0, @function
kernel0:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel0PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel0, .-kernel0
.globl _Z27__device_stub__Z7kernel1PiiPii
.type _Z27__device_stub__Z7kernel1PiiPii, @function
_Z27__device_stub__Z7kernel1PiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z7kernel1PiiPii, .-_Z27__device_stub__Z7kernel1PiiPii
.globl kernel1
.type kernel1, @function
kernel1:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel1PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size kernel1, .-kernel1
.globl _Z27__device_stub__Z7kernel2PiiPii
.type _Z27__device_stub__Z7kernel2PiiPii, @function
_Z27__device_stub__Z7kernel2PiiPii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z27__device_stub__Z7kernel2PiiPii, .-_Z27__device_stub__Z7kernel2PiiPii
.globl kernel2
.type kernel2, @function
kernel2:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel2PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size kernel2, .-kernel2
.globl _Z27__device_stub__Z7kernel3PiiPii
.type _Z27__device_stub__Z7kernel3PiiPii, @function
_Z27__device_stub__Z7kernel3PiiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z27__device_stub__Z7kernel3PiiPii, .-_Z27__device_stub__Z7kernel3PiiPii
.globl kernel3
.type kernel3, @function
kernel3:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel3PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size kernel3, .-kernel3
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel3"
.LC1:
.string "kernel2"
.LC2:
.string "kernel1"
.LC3:
.string "kernel0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kernel2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq kernel1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq kernel0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel0
.globl kernel0
.p2align 8
.type kernel0,@function
kernel0:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s0
global_load_b32 v3, v[1:2], off
v_add3_u32 v0, v0, v4, s15
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, v3, v0
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
global_store_b32 v[1:2], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel0, .Lfunc_end0-kernel0
.section .AMDGPU.csdata,"",@progbits
.text
.protected kernel1
.globl kernel1
.p2align 8
.type kernel1,@function
kernel1:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s0
global_load_b32 v3, v[1:2], off
v_add3_u32 v0, v0, v4, s15
.LBB1_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, v3, v0
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB1_2
global_store_b32 v[1:2], v3, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size kernel1, .Lfunc_end1-kernel1
.section .AMDGPU.csdata,"",@progbits
.text
.protected kernel2
.globl kernel2
.p2align 8
.type kernel2,@function
kernel2:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s0
global_load_b32 v3, v[1:2], off
v_add3_u32 v0, v0, v4, s15
.LBB2_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, v3, v0
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB2_2
global_store_b32 v[1:2], v3, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size kernel2, .Lfunc_end2-kernel2
.section .AMDGPU.csdata,"",@progbits
.text
.protected kernel3
.globl kernel3
.p2align 8
.type kernel3,@function
kernel3:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB3_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s0
global_load_b32 v3, v[1:2], off
v_add3_u32 v0, v0, v4, s15
.LBB3_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, v3, v0
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB3_2
global_store_b32 v[1:2], v3, off
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size kernel3, .Lfunc_end3-kernel3
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel0.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel1
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel1.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel2
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel3
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel3.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel2(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel3(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
} | .text
.file "kernel.hip"
.globl __device_stub__kernel0 # -- Begin function __device_stub__kernel0
.p2align 4, 0x90
.type __device_stub__kernel0,@function
__device_stub__kernel0: # @__device_stub__kernel0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel0, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel0, .Lfunc_end0-__device_stub__kernel0
.cfi_endproc
# -- End function
.globl __device_stub__kernel1 # -- Begin function __device_stub__kernel1
.p2align 4, 0x90
.type __device_stub__kernel1,@function
__device_stub__kernel1: # @__device_stub__kernel1
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel1, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__kernel1, .Lfunc_end1-__device_stub__kernel1
.cfi_endproc
# -- End function
.globl __device_stub__kernel2 # -- Begin function __device_stub__kernel2
.p2align 4, 0x90
.type __device_stub__kernel2,@function
__device_stub__kernel2: # @__device_stub__kernel2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel2, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__kernel2, .Lfunc_end2-__device_stub__kernel2
.cfi_endproc
# -- End function
.globl __device_stub__kernel3 # -- Begin function __device_stub__kernel3
.p2align 4, 0x90
.type __device_stub__kernel3,@function
__device_stub__kernel3: # @__device_stub__kernel3
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__kernel3, .Lfunc_end3-__device_stub__kernel3
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel0, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel3, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel0,@object # @kernel0
.section .rodata,"a",@progbits
.globl kernel0
.p2align 3, 0x0
kernel0:
.quad __device_stub__kernel0
.size kernel0, 8
.type kernel1,@object # @kernel1
.globl kernel1
.p2align 3, 0x0
kernel1:
.quad __device_stub__kernel1
.size kernel1, 8
.type kernel2,@object # @kernel2
.globl kernel2
.p2align 3, 0x0
kernel2:
.quad __device_stub__kernel2
.size kernel2, 8
.type kernel3,@object # @kernel3
.globl kernel3
.p2align 3, 0x0
kernel3:
.quad __device_stub__kernel3
.size kernel3, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel0"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel1"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "kernel2"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "kernel3"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel0
.addrsig_sym __device_stub__kernel1
.addrsig_sym __device_stub__kernel2
.addrsig_sym __device_stub__kernel3
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel0
.addrsig_sym kernel1
.addrsig_sym kernel2
.addrsig_sym kernel3
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185501_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7kernel0PiiPii
.type _Z27__device_stub__Z7kernel0PiiPii, @function
_Z27__device_stub__Z7kernel0PiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7kernel0PiiPii, .-_Z27__device_stub__Z7kernel0PiiPii
.globl kernel0
.type kernel0, @function
kernel0:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel0PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel0, .-kernel0
.globl _Z27__device_stub__Z7kernel1PiiPii
.type _Z27__device_stub__Z7kernel1PiiPii, @function
_Z27__device_stub__Z7kernel1PiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z7kernel1PiiPii, .-_Z27__device_stub__Z7kernel1PiiPii
.globl kernel1
.type kernel1, @function
kernel1:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel1PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size kernel1, .-kernel1
.globl _Z27__device_stub__Z7kernel2PiiPii
.type _Z27__device_stub__Z7kernel2PiiPii, @function
_Z27__device_stub__Z7kernel2PiiPii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z27__device_stub__Z7kernel2PiiPii, .-_Z27__device_stub__Z7kernel2PiiPii
.globl kernel2
.type kernel2, @function
kernel2:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel2PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size kernel2, .-kernel2
.globl _Z27__device_stub__Z7kernel3PiiPii
.type _Z27__device_stub__Z7kernel3PiiPii, @function
_Z27__device_stub__Z7kernel3PiiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z27__device_stub__Z7kernel3PiiPii, .-_Z27__device_stub__Z7kernel3PiiPii
.globl kernel3
.type kernel3, @function
kernel3:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel3PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size kernel3, .-kernel3
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel3"
.LC1:
.string "kernel2"
.LC2:
.string "kernel1"
.LC3:
.string "kernel0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kernel2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq kernel1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq kernel0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__kernel0 # -- Begin function __device_stub__kernel0
.p2align 4, 0x90
.type __device_stub__kernel0,@function
__device_stub__kernel0: # @__device_stub__kernel0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel0, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel0, .Lfunc_end0-__device_stub__kernel0
.cfi_endproc
# -- End function
.globl __device_stub__kernel1 # -- Begin function __device_stub__kernel1
.p2align 4, 0x90
.type __device_stub__kernel1,@function
__device_stub__kernel1: # @__device_stub__kernel1
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel1, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__kernel1, .Lfunc_end1-__device_stub__kernel1
.cfi_endproc
# -- End function
.globl __device_stub__kernel2 # -- Begin function __device_stub__kernel2
.p2align 4, 0x90
.type __device_stub__kernel2,@function
__device_stub__kernel2: # @__device_stub__kernel2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel2, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__kernel2, .Lfunc_end2-__device_stub__kernel2
.cfi_endproc
# -- End function
.globl __device_stub__kernel3 # -- Begin function __device_stub__kernel3
.p2align 4, 0x90
.type __device_stub__kernel3,@function
__device_stub__kernel3: # @__device_stub__kernel3
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__kernel3, .Lfunc_end3-__device_stub__kernel3
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel0, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel3, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel0,@object # @kernel0
.section .rodata,"a",@progbits
.globl kernel0
.p2align 3, 0x0
kernel0:
.quad __device_stub__kernel0
.size kernel0, 8
.type kernel1,@object # @kernel1
.globl kernel1
.p2align 3, 0x0
kernel1:
.quad __device_stub__kernel1
.size kernel1, 8
.type kernel2,@object # @kernel2
.globl kernel2
.p2align 3, 0x0
kernel2:
.quad __device_stub__kernel2
.size kernel2, 8
.type kernel3,@object # @kernel3
.globl kernel3
.p2align 3, 0x0
kernel3:
.quad __device_stub__kernel3
.size kernel3, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel0"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel1"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "kernel2"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "kernel3"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel0
.addrsig_sym __device_stub__kernel1
.addrsig_sym __device_stub__kernel2
.addrsig_sym __device_stub__kernel3
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel0
.addrsig_sym kernel1
.addrsig_sym kernel2
.addrsig_sym kernel3
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} | .file "tmpxft_00013531_00000000-6_atomVel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Average velocity"
.LC14:
.string "width"
.LC15:
.string "Atom Index "
.LC16:
.string "Atom Velocity "
.LC17:
.string " "
.LC18:
.string "Average: "
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -7999488(%rsp), %r11
.cfi_def_cfa 11, 7999544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $584, %rsp
.cfi_def_cfa_offset 8000128
movq %fs:40, %rax
movq %rax, 8000056(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd .LC3(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
movsd .LC0(%rip), %xmm7
movsd %xmm7, (%rsp)
movl $0, %ebx
jmp .L22
.L53:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L8:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L54:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L12:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L55:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L56:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
.L4:
addl $1, %ebx
cmpl $1000000, %ebx
je .L52
.L22:
pxor %xmm0, %xmm0
movsd (%rsp), %xmm2
movapd %xmm2, %xmm4
comisd %xmm0, %xmm2
jb .L4
mulsd %xmm2, %xmm4
movapd %xmm4, %xmm0
movsd %xmm4, 8(%rsp)
mulsd .LC4(%rip), %xmm0
xorpd .LC5(%rip), %xmm0
divsd .LC6(%rip), %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
mulsd .LC7(%rip), %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
call rand@PLT
call rand@PLT
call rand@PLT
call rand@PLT
leaq 40(%rsp), %r14
leaq 32(%rsp), %r15
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r15
movq 40(%rsp), %r14
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC13(%rip), %xmm1
movsd 8(%rsp), %xmm5
divsd %xmm5, %xmm1
divsd %xmm1, %xmm0
movsd (%rsp), %xmm2
movapd %xmm2, %xmm3
subsd %xmm0, %xmm3
movsd %xmm3, 16(%rsp)
movslq %r13d, %rax
movsd %xmm3, 48(%rsp,%rax,8)
movq %rbp, %xmm0
mulsd %xmm3, %xmm0
movq %r15, %xmm6
mulsd %xmm0, %xmm6
movq %xmm6, %r15
movq %r14, %xmm7
mulsd %xmm0, %xmm7
movsd %xmm7, 24(%rsp)
movq %r12, %xmm6
mulsd %xmm3, %xmm6
movq %xmm6, %r12
subsd %xmm5, %xmm2
movsd %xmm2, (%rsp)
movl $5, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L53
cmpb $0, 56(%r14)
je .L8
movzbl 67(%r14), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L54
cmpb $0, 56(%r14)
je .L12
movzbl 67(%r14), %esi
.L13:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L55
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r15, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC17(%rip), %r14
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 24(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L56
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
jmp .L21
.L52:
cmpl $999999, %r13d
jg .L23
movslq %r13d, %rax
leaq 48(%rsp,%rax,8), %r12
movsd .LC0(%rip), %xmm7
movsd %xmm7, (%rsp)
jmp .L40
.L61:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L26:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L62:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L63:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L34:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L64:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L38:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L39:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
addq $8, %r12
cmpl $1000000, %r13d
je .L23
.L40:
movsd (%rsp), %xmm7
movapd %xmm7, %xmm6
mulsd %xmm7, %xmm6
movsd .LC4(%rip), %xmm0
movsd %xmm6, 8(%rsp)
mulsd %xmm6, %xmm0
xorpd .LC5(%rip), %xmm0
divsd .LC6(%rip), %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd .LC7(%rip), %xmm0
mulsd 8(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
call rand@PLT
call rand@PLT
call rand@PLT
call rand@PLT
leaq 40(%rsp), %r14
leaq 32(%rsp), %r15
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %rbp
movq 40(%rsp), %rbx
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r15
movq 40(%rsp), %r14
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC13(%rip), %xmm1
movsd 8(%rsp), %xmm5
divsd %xmm5, %xmm1
divsd %xmm1, %xmm0
movsd (%rsp), %xmm7
addsd %xmm7, %xmm0
movapd %xmm0, %xmm6
movsd %xmm0, 16(%rsp)
movsd %xmm0, (%r12)
movq %rbx, %xmm0
mulsd %xmm6, %xmm0
movq %r15, %xmm2
mulsd %xmm0, %xmm2
movq %xmm2, %r15
movq %r14, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, 24(%rsp)
movq %rbp, %xmm2
mulsd %xmm6, %xmm2
movq %xmm2, %rbp
addsd %xmm5, %xmm7
movsd %xmm7, (%rsp)
movl $5, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L61
cmpb $0, 56(%r14)
je .L26
movzbl 67(%r14), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L62
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L63
cmpb $0, 56(%r14)
je .L34
movzbl 67(%r14), %esi
.L35:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r15, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC17(%rip), %r14
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 24(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L64
cmpb $0, 56(%rbp)
je .L38
movzbl 67(%rbp), %esi
jmp .L39
.L23:
leaq 48(%rsp), %rax
movslq %r13d, %rdx
leaq (%rax,%rdx,8), %rdx
pxor %xmm0, %xmm0
.L41:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L41
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
movq %xmm0, %rbx
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $8000072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4189:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 137259829
.long 1083270925
.align 8
.LC3:
.long 519614879
.long 1083417341
.align 8
.LC4:
.long 1292013295
.long 981494910
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long 1983905792
.long 1002663404
.align 8
.LC7:
.long -266631570
.long 1076437497
.align 8
.LC8:
.long -732719678
.long 1038212476
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC11:
.long 1839270434
.long 1103388464
.align 8
.LC12:
.long 1839270434
.long 1102339888
.align 8
.LC13:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <hip/hip_runtime.h>
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <hip/hip_runtime.h>
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
#include <hip/hip_runtime.h>
#include <cmath>
#include <math.h>
#include <iostream>
#include <stdlib.h>
#include <cstdlib> // needed for rand
#include <ctime>//neded for srand(time(0))
#include <fstream> //needed for files
#include <vector>
#include <cfloat>
#include <string>
#define N 1000000
using namespace std;
int main() {
double mass = 6.63352088E-27; //mass in kg for one atom (ARGON)
float k = 1.3806488E-23; //m^2 kg s^-2 K^-1
double temp = 298; //kelvin
double pi = 3.14159;
double avgVelocity = 0;
double velocity[N],velX[N],velY[N],velZ[N],x[N],y[N],z[N],theta[N],phi[N];
int atomIndexL = 0;
double velIndex = 0;
double width = 0;
double mostProbVel = 0;
int atomIndex=0;
//Set range for possible values (0-2*average or +-3 standard deviations)
avgVelocity = (sqrt(2*k*temp/mass))*(2/(sqrt(pi)));
cout<<"Average velocity" << avgVelocity<< endl;
mostProbVel = sqrt (2*k*temp/mass);
velIndex = mostProbVel;
//most probable velocity is different than average velocity because the distribution is skewed.
//We want to start at the "top of the hill" so we always overestimate the boxes and don't
//run into rounding errors
/*for(atomIndex = 0; atomIndex <N; atomIndex++){
if(atomIndex == 0){
width = pow(3, 1/3)/(pow((mass/(2*pi*k*temp)),1/2)*pow(N, 1/3)*pow(4*pi, 1/3));
}*/
//creates atoms left of the hill until the velocity is equal to zero
for (atomIndexL=0; atomIndexL < N; atomIndexL++ ){
if (velIndex >= 0.0000){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex - static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex-width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndexL << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
atomIndex++;
}
}
velIndex = mostProbVel;
//creates remaining atoms to the right of the most probable velocity
for (; atomIndex<N; atomIndex++){
width = 1/((sqrt((mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))*(mass/(2*pi*k*temp))))*(4*pi*(velIndex*velIndex))*(exp(-(mass*(velIndex*velIndex))/(2*k*temp)))*N);
x[atomIndex]= static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
y[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
z[atomIndex] = static_cast <double> (rand()) / static_cast <double> (RAND_MAX/500);
theta[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(M_PI));
phi[atomIndex] = static_cast<double>(rand()) / static_cast<double>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
velocity[atomIndex]=velIndex + static_cast <double> (rand()) / static_cast <double> (RAND_MAX/width);
velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
velIndex=velIndex+width;
//Update index
cout << "width" << width << endl;
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
}
//for (; atomIndex <N; atomIndex++){
//x[atomIndex]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// y[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// z[atomIndex] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
// theta[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
// phi[atomIndex] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
//Randomize Velocity within intvel, convert to cartesian coordinates
// velocity[atomIndex]=velIndex;
// velX[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*cos(phi[atomIndex]);
// velY[atomIndex]=velocity[atomIndex]*sin(theta[atomIndex])*sin(phi[atomIndex]);
// velZ[atomIndex]=velocity[atomIndex]*cos(theta[atomIndex]);
// velIndex=velIndex+width;
//Update index
// cout << "width" << width << endl;
//cout <<"Atom Index " << atomIndex << endl;
// cout << "Atom Velocity " << velocity[atomIndex] << endl;
// cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
/* velocity[N-1]=velIndex;
x[N-1]= static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
y[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
z[N-1] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX/500);
theta[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(M_PI));
phi[N-1] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX/(2*M_PI));
velX[N-1]=velocity[N-1]*sin(theta[N-1])*cos(phi[N-1]);
velY[N-1]=velocity[N-1]*sin(theta[N-1])*sin(phi[N-1]);
velZ[N-1]=velocity[N-1]*cos(theta[N-1]);
cout <<"Atom Index " << atomIndex << endl;
cout << "Atom Velocity " << velocity[atomIndex] << endl;
cout<< velX[atomIndex] << " " << velY[atomIndex] << " " << velZ[atomIndex] << endl;
*/
double avgCheck = 0;
//check out average
for(int j=0; j<atomIndex; j++){
avgCheck = avgCheck + velocity [j];
}
avgCheck = avgCheck / atomIndex;
cout << "Average: " << avgCheck << endl;
return 0;
} | .text
.file "atomVel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4093a2fd1ef8b19f # double 1256.7471884592449
.LCPI0_1:
.quad 0x4091670d082e6b35 # double 1113.7627265217718
.LCPI0_2:
.quad 0x402921f9f01b866e # double 12.56636
.LCPI0_3:
.quad 0x3de1dd7cd45395c2 # double 1.2998633607268559E-10
.LCPI0_4:
.quad 0xba806c7e4d028eef # double -6.6335208800000003E-27
.LCPI0_5:
.quad 0x3bc36dec76400000 # double 8.2286664717564733E-21
.LCPI0_6:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_7:
.quad 0x3ff0000000000000 # double 1
.LCPI0_8:
.quad 0x41c45f306da10a22 # double 683565275.25812173
.LCPI0_9:
.quad 0x41b45f306da10a22 # double 341782637.62906086
.LCPI0_10:
.quad 0xc1dfffffffc00000 # double -2147483647
.LCPI0_11:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $8000072, %rsp # imm = 0x7A1248
.cfi_def_cfa_offset 8000112
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_51
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %ebp, %ebp
xorpd %xmm1, %xmm1
xorl %ebx, %ebx
jmp .LBB0_5
.LBB0_26: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl %eax, %ecx
movq %r15, %rax
.LBB0_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit142
# in Loop: Header=BB0_5 Depth=1
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incl %ebp
xorpd %xmm1, %xmm1
.LBB0_28: # in Loop: Header=BB0_5 Depth=1
incl %ebx
cmpl $1000000, %ebx # imm = 0xF4240
je .LBB0_9
.LBB0_5: # =>This Inner Loop Header: Depth=1
ucomisd %xmm1, %xmm0
jb .LBB0_28
# %bb.6: # in Loop: Header=BB0_5 Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
mulsd .LCPI0_4(%rip), %xmm0
divsd .LCPI0_5(%rip), %xmm0
callq exp
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI0_6(%rip), %xmm0
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq rand
movslq %ebp, %r14
callq rand
callq rand
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_8(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_9(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_10(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
divsd %xmm0, %xmm1
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm1, 64(%rsp,%r14,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_14
# %bb.8: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_15
.LBB0_14: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
# in Loop: Header=BB0_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_18
# %bb.17: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_19
.LBB0_18: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
# in Loop: Header=BB0_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i134
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_23
.LBB0_22: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit137
# in Loop: Header=BB0_5 Depth=1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
mulsd 16(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i139
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
je .LBB0_26
# %bb.25: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_27
.LBB0_9: # %.preheader168
cmpl $999999, %ebp # imm = 0xF423F
jg .LBB0_44
# %bb.10: # %.lr.ph.preheader
movslq %ebp, %rbx
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_41: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl %eax, %ecx
movq %r15, %rax
.LBB0_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit162
# in Loop: Header=BB0_11 Depth=1
addsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
je .LBB0_43
.LBB0_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
mulsd .LCPI0_4(%rip), %xmm0
divsd .LCPI0_5(%rip), %xmm0
callq exp
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI0_6(%rip), %xmm0
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq rand
callq rand
callq rand
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_8(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_9(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_11(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
divsd %xmm0, %xmm1
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm1, 64(%rsp,%rbx,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i144
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_29
# %bb.13: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit147
# in Loop: Header=BB0_11 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_33
# %bb.32: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit152
# in Loop: Header=BB0_11 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i154
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_37: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit157
# in Loop: Header=BB0_11 Depth=1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
mulsd 16(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i159
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
je .LBB0_41
# %bb.40: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_42
.LBB0_43:
movl $1000000, %ebp # imm = 0xF4240
.LBB0_44: # %.lr.ph184.preheader
movl %ebp, %eax
xorpd %xmm1, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_45: # %.lr.ph184
# =>This Inner Loop Header: Depth=1
addsd 64(%rsp,%rcx,8), %xmm1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_45
# %bb.46: # %._crit_edge
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_51
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i164
cmpb $0, 56(%rbx)
je .LBB0_49
# %bb.48:
movzbl 67(%rbx), %ecx
jmp .LBB0_50
.LBB0_49:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit167
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8000072, %rsp # imm = 0x7A1248
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_51:
.cfi_def_cfa_offset 8000112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Average velocity"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "width"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Atom Index "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Atom Velocity "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Average: "
.size .L.str.5, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00013531_00000000-6_atomVel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Average velocity"
.LC14:
.string "width"
.LC15:
.string "Atom Index "
.LC16:
.string "Atom Velocity "
.LC17:
.string " "
.LC18:
.string "Average: "
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -7999488(%rsp), %r11
.cfi_def_cfa 11, 7999544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $584, %rsp
.cfi_def_cfa_offset 8000128
movq %fs:40, %rax
movq %rax, 8000056(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd .LC3(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
movsd .LC0(%rip), %xmm7
movsd %xmm7, (%rsp)
movl $0, %ebx
jmp .L22
.L53:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L8:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L54:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L12:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L55:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L56:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
.L4:
addl $1, %ebx
cmpl $1000000, %ebx
je .L52
.L22:
pxor %xmm0, %xmm0
movsd (%rsp), %xmm2
movapd %xmm2, %xmm4
comisd %xmm0, %xmm2
jb .L4
mulsd %xmm2, %xmm4
movapd %xmm4, %xmm0
movsd %xmm4, 8(%rsp)
mulsd .LC4(%rip), %xmm0
xorpd .LC5(%rip), %xmm0
divsd .LC6(%rip), %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
mulsd .LC7(%rip), %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
call rand@PLT
call rand@PLT
call rand@PLT
call rand@PLT
leaq 40(%rsp), %r14
leaq 32(%rsp), %r15
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r15
movq 40(%rsp), %r14
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC13(%rip), %xmm1
movsd 8(%rsp), %xmm5
divsd %xmm5, %xmm1
divsd %xmm1, %xmm0
movsd (%rsp), %xmm2
movapd %xmm2, %xmm3
subsd %xmm0, %xmm3
movsd %xmm3, 16(%rsp)
movslq %r13d, %rax
movsd %xmm3, 48(%rsp,%rax,8)
movq %rbp, %xmm0
mulsd %xmm3, %xmm0
movq %r15, %xmm6
mulsd %xmm0, %xmm6
movq %xmm6, %r15
movq %r14, %xmm7
mulsd %xmm0, %xmm7
movsd %xmm7, 24(%rsp)
movq %r12, %xmm6
mulsd %xmm3, %xmm6
movq %xmm6, %r12
subsd %xmm5, %xmm2
movsd %xmm2, (%rsp)
movl $5, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L53
cmpb $0, 56(%r14)
je .L8
movzbl 67(%r14), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L54
cmpb $0, 56(%r14)
je .L12
movzbl 67(%r14), %esi
.L13:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L55
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r15, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC17(%rip), %r14
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 24(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L56
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
jmp .L21
.L52:
cmpl $999999, %r13d
jg .L23
movslq %r13d, %rax
leaq 48(%rsp,%rax,8), %r12
movsd .LC0(%rip), %xmm7
movsd %xmm7, (%rsp)
jmp .L40
.L61:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L26:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L62:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L63:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L34:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L64:
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L38:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L39:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
addq $8, %r12
cmpl $1000000, %r13d
je .L23
.L40:
movsd (%rsp), %xmm7
movapd %xmm7, %xmm6
mulsd %xmm7, %xmm6
movsd .LC4(%rip), %xmm0
movsd %xmm6, 8(%rsp)
mulsd %xmm6, %xmm0
xorpd .LC5(%rip), %xmm0
divsd .LC6(%rip), %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd .LC7(%rip), %xmm0
mulsd 8(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
call rand@PLT
call rand@PLT
call rand@PLT
call rand@PLT
leaq 40(%rsp), %r14
leaq 32(%rsp), %r15
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %rbp
movq 40(%rsp), %rbx
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r15, %rsi
movq %r14, %rdi
call sincos@PLT
movq 32(%rsp), %r15
movq 40(%rsp), %r14
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC13(%rip), %xmm1
movsd 8(%rsp), %xmm5
divsd %xmm5, %xmm1
divsd %xmm1, %xmm0
movsd (%rsp), %xmm7
addsd %xmm7, %xmm0
movapd %xmm0, %xmm6
movsd %xmm0, 16(%rsp)
movsd %xmm0, (%r12)
movq %rbx, %xmm0
mulsd %xmm6, %xmm0
movq %r15, %xmm2
mulsd %xmm0, %xmm2
movq %xmm2, %r15
movq %r14, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, 24(%rsp)
movq %rbp, %xmm2
mulsd %xmm6, %xmm2
movq %xmm2, %rbp
addsd %xmm5, %xmm7
movsd %xmm7, (%rsp)
movl $5, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L61
cmpb $0, 56(%r14)
je .L26
movzbl 67(%r14), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L62
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L63
cmpb $0, 56(%r14)
je .L34
movzbl 67(%r14), %esi
.L35:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r15, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC17(%rip), %r14
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 24(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L64
cmpb $0, 56(%rbp)
je .L38
movzbl 67(%rbp), %esi
jmp .L39
.L23:
leaq 48(%rsp), %rax
movslq %r13d, %rdx
leaq (%rax,%rdx,8), %rdx
pxor %xmm0, %xmm0
.L41:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L41
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
movq %xmm0, %rbx
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8000056(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $8000072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4189:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 137259829
.long 1083270925
.align 8
.LC3:
.long 519614879
.long 1083417341
.align 8
.LC4:
.long 1292013295
.long 981494910
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long 1983905792
.long 1002663404
.align 8
.LC7:
.long -266631570
.long 1076437497
.align 8
.LC8:
.long -732719678
.long 1038212476
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC11:
.long 1839270434
.long 1103388464
.align 8
.LC12:
.long 1839270434
.long 1102339888
.align 8
.LC13:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomVel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4093a2fd1ef8b19f # double 1256.7471884592449
.LCPI0_1:
.quad 0x4091670d082e6b35 # double 1113.7627265217718
.LCPI0_2:
.quad 0x402921f9f01b866e # double 12.56636
.LCPI0_3:
.quad 0x3de1dd7cd45395c2 # double 1.2998633607268559E-10
.LCPI0_4:
.quad 0xba806c7e4d028eef # double -6.6335208800000003E-27
.LCPI0_5:
.quad 0x3bc36dec76400000 # double 8.2286664717564733E-21
.LCPI0_6:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_7:
.quad 0x3ff0000000000000 # double 1
.LCPI0_8:
.quad 0x41c45f306da10a22 # double 683565275.25812173
.LCPI0_9:
.quad 0x41b45f306da10a22 # double 341782637.62906086
.LCPI0_10:
.quad 0xc1dfffffffc00000 # double -2147483647
.LCPI0_11:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $8000072, %rsp # imm = 0x7A1248
.cfi_def_cfa_offset 8000112
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_51
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %ebp, %ebp
xorpd %xmm1, %xmm1
xorl %ebx, %ebx
jmp .LBB0_5
.LBB0_26: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl %eax, %ecx
movq %r15, %rax
.LBB0_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit142
# in Loop: Header=BB0_5 Depth=1
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incl %ebp
xorpd %xmm1, %xmm1
.LBB0_28: # in Loop: Header=BB0_5 Depth=1
incl %ebx
cmpl $1000000, %ebx # imm = 0xF4240
je .LBB0_9
.LBB0_5: # =>This Inner Loop Header: Depth=1
ucomisd %xmm1, %xmm0
jb .LBB0_28
# %bb.6: # in Loop: Header=BB0_5 Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
mulsd .LCPI0_4(%rip), %xmm0
divsd .LCPI0_5(%rip), %xmm0
callq exp
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI0_6(%rip), %xmm0
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq rand
movslq %ebp, %r14
callq rand
callq rand
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_8(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_9(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_10(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
divsd %xmm0, %xmm1
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm1, 64(%rsp,%r14,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_14
# %bb.8: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_15
.LBB0_14: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
# in Loop: Header=BB0_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_18
# %bb.17: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_19
.LBB0_18: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
# in Loop: Header=BB0_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i134
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_23
.LBB0_22: # in Loop: Header=BB0_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit137
# in Loop: Header=BB0_5 Depth=1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
mulsd 16(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i139
# in Loop: Header=BB0_5 Depth=1
cmpb $0, 56(%r14)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
je .LBB0_26
# %bb.25: # in Loop: Header=BB0_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_27
.LBB0_9: # %.preheader168
cmpl $999999, %ebp # imm = 0xF423F
jg .LBB0_44
# %bb.10: # %.lr.ph.preheader
movslq %ebp, %rbx
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_41: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl %eax, %ecx
movq %r15, %rax
.LBB0_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit162
# in Loop: Header=BB0_11 Depth=1
addsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
je .LBB0_43
.LBB0_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
mulsd .LCPI0_4(%rip), %xmm0
divsd .LCPI0_5(%rip), %xmm0
callq exp
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI0_6(%rip), %xmm0
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq rand
callq rand
callq rand
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_8(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_9(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_11(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
divsd %xmm0, %xmm1
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm1, 64(%rsp,%rbx,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i144
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_29
# %bb.13: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit147
# in Loop: Header=BB0_11 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_33
# %bb.32: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit152
# in Loop: Header=BB0_11 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i154
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_37: # in Loop: Header=BB0_11 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit157
# in Loop: Header=BB0_11 Depth=1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
mulsd 16(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_51
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i159
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r14)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
je .LBB0_41
# %bb.40: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_42
.LBB0_43:
movl $1000000, %ebp # imm = 0xF4240
.LBB0_44: # %.lr.ph184.preheader
movl %ebp, %eax
xorpd %xmm1, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_45: # %.lr.ph184
# =>This Inner Loop Header: Depth=1
addsd 64(%rsp,%rcx,8), %xmm1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_45
# %bb.46: # %._crit_edge
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_51
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i164
cmpb $0, 56(%rbx)
je .LBB0_49
# %bb.48:
movzbl 67(%rbx), %ecx
jmp .LBB0_50
.LBB0_49:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit167
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8000072, %rsp # imm = 0x7A1248
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_51:
.cfi_def_cfa_offset 8000112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Average velocity"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "width"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Atom Index "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Atom Velocity "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Average: "
.size .L.str.5, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | code for sm_80
Function : _Z14count_zero_onePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 BRA 0x130 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00c0*/ FSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fda0003f0d000 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005027a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fc800000001ff */
/*0100*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0110*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e784 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0160*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e784 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .file "tmpxft_00192b9b_00000000-6_count_zero_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14count_zero_onePfS_iPfS_i
.type _Z37__device_stub__Z14count_zero_onePfS_iPfS_i, @function
_Z37__device_stub__Z14count_zero_onePfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14count_zero_onePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14count_zero_onePfS_iPfS_i, .-_Z37__device_stub__Z14count_zero_onePfS_iPfS_i
.globl _Z14count_zero_onePfS_i
.type _Z14count_zero_onePfS_i, @function
_Z14count_zero_onePfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14count_zero_onePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14count_zero_onePfS_i, .-_Z14count_zero_onePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14count_zero_onePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14count_zero_onePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14count_zero_onePfS_i
.globl _Z14count_zero_onePfS_i
.p2align 8
.type _Z14count_zero_onePfS_i,@function
_Z14count_zero_onePfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, -1
global_load_b32 v2, v[0:1], off
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v2
s_cbranch_execz .LBB0_5
s_mov_b32 s6, exec_lo
v_cmpx_eq_f32_e32 1.0, v2
s_add_u32 s0, s2, 4
s_mov_b32 s5, exec_lo
s_addc_u32 s1, s3, 0
s_or_b32 exec_lo, exec_lo, s6
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
s_or_not1_b32 s0, s5, exec_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
global_load_b32 v3, v[0:1], off
s_mov_b32 s0, 0
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14count_zero_onePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14count_zero_onePfS_i, .Lfunc_end0-_Z14count_zero_onePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14count_zero_onePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14count_zero_onePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .text
.file "count_zero_one.hip"
.globl _Z29__device_stub__count_zero_onePfS_i # -- Begin function _Z29__device_stub__count_zero_onePfS_i
.p2align 4, 0x90
.type _Z29__device_stub__count_zero_onePfS_i,@function
_Z29__device_stub__count_zero_onePfS_i: # @_Z29__device_stub__count_zero_onePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14count_zero_onePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__count_zero_onePfS_i, .Lfunc_end0-_Z29__device_stub__count_zero_onePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14count_zero_onePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14count_zero_onePfS_i,@object # @_Z14count_zero_onePfS_i
.section .rodata,"a",@progbits
.globl _Z14count_zero_onePfS_i
.p2align 3, 0x0
_Z14count_zero_onePfS_i:
.quad _Z29__device_stub__count_zero_onePfS_i
.size _Z14count_zero_onePfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14count_zero_onePfS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__count_zero_onePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14count_zero_onePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14count_zero_onePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 BRA 0x130 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00c0*/ FSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fda0003f0d000 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005027a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fc800000001ff */
/*0100*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0110*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e784 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0160*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e784 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14count_zero_onePfS_i
.globl _Z14count_zero_onePfS_i
.p2align 8
.type _Z14count_zero_onePfS_i,@function
_Z14count_zero_onePfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, -1
global_load_b32 v2, v[0:1], off
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v2
s_cbranch_execz .LBB0_5
s_mov_b32 s6, exec_lo
v_cmpx_eq_f32_e32 1.0, v2
s_add_u32 s0, s2, 4
s_mov_b32 s5, exec_lo
s_addc_u32 s1, s3, 0
s_or_b32 exec_lo, exec_lo, s6
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
s_or_not1_b32 s0, s5, exec_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
global_load_b32 v3, v[0:1], off
s_mov_b32 s0, 0
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14count_zero_onePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14count_zero_onePfS_i, .Lfunc_end0-_Z14count_zero_onePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14count_zero_onePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14count_zero_onePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192b9b_00000000-6_count_zero_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14count_zero_onePfS_iPfS_i
.type _Z37__device_stub__Z14count_zero_onePfS_iPfS_i, @function
_Z37__device_stub__Z14count_zero_onePfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14count_zero_onePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14count_zero_onePfS_iPfS_i, .-_Z37__device_stub__Z14count_zero_onePfS_iPfS_i
.globl _Z14count_zero_onePfS_i
.type _Z14count_zero_onePfS_i, @function
_Z14count_zero_onePfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14count_zero_onePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14count_zero_onePfS_i, .-_Z14count_zero_onePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14count_zero_onePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14count_zero_onePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "count_zero_one.hip"
.globl _Z29__device_stub__count_zero_onePfS_i # -- Begin function _Z29__device_stub__count_zero_onePfS_i
.p2align 4, 0x90
.type _Z29__device_stub__count_zero_onePfS_i,@function
_Z29__device_stub__count_zero_onePfS_i: # @_Z29__device_stub__count_zero_onePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14count_zero_onePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__count_zero_onePfS_i, .Lfunc_end0-_Z29__device_stub__count_zero_onePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14count_zero_onePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14count_zero_onePfS_i,@object # @_Z14count_zero_onePfS_i
.section .rodata,"a",@progbits
.globl _Z14count_zero_onePfS_i
.p2align 3, 0x0
_Z14count_zero_onePfS_i:
.quad _Z29__device_stub__count_zero_onePfS_i
.size _Z14count_zero_onePfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14count_zero_onePfS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__count_zero_onePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14count_zero_onePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
cufftReal *hostInputData = (cufftReal*)malloc(N*BATCH*sizeof(cufftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
cufftReal *deviceInputData;
gpuErrchk(cudaMalloc((void**)&deviceInputData, N * BATCH * sizeof(cufftReal)));
cudaMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(cufftReal), cudaMemcpyHostToDevice);
// --- Host side output data allocation
cufftComplex *hostOutputData = (cufftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex));
// --- Device side output data allocation
cufftComplex *deviceOutputData; gpuErrchk(cudaMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex)));
// --- Batched 1D FFTs
cufftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
cufftPlan1d(&handle, FFTSIZE, CUFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
cufftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, CUFFT_R2C, batch);
}
cufftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(cudaMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex), cudaMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
cufftDestroy(handle);
gpuErrchk(cudaFree(deviceOutputData));
gpuErrchk(cudaFree(deviceInputData));
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
cufftReal *hostInputData = (cufftReal*)malloc(N*BATCH*sizeof(cufftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
cufftReal *deviceInputData;
gpuErrchk(cudaMalloc((void**)&deviceInputData, N * BATCH * sizeof(cufftReal)));
cudaMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(cufftReal), cudaMemcpyHostToDevice);
// --- Host side output data allocation
cufftComplex *hostOutputData = (cufftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex));
// --- Device side output data allocation
cufftComplex *deviceOutputData; gpuErrchk(cudaMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex)));
// --- Batched 1D FFTs
cufftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
cufftPlan1d(&handle, FFTSIZE, CUFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
cufftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, CUFFT_R2C, batch);
}
cufftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(cudaMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex), cudaMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
cufftDestroy(handle);
gpuErrchk(cudaFree(deviceOutputData));
gpuErrchk(cudaFree(deviceInputData));
} | .file "tmpxft_000444c9_00000000-6_test1_planmany.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2080:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Please specify 1 (plan1d) or 2 (planmany).\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/leimingyu/cuda_fft/master/cufft/tests/test1_planmany.cu"
.section .rodata.str1.1
.LC5:
.string "cufftplan1d\n"
.LC6:
.string "cufftplan2d\n"
.LC7:
.string "%i %i %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L26
movq %rsi, %r13
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L14:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L15:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 40(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L15
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $51, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $58, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $8, 28(%rsp)
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1, %eax
je .L27
cmpl $2, %eax
je .L28
.L17:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecR2C@PLT
movl $2, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $89, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC7(%rip), %r12
.L18:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,8), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbp,%rbx,8), %xmm1
movl %ebx, %ecx
movl $0, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L18
movl $0, %ebx
leaq .LC7(%rip), %r12
.L19:
pxor %xmm0, %xmm0
cvtss2sd 40(%rbp,%rbx,8), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 44(%rbp,%rbx,8), %xmm1
movl %ebx, %ecx
movl $1, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L19
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $96, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $42, %edx
movl $8, %esi
call cufftPlan1d@PLT
jmp .L17
.L28:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 4(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $2
.cfi_def_cfa_offset 112
pushq $42
.cfi_def_cfa_offset 120
pushq $5
.cfi_def_cfa_offset 128
pushq $1
.cfi_def_cfa_offset 136
leaq 76(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 144
movl $8, %r9d
movl $1, %r8d
movl $1, %esi
call cufftPlanMany@PLT
addq $48, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
cufftReal *hostInputData = (cufftReal*)malloc(N*BATCH*sizeof(cufftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
cufftReal *deviceInputData;
gpuErrchk(cudaMalloc((void**)&deviceInputData, N * BATCH * sizeof(cufftReal)));
cudaMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(cufftReal), cudaMemcpyHostToDevice);
// --- Host side output data allocation
cufftComplex *hostOutputData = (cufftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex));
// --- Device side output data allocation
cufftComplex *deviceOutputData; gpuErrchk(cudaMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex)));
// --- Batched 1D FFTs
cufftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
cufftPlan1d(&handle, FFTSIZE, CUFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
cufftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, CUFFT_R2C, batch);
}
cufftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(cudaMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(cufftComplex), cudaMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
cufftDestroy(handle);
gpuErrchk(cudaFree(deviceOutputData));
gpuErrchk(cudaFree(deviceInputData));
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/********/
/* MAIN */
/********/
int main (int argc, char* argv[])
{
if(argc != 2) {
printf("Please specify 1 (plan1d) or 2 (planmany).\n");
return -1;
};
int N = FFTSIZE;
N = N + 2;
// --- Host side input data allocation and initialization
hipfftReal *hostInputData = (hipfftReal*)malloc(N*BATCH*sizeof(hipfftReal));
for (int i=0; i<BATCH; i++) {
for (int j=0; j<N; j++){
//hostInputData[i*FFTSIZE + j] = (cufftReal)(j + 1);
//hostInputData[i*FFTSIZE + j] = 100.f;
hostInputData[i*N+ j] = (float)(j % 10);
printf("%f ", hostInputData[i*N + j]);
}
printf("\n");
}
printf("\n");
// --- Device side input data allocation and initialization
hipfftReal *deviceInputData;
gpuErrchk(hipMalloc((void**)&deviceInputData, N * BATCH * sizeof(hipfftReal)));
hipMemcpy(deviceInputData, hostInputData, N * BATCH * sizeof(hipfftReal), hipMemcpyHostToDevice);
// --- Host side output data allocation
hipfftComplex *hostOutputData = (hipfftComplex*)malloc((FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex));
// --- Device side output data allocation
hipfftComplex *deviceOutputData; gpuErrchk(hipMalloc((void**)&deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex)));
// --- Batched 1D FFTs
hipfftHandle handle;
int rank = 1; // --- 1D FFTs
int n[] = { FFTSIZE }; // --- Size of the Fourier transform
int istride = 1, ostride = 1; // --- Distance between two successive input/output elements
int idist = FFTSIZE, odist = (FFTSIZE / 2 + 1); // --- Distance between batches
int inembed[] = { 0 }; // --- Input size with pitch (ignored for 1D transforms)
int onembed[] = { 0 }; // --- Output size with pitch (ignored for 1D transforms)
int batch = BATCH; // --- Number of batched executions
int plantype = atoi(argv[1]);
if(plantype == 1) {
printf("cufftplan1d\n");
hipfftPlan1d(&handle, FFTSIZE, HIPFFT_R2C, BATCH);
}
if(plantype == 2) {
printf("cufftplan2d\n");
hipfftPlanMany(&handle, rank, n,
inembed, istride, idist,
onembed, ostride, odist, HIPFFT_R2C, batch);
}
hipfftExecR2C(handle, deviceInputData, deviceOutputData);
// --- Device->Host copy of the results
gpuErrchk(hipMemcpy(hostOutputData, deviceOutputData, (FFTSIZE / 2 + 1) * BATCH * sizeof(hipfftComplex), hipMemcpyDeviceToHost));
for (int i=0; i<BATCH; i++)
for (int j=0; j<(FFTSIZE / 2 + 1); j++)
printf("%i %i %f %f\n", i, j, hostOutputData[i*(FFTSIZE / 2 + 1) + j].x, hostOutputData[i*(FFTSIZE / 2 + 1) + j].y);
hipfftDestroy(handle);
gpuErrchk(hipFree(deviceOutputData));
gpuErrchk(hipFree(deviceInputData));
} |
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