system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col... | .text
.file "exemplo3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ccca_00000000-6_exemplo3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... | .text
.file "exemplo3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the ri... | .file "tmpxft_000b1215_00000000-6__upfirdn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the ri... | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the ri... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the ri... | .text
.file "_upfirdn.hip"
.globl __device_stub___cupy_upfirdn1D_float32 # -- Begin function __device_stub___cupy_upfirdn1D_float32
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_float32,@function
__device_stub___cupy_upfirdn1D_float32: # @__device_stub___cupy_upfirdn1D_float32
.cfi_startproc
# %bb.0:
subq $168,... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include <device_fun... | .file "tmpxft_0010d211_00000000-6_cuda_FW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include <device_fun... | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((an... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((an... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22calculateSequencialGPUPi
.globl _Z22calculateSequencialGPUPi
.p2align 8
.type _Z22calculateSequencialGPUPi,@function
_Z22calculateSequencialGPUPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s14, 0
s_waitcnt lg... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include <sys/time.h>
//#include <Windows.h>
#ifndef __HIPCC__
#define __HIPCC__
#endif
#include <hip/device_functions.h>
#define gpuErrchk(ans) { gpuAssert((an... | .text
.file "cuda_FW.hip"
.globl _Z21generate_random_graphPi # -- Begin function _Z21generate_random_graphPi
.p2align 4, 0x90
.type _Z21generate_random_graphPi,@function
_Z21generate_random_graphPi: # @_Z21generate_random_graphPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_d... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010d211_00000000-6_cuda_FW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "cuda_FW.hip"
.globl _Z21generate_random_graphPi # -- Begin function _Z21generate_random_graphPi
.p2align 4, 0x90
.type _Z21generate_random_graphPi,@function
_Z21generate_random_graphPi: # @_Z21generate_random_graphPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_d... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype marg... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype marg... | .file "tmpxft_001054af_00000000-6_clusters_triplet_loss_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinar... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// const int dim, const Dtype marg... | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// co... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// co... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <algorithm>
//#include <vector>
//
//#include "caffe/layers/clusters_triplet_loss_layer.hpp"
//#include "caffe/util/math_functions.hpp"
//
//namespace caffe {
//
// template <typename Dtype>
// __global__ void ClustersTripletForward(const int nthreads, const int batch_size,
// co... | .text
.file "clusters_triplet_loss_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenC... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001054af_00000000-6_clusters_triplet_loss_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinar... | .text
.file "clusters_triplet_loss_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenC... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfff... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .file "tmpxft_001a29b6_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_se... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(void) {
}
int main(int argc, char **argv) {
kernel<<<1,1>>>();
printf("La la\n");
return 0;
} | .text
.file "simple_hello.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rs... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfff... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_se... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a29b6_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... | .text
.file "simple_hello.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rs... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] ... | code for sm_80
Function : _Z13cuda_add_impllPfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] ... | .file "tmpxft_0011ecce_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] ... | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cuda_add_impllPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 8
.type _Z13cuda_add_impllPfPKfS1_,@function
_Z13cuda_add_impllPfPKfS1_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
#include <hip/hip_runtime.h>
#include <cstdint>
using namespace std;
__global__ void cuda_add_impl(int64_t N, float* O, const float* X, const float* Y) {
auto offset = threadIdx.x;
if (offset < N) {
O[offset] = Y[offset] + X... | .text
.file "cuda_add.hip"
.globl _Z28__device_stub__cuda_add_impllPfPKfS1_ # -- Begin function _Z28__device_stub__cuda_add_impllPfPKfS1_
.p2align 4, 0x90
.type _Z28__device_stub__cuda_add_impllPfPKfS1_,@function
_Z28__device_stub__cuda_add_impllPfPKfS1_: # @_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_startproc
# %b... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cuda_add_impllPfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cuda_add_impllPfPKfS1_
.globl _Z13cuda_add_impllPfPKfS1_
.p2align 8
.type _Z13cuda_add_impllPfPKfS1_,@function
_Z13cuda_add_impllPfPKfS1_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ecce_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "cuda_add.hip"
.globl _Z28__device_stub__cuda_add_impllPfPKfS1_ # -- Begin function _Z28__device_stub__cuda_add_impllPfPKfS1_
.p2align 4, 0x90
.type _Z28__device_stub__cuda_add_impllPfPKfS1_,@function
_Z28__device_stub__cuda_add_impllPfPKfS1_: # @_Z28__device_stub__cuda_add_impllPfPKfS1_
.cfi_startproc
# %b... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__glob... | code for sm_80
Function : _Z8gpu_iopsm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xf... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__glob... | .file "tmpxft_000fd003_00000000-6_gpu_mem_bench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //gpu_bench.cu
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long MEGABYTE = 1048576;
__glob... | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_iopsm
.globl _Z8gpu_iopsm
.p2align 8
.type _Z8gpu_iopsm,@function
_Z8gpu_iopsm:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_iopsm
.amdhsa_group_segment_fixed_size 0
.amdhsa_priv... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //gpu_bench.cu
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
unsigned long MAX_OPS = 20000000;
const long... | .text
.file "gpu_mem_bench.hip"
.globl _Z23__device_stub__gpu_iopsm # -- Begin function _Z23__device_stub__gpu_iopsm
.p2align 4, 0x90
.type _Z23__device_stub__gpu_iopsm,@function
_Z23__device_stub__gpu_iopsm: # @_Z23__device_stub__gpu_iopsm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpu_iopsm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xf... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_iopsm
.globl _Z8gpu_iopsm
.p2align 8
.type _Z8gpu_iopsm,@function
_Z8gpu_iopsm:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_iopsm
.amdhsa_group_segment_fixed_size 0
.amdhsa_priv... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fd003_00000000-6_gpu_mem_bench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "gpu_mem_bench.hip"
.globl _Z23__device_stub__gpu_iopsm # -- Begin function _Z23__device_stub__gpu_iopsm
.p2align 4, 0x90
.type _Z23__device_stub__gpu_iopsm,@function
_Z23__device_stub__gpu_iopsm: # @_Z23__device_stub__gpu_iopsm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | code for sm_80
Function : gradalex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 *... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .file "tmpxft_0006c1b6_00000000-6_gradalex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gradalex
.globl gradalex
.p2align 8
.type gradalex,@function
gradalex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CY... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gradalex(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>-0.5)
{c[i] += a[i];}
else
{c[i] -= 0.5*a[i]/b[i];}
}
}
} | .text
.file "gradalex.hip"
.globl __device_stub__gradalex # -- Begin function __device_stub__gradalex
.p2align 4, 0x90
.type __device_stub__gradalex,@function
__device_stub__gradalex: # @__device_stub__gradalex
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
mov... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : gradalex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 *... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gradalex
.globl gradalex
.p2align 8
.type gradalex,@function
gradalex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CY... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006c1b6_00000000-6_gradalex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "gradalex.hip"
.globl __device_stub__gradalex # -- Begin function __device_stub__gradalex
.p2align 4, 0x90
.type __device_stub__gradalex,@function
__device_stub__gradalex: # @__device_stub__gradalex
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
mov... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], arra... | code for sm_80
Function : _Z9maxKernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], arra... | .file "tmpxft_0004b236_00000000-6_maxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdata[tid] = fmaxf(array[i], arra... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdat... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdat... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxKernelPfiS_
.globl _Z9maxKernelPfiS_
.p2align 8
.type _Z9maxKernelPfiS_,@function
_Z9maxKernelPfiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_lshl_b32 s10, s15, 1
s_add_u32 s4, s0, 24
s_addc_u32 ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void maxKernel(float *array, int size, float* max)
{
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int stride = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
while (i < size)
{
sdat... | .text
.file "maxKernel.hip"
.globl _Z24__device_stub__maxKernelPfiS_ # -- Begin function _Z24__device_stub__maxKernelPfiS_
.p2align 4, 0x90
.type _Z24__device_stub__maxKernelPfiS_,@function
_Z24__device_stub__maxKernelPfiS_: # @_Z24__device_stub__maxKernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9maxKernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxKernelPfiS_
.globl _Z9maxKernelPfiS_
.p2align 8
.type _Z9maxKernelPfiS_,@function
_Z9maxKernelPfiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_lshl_b32 s10, s15, 1
s_add_u32 s4, s0, 24
s_addc_u32 ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b236_00000000-6_maxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "maxKernel.hip"
.globl _Z24__device_stub__maxKernelPfiS_ # -- Begin function _Z24__device_stub__maxKernelPfiS_
.p2align 4, 0x90
.type _Z24__device_stub__maxKernelPfiS_,@function
_Z24__device_stub__maxKernelPfiS_: # @_Z24__device_stub__maxKernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_colum... | code for sm_80
Function : _Z7mat_dotPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_colum... | .file "tmpxft_0013a2b0_00000000-6_mat_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; k++)
c_at_ij += a[i * a_colum... | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_dotPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.p2align 8
.type _Z7mat_dotPfS_S_iiii,@function
_Z7mat_dotPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_dot(float *a, float *b, float *c,
int a_rows, int a_columns, int b_rows, int b_columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < a_rows && j < b_columns)
{
float c_at_ij = 0;
for (int k = 0; k < a_columns; ... | .text
.file "mat_dot.hip"
.globl _Z22__device_stub__mat_dotPfS_S_iiii # -- Begin function _Z22__device_stub__mat_dotPfS_S_iiii
.p2align 4, 0x90
.type _Z22__device_stub__mat_dotPfS_S_iiii,@function
_Z22__device_stub__mat_dotPfS_S_iiii: # @_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cf... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mat_dotPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_dotPfS_S_iiii
.globl _Z7mat_dotPfS_S_iiii
.p2align 8
.type _Z7mat_dotPfS_S_iiii,@function
_Z7mat_dotPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a2b0_00000000-6_mat_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "mat_dot.hip"
.globl _Z22__device_stub__mat_dotPfS_S_iiii # -- Begin function _Z22__device_stub__mat_dotPfS_S_iiii
.p2align 4, 0x90
.type _Z22__device_stub__mat_dotPfS_S_iiii,@function
_Z22__device_stub__mat_dotPfS_S_iiii: # @_Z22__device_stub__mat_dotPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float i... | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.G... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float i... | .file "tmpxft_00177b62_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid + 1];
}
}
int main() {
float i... | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid +... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid +... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_delay_a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void test(float *data) {
unsigned int tid = threadIdx.x;
if(tid < 32) {
volatile float *in = data;
in[tid] += in[tid + 32];
in[tid] += in[tid + 16];
in[tid] += in[tid + 8];
in[tid] += in[tid + 4];
in[tid] += in[tid + 2];
in[tid] += in[tid +... | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.G... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_delay_a... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177b62_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if... | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.globl _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii
.p2align 8
.type _Z11maskComputeP15HIP_vector_typeIhLj4EEPbii,@function
_Z11maskComputeP15HIP_vector_typeIhLj4EEPbii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/host_vector.h>
#define THREADS_PER_BLOCK 256
using namespace std;
__global__ void maskCompute(uchar4 *sourceImg,bool *mask,int cols,int rows)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int size=cols*rows;
mask[id]=0;
if(id<size)
{
if(... | .text
.file "blend.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__maskComputeP15HIP_vector_typeIhLj4EEPbii # -- Begin function _Z26__device_stub__ma... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main... | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main... | .file "tmpxft_0013a90b_00000000-6_vec-add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a[idx] + b[idx];
}
}
int main... | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Author: Sudnya Padalikar
// Date: 01/18/2014
// Brief: vector addition kernel in cuda
#include <hip/hip_runtime.h>
#include <stdio.h>
// Kernel that executes on the CUDA device
__global__ void vector_add(float *c, float *a, float *b, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[idx] = a... | .text
.file "vec-add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cf... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a90b_00000000-6_vec-add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "vec-add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++... | code for sm_80
Function : kernel3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++... | .file "tmpxft_00185501_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++... | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel0
.globl kernel0
.p2align 8
.type kernel0,@function
kernel0:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kernel0(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = 0; i < loop; i++) {
for (int j = 0; j < loop; j++) {
C[id] += id;
}
}
}
extern "C" __global__ void kernel1(int* C, int loop) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
... | .text
.file "kernel.hip"
.globl __device_stub__kernel0 # -- Begin function __device_stub__kernel0
.p2align 4, 0x90
.type __device_stub__kernel0,@function
__device_stub__kernel0: # @__device_stub__kernel0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185501_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl __device_stub__kernel0 # -- Begin function __device_stub__kernel0
.p2align 4, 0x90
.type __device_stub__kernel0,@function
__device_stub__kernel0: # @__device_stub__kernel0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... | .file "tmpxft_00013531_00000000-6_atomVel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //includes creating atoms with mass and temperature using probability function
//based on velocity intervals ranging 3 standard deviations with random angles
//converts spherical coordinates to cartesian coordinates for intial velocities
//Paige Diamond, Zeke Elkins, Shannon White, Kayla Huff, Tim Webber
// 10-30-2014
... | .text
.file "atomVel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00013531_00000000-6_atomVel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... | .text
.file "atomVel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | code for sm_80
Function : _Z14count_zero_onePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .file "tmpxft_00192b9b_00000000-6_count_zero_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14count_zero_onePfS_i
.globl _Z14count_zero_onePfS_i
.p2align 8
.type _Z14count_zero_onePfS_i,@function
_Z14count_zero_onePfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xf... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_zero_one(float *vec, float *data, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) ){
if (vec[xIndex] == 0)
atomicAdd(data,1);
else if (vec[xIndex] == 1)
atomicAdd(data+1,1);
}
} | .text
.file "count_zero_one.hip"
.globl _Z29__device_stub__count_zero_onePfS_i # -- Begin function _Z29__device_stub__count_zero_onePfS_i
.p2align 4, 0x90
.type _Z29__device_stub__count_zero_onePfS_i,@function
_Z29__device_stub__count_zero_onePfS_i: # @_Z29__device_stub__count_zero_onePfS_i
.cfi_startproc
# %bb.0:
subq... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14count_zero_onePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14count_zero_onePfS_i
.globl _Z14count_zero_onePfS_i
.p2align 8
.type _Z14count_zero_onePfS_i,@function
_Z14count_zero_onePfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xf... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192b9b_00000000-6_count_zero_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "count_zero_one.hip"
.globl _Z29__device_stub__count_zero_onePfS_i # -- Begin function _Z29__device_stub__count_zero_onePfS_i
.p2align 4, 0x90
.type _Z29__device_stub__count_zero_onePfS_i,@function
_Z29__device_stub__count_zero_onePfS_i: # @_Z29__device_stub__count_zero_onePfS_i
.cfi_startproc
# %bb.0:
subq... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, ... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, ... | .file "tmpxft_000444c9_00000000-6_test1_planmany.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, ... | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define FFTSIZE 8
#define BATCH 2
/********************/
/* CUDA ERROR CHECK */
/********************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, ... |
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