system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
cudaError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize);
__device__ __inline__ float dot(const float2 a, const float2 b)
{
return (a.x * b.x) + (a.y * b.y);
}
__device__ float2 calculatePosition(int x, int y, float width, float height)
{
float2 fragSize = make_float2(2 / width, 2 / height);
return make_float2(fragSize.x * x + fragSize.y / 2 - 1, (fragSize.y * y + fragSize.y / 2 - 1) * -1);
}
__global__ void baryKernel(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int *width, int *height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < *width && y < *height)
{
float2 pos = calculatePosition(x, y, *width, *height);
float2 t0 = make_float2(v2->x, v2->y);
float2 t1 = make_float2(v0->x, v0->y);
float2 t2 = make_float2(v1->x, v1->y);
float2 v0 = make_float2(t1.x - t0.x, t1.y - t0.y);
float2 v1 = make_float2(t2.x - t0.x, t2.y - t0.y);
float2 v2 = make_float2(pos.x - t0.x, pos.y - t0.y);
float d00 = dot(v0, v0);
float d01 = dot(v0, v1);
float d11 = dot(v1, v1);
float d20 = dot(v2, v0);
float d21 = dot(v2, v1);
float denom = d00 * d11 - d01 * d01;
float baryX = (d11 * d20 - d01 * d21) / denom;
float baryY = (d00 * d21 - d01 * d20) / denom;
float baryZ = 1 - baryX - baryY;
if (baryX > 0 && baryY > 0 && baryZ > 0)
{
dOut[y * *width + x] = *da * baryX + *db * baryY + *dc * baryZ;
}
else
{
dOut[y * *width + x] = 0;
}
}
}
int main()
{
printf("\n\n\nBarycentric:\n");
int2 framebufferSize = make_int2(50, 50);
float3 bary_v0 = make_float3(0, 1, 0);
float3 bary_v1 = make_float3(1, -1, 0);
float3 bary_v2 = make_float3(-1, -1, 0);
float bary_da = 3;
float bary_db = 2;
float bary_dc = 1;
float *bary_dOut = (float*)malloc(framebufferSize.x * framebufferSize.y * sizeof(float*));
// Barycentric in parallel.
cudaError_t cudaStatus = barycentricCuda(&bary_v0, &bary_v1, &bary_v2, &bary_da, &bary_db, &bary_dc, bary_dOut, framebufferSize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "barycentricCuda failed!");
return 1;
}
printf("{\n");
for (int y = 0; y < framebufferSize.y; y++)
{
printf(" {");
for (int x = 0; x < framebufferSize.x; x++)
{
printf("%.1f|", bary_dOut[x + y * framebufferSize.y]);
}
printf("}\n");
}
printf("}\n");
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
#define myMalloc(VAR, SIZE, TYPE) cudaStatus = cudaMalloc((void**)&VAR, SIZE * sizeof(TYPE)); \
if (cudaStatus != cudaSuccess) {\
fprintf(stderr, "cudaMalloc failed!"); \
goto Error; \
}
#define myVarOnGPU(VAR, SOURCEVAR, SIZE, TYPE) cudaStatus = cudaMalloc((void**)&VAR, SIZE * sizeof(TYPE));\
if (cudaStatus != cudaSuccess) {\
fprintf(stderr, "cudaMalloc failed!");\
goto Error;\
}\
cudaStatus = cudaMemcpy(VAR, SOURCEVAR, SIZE * sizeof(TYPE), cudaMemcpyHostToDevice);\
if (cudaStatus != cudaSuccess) {\
fprintf(stderr, "cudaMemcpy failed!");\
goto Error;\
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize)
{
int length = framebufferSize.x * framebufferSize.y;
int bytes = length * sizeof(float);
const dim3 windowSize(framebufferSize.x, framebufferSize.y);
const dim3 blockSize(16, 16, 1);
const dim3 gridSize(windowSize.x / blockSize.x + 1, windowSize.y / blockSize.y + 1);
float3 *dev_v0 = 0;
float3 *dev_v1 = 0;
float3 *dev_v2 = 0;
float *dev_da = 0;
float *dev_db = 0;
float *dev_dc = 0;
struct cudaPitchedPtr dstGPU;
int *dev_width = 0;
int *dev_height = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate and populate GPU buffers for vectors and data.
myVarOnGPU(dev_v0, v0, 1, float3);
myVarOnGPU(dev_v1, v1, 1, float3);
myVarOnGPU(dev_v2, v2, 1, float3);
myVarOnGPU(dev_da, da, 1, float);
myVarOnGPU(dev_db, db, 1, float);
myVarOnGPU(dev_dc, dc, 1, float);
myVarOnGPU(dev_width, &framebufferSize.x, 1, int);
myVarOnGPU(dev_height, &framebufferSize.y, 1, int);
cudaStatus = cudaMalloc3D(&dstGPU, make_cudaExtent(framebufferSize.x * sizeof(float), framebufferSize.y, 1));
// Launch a kernel on the GPU with one thread for each element.
baryKernel <<<gridSize, blockSize>>> (dev_v0, dev_v1, dev_v2, dev_da, dev_db, dev_dc, (float *)dstGPU.ptr, dev_width, dev_height);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "barycentricCuda launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching barycentricCuda!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(dOut, dstGPU.ptr, bytes, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dstGPU.ptr);
cudaFree(dev_dc);
cudaFree(dev_db);
cudaFree(dev_da);
cudaFree(dev_v2);
cudaFree(dev_v0);
cudaFree(dev_v1);
return cudaStatus;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize);
__device__ __inline__ float dot(const float2 a, const float2 b)
{
return (a.x * b.x) + (a.y * b.y);
}
__device__ float2 calculatePosition(int x, int y, float width, float height)
{
float2 fragSize = make_float2(2 / width, 2 / height);
return make_float2(fragSize.x * x + fragSize.y / 2 - 1, (fragSize.y * y + fragSize.y / 2 - 1) * -1);
}
__global__ void baryKernel(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int *width, int *height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < *width && y < *height)
{
float2 pos = calculatePosition(x, y, *width, *height);
float2 t0 = make_float2(v2->x, v2->y);
float2 t1 = make_float2(v0->x, v0->y);
float2 t2 = make_float2(v1->x, v1->y);
float2 v0 = make_float2(t1.x - t0.x, t1.y - t0.y);
float2 v1 = make_float2(t2.x - t0.x, t2.y - t0.y);
float2 v2 = make_float2(pos.x - t0.x, pos.y - t0.y);
float d00 = dot(v0, v0);
float d01 = dot(v0, v1);
float d11 = dot(v1, v1);
float d20 = dot(v2, v0);
float d21 = dot(v2, v1);
float denom = d00 * d11 - d01 * d01;
float baryX = (d11 * d20 - d01 * d21) / denom;
float baryY = (d00 * d21 - d01 * d20) / denom;
float baryZ = 1 - baryX - baryY;
if (baryX > 0 && baryY > 0 && baryZ > 0)
{
dOut[y * *width + x] = *da * baryX + *db * baryY + *dc * baryZ;
}
else
{
dOut[y * *width + x] = 0;
}
}
}
int main()
{
printf("\n\n\nBarycentric:\n");
int2 framebufferSize = make_int2(50, 50);
float3 bary_v0 = make_float3(0, 1, 0);
float3 bary_v1 = make_float3(1, -1, 0);
float3 bary_v2 = make_float3(-1, -1, 0);
float bary_da = 3;
float bary_db = 2;
float bary_dc = 1;
float *bary_dOut = (float*)malloc(framebufferSize.x * framebufferSize.y * sizeof(float*));
// Barycentric in parallel.
hipError_t cudaStatus = barycentricCuda(&bary_v0, &bary_v1, &bary_v2, &bary_da, &bary_db, &bary_dc, bary_dOut, framebufferSize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda failed!");
return 1;
}
printf("{\n");
for (int y = 0; y < framebufferSize.y; y++)
{
printf(" {");
for (int x = 0; x < framebufferSize.x; x++)
{
printf("%.1f|", bary_dOut[x + y * framebufferSize.y]);
}
printf("}\n");
}
printf("}\n");
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
#define myMalloc(VAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE)); \
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!"); \
goto Error; \
}
#define myVarOnGPU(VAR, SOURCEVAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE));\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!");\
goto Error;\
}\
cudaStatus = hipMemcpy(VAR, SOURCEVAR, SIZE * sizeof(TYPE), hipMemcpyHostToDevice);\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMemcpy failed!");\
goto Error;\
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize)
{
int length = framebufferSize.x * framebufferSize.y;
int bytes = length * sizeof(float);
const dim3 windowSize(framebufferSize.x, framebufferSize.y);
const dim3 blockSize(16, 16, 1);
const dim3 gridSize(windowSize.x / blockSize.x + 1, windowSize.y / blockSize.y + 1);
float3 *dev_v0 = 0;
float3 *dev_v1 = 0;
float3 *dev_v2 = 0;
float *dev_da = 0;
float *dev_db = 0;
float *dev_dc = 0;
struct hipPitchedPtr dstGPU;
int *dev_width = 0;
int *dev_height = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate and populate GPU buffers for vectors and data.
myVarOnGPU(dev_v0, v0, 1, float3);
myVarOnGPU(dev_v1, v1, 1, float3);
myVarOnGPU(dev_v2, v2, 1, float3);
myVarOnGPU(dev_da, da, 1, float);
myVarOnGPU(dev_db, db, 1, float);
myVarOnGPU(dev_dc, dc, 1, float);
myVarOnGPU(dev_width, &framebufferSize.x, 1, int);
myVarOnGPU(dev_height, &framebufferSize.y, 1, int);
cudaStatus = hipMalloc3D(&dstGPU, make_hipExtent(framebufferSize.x * sizeof(float), framebufferSize.y, 1));
// Launch a kernel on the GPU with one thread for each element.
baryKernel <<<gridSize, blockSize>>> (dev_v0, dev_v1, dev_v2, dev_da, dev_db, dev_dc, (float *)dstGPU.ptr, dev_width, dev_height);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching barycentricCuda!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(dOut, dstGPU.ptr, bytes, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dstGPU.ptr);
hipFree(dev_dc);
hipFree(dev_db);
hipFree(dev_da);
hipFree(dev_v2);
hipFree(dev_v0);
hipFree(dev_v1);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize);
__device__ __inline__ float dot(const float2 a, const float2 b)
{
return (a.x * b.x) + (a.y * b.y);
}
__device__ float2 calculatePosition(int x, int y, float width, float height)
{
float2 fragSize = make_float2(2 / width, 2 / height);
return make_float2(fragSize.x * x + fragSize.y / 2 - 1, (fragSize.y * y + fragSize.y / 2 - 1) * -1);
}
__global__ void baryKernel(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int *width, int *height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < *width && y < *height)
{
float2 pos = calculatePosition(x, y, *width, *height);
float2 t0 = make_float2(v2->x, v2->y);
float2 t1 = make_float2(v0->x, v0->y);
float2 t2 = make_float2(v1->x, v1->y);
float2 v0 = make_float2(t1.x - t0.x, t1.y - t0.y);
float2 v1 = make_float2(t2.x - t0.x, t2.y - t0.y);
float2 v2 = make_float2(pos.x - t0.x, pos.y - t0.y);
float d00 = dot(v0, v0);
float d01 = dot(v0, v1);
float d11 = dot(v1, v1);
float d20 = dot(v2, v0);
float d21 = dot(v2, v1);
float denom = d00 * d11 - d01 * d01;
float baryX = (d11 * d20 - d01 * d21) / denom;
float baryY = (d00 * d21 - d01 * d20) / denom;
float baryZ = 1 - baryX - baryY;
if (baryX > 0 && baryY > 0 && baryZ > 0)
{
dOut[y * *width + x] = *da * baryX + *db * baryY + *dc * baryZ;
}
else
{
dOut[y * *width + x] = 0;
}
}
}
int main()
{
printf("\n\n\nBarycentric:\n");
int2 framebufferSize = make_int2(50, 50);
float3 bary_v0 = make_float3(0, 1, 0);
float3 bary_v1 = make_float3(1, -1, 0);
float3 bary_v2 = make_float3(-1, -1, 0);
float bary_da = 3;
float bary_db = 2;
float bary_dc = 1;
float *bary_dOut = (float*)malloc(framebufferSize.x * framebufferSize.y * sizeof(float*));
// Barycentric in parallel.
hipError_t cudaStatus = barycentricCuda(&bary_v0, &bary_v1, &bary_v2, &bary_da, &bary_db, &bary_dc, bary_dOut, framebufferSize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda failed!");
return 1;
}
printf("{\n");
for (int y = 0; y < framebufferSize.y; y++)
{
printf(" {");
for (int x = 0; x < framebufferSize.x; x++)
{
printf("%.1f|", bary_dOut[x + y * framebufferSize.y]);
}
printf("}\n");
}
printf("}\n");
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
#define myMalloc(VAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE)); \
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!"); \
goto Error; \
}
#define myVarOnGPU(VAR, SOURCEVAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE));\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!");\
goto Error;\
}\
cudaStatus = hipMemcpy(VAR, SOURCEVAR, SIZE * sizeof(TYPE), hipMemcpyHostToDevice);\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMemcpy failed!");\
goto Error;\
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize)
{
int length = framebufferSize.x * framebufferSize.y;
int bytes = length * sizeof(float);
const dim3 windowSize(framebufferSize.x, framebufferSize.y);
const dim3 blockSize(16, 16, 1);
const dim3 gridSize(windowSize.x / blockSize.x + 1, windowSize.y / blockSize.y + 1);
float3 *dev_v0 = 0;
float3 *dev_v1 = 0;
float3 *dev_v2 = 0;
float *dev_da = 0;
float *dev_db = 0;
float *dev_dc = 0;
struct hipPitchedPtr dstGPU;
int *dev_width = 0;
int *dev_height = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate and populate GPU buffers for vectors and data.
myVarOnGPU(dev_v0, v0, 1, float3);
myVarOnGPU(dev_v1, v1, 1, float3);
myVarOnGPU(dev_v2, v2, 1, float3);
myVarOnGPU(dev_da, da, 1, float);
myVarOnGPU(dev_db, db, 1, float);
myVarOnGPU(dev_dc, dc, 1, float);
myVarOnGPU(dev_width, &framebufferSize.x, 1, int);
myVarOnGPU(dev_height, &framebufferSize.y, 1, int);
cudaStatus = hipMalloc3D(&dstGPU, make_hipExtent(framebufferSize.x * sizeof(float), framebufferSize.y, 1));
// Launch a kernel on the GPU with one thread for each element.
baryKernel <<<gridSize, blockSize>>> (dev_v0, dev_v1, dev_v2, dev_da, dev_db, dev_dc, (float *)dstGPU.ptr, dev_width, dev_height);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching barycentricCuda!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(dOut, dstGPU.ptr, bytes, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dstGPU.ptr);
hipFree(dev_dc);
hipFree(dev_db);
hipFree(dev_da);
hipFree(dev_v2);
hipFree(dev_v0);
hipFree(dev_v1);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.globl _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 8
.type _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@function
_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s5, s[0:1], 0x54
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x40
s_load_b32 s3, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[6:7], 0x0
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_cvt_f32_i32_e32 v0, s4
v_cvt_f32_i32_e32 v3, s2
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
v_div_scale_f32 v4, null, v0, v0, 2.0
v_div_scale_f32 v5, null, v3, v3, 2.0
v_div_scale_f32 v10, vcc_lo, 2.0, v0, 2.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
v_div_scale_f32 v8, s2, 2.0, v3, 2.0
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v4, v9, v10
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v9, v10
v_div_fmas_f32 v4, v4, v6, v9
v_cvt_f32_i32_e32 v6, v2
v_mul_f32_e32 v11, v8, v7
s_mov_b32 vcc_lo, s2
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[6:7], 0x0
s_load_b64 s[6:7], s[8:9], 0x0
s_load_b64 s[8:9], s[10:11], 0x0
v_div_fixup_f32 v0, v4, v0, 2.0
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v7, s8, s2
v_div_fixup_f32 v3, v5, v3, 2.0
v_cvt_f32_i32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0.5, v3
v_fma_f32 v0, v0, v5, v4
v_fmac_f32_e32 v4, v3, v6
v_sub_f32_e64 v5, s9, s3
v_sub_f32_e64 v6, s6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v0, -1.0, v0
v_add_f32_e32 v3, -1.0, v4
v_sub_f32_e64 v4, s7, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e64 v3, -v3, s3
v_mul_f32_e32 v8, v4, v5
v_subrev_f32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v10, v4, v4 :: v_dual_mul_f32 v9, v3, v5
v_dual_mul_f32 v3, v3, v4 :: v_dual_fmac_f32 v8, v6, v7
v_mul_f32_e32 v4, v5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v10, v6, v6 :: v_dual_fmac_f32 v9, v0, v7
v_fmac_f32_e32 v3, v0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v0, v8, v8
v_dual_fmac_f32 v4, v7, v7 :: v_dual_mul_f32 v5, v8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v3, v8
v_fma_f32 v7, v10, v4, -v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, v3, v4, -v5
v_fma_f32 v3, v10, v9, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v7, v7, v0
v_div_scale_f32 v5, null, v7, v7, v3
v_div_scale_f32 v11, vcc_lo, v0, v7, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v8, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v4, v6, 1.0
v_fma_f32 v10, -v5, v8, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v9, v6
v_fmac_f32_e32 v8, v10, v8
v_div_scale_f32 v9, s2, v3, v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v11, v6
v_mul_f32_e32 v12, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v4, v10, v11
v_fma_f32 v14, -v5, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v13, v6
v_fmac_f32_e32 v12, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v10, v11
v_fma_f32 v5, -v5, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v10
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v5, v5, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v4, v7, v0
v_div_fixup_f32 v4, v5, v7, v3
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v3, 1.0, v0
v_cmp_lt_f32_e32 vcc_lo, 0, v0
v_cmp_lt_f32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v3
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[10:11], 0x0
s_load_b32 s5, s[8:9], 0x0
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v5, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s5, v0
v_fmac_f32_e32 v5, s6, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x30
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, .Lfunc_end0-_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize);
__device__ __inline__ float dot(const float2 a, const float2 b)
{
return (a.x * b.x) + (a.y * b.y);
}
__device__ float2 calculatePosition(int x, int y, float width, float height)
{
float2 fragSize = make_float2(2 / width, 2 / height);
return make_float2(fragSize.x * x + fragSize.y / 2 - 1, (fragSize.y * y + fragSize.y / 2 - 1) * -1);
}
__global__ void baryKernel(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int *width, int *height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < *width && y < *height)
{
float2 pos = calculatePosition(x, y, *width, *height);
float2 t0 = make_float2(v2->x, v2->y);
float2 t1 = make_float2(v0->x, v0->y);
float2 t2 = make_float2(v1->x, v1->y);
float2 v0 = make_float2(t1.x - t0.x, t1.y - t0.y);
float2 v1 = make_float2(t2.x - t0.x, t2.y - t0.y);
float2 v2 = make_float2(pos.x - t0.x, pos.y - t0.y);
float d00 = dot(v0, v0);
float d01 = dot(v0, v1);
float d11 = dot(v1, v1);
float d20 = dot(v2, v0);
float d21 = dot(v2, v1);
float denom = d00 * d11 - d01 * d01;
float baryX = (d11 * d20 - d01 * d21) / denom;
float baryY = (d00 * d21 - d01 * d20) / denom;
float baryZ = 1 - baryX - baryY;
if (baryX > 0 && baryY > 0 && baryZ > 0)
{
dOut[y * *width + x] = *da * baryX + *db * baryY + *dc * baryZ;
}
else
{
dOut[y * *width + x] = 0;
}
}
}
int main()
{
printf("\n\n\nBarycentric:\n");
int2 framebufferSize = make_int2(50, 50);
float3 bary_v0 = make_float3(0, 1, 0);
float3 bary_v1 = make_float3(1, -1, 0);
float3 bary_v2 = make_float3(-1, -1, 0);
float bary_da = 3;
float bary_db = 2;
float bary_dc = 1;
float *bary_dOut = (float*)malloc(framebufferSize.x * framebufferSize.y * sizeof(float*));
// Barycentric in parallel.
hipError_t cudaStatus = barycentricCuda(&bary_v0, &bary_v1, &bary_v2, &bary_da, &bary_db, &bary_dc, bary_dOut, framebufferSize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda failed!");
return 1;
}
printf("{\n");
for (int y = 0; y < framebufferSize.y; y++)
{
printf(" {");
for (int x = 0; x < framebufferSize.x; x++)
{
printf("%.1f|", bary_dOut[x + y * framebufferSize.y]);
}
printf("}\n");
}
printf("}\n");
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
#define myMalloc(VAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE)); \
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!"); \
goto Error; \
}
#define myVarOnGPU(VAR, SOURCEVAR, SIZE, TYPE) cudaStatus = hipMalloc((void**)&VAR, SIZE * sizeof(TYPE));\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMalloc failed!");\
goto Error;\
}\
cudaStatus = hipMemcpy(VAR, SOURCEVAR, SIZE * sizeof(TYPE), hipMemcpyHostToDevice);\
if (cudaStatus != hipSuccess) {\
fprintf(stderr, "hipMemcpy failed!");\
goto Error;\
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t barycentricCuda(const float3 *v0, const float3 *v1, const float3 *v2, const float *da, const float *db, const float *dc, float *dOut, int2 framebufferSize)
{
int length = framebufferSize.x * framebufferSize.y;
int bytes = length * sizeof(float);
const dim3 windowSize(framebufferSize.x, framebufferSize.y);
const dim3 blockSize(16, 16, 1);
const dim3 gridSize(windowSize.x / blockSize.x + 1, windowSize.y / blockSize.y + 1);
float3 *dev_v0 = 0;
float3 *dev_v1 = 0;
float3 *dev_v2 = 0;
float *dev_da = 0;
float *dev_db = 0;
float *dev_dc = 0;
struct hipPitchedPtr dstGPU;
int *dev_width = 0;
int *dev_height = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate and populate GPU buffers for vectors and data.
myVarOnGPU(dev_v0, v0, 1, float3);
myVarOnGPU(dev_v1, v1, 1, float3);
myVarOnGPU(dev_v2, v2, 1, float3);
myVarOnGPU(dev_da, da, 1, float);
myVarOnGPU(dev_db, db, 1, float);
myVarOnGPU(dev_dc, dc, 1, float);
myVarOnGPU(dev_width, &framebufferSize.x, 1, int);
myVarOnGPU(dev_height, &framebufferSize.y, 1, int);
cudaStatus = hipMalloc3D(&dstGPU, make_hipExtent(framebufferSize.x * sizeof(float), framebufferSize.y, 1));
// Launch a kernel on the GPU with one thread for each element.
baryKernel <<<gridSize, blockSize>>> (dev_v0, dev_v1, dev_v2, dev_da, dev_db, dev_dc, (float *)dstGPU.ptr, dev_width, dev_height);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "barycentricCuda launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching barycentricCuda!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(dOut, dstGPU.ptr, bytes, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dstGPU.ptr);
hipFree(dev_dc);
hipFree(dev_db);
hipFree(dev_da);
hipFree(dev_v2);
hipFree(dev_v0);
hipFree(dev_v1);
return cudaStatus;
} | .text
.file "kernel.hip"
.globl _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_ # -- Begin function _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 4, 0x90
.type _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@function
_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_: # @_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, .Lfunc_end0-_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.zero 4
.zero 4
.LCPI1_1:
.long 0x3f800000 # float 1
.long 0xbf800000 # float -1
.zero 4
.zero 4
.LCPI1_2:
.long 0xbf800000 # float -1
.long 0xbf800000 # float -1
.zero 4
.zero 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp)
movl $0, 56(%rsp)
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%rsp)
movl $0, 40(%rsp)
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp)
movl $0, 24(%rsp)
movl $1077936128, 12(%rsp) # imm = 0x40400000
movl $1073741824, 8(%rsp) # imm = 0x40000000
movl $1065353216, 4(%rsp) # imm = 0x3F800000
movl $20000, %edi # imm = 0x4E20
callq malloc
movq %rax, %rbx
movabsq $214748364850, %rax # imm = 0x3200000032
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
leaq 8(%rsp), %r8
leaq 4(%rsp), %r9
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
callq _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
addq $16, %rsp
.cfi_adjust_cfa_offset -16
testl %eax, %eax
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq $50, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
incq %r14
addq $200, %rbx
cmpq $50, %r14
jne .LBB1_3
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_7
.LBB1_9:
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $23, %esi
jmp .LBB1_8
.LBB1_7:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $22, %esi
.LBB1_8:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_9
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE # -- Begin function _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.p2align 4, 0x90
.type _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE,@function
_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE: # @_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 408(%rsp), %eax
movl %eax, 92(%rsp) # 4-byte Spill
movl 412(%rsp), %eax
movl %eax, 88(%rsp) # 4-byte Spill
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 80(%rsp)
movq $0, 72(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_29
# %bb.1:
leaq 64(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.2:
movq 64(%rsp), %rdi
movl $12, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.3:
leaq 56(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.4:
movq 56(%rsp), %rdi
movl $12, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.5:
leaq 48(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.6:
movq 48(%rsp), %rdi
movl $12, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.7:
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.8:
movq 40(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.9:
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.10:
movq 32(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.11:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.12:
movq 24(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.13:
leaq 80(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.14:
movq 80(%rsp), %rdi
leaq 408(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.15:
leaq 72(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.16:
leaq 412(%rsp), %rsi
movq 72(%rsp), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.17:
movl 92(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
shrl $4, %eax
movl 88(%rsp), %r14d # 4-byte Reload
movl %r14d, %ecx
shrl $4, %ecx
incl %ecx
shlq $32, %rcx
leaq (%rax,%rcx), %rbx
incq %rbx
movslq 408(%rsp), %rax
shlq $2, %rax
movslq 412(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 224(%rsp)
movq $1, 232(%rsp)
movups 216(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $1, 16(%rsp)
leaq 312(%rsp), %rdi
callq hipMalloc3D
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
movq 24(%rsp), %r8
movq 312(%rsp), %r9
movq 80(%rsp), %r10
movq 72(%rsp), %r11
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movq %rsi, 184(%rsp)
movq %rdi, 176(%rsp)
movq %r8, 168(%rsp)
movq %r9, 160(%rsp)
movq %r10, 152(%rsp)
movq %r11, 144(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rax
movq 96(%rsp), %rdi
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 240(%rsp), %r9
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %edi
callq hipLaunchKernel
.LBB2_19:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_30
# %bb.20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_31
# %bb.21:
imull %r14d, %ebp
movq 400(%rsp), %rdi
shll $2, %ebp
movq 312(%rsp), %rsi
movslq %ebp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_28
# %bb.22:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_27
.LBB2_23:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
jmp .LBB2_25
.LBB2_24:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
.LBB2_25:
movl $17, %esi
.LBB2_26:
movl $1, %edx
.LBB2_27:
callq fwrite@PLT
.LBB2_28:
movq 312(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_29:
.cfi_def_cfa_offset 400
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $63, %esi
jmp .LBB2_26
.LBB2_30:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_28
.LBB2_31:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_28
.Lfunc_end2:
.size _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE, .Lfunc_end2-_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@object # @_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.section .rodata,"a",@progbits
.globl _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 3, 0x0
_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_:
.quad _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.size _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "barycentricCuda failed!"
.size .L.str.1, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " {"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.1f|"
.size .L.str.4, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceReset failed!"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.7, 64
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc failed!"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy failed!"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "barycentricCuda launch failed: %s\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching barycentricCuda!\n"
.size .L.str.11, 78
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n\nBarycentric:"
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "{"
.size .Lstr.1, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "}"
.size .Lstr.3, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x19c] ; /* 0x0000670000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fc400078e0202 */
/*0080*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e260000002600 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x004fda0003f06070 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ MOV R5, c[0x0][0x1a4] ; /* 0x0000690000057a02 */
/* 0x001fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff047624 */
/* 0x000fca00078e00ff */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e240000002200 */
/*00f0*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0207 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fda0003f06070 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ I2F R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000201400 */
/*0130*/ UMOV UR6, 0x40000000 ; /* 0x4000000000067882 */
/* 0x000fe40000000000 */
/*0140*/ IMAD.U32 R9, RZ, RZ, UR6 ; /* 0x00000006ff097e24 */
/* 0x000fca000f8e00ff */
/*0150*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x001e300000001000 */
/*0160*/ FCHK P0, R9, R6 ; /* 0x0000000609007302 */
/* 0x000e620000000000 */
/*0170*/ FFMA R4, -R6, R7, 1 ; /* 0x3f80000006047423 */
/* 0x001fc80000000107 */
/*0180*/ FFMA R4, R7, R4, R7 ; /* 0x0000000407047223 */
/* 0x000fc80000000007 */
/*0190*/ FFMA R7, R4, 2, RZ ; /* 0x4000000004077823 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R8, -R6, R7, 2 ; /* 0x4000000006087423 */
/* 0x000fc80000000107 */
/*01b0*/ FFMA R4, R4, R8, R7 ; /* 0x0000000804047223 */
/* 0x000fe20000000007 */
/*01c0*/ @!P0 BRA 0x220 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*01d0*/ MOV R7, R6 ; /* 0x0000000600077202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40000000 ; /* 0x40000000ff0b7424 */
/* 0x000fe200078e00ff */
/*01f0*/ MOV R10, 0x210 ; /* 0x00000210000a7802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x8d0 ; /* 0x000006c000007944 */
/* 0x000fea0003c00000 */
/*0210*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe40000000f00 */
/*0220*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e220000201400 */
/*0230*/ UMOV UR6, 0x40000000 ; /* 0x4000000000067882 */
/* 0x000fe40000000000 */
/*0240*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fca000f8e00ff */
/*0250*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e300000001000 */
/*0260*/ FCHK P0, R10, R5 ; /* 0x000000050a007302 */
/* 0x000e620000000000 */
/*0270*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0280*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0290*/ FFMA R6, R7, 2, RZ ; /* 0x4000000007067823 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R8, -R5, R6, 2 ; /* 0x4000000005087423 */
/* 0x000fc80000000106 */
/*02b0*/ FFMA R7, R7, R8, R6 ; /* 0x0000000807077223 */
/* 0x000fe20000000006 */
/*02c0*/ @!P0 BRA 0x320 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*02d0*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40000000 ; /* 0x40000000ff0b7424 */
/* 0x000fe200078e00ff */
/*02f0*/ MOV R10, 0x310 ; /* 0x00000310000a7802 */
/* 0x000fe40000000f00 */
/*0300*/ CALL.REL.NOINC 0x8d0 ; /* 0x000005c000007944 */
/* 0x000fea0003c00000 */
/*0310*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x000fe40000000f00 */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff107624 */
/* 0x000fe200078e00ff */
/*0330*/ MOV R17, c[0x0][0x174] ; /* 0x00005d0000117a02 */
/* 0x000fe20000000f00 */
/*0340*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0e7624 */
/* 0x000fe200078e00ff */
/*0350*/ MOV R15, c[0x0][0x164] ; /* 0x00005900000f7a02 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff127624 */
/* 0x000fe200078e00ff */
/*0370*/ MOV R19, c[0x0][0x16c] ; /* 0x00005b0000137a02 */
/* 0x000fe20000000f00 */
/*0380*/ LDG.E R8, [R16.64+0x4] ; /* 0x0000040410087981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R5, [R14.64+0x4] ; /* 0x000004040e057981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R13, [R18.64+0x4] ; /* 0x00000404120d7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000328000c1e1900 */
/*03c0*/ LDG.E R6, [R14.64] ; /* 0x000000040e067981 */
/* 0x000128000c1e1900 */
/*03d0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000f62000c1e1900 */
/*03e0*/ I2F R20, R2 ; /* 0x0000000200147306 */
/* 0x000e620000201400 */
/*03f0*/ BSSY B0, 0x660 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0400*/ FMUL R14, R7, 0.5 ; /* 0x3f000000070e7820 */
/* 0x001fcc0000400000 */
/*0410*/ I2F R21, R3 ; /* 0x0000000300157306 */
/* 0x000e220000201400 */
/*0420*/ FFMA R20, R20, R7, R14.reuse ; /* 0x0000000714147223 */
/* 0x102fe4000000000e */
/*0430*/ FFMA R4, R21, R4, R14 ; /* 0x0000000415047223 */
/* 0x001fc8000000000e */
/*0440*/ FADD R4, R4, -1 ; /* 0xbf80000004047421 */
/* 0x000fe40000000000 */
/*0450*/ FADD R10, R5, -R8 ; /* 0x80000008050a7221 */
/* 0x004fe40000000000 */
/*0460*/ FADD R13, -R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fc80000000100 */
/*0470*/ FMUL R5, R10, R13.reuse ; /* 0x0000000d0a057220 */
/* 0x080fe40000400000 */
/*0480*/ FMUL R17, R13, R13 ; /* 0x0000000d0d117220 */
/* 0x000fe40000400000 */
/*0490*/ FADD R11, R6, -R9 ; /* 0x80000009060b7221 */
/* 0x010fe40000000000 */
/*04a0*/ FMUL R6, R10, R10 ; /* 0x0000000a0a067220 */
/* 0x000fe40000400000 */
/*04b0*/ FADD R12, -R9, R12 ; /* 0x0000000c090c7221 */
/* 0x020fe40000000100 */
/*04c0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */
/* 0x000fc40000000006 */
/*04d0*/ FFMA R5, R11, R12.reuse, R5 ; /* 0x0000000c0b057223 */
/* 0x080fe40000000005 */
/*04e0*/ FFMA R15, R12, R12, R17 ; /* 0x0000000c0c0f7223 */
/* 0x000fe40000000011 */
/*04f0*/ FADD R17, R20, -1 ; /* 0xbf80000014117421 */
/* 0x000fe40000000000 */
/*0500*/ FMUL R16, R5, R5 ; /* 0x0000000505107220 */
/* 0x000fe40000400000 */
/*0510*/ FADD R17, -R17, -R8 ; /* 0x8000000811117221 */
/* 0x000fe40000000100 */
/*0520*/ FFMA R7, R6, R15, -R16 ; /* 0x0000000f06077223 */
/* 0x000fc40000000810 */
/*0530*/ FADD R4, R4, -R9 ; /* 0x8000000904047221 */
/* 0x000fe40000000000 */
/*0540*/ FMUL R13, R13, R17.reuse ; /* 0x000000110d0d7220 */
/* 0x080fe20000400000 */
/*0550*/ MUFU.RCP R14, R7 ; /* 0x00000007000e7308 */
/* 0x000e220000001000 */
/*0560*/ FMUL R8, R10, R17 ; /* 0x000000110a087220 */
/* 0x000fe40000400000 */
/*0570*/ FFMA R12, R12, R4.reuse, R13 ; /* 0x000000040c0c7223 */
/* 0x080fe4000000000d */
/*0580*/ FFMA R8, R11, R4, R8 ; /* 0x000000040b087223 */
/* 0x000fe40000000008 */
/*0590*/ FMUL R4, R5, R12 ; /* 0x0000000c05047220 */
/* 0x000fc80000400000 */
/*05a0*/ FFMA R11, R15, R8, -R4 ; /* 0x000000080f0b7223 */
/* 0x000fc80000000804 */
/*05b0*/ FCHK P0, R11, R7 ; /* 0x000000070b007302 */
/* 0x000e620000000000 */
/*05c0*/ FFMA R9, -R7, R14, 1 ; /* 0x3f80000007097423 */
/* 0x001fc8000000010e */
/*05d0*/ FFMA R9, R14, R9, R14 ; /* 0x000000090e097223 */
/* 0x000fc8000000000e */
/*05e0*/ FFMA R4, R11, R9, RZ ; /* 0x000000090b047223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R10, -R7, R4, R11 ; /* 0x00000004070a7223 */
/* 0x000fc8000000010b */
/*0600*/ FFMA R4, R9, R10, R4 ; /* 0x0000000a09047223 */
/* 0x000fe20000000004 */
/*0610*/ @!P0 BRA 0x650 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0620*/ MOV R10, 0x640 ; /* 0x00000640000a7802 */
/* 0x000fe40000000f00 */
/*0630*/ CALL.REL.NOINC 0x8d0 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*0640*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0009 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ MUFU.RCP R10, R7 ; /* 0x00000007000a7308 */
/* 0x000e220000001000 */
/*0670*/ FMUL R5, R5, R8 ; /* 0x0000000805057220 */
/* 0x000fe20000400000 */
/*0680*/ BSSY B0, 0x750 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*0690*/ FFMA R11, R6, R12, -R5 ; /* 0x0000000c060b7223 */
/* 0x000fc80000000805 */
/*06a0*/ FCHK P0, R11, R7 ; /* 0x000000070b007302 */
/* 0x000e620000000000 */
/*06b0*/ FFMA R9, -R7, R10, 1 ; /* 0x3f80000007097423 */
/* 0x001fc8000000010a */
/*06c0*/ FFMA R10, R10, R9, R10 ; /* 0x000000090a0a7223 */
/* 0x000fc8000000000a */
/*06d0*/ FFMA R6, R10, R11, RZ ; /* 0x0000000b0a067223 */
/* 0x000fc800000000ff */
/*06e0*/ FFMA R5, -R7, R6, R11 ; /* 0x0000000607057223 */
/* 0x000fc8000000010b */
/*06f0*/ FFMA R5, R10, R5, R6 ; /* 0x000000050a057223 */
/* 0x000fe20000000006 */
/*0700*/ @!P0 BRA 0x740 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0710*/ MOV R10, 0x730 ; /* 0x00000730000a7802 */
/* 0x000fe40000000f00 */
/*0720*/ CALL.REL.NOINC 0x8d0 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*0730*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ FSETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f04000 */
/*0760*/ FADD R12, -R4, 1 ; /* 0x3f800000040c7421 */
/* 0x000fe20000000100 */
/*0770*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0780*/ IMAD R2, R2, R0, R3 ; /* 0x0000000002027224 */
/* 0x000fe200078e0203 */
/*0790*/ FSETP.GT.AND P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720b */
/* 0x000fc80000704000 */
/*07a0*/ FSETP.GT.AND P0, PT, R12, R5, P0 ; /* 0x000000050c00720b */
/* 0x000fc80000704000 */
/*07b0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fd200078e0007 */
/*07c0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*07d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*07f0*/ MOV R9, c[0x0][0x184] ; /* 0x0000610000097a02 */
/* 0x000fe20000000f00 */
/*0800*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe200078e00ff */
/*0810*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fc60000000f00 */
/*0820*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0830*/ MOV R11, c[0x0][0x18c] ; /* 0x00006300000b7a02 */
/* 0x000fe40000000f00 */
/*0840*/ MOV R10, c[0x0][0x188] ; /* 0x00006200000a7a02 */
/* 0x000fe20000000f00 */
/*0850*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f22000c1e1900 */
/*0870*/ FMUL R0, R8, R5 ; /* 0x0000000508007220 */
/* 0x004fe40000400000 */
/*0880*/ FADD R5, R12, -R5 ; /* 0x800000050c057221 */
/* 0x000fc40000000000 */
/*0890*/ FFMA R0, R7, R4, R0 ; /* 0x0000000407007223 */
/* 0x008fc80000000000 */
/*08a0*/ FFMA R5, R5, R11, R0 ; /* 0x0000000b05057223 */
/* 0x010fca0000000000 */
/*08b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ SHF.R.U32.HI R13, RZ, 0x17, R7 ; /* 0x00000017ff0d7819 */
/* 0x000fe20000011607 */
/*08e0*/ BSSY B1, 0xf20 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*08f0*/ SHF.R.U32.HI R9, RZ, 0x17, R11 ; /* 0x00000017ff097819 */
/* 0x000fe2000001160b */
/*0900*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0007 */
/*0910*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fe400078ec0ff */
/*0920*/ LOP3.LUT R16, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09107812 */
/* 0x000fe400078ec0ff */
/*0930*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R15, R16, -0x1, RZ ; /* 0xffffffff100f7810 */
/* 0x000fc40007ffe0ff */
/*0950*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*0960*/ ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; /* 0x000000fd0f00780c */
/* 0x000fda0000704470 */
/*0970*/ @!P0 MOV R9, RZ ; /* 0x000000ff00098202 */
/* 0x000fe20000000f00 */
/*0980*/ @!P0 BRA 0xb00 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0990*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*09a0*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*09b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09c0*/ @P0 BRA 0xf00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT P0, RZ, R14, 0x7fffffff, R11, 0xc8, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000780c80b */
/*09e0*/ @!P0 BRA 0xee0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*0a00*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*0a20*/ @!P1 BRA !P2, 0xee0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a30*/ LOP3.LUT P2, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000784c0ff */
/*0a40*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a50*/ @P1 BRA 0xec0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fc8000782c0ff */
/*0a70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a80*/ @P0 BRA 0xe90 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f06270 */
/*0aa0*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0ab0*/ @P0 MOV R9, RZ ; /* 0x000000ff00090202 */
/* 0x000fe20000000f00 */
/*0ac0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0ad0*/ @!P0 FFMA R11, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b0b8823 */
/* 0x000fe400000000ff */
/*0ae0*/ @!P1 FFMA R14, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070e9823 */
/* 0x000fe200000000ff */
/*0af0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ LEA R15, R13, 0xc0800000, 0x17 ; /* 0xc08000000d0f7811 */
/* 0x000fe200078eb8ff */
/*0b10*/ BSSY B2, 0xe80 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0b20*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fe40007ffe0ff */
/*0b30*/ IADD3 R17, -R15, R14, RZ ; /* 0x0000000e0f117210 */
/* 0x000fc60007ffe1ff */
/*0b40*/ IMAD R11, R16.reuse, -0x800000, R11 ; /* 0xff800000100b7824 */
/* 0x040fe200078e020b */
/*0b50*/ MUFU.RCP R14, R17 ; /* 0x00000011000e7308 */
/* 0x000e220000001000 */
/*0b60*/ FADD.FTZ R18, -R17, -RZ ; /* 0x800000ff11127221 */
/* 0x000fe20000010100 */
/*0b70*/ IADD3 R16, R16, 0x7f, -R13 ; /* 0x0000007f10107810 */
/* 0x000fc80007ffe80d */
/*0b80*/ IADD3 R16, R16, R9, RZ ; /* 0x0000000910107210 */
/* 0x000fe20007ffe0ff */
/*0b90*/ FFMA R15, R14, R18, 1 ; /* 0x3f8000000e0f7423 */
/* 0x001fc80000000012 */
/*0ba0*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fc8000000000e */
/*0bb0*/ FFMA R15, R11, R14, RZ ; /* 0x0000000e0b0f7223 */
/* 0x000fc800000000ff */
/*0bc0*/ FFMA R19, R18, R15, R11 ; /* 0x0000000f12137223 */
/* 0x000fc8000000000b */
/*0bd0*/ FFMA R15, R14, R19, R15 ; /* 0x000000130e0f7223 */
/* 0x000fc8000000000f */
/*0be0*/ FFMA R18, R18, R15, R11 ; /* 0x0000000f12127223 */
/* 0x000fc8000000000b */
/*0bf0*/ FFMA R11, R14, R18, R15 ; /* 0x000000120e0b7223 */
/* 0x000fca000000000f */
/*0c00*/ SHF.R.U32.HI R13, RZ, 0x17, R11 ; /* 0x00000017ff0d7819 */
/* 0x000fc8000001160b */
/*0c10*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fca00078ec0ff */
/*0c20*/ IMAD.IADD R17, R13, 0x1, R16 ; /* 0x000000010d117824 */
/* 0x000fca00078e0210 */
/*0c30*/ IADD3 R9, R17, -0x1, RZ ; /* 0xffffffff11097810 */
/* 0x000fc80007ffe0ff */
/*0c40*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0c50*/ @!P0 BRA 0xe60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*0c70*/ @P0 BRA 0xe30 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0c90*/ @P0 BRA 0xe70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0cb0*/ LOP3.LUT R11, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0b7812 */
/* 0x000fd600078ec0ff */
/*0cc0*/ @!P0 BRA 0xe70 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ FFMA.RZ R9, R14.reuse, R18.reuse, R15.reuse ; /* 0x000000120e097223 */
/* 0x1c0fe2000000c00f */
/*0ce0*/ IADD3 R16, R17.reuse, 0x20, RZ ; /* 0x0000002011107810 */
/* 0x040fe40007ffe0ff */
/*0cf0*/ ISETP.NE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f45270 */
/*0d00*/ LOP3.LUT R13, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090d7812 */
/* 0x000fe200078ec0ff */
/*0d10*/ FFMA.RP R9, R14.reuse, R18.reuse, R15.reuse ; /* 0x000000120e097223 */
/* 0x1c0fe2000000800f */
/*0d20*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f25270 */
/*0d30*/ FFMA.RM R14, R14, R18, R15 ; /* 0x000000120e0e7223 */
/* 0x000fe2000000400f */
/*0d40*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe400078efcff */
/*0d50*/ IADD3 R15, -R17, RZ, RZ ; /* 0x000000ff110f7210 */
/* 0x000fc40007ffe1ff */
/*0d60*/ SHF.L.U32 R16, R13, R16, RZ ; /* 0x000000100d107219 */
/* 0x000fe400000006ff */
/*0d70*/ FSETP.NEU.FTZ.AND P0, PT, R9, R14, PT ; /* 0x0000000e0900720b */
/* 0x000fe40003f1d000 */
/*0d80*/ SEL R14, R15, RZ, P2 ; /* 0x000000ff0f0e7207 */
/* 0x000fe40001000000 */
/*0d90*/ ISETP.NE.AND P1, PT, R16, RZ, P1 ; /* 0x000000ff1000720c */
/* 0x000fe40000f25270 */
/*0da0*/ SHF.R.U32.HI R14, RZ, R14, R13 ; /* 0x0000000eff0e7219 */
/* 0x000fe4000001160d */
/*0db0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0dc0*/ SHF.R.U32.HI R16, RZ, 0x1, R14 ; /* 0x00000001ff107819 */
/* 0x000fe4000001160e */
/*0dd0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0de0*/ LOP3.LUT R9, R9, 0x1, R16, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef810 */
/*0df0*/ LOP3.LUT R9, R9, R14, RZ, 0xc0, !PT ; /* 0x0000000e09097212 */
/* 0x000fc800078ec0ff */
/*0e00*/ IADD3 R16, R16, R9, RZ ; /* 0x0000000910107210 */
/* 0x000fc80007ffe0ff */
/*0e10*/ LOP3.LUT R11, R16, R11, RZ, 0xfc, !PT ; /* 0x0000000b100b7212 */
/* 0x000fe200078efcff */
/*0e20*/ BRA 0xe70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R11, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0b7812 */
/* 0x000fc800078ec0ff */
/*0e40*/ LOP3.LUT R11, R11, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000b0b7812 */
/* 0x000fe200078efcff */
/*0e50*/ BRA 0xe70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD R11, R16, 0x800000, R11 ; /* 0x00800000100b7824 */
/* 0x000fe400078e020b */
/*0e70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e80*/ BRA 0xf10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e90*/ LOP3.LUT R11, R14, 0x80000000, R11, 0x48, !PT ; /* 0x800000000e0b7812 */
/* 0x000fc800078e480b */
/*0ea0*/ LOP3.LUT R11, R11, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000b0b7812 */
/* 0x000fe200078efcff */
/*0eb0*/ BRA 0xf10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ LOP3.LUT R11, R14, 0x80000000, R11, 0x48, !PT ; /* 0x800000000e0b7812 */
/* 0x000fe200078e480b */
/*0ed0*/ BRA 0xf10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ MUFU.RSQ R11, -QNAN ; /* 0xffc00000000b7908 */
/* 0x000e220000001400 */
/*0ef0*/ BRA 0xf10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f00*/ FADD.FTZ R11, R11, R7 ; /* 0x000000070b0b7221 */
/* 0x000fe40000010000 */
/*0f10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f20*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x001fe20000000f00 */
/*0f30*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fcc00000001ff */
/*0f40*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0b00a007950 */
/* 0x000fea0003c3ffff */
/*0f50*/ BRA 0xf50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.globl _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 8
.type _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@function
_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s5, s[0:1], 0x54
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x40
s_load_b32 s3, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[6:7], 0x0
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_cvt_f32_i32_e32 v0, s4
v_cvt_f32_i32_e32 v3, s2
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
v_div_scale_f32 v4, null, v0, v0, 2.0
v_div_scale_f32 v5, null, v3, v3, 2.0
v_div_scale_f32 v10, vcc_lo, 2.0, v0, 2.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
v_div_scale_f32 v8, s2, 2.0, v3, 2.0
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v4, v9, v10
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v9, v10
v_div_fmas_f32 v4, v4, v6, v9
v_cvt_f32_i32_e32 v6, v2
v_mul_f32_e32 v11, v8, v7
s_mov_b32 vcc_lo, s2
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[6:7], 0x0
s_load_b64 s[6:7], s[8:9], 0x0
s_load_b64 s[8:9], s[10:11], 0x0
v_div_fixup_f32 v0, v4, v0, 2.0
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v7, s8, s2
v_div_fixup_f32 v3, v5, v3, 2.0
v_cvt_f32_i32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0.5, v3
v_fma_f32 v0, v0, v5, v4
v_fmac_f32_e32 v4, v3, v6
v_sub_f32_e64 v5, s9, s3
v_sub_f32_e64 v6, s6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v0, -1.0, v0
v_add_f32_e32 v3, -1.0, v4
v_sub_f32_e64 v4, s7, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e64 v3, -v3, s3
v_mul_f32_e32 v8, v4, v5
v_subrev_f32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v10, v4, v4 :: v_dual_mul_f32 v9, v3, v5
v_dual_mul_f32 v3, v3, v4 :: v_dual_fmac_f32 v8, v6, v7
v_mul_f32_e32 v4, v5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v10, v6, v6 :: v_dual_fmac_f32 v9, v0, v7
v_fmac_f32_e32 v3, v0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v0, v8, v8
v_dual_fmac_f32 v4, v7, v7 :: v_dual_mul_f32 v5, v8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v3, v8
v_fma_f32 v7, v10, v4, -v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, v3, v4, -v5
v_fma_f32 v3, v10, v9, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v7, v7, v0
v_div_scale_f32 v5, null, v7, v7, v3
v_div_scale_f32 v11, vcc_lo, v0, v7, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v8, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v4, v6, 1.0
v_fma_f32 v10, -v5, v8, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v9, v6
v_fmac_f32_e32 v8, v10, v8
v_div_scale_f32 v9, s2, v3, v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v11, v6
v_mul_f32_e32 v12, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v4, v10, v11
v_fma_f32 v14, -v5, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v13, v6
v_fmac_f32_e32 v12, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v10, v11
v_fma_f32 v5, -v5, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v10
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v5, v5, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v4, v7, v0
v_div_fixup_f32 v4, v5, v7, v3
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v3, 1.0, v0
v_cmp_lt_f32_e32 vcc_lo, 0, v0
v_cmp_lt_f32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v3
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[10:11], 0x0
s_load_b32 s5, s[8:9], 0x0
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v5, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s5, v0
v_fmac_f32_e32 v5, s6, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x30
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, .Lfunc_end0-_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001270e4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17calculatePositioniiff
.type _Z17calculatePositioniiff, @function
_Z17calculatePositioniiff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z17calculatePositioniiff, .-_Z17calculatePositioniiff
.globl _Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_
.type _Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_, @function
_Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_:
.LFB2085:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_, .-_Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_
.globl _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_
.type _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_, @function
_Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_, .-_Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.section .rodata.str1.8
.align 8
.LC3:
.string "barycentricCuda launch failed: %s\n"
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching barycentricCuda!\n"
.text
.globl _Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2
.type _Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2, @function
_Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, (%rsp)
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq 272(%rsp), %r15
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl 280(%rsp), %r13d
movl 284(%rsp), %r14d
movl $1, 112(%rsp)
movl %r13d, %eax
shrl $4, %eax
addl $1, %eax
movl %eax, 116(%rsp)
movl %r14d, %eax
shrl $4, %eax
addl $1, %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L37
leaq 40(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
movl $1, %ecx
movl $12, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
leaq 48(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movl $1, %ecx
movl $12, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
leaq 56(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L42
movl $1, %ecx
movl $12, %edx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
leaq 64(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L45
leaq 72(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L46
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
leaq 80(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
leaq 88(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L50
leaq 280(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L51
leaq 96(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
leaq 284(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
movslq 284(%rsp), %rdx
movslq 280(%rsp), %rax
salq $2, %rax
movq %rax, 128(%rsp)
movq %rdx, 136(%rsp)
leaq 160(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 304
movdqa 160(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $1, 16(%rsp)
call cudaMalloc3D@PLT
movl $16, 136(%rsp)
movl $16, 140(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 272
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L32:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
movl %r13d, %edx
imull %r14d, %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq 160(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L15
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L37:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 160(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl %ebx, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L39:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L40:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L41:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L42:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L43:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L44:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L45:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L46:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L47:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L48:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L49:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L50:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L51:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L52:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L53:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L54:
subq $8, %rsp
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 184(%rsp)
.cfi_def_cfa_offset 304
movq 112(%rsp), %r9
movq 104(%rsp), %r8
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z59__device_stub__Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_PK6float3S1_S1_PKfS3_S3_PfPiS5_
addq $32, %rsp
.cfi_def_cfa_offset 272
jmp .L32
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L56:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2, .-_Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2
.section .rodata.str1.1
.LC5:
.string "\n\n\nBarycentric:\n"
.LC11:
.string "barycentricCuda failed!"
.LC12:
.string "{\n"
.LC13:
.string " {"
.LC14:
.string "%.1f|"
.LC15:
.string "}\n"
.LC16:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0x00000000, 20(%rsp)
movss .LC7(%rip), %xmm0
movss %xmm0, 24(%rsp)
movl $0x00000000, 28(%rsp)
movss %xmm0, 32(%rsp)
movss .LC8(%rip), %xmm1
movss %xmm1, 36(%rsp)
movl $0x00000000, 40(%rsp)
movss %xmm1, 44(%rsp)
movss %xmm1, 48(%rsp)
movl $0x00000000, 52(%rsp)
movl $0x40400000, 8(%rsp)
movl $0x40000000, 12(%rsp)
movss %xmm0, 16(%rsp)
movl $20000, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rcx
leaq 44(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq 20(%rsp), %rdi
pushq $50
.cfi_def_cfa_offset 136
movl $50, 4(%rsp)
pushq %rax
.cfi_def_cfa_offset 144
leaq 32(%rsp), %r9
leaq 28(%rsp), %r8
call _Z15barycentricCudaPK6float3S1_S1_PKfS3_S3_Pf4int2
addq $16, %rsp
.cfi_def_cfa_offset 128
testl %eax, %eax
jne .L68
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 200(%r13), %rbp
addq $10200, %r13
leaq .LC13(%rip), %r15
leaq .LC14(%rip), %r12
leaq .LC15(%rip), %r14
.L62:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -200(%rbp), %rbx
.L61:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L61
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $200, %rbp
cmpq %r13, %rbp
jne .L62
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L69
.L58:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L70
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L58
.L69:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L58
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z10baryKernelPK6float3S1_S1_PKfS3_S3_PfPiS5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long -1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_ # -- Begin function _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 4, 0x90
.type _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@function
_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_: # @_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, .Lfunc_end0-_Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.zero 4
.zero 4
.LCPI1_1:
.long 0x3f800000 # float 1
.long 0xbf800000 # float -1
.zero 4
.zero 4
.LCPI1_2:
.long 0xbf800000 # float -1
.long 0xbf800000 # float -1
.zero 4
.zero 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp)
movl $0, 56(%rsp)
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%rsp)
movl $0, 40(%rsp)
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp)
movl $0, 24(%rsp)
movl $1077936128, 12(%rsp) # imm = 0x40400000
movl $1073741824, 8(%rsp) # imm = 0x40000000
movl $1065353216, 4(%rsp) # imm = 0x3F800000
movl $20000, %edi # imm = 0x4E20
callq malloc
movq %rax, %rbx
movabsq $214748364850, %rax # imm = 0x3200000032
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
leaq 8(%rsp), %r8
leaq 4(%rsp), %r9
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
callq _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
addq $16, %rsp
.cfi_adjust_cfa_offset -16
testl %eax, %eax
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq $50, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
incq %r14
addq $200, %rbx
cmpq $50, %r14
jne .LBB1_3
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_7
.LBB1_9:
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $23, %esi
jmp .LBB1_8
.LBB1_7:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $22, %esi
.LBB1_8:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_9
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE # -- Begin function _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.p2align 4, 0x90
.type _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE,@function
_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE: # @_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 408(%rsp), %eax
movl %eax, 92(%rsp) # 4-byte Spill
movl 412(%rsp), %eax
movl %eax, 88(%rsp) # 4-byte Spill
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 80(%rsp)
movq $0, 72(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_29
# %bb.1:
leaq 64(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.2:
movq 64(%rsp), %rdi
movl $12, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.3:
leaq 56(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.4:
movq 56(%rsp), %rdi
movl $12, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.5:
leaq 48(%rsp), %rdi
movl $12, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.6:
movq 48(%rsp), %rdi
movl $12, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.7:
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.8:
movq 40(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.9:
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.10:
movq 32(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.11:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.12:
movq 24(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.13:
leaq 80(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.14:
movq 80(%rsp), %rdi
leaq 408(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.15:
leaq 72(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
# %bb.16:
leaq 412(%rsp), %rsi
movq 72(%rsp), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_24
# %bb.17:
movl 92(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
shrl $4, %eax
movl 88(%rsp), %r14d # 4-byte Reload
movl %r14d, %ecx
shrl $4, %ecx
incl %ecx
shlq $32, %rcx
leaq (%rax,%rcx), %rbx
incq %rbx
movslq 408(%rsp), %rax
shlq $2, %rax
movslq 412(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 224(%rsp)
movq $1, 232(%rsp)
movups 216(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $1, 16(%rsp)
leaq 312(%rsp), %rdi
callq hipMalloc3D
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
movq 24(%rsp), %r8
movq 312(%rsp), %r9
movq 80(%rsp), %r10
movq 72(%rsp), %r11
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movq %rsi, 184(%rsp)
movq %rdi, 176(%rsp)
movq %r8, 168(%rsp)
movq %r9, 160(%rsp)
movq %r10, 152(%rsp)
movq %r11, 144(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rax
movq 96(%rsp), %rdi
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 240(%rsp), %r9
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %edi
callq hipLaunchKernel
.LBB2_19:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_30
# %bb.20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_31
# %bb.21:
imull %r14d, %ebp
movq 400(%rsp), %rdi
shll $2, %ebp
movq 312(%rsp), %rsi
movslq %ebp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_28
# %bb.22:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_27
.LBB2_23:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
jmp .LBB2_25
.LBB2_24:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
.LBB2_25:
movl $17, %esi
.LBB2_26:
movl $1, %edx
.LBB2_27:
callq fwrite@PLT
.LBB2_28:
movq 312(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_29:
.cfi_def_cfa_offset 400
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $63, %esi
jmp .LBB2_26
.LBB2_30:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_28
.LBB2_31:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_28
.Lfunc_end2:
.size _Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE, .Lfunc_end2-_Z15barycentricCudaPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfS_IiLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_,@object # @_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.section .rodata,"a",@progbits
.globl _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.p2align 3, 0x0
_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_:
.quad _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.size _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "barycentricCuda failed!"
.size .L.str.1, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " {"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.1f|"
.size .L.str.4, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceReset failed!"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.7, 64
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc failed!"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy failed!"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "barycentricCuda launch failed: %s\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching barycentricCuda!\n"
.size .L.str.11, 78
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n\nBarycentric:"
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "{"
.size .Lstr.1, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "}"
.size .Lstr.3, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10baryKernelPK15HIP_vector_typeIfLj3EES2_S2_PKfS4_S4_PfPiS6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
cudaThreadSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
} | code for sm_80
Function : _Z7sumadorPiS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R7, R0, c[0x0][0x0], RZ ; /* 0x0000000000077a24 */
/* 0x001fc800078e02ff */
/*0040*/ IMAD.IADD R4, R7, 0x1, R2 ; /* 0x0000000107047824 */
/* 0x002fc800078e0202 */
/*0050*/ I2F R3, R4 ; /* 0x0000000400037306 */
/* 0x000e240000201400 */
/*0060*/ FSETP.GT.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0b */
/* 0x001fda0003f04000 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x0000a2000c1e1900 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x34000000 ; /* 0x34000000ff087424 */
/* 0x000fe200078e00ff */
/*00e0*/ I2F.U32 R7, R7 ; /* 0x0000000700077306 */
/* 0x000e620000201000 */
/*00f0*/ FFMA R3, RZ, -RZ, RZ ; /* 0x800000ffff037223 */
/* 0x000fe200000000ff */
/*0100*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0110*/ FFMA R8, R8, 8388608, RZ ; /* 0x4b00000008087823 */
/* 0x000fe400000000ff */
/*0120*/ FMUL R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000400000 */
/*0130*/ FFMA R11, RZ, 1.4426950216293334961, R8 ; /* 0x3fb8aa3bff0b7823 */
/* 0x000fc40000000008 */
/*0140*/ FFMA R6, RZ, R6, 0.0032181653659790754318 ; /* 0x3b52e7dbff067423 */
/* 0x000fe40000000006 */
/*0150*/ FADD R8, R8, -R11 ; /* 0x8000000b08087221 */
/* 0x000fe40000000000 */
/*0160*/ FFMA R6, RZ, R6, 0.018033718690276145935 ; /* 0x3c93bb73ff067423 */
/* 0x000fe40000000006 */
/*0170*/ FFMA R8, RZ, 1.4426950216293334961, R8 ; /* 0x3fb8aa3bff087823 */
/* 0x000fe40000000008 */
/*0180*/ FFMA R6, RZ, R6, 0.12022458761930465698 ; /* 0x3df6384fff067423 */
/* 0x000fe40000000006 */
/*0190*/ FFMA R8, R3, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b03087823 */
/* 0x000fc40000000008 */
/*01a0*/ FMUL R6, RZ, R6 ; /* 0x00000006ff067220 */
/* 0x000fe40000400000 */
/*01b0*/ FFMA R8, RZ, 1.9251366722983220825e-08, R8 ; /* 0x32a55e34ff087823 */
/* 0x000fe40000000008 */
/*01c0*/ FMUL R4, R6, 3 ; /* 0x4040000006047820 */
/* 0x001fc80000400000 */
/*01d0*/ FFMA R3, R3, R4, R8 ; /* 0x0000000403037223 */
/* 0x000fc80000000008 */
/*01e0*/ FFMA R6, RZ, R6, R3 ; /* 0x00000006ff067223 */
/* 0x000fe40000000003 */
/*01f0*/ I2F.U32 R3, R2 ; /* 0x0000000200037306 */
/* 0x0000e40000201000 */
/*0200*/ FADD R4, R11, R6 ; /* 0x000000060b047221 */
/* 0x000fc80000000000 */
/*0210*/ FADD R5, -R11, R4 ; /* 0x000000040b057221 */
/* 0x000fc80000000100 */
/*0220*/ FADD R5, R6, -R5 ; /* 0x8000000506057221 */
/* 0x000fe40000000000 */
/*0230*/ FADD R6, -R7, c[0x0][0x170] ; /* 0x00005c0007067621 */
/* 0x002fe20000000100 */
/*0240*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x0041e80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x008fec0000010000 */
/*0260*/ I2F R7, UR5 ; /* 0x0000000500077d06 */
/* 0x000e620008201400 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff087424 */
/* 0x000fe400078e00ff */
/*0280*/ FADD R15, R7, -1 ; /* 0xbf800000070f7421 */
/* 0x002fca0000000000 */
/*0290*/ FSETP.NEU.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x000fda0003f0d000 */
/*02a0*/ @!P0 BRA 0x440 ; /* 0x0000019000008947 */
/* 0x001fea0003800000 */
/*02b0*/ FMUL R9, R4.reuse, R15.reuse ; /* 0x0000000f04097220 */
/* 0x0c1fe20000400000 */
/*02c0*/ HFMA2.MMA R13, -RZ, RZ, 0.64013671875, -15.109375 ; /* 0x391fcb8eff0d7435 */
/* 0x000fe200000001ff */
/*02d0*/ FSETP.GTU.AND P2, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fe40003f4c200 */
/*02e0*/ FRND R8, R9 ; /* 0x0000000900087307 */
/* 0x000e220000201000 */
/*02f0*/ FFMA R10, R4, R15, -R9 ; /* 0x0000000f040a7223 */
/* 0x000fe20000000809 */
/*0300*/ FSETP.GT.AND P0, PT, |R9|, 152, PT ; /* 0x431800000900780b */
/* 0x000fc60003f04200 */
/*0310*/ FFMA R11, R5, R15, R10 ; /* 0x0000000f050b7223 */
/* 0x000fe4000000000a */
/*0320*/ FADD R10, R9, -R8 ; /* 0x80000008090a7221 */
/* 0x001fe20000000000 */
/*0330*/ FSETP.GT.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fc60003f24000 */
/*0340*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x000fe20000000000 */
/*0350*/ SEL R8, RZ, 0x83000000, P1 ; /* 0x83000000ff087807 */
/* 0x000fe40000800000 */
/*0360*/ FSETP.GEU.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe20003f2e000 */
/*0370*/ FFMA R11, R10, R13, 0.0013391353422775864601 ; /* 0x3aaf85ed0a0b7423 */
/* 0x000fe2000000000d */
/*0380*/ IADD3 R12, R8, 0x7f000000, RZ ; /* 0x7f000000080c7810 */
/* 0x000fc60007ffe0ff */
/*0390*/ FFMA R13, R10.reuse, R11, 0.0096188392490148544312 ; /* 0x3c1d98560a0d7423 */
/* 0x040fe4000000000b */
/*03a0*/ F2I.NTZ R11, R9 ; /* 0x00000009000b7305 */
/* 0x000e240000203100 */
/*03b0*/ FFMA R13, R10, R13, 0.055503588169813156128 ; /* 0x3d6357bb0a0d7423 */
/* 0x000fc8000000000d */
/*03c0*/ FFMA R13, R10, R13, 0.24022644758224487305 ; /* 0x3e75fdec0a0d7423 */
/* 0x000fc8000000000d */
/*03d0*/ FFMA R13, R10, R13, 0.69314718246459960938 ; /* 0x3f3172180a0d7423 */
/* 0x000fc8000000000d */
/*03e0*/ FFMA R13, R10, R13, 1 ; /* 0x3f8000000a0d7423 */
/* 0x000fe4000000000d */
/*03f0*/ IMAD R11, R11, 0x800000, -R8 ; /* 0x008000000b0b7824 */
/* 0x001fe200078e0a08 */
/*0400*/ FSEL R8, RZ, +INF , !P1 ; /* 0x7f800000ff087808 */
/* 0x000fe20004800000 */
/*0410*/ FMUL R12, R12, R13 ; /* 0x0000000d0c0c7220 */
/* 0x000fc80000400000 */
/*0420*/ @!P0 FMUL R8, R11, R12 ; /* 0x0000000c0b088220 */
/* 0x000fe40000400000 */
/*0430*/ @P2 FADD R8, R15, 2 ; /* 0x400000000f082421 */
/* 0x000fca0000000000 */
/*0440*/ FSETP.GEU.AND P0, PT, R8, 512, PT ; /* 0x440000000800780b */
/* 0x000fda0003f0e000 */
/*0450*/ @P0 BRA 0x800 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*0460*/ FMUL R9, R4.reuse, R7.reuse ; /* 0x0000000704097220 */
/* 0x0c1fe20000400000 */
/*0470*/ MOV R13, 0x391fcb8e ; /* 0x391fcb8e000d7802 */
/* 0x000fe20000000f00 */
/*0480*/ UMOV UR4, 0x44000000 ; /* 0x4400000000047882 */
/* 0x000fe20000000000 */
/*0490*/ FSETP.GTU.AND P2, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe20003f4c200 */
/*04a0*/ FRND R12, R9 ; /* 0x00000009000c7307 */
/* 0x000e220000201000 */
/*04b0*/ FFMA R10, R4, R7, -R9 ; /* 0x00000007040a7223 */
/* 0x000fe20000000809 */
/*04c0*/ FSETP.GEU.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f2e000 */
/*04d0*/ FFMA R10, R5, R7, R10 ; /* 0x00000007050a7223 */
/* 0x000fe4000000000a */
/*04e0*/ FADD R11, R9, -R12 ; /* 0x8000000c090b7221 */
/* 0x001fe20000000000 */
/*04f0*/ FSETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fc60003f04000 */
/*0500*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x000fe20000000000 */
/*0510*/ SEL R12, RZ, 0x83000000, P0 ; /* 0x83000000ff0c7807 */
/* 0x000fe40000000000 */
/*0520*/ FSETP.GT.AND P0, PT, |R9|, 152, PT ; /* 0x431800000900780b */
/* 0x000fe20003f04200 */
/*0530*/ FFMA R11, R10, R13, 0.0013391353422775864601 ; /* 0x3aaf85ed0a0b7423 */
/* 0x000fe2000000000d */
/*0540*/ IADD3 R14, R12, 0x7f000000, RZ ; /* 0x7f0000000c0e7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ F2I.NTZ R13, R9 ; /* 0x00000009000d7305 */
/* 0x000e240000203100 */
/*0560*/ FFMA R11, R10, R11, 0.0096188392490148544312 ; /* 0x3c1d98560a0b7423 */
/* 0x000fc8000000000b */
/*0570*/ FFMA R11, R10, R11, 0.055503588169813156128 ; /* 0x3d6357bb0a0b7423 */
/* 0x000fc8000000000b */
/*0580*/ FFMA R11, R10, R11, 0.24022644758224487305 ; /* 0x3e75fdec0a0b7423 */
/* 0x000fc8000000000b */
/*0590*/ FFMA R11, R10.reuse, R11, 0.69314718246459960938 ; /* 0x3f3172180a0b7423 */
/* 0x040fe4000000000b */
/*05a0*/ IMAD R12, R13, 0x800000, -R12 ; /* 0x008000000d0c7824 */
/* 0x001fe200078e0a0c */
/*05b0*/ MOV R13, UR4 ; /* 0x00000004000d7c02 */
/* 0x000fe20008000f00 */
/*05c0*/ FFMA R11, R10, R11, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000000b */
/*05d0*/ FMUL R11, R11, R14 ; /* 0x0000000e0b0b7220 */
/* 0x000fc80000400000 */
/*05e0*/ FMUL R11, R11, R12 ; /* 0x0000000c0b0b7220 */
/* 0x000fe20000400000 */
/*05f0*/ @P0 FSEL R11, RZ, +INF , !P1 ; /* 0x7f800000ff0b0808 */
/* 0x000fe20004800000 */
/*0600*/ @P2 FADD R11, R7, 2 ; /* 0x40000000070b2421 */
/* 0x000fc80000000000 */
/*0610*/ F2I.TRUNC.NTZ R7, R11 ; /* 0x0000000b00077305 */
/* 0x000e30000020f100 */
/*0620*/ I2F R14, R7 ; /* 0x00000007000e7306 */
/* 0x001e300000201400 */
/*0630*/ MUFU.RCP R9, R14 ; /* 0x0000000e00097308 */
/* 0x001e300000001000 */
/*0640*/ FCHK P0, R13, R14 ; /* 0x0000000e0d007302 */
/* 0x000e620000000000 */
/*0650*/ FFMA R10, -R14, R9, 1 ; /* 0x3f8000000e0a7423 */
/* 0x001fc80000000109 */
/*0660*/ FFMA R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000009 */
/*0670*/ FFMA R9, R10, 512, RZ ; /* 0x440000000a097823 */
/* 0x000fc800000000ff */
/*0680*/ FFMA R12, -R14, R9, 512 ; /* 0x440000000e0c7423 */
/* 0x000fc80000000109 */
/*0690*/ FFMA R10, R10, R12, R9 ; /* 0x0000000c0a0a7223 */
/* 0x000fe20000000009 */
/*06a0*/ @!P0 BRA 0x6e0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*06b0*/ MOV R10, 0x6d0 ; /* 0x000006d0000a7802 */
/* 0x000fe40000000f00 */
/*06c0*/ CALL.REL.NOINC 0x870 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*06d0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x001fca00078e0009 */
/*06e0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x000fe20003f04000 */
/*06f0*/ BSSY B0, 0x7d0 ; /* 0x000000d000007945 */
/* 0x000fd80003800000 */
/*0700*/ @!P0 BRA 0x7c0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0710*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*0720*/ IMAD R11, R7, R2, RZ ; /* 0x00000002070b7224 */
/* 0x000fca00078e02ff */
/*0730*/ IADD3 R7, R8, R11, RZ ; /* 0x0000000b08077210 */
/* 0x001fcc0007ffe0ff */
/*0740*/ I2F.U32 R7, R7 ; /* 0x0000000700077306 */
/* 0x000e240000201000 */
/*0750*/ FSETP.GT.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x001fda0003f04000 */
/*0760*/ @P0 IMAD.SHL.U32 R9, R11, 0x4, RZ ; /* 0x000000040b090824 */
/* 0x000fe200078e00ff */
/*0770*/ @P0 LDS R10, [R11.X4] ; /* 0x000000000b0a0984 */
/* 0x000fe80000004800 */
/*0780*/ @P0 LEA R9, R8, R9, 0x2 ; /* 0x0000000908090211 */
/* 0x000fcc00078e10ff */
/*0790*/ @P0 LDS R9, [R9] ; /* 0x0000000009090984 */
/* 0x000e240000000800 */
/*07a0*/ @P0 IADD3 R10, R9, R10, RZ ; /* 0x0000000a090a0210 */
/* 0x001fca0007ffe0ff */
/*07b0*/ @P0 STS [R11.X4], R10 ; /* 0x0000000a0b000388 */
/* 0x0001e40000004800 */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07e0*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fca000fffe03f */
/*07f0*/ BRA 0x260 ; /* 0xfffffa6000007947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0810*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0820*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0003 */
/*0850*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ SHF.R.U32.HI R9, RZ, 0x17, R14 ; /* 0x00000017ff097819 */
/* 0x000fe4000001160e */
/*0880*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x000fe40000000f00 */
/*0890*/ LOP3.LUT R18, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09127812 */
/* 0x000fc800078ec0ff */
/*08a0*/ IADD3 R13, R18, -0x1, RZ ; /* 0xffffffff120d7810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fda0003f04070 */
/*08c0*/ @!P0 MOV R11, RZ ; /* 0x000000ff000b8202 */
/* 0x000fe20000000f00 */
/*08d0*/ @!P0 BRA 0x9e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08e0*/ FSETP.GTU.FTZ.AND P0, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe20003f1c200 */
/*08f0*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x000fd800078e000e */
/*0900*/ @P0 BRA 0xdb0 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0910*/ HFMA2.MMA R11, -RZ, RZ, 4, 0 ; /* 0x44000000ff0b7435 */
/* 0x000fd400000001ff */
/*0920*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R11, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c80b */
/*0930*/ @!P0 BRA 0xd90 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0940*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1d200 */
/*0950*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0970*/ @P0 BRA 0xd70 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c0ff */
/*0990*/ @!P0 BRA 0xd40 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*09b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fd60000000f00 */
/*09c0*/ @!P0 FFMA R12, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f800000090c8823 */
/* 0x000fe200000000ff */
/*09d0*/ @!P0 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b8810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ LEA R9, R18, 0xc0800000, 0x17 ; /* 0xc080000012097811 */
/* 0x000fe200078eb8ff */
/*09f0*/ UMOV UR4, 0x44000000 ; /* 0x4400000000047882 */
/* 0x000fe20000000000 */
/*0a00*/ IADD3 R11, R11, 0x88, -R18 ; /* 0x000000880b0b7810 */
/* 0x000fe20007ffe812 */
/*0a10*/ UIADD3 UR4, UR4, -0x4800000, URZ ; /* 0xfb80000004047890 */
/* 0x000fe4000fffe03f */
/*0a20*/ IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0c7824 */
/* 0x000fc800078e0a09 */
/*0a30*/ MUFU.RCP R9, R12 ; /* 0x0000000c00097308 */
/* 0x000e220000001000 */
/*0a40*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fc80000010100 */
/*0a50*/ FFMA R16, R9, R14, 1 ; /* 0x3f80000009107423 */
/* 0x001fc8000000000e */
/*0a60*/ FFMA R15, R9, R16, R9 ; /* 0x00000010090f7223 */
/* 0x000fc80000000009 */
/*0a70*/ FFMA R9, R15, UR4, RZ ; /* 0x000000040f097c23 */
/* 0x000fc800080000ff */
/*0a80*/ FFMA R16, R14, R9, UR4 ; /* 0x000000040e107e23 */
/* 0x000fc80008000009 */
/*0a90*/ FFMA R16, R15, R16, R9 ; /* 0x000000100f107223 */
/* 0x000fc80000000009 */
/*0aa0*/ FFMA R14, R14, R16, UR4 ; /* 0x000000040e0e7e23 */
/* 0x000fc80008000010 */
/*0ab0*/ FFMA R9, R15, R14, R16 ; /* 0x0000000e0f097223 */
/* 0x000fca0000000010 */
/*0ac0*/ SHF.R.U32.HI R12, RZ, 0x17, R9 ; /* 0x00000017ff0c7819 */
/* 0x000fc80000011609 */
/*0ad0*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fc800078ec0ff */
/*0ae0*/ IADD3 R17, R12, R11, RZ ; /* 0x0000000b0c117210 */
/* 0x000fc80007ffe0ff */
/*0af0*/ IADD3 R12, R17, -0x1, RZ ; /* 0xffffffff110c7810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xdc0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xdc0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R11, R15, R14.reuse, R16.reuse ; /* 0x0000000e0f0b7223 */
/* 0x180fe2000000c010 */
/*0ba0*/ ISETP.NE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f45270 */
/*0bb0*/ FFMA.RM R12, R15, R14.reuse, R16.reuse ; /* 0x0000000e0f0c7223 */
/* 0x180fe20000004010 */
/*0bc0*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0bd0*/ LOP3.LUT R13, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0d7812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R11, R15, R14, R16 ; /* 0x0000000e0f0b7223 */
/* 0x000fe20000008010 */
/*0bf0*/ IADD3 R14, R17, 0x20, RZ ; /* 0x00000020110e7810 */
/* 0x000fe40007ffe0ff */
/*0c00*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe400078efcff */
/*0c10*/ IADD3 R15, -R17, RZ, RZ ; /* 0x000000ff110f7210 */
/* 0x000fc40007ffe1ff */
/*0c20*/ SHF.L.U32 R14, R13, R14, RZ ; /* 0x0000000e0d0e7219 */
/* 0x000fe400000006ff */
/*0c30*/ FSETP.NEU.FTZ.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720b */
/* 0x000fe40003f1d000 */
/*0c40*/ SEL R12, R15, RZ, P2 ; /* 0x000000ff0f0c7207 */
/* 0x000fe40001000000 */
/*0c50*/ ISETP.NE.AND P1, PT, R14, RZ, P1 ; /* 0x000000ff0e00720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R12, RZ, R12, R13 ; /* 0x0000000cff0c7219 */
/* 0x000fe4000001160d */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0c80*/ SHF.R.U32.HI R14, RZ, 0x1, R12 ; /* 0x00000001ff0e7819 */
/* 0x000fe4000001160c */
/*0c90*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R11, R11, 0x1, R14, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef80e */
/*0cb0*/ LOP3.LUT R11, R11, R12, RZ, 0xc0, !PT ; /* 0x0000000c0b0b7212 */
/* 0x000fca00078ec0ff */
/*0cc0*/ IMAD.IADD R14, R14, 0x1, R11 ; /* 0x000000010e0e7824 */
/* 0x000fca00078e020b */
/*0cd0*/ LOP3.LUT R9, R14, R9, RZ, 0xfc, !PT ; /* 0x000000090e097212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xdc0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xdc0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0d20*/ LEA R9, R11, R9, 0x17 ; /* 0x000000090b097211 */
/* 0x000fe200078eb8ff */
/*0d30*/ BRA 0xdc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R9, R12, 0x80000000, R11, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fc800078e480b */
/*0d50*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0d60*/ BRA 0xdc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT R9, R12, 0x80000000, R11, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078e480b */
/*0d80*/ BRA 0xdc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d90*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*0da0*/ BRA 0xdc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0db0*/ FADD.FTZ R9, R9, 512 ; /* 0x4400000009097421 */
/* 0x000fe40000010000 */
/*0dc0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fcc00000001ff */
/*0dd0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff2200a007950 */
/* 0x000fea0003c3ffff */
/*0de0*/ BRA 0xde0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
cudaThreadSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
} | .file "tmpxft_0019d548_00000000-6_sum_test_shared_multi_block_final.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z6printii
.type _Z6printii, @function
_Z6printii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6printii, .-_Z6printii
.globl _Z14init_CPU_arrayPii
.type _Z14init_CPU_arrayPii, @function
_Z14init_CPU_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z14init_CPU_arrayPii, .-_Z14init_CPU_arrayPii
.globl _Z15print_CPU_arrayPii
.type _Z15print_CPU_arrayPii, @function
_Z15print_CPU_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L11:
movl (%rbx), %edi
call _Z6printii
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z15print_CPU_arrayPii, .-_Z15print_CPU_arrayPii
.globl _Z29__device_stub__Z7sumadorPiS_fPiS_f
.type _Z29__device_stub__Z7sumadorPiS_fPiS_f, @function
_Z29__device_stub__Z7sumadorPiS_fPiS_f:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sumadorPiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z7sumadorPiS_fPiS_f, .-_Z29__device_stub__Z7sumadorPiS_fPiS_f
.globl _Z7sumadorPiS_f
.type _Z7sumadorPiS_f, @function
_Z7sumadorPiS_f:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7sumadorPiS_f, .-_Z7sumadorPiS_f
.section .rodata.str1.1
.LC6:
.string "elementos restantes: %d \n"
.LC7:
.string "bloques usados: %d \n\n"
.LC8:
.string "RESULTADO DE LA SUMA:"
.LC9:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $4096000, %edi
call malloc@PLT
movq %rax, arreglo_suma1(%rip)
movl $4096000, %esi
leaq d_arreglo_suma1(%rip), %rdi
call cudaMalloc@PLT
movl $4096000, %edi
call malloc@PLT
movq %rax, arreglo_result(%rip)
movl $4096000, %esi
leaq d_arreglo_suma2(%rip), %rdi
call cudaMalloc@PLT
movl $1024000, %esi
movq arreglo_suma1(%rip), %rdi
call _Z14init_CPU_arrayPii
movl $1, %ecx
movl $4096000, %edx
movq arreglo_suma1(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call cudaMemcpy@PLT
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %ebx
jmp .L26
.L28:
cvttsd2sil %xmm2, %ebp
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaThreadSynchronize@PLT
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rdx
movq %rdx, d_arreglo_suma1(%rip)
movq %rax, d_arreglo_suma2(%rip)
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movq %xmm5, %rbp
movapd %xmm5, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movsd .LC2(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L33
movq %rbp, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm1
movsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L27
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L27:
cvttsd2sil %xmm3, %r12d
addl $1, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm1
movsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm2
movsd .LC10(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC3(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC5(%rip), %xmm3
andpd %xmm3, %xmm2
addsd %xmm2, %xmm1
movsd .LC10(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
jmp .L28
.L32:
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movq d_arreglo_suma2(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
jmp .L29
.L33:
movl $2, %ecx
movl $4096000, %edx
movq d_arreglo_suma1(%rip), %rsi
movq arreglo_result(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %esi
movq arreglo_result(%rip), %rdi
call _Z15print_CPU_arrayPii
movq arreglo_suma1(%rip), %rdi
call free@PLT
movq d_arreglo_suma1(%rip), %rdi
call cudaFree@PLT
movq arreglo_result(%rip), %rdi
call free@PLT
movq d_arreglo_suma2(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7sumadorPiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumadorPiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_arreglo_suma2
.bss
.align 8
.type d_arreglo_suma2, @object
.size d_arreglo_suma2, 8
d_arreglo_suma2:
.zero 8
.globl arreglo_result
.align 8
.type arreglo_result, @object
.size arreglo_result, 8
arreglo_result:
.zero 8
.globl d_arreglo_suma1
.align 8
.type d_arreglo_suma1, @object
.size d_arreglo_suma1, 8
d_arreglo_suma1:
.zero 8
.globl arreglo_suma1
.align 8
.type arreglo_suma1, @object
.size arreglo_suma1, 8
arreglo_suma1:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1082130432
.align 8
.LC2:
.long 0
.long 1093615616
.align 8
.LC3:
.long 0
.long 1127219200
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1072693248
.set .LC10,.LC4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
cudaThreadSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
} | #include "hip/hip_runtime.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
hipMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), hipMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
hipDeviceSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
hipMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), hipMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
hipFree (d_arreglo_suma1);
free(arreglo_result);
hipFree (d_arreglo_suma2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
hipMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), hipMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
hipDeviceSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
hipMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), hipMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
hipFree (d_arreglo_suma1);
free(arreglo_result);
hipFree (d_arreglo_suma2);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sumadorPiS_f
.globl _Z7sumadorPiS_f
.p2align 8
.type _Z7sumadorPiS_f,@function
_Z7sumadorPiS_f:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s15, s3
v_add_nc_u32_e32 v1, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v1
v_cmpx_nlt_f32_e32 s2, v2
s_cbranch_execz .LBB0_9
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s4, s15
s_mov_b32 s5, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_cvt_f32_u32_e32 v2, s3
v_cvt_f32_u32_e32 v1, v0
s_mov_b32 s3, 1
v_sub_f32_e32 v2, s2, v2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, 1
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
.LBB0_4:
v_cvt_f32_i32_e32 v3, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, -1.0, v3
v_cmp_eq_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v6, v5
v_frexp_exp_i32_f32_e32 v5, v5
v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, 0, 1, s2
v_subrev_co_ci_u32_e64 v5, s2, 0, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v6, v6, v7
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, 1.0, v6
v_rcp_f32_e32 v8, v7
v_add_f32_e32 v11, -1.0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_add_f32 v9, -1.0, v6 :: v_dual_sub_f32 v6, v6, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, v9, v8
v_mul_f32_e32 v12, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v10, v7, -v12
v_fmac_f32_e32 v7, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v12, v7
v_dual_sub_f32 v11, v9, v6 :: v_dual_sub_f32 v12, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v12, v7
v_sub_f32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v9, v6
v_add_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v11, v6
v_mul_f32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v10, v6
v_sub_f32_e32 v8, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, v7, v7 :: v_dual_sub_f32 v6, v6, v8
v_fma_f32 v8, v7, v7, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v6, v6
v_fmac_f32_e32 v8, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v9, v8
v_fmaak_f32 v11, s5, v10, 0x3e91f4c4
v_sub_f32_e32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v11, v10, v11, 0x3ecccdef :: v_dual_sub_f32 v8, v8, v9
v_mul_f32_e32 v14, v7, v10
v_mul_f32_e32 v12, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, v10, v7, -v14
v_fma_f32 v9, v10, v11, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v9, v8, v11
v_fmac_f32_e32 v15, v10, v6
v_ldexp_f32 v6, v6, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v11, v12, v9
v_fmac_f32_e32 v15, v8, v7
v_ldexp_f32 v7, v7, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v11, v12 :: v_dual_add_f32 v13, 0x3f2aaaaa, v11
v_dual_sub_f32 v9, v9, v12 :: v_dual_add_f32 v12, 0xbf2aaaaa, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 0x31739010, v9
v_sub_f32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v11
v_add_f32_e32 v8, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v10, v14, v15 :: v_dual_sub_f32 v11, v13, v8
v_dual_mul_f32 v12, v10, v8 :: v_dual_add_f32 v9, v9, v11
v_sub_f32_e32 v13, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v10, v8, -v12
v_sub_f32_e32 v13, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v10, v9
v_fmac_f32_e32 v11, v13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v12, v11
v_sub_f32_e32 v10, v8, v12
v_mul_f32_e32 v12, 0x3f317218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v11, v10
v_add_f32_e32 v9, v7, v8
v_fma_f32 v11, v5, 0x3f317218, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v6, v6, v10 :: v_dual_sub_f32 v7, v9, v7
v_fmac_f32_e32 v11, 0xb102e308, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v8, v7
v_add_f32_e32 v5, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v12, v11 :: v_dual_add_f32 v7, v9, v5
v_sub_f32_e32 v12, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v6, v7 :: v_dual_sub_f32 v9, v7, v9
v_sub_f32_e32 v10, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v13, v8, v10
v_sub_f32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v7, v10 :: v_dual_sub_f32 v6, v6, v13
v_dual_add_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v11, v5
v_add_f32_e32 v6, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v9, v11 :: v_dual_add_f32 v10, v8, v6
v_dual_sub_f32 v9, v9, v7 :: v_dual_sub_f32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v8 :: v_dual_sub_f32 v5, v5, v7
v_sub_f32_e32 v7, v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v5
v_sub_f32_e32 v7, v6, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v8, v4, v6 :: v_dual_sub_f32 v5, v5, v7
v_fma_f32 v6, v4, v6, -v8
v_cmp_class_f32_e64 s2, v8, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v4, v5
v_add_f32_e32 v5, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, v5, v8, s2
v_sub_f32_e32 v5, v5, v8
v_cmp_eq_f32_e64 s2, 0x42b17218, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v6, v5
v_cndmask_b32_e64 v9, 0, 0x37000000, s2
v_cmp_neq_f32_e64 s2, 0x7f800000, |v7|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v7, v9
v_cndmask_b32_e64 v5, 0, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, 0x3fb8aa3b, v10
v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v10
v_add_f32_e32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v12, v10, 0x3fb8aa3b, -v11
v_rndne_f32_e32 v13, v11
v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
v_cvt_i32_f32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v11, v12
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, v6, s2
v_cmp_nlt_f32_e64 s2, 0x42b17218, v10
v_cndmask_b32_e64 v6, 0x7f800000, v6, s2
v_cmp_eq_f32_e64 s2, |v4|, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v6, v5, v6
v_cndmask_b32_e64 v7, 0, |v4|, s2
v_cmp_eq_f32_e64 s2, 0x7f800000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v5, v6, s2
v_cndmask_b32_e64 v6, v7, 1.0, vcc_lo
v_cmp_class_f32_e64 s2, v4, 0x204
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, |v5|, v6, s2
s_mov_b32 s2, -1
v_cmp_gt_f32_e32 vcc_lo, 0x44000000, v4
s_cbranch_vccz .LBB0_3
v_mul_f32_e32 v5, 0x3f317218, v3
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, v3, 0x3f317218, -v5
v_cmp_class_f32_e64 vcc_lo, v5, 0x204
v_fmac_f32_e32 v6, 0xb102e308, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v5, v6
v_cndmask_b32_e32 v7, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
v_sub_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x3fb8aa3b, v9
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
v_sub_f32_e32 v3, v3, v5
v_cvt_i32_f32_e32 v5, v12
v_add_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v6, v3
v_exp_f32_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
v_add_f32_e32 v3, v8, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v3, v5, v3, v5
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e64 v3, |v3|
v_cvt_f32_i32_e32 v5, v3
v_mul_lo_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v6, null, v5, v5, 0x44000000
v_div_scale_f32 v9, vcc_lo, 0x44000000, v5, 0x44000000
v_add_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_div_fixup_f32 v5, v6, v5, 0x44000000
v_cvt_f32_u32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, v5, v1
v_cmp_gt_f32_e64 s2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s2
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v3, 2, v3
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
s_branch .LBB0_2
.LBB0_7:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s5, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sumadorPiS_f
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sumadorPiS_f, .Lfunc_end0-_Z7sumadorPiS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sumadorPiS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sumadorPiS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
#define threads_per_block 512
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[threads_per_block];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid > N)
{
return;
}
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < threads_per_block; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < ((float)threads_per_block/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
// compartida[threadIdx.x * acceso + offset] = 0;
}
__syncthreads();
}
//el primer thread de cada grupo guarda el resultado
if(threadIdx.x == 0)
result[blockIdx.x] = compartida[0];
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 1024000;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
hipMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), hipMemcpyHostToDevice);
// int threads_per_block = 10;
// int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miBloque1D_1(threads_per_block,1);
for(int i=0; pow(threads_per_block, i) < N ; i++)
{
int remaining_elements = ceil((float)N/pow(threads_per_block, i));
int block_count = ceil((float)N/pow(threads_per_block, i+1));
dim3 miGrid1D_1(block_count,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, remaining_elements);
hipDeviceSynchronize();
int* tmp = d_arreglo_suma1;
d_arreglo_suma1 = d_arreglo_suma2;
d_arreglo_suma2 = tmp;
printf("elementos restantes: %d \n", remaining_elements);
printf("bloques usados: %d \n\n", block_count);
}
//##################################################################################
//################################### READ BACK #####################################
hipMemcpy(arreglo_result, d_arreglo_suma1, N * sizeof(int), hipMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_array(arreglo_result, 1);
free(arreglo_suma1);
hipFree (d_arreglo_suma1);
free(arreglo_result);
hipFree (d_arreglo_suma2);
} | .text
.file "sum_test_shared_multi_block_final.hip"
.globl _Z6printii # -- Begin function _Z6printii
.p2align 4, 0x90
.type _Z6printii,@function
_Z6printii: # @_Z6printii
.cfi_startproc
# %bb.0:
movl %edi, %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z6printii, .Lfunc_end0-_Z6printii
.cfi_endproc
# -- End function
.globl _Z14init_CPU_arrayPii # -- Begin function _Z14init_CPU_arrayPii
.p2align 4, 0x90
.type _Z14init_CPU_arrayPii,@function
_Z14init_CPU_arrayPii: # @_Z14init_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_CPU_arrayPii, .Lfunc_end1-_Z14init_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z15print_CPU_arrayPii # -- Begin function _Z15print_CPU_arrayPii
.p2align 4, 0x90
.type _Z15print_CPU_arrayPii,@function
_Z15print_CPU_arrayPii: # @_Z15print_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z15print_CPU_arrayPii, .Lfunc_end2-_Z15print_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sumadorPiS_f # -- Begin function _Z22__device_stub__sumadorPiS_f
.p2align 4, 0x90
.type _Z22__device_stub__sumadorPiS_f,@function
_Z22__device_stub__sumadorPiS_f: # @_Z22__device_stub__sumadorPiS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__sumadorPiS_f, .Lfunc_end3-_Z22__device_stub__sumadorPiS_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412f400000000000 # double 1024000
.LCPI4_1:
.quad 0x4022000000000000 # double 9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, arreglo_suma1(%rip)
movl $d_arreglo_suma1, %edi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, arreglo_result(%rip)
movl $d_arreglo_suma2, %edi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
xorl %eax, %eax
movq arreglo_suma1(%rip), %rsi
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rsi,%rax,4)
incq %rax
cmpq $1024000, %rax # imm = 0xFA000
jne .LBB4_1
# %bb.2: # %_Z14init_CPU_arrayPii.exit
movabsq $4294967296, %r12 # imm = 0x100000000
movq d_arreglo_suma1(%rip), %rdi
movl $1, %r13d
movl $4096000, %edx # imm = 0x3E8000
movl $1, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq exp2@PLT
leaq 512(%r12), %rbx
leaq 80(%rsp), %rbp
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
callq hipDeviceSynchronize
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rcx, d_arreglo_suma1(%rip)
movq %rax, d_arreglo_suma2(%rip)
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq exp2@PLT
incl %r13d
cmpl $4, %r13d
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp2@PLT
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd .LCPI4_1(%rip), %xmm0
callq exp2@PLT
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
movq %r15, %rdi
orq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7sumadorPiS_f, %edi
movq %rbp, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6: # %.lr.ph.i29
movq arreglo_result(%rip), %rdi
movq d_arreglo_suma1(%rip), %rsi
movl $4096000, %edx # imm = 0x3E8000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
callq puts@PLT
movq arreglo_result(%rip), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq arreglo_suma1(%rip), %rdi
callq free
movq d_arreglo_suma1(%rip), %rdi
callq hipFree
movq arreglo_result(%rip), %rdi
callq free
movq d_arreglo_suma2(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumadorPiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type _Z7sumadorPiS_f,@object # @_Z7sumadorPiS_f
.section .rodata,"a",@progbits
.globl _Z7sumadorPiS_f
.p2align 3, 0x0
_Z7sumadorPiS_f:
.quad _Z22__device_stub__sumadorPiS_f
.size _Z7sumadorPiS_f, 8
.type arreglo_suma1,@object # @arreglo_suma1
.bss
.globl arreglo_suma1
.p2align 3, 0x0
arreglo_suma1:
.quad 0
.size arreglo_suma1, 8
.type d_arreglo_suma1,@object # @d_arreglo_suma1
.globl d_arreglo_suma1
.p2align 3, 0x0
d_arreglo_suma1:
.quad 0
.size d_arreglo_suma1, 8
.type arreglo_result,@object # @arreglo_result
.globl arreglo_result
.p2align 3, 0x0
arreglo_result:
.quad 0
.size arreglo_result, 8
.type d_arreglo_suma2,@object # @d_arreglo_suma2
.globl d_arreglo_suma2
.p2align 3, 0x0
d_arreglo_suma2:
.quad 0
.size d_arreglo_suma2, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "elementos restantes: %d \n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "bloques usados: %d \n\n"
.size .L.str.2, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "RESULTADO DE LA SUMA:"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sumadorPiS_f"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumadorPiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumadorPiS_f
.addrsig_sym d_arreglo_suma1
.addrsig_sym d_arreglo_suma2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d548_00000000-6_sum_test_shared_multi_block_final.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z6printii
.type _Z6printii, @function
_Z6printii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6printii, .-_Z6printii
.globl _Z14init_CPU_arrayPii
.type _Z14init_CPU_arrayPii, @function
_Z14init_CPU_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z14init_CPU_arrayPii, .-_Z14init_CPU_arrayPii
.globl _Z15print_CPU_arrayPii
.type _Z15print_CPU_arrayPii, @function
_Z15print_CPU_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L11:
movl (%rbx), %edi
call _Z6printii
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z15print_CPU_arrayPii, .-_Z15print_CPU_arrayPii
.globl _Z29__device_stub__Z7sumadorPiS_fPiS_f
.type _Z29__device_stub__Z7sumadorPiS_fPiS_f, @function
_Z29__device_stub__Z7sumadorPiS_fPiS_f:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sumadorPiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z7sumadorPiS_fPiS_f, .-_Z29__device_stub__Z7sumadorPiS_fPiS_f
.globl _Z7sumadorPiS_f
.type _Z7sumadorPiS_f, @function
_Z7sumadorPiS_f:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7sumadorPiS_f, .-_Z7sumadorPiS_f
.section .rodata.str1.1
.LC6:
.string "elementos restantes: %d \n"
.LC7:
.string "bloques usados: %d \n\n"
.LC8:
.string "RESULTADO DE LA SUMA:"
.LC9:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $4096000, %edi
call malloc@PLT
movq %rax, arreglo_suma1(%rip)
movl $4096000, %esi
leaq d_arreglo_suma1(%rip), %rdi
call cudaMalloc@PLT
movl $4096000, %edi
call malloc@PLT
movq %rax, arreglo_result(%rip)
movl $4096000, %esi
leaq d_arreglo_suma2(%rip), %rdi
call cudaMalloc@PLT
movl $1024000, %esi
movq arreglo_suma1(%rip), %rdi
call _Z14init_CPU_arrayPii
movl $1, %ecx
movl $4096000, %edx
movq arreglo_suma1(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call cudaMemcpy@PLT
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %ebx
jmp .L26
.L28:
cvttsd2sil %xmm2, %ebp
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaThreadSynchronize@PLT
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rdx
movq %rdx, d_arreglo_suma1(%rip)
movq %rax, d_arreglo_suma2(%rip)
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movq %xmm5, %rbp
movapd %xmm5, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movsd .LC2(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L33
movq %rbp, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm1
movsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L27
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L27:
cvttsd2sil %xmm3, %r12d
addl $1, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm1
movsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm2
movsd .LC10(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC3(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC5(%rip), %xmm3
andpd %xmm3, %xmm2
addsd %xmm2, %xmm1
movsd .LC10(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
jmp .L28
.L32:
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movq d_arreglo_suma2(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
jmp .L29
.L33:
movl $2, %ecx
movl $4096000, %edx
movq d_arreglo_suma1(%rip), %rsi
movq arreglo_result(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %esi
movq arreglo_result(%rip), %rdi
call _Z15print_CPU_arrayPii
movq arreglo_suma1(%rip), %rdi
call free@PLT
movq d_arreglo_suma1(%rip), %rdi
call cudaFree@PLT
movq arreglo_result(%rip), %rdi
call free@PLT
movq d_arreglo_suma2(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7sumadorPiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumadorPiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_arreglo_suma2
.bss
.align 8
.type d_arreglo_suma2, @object
.size d_arreglo_suma2, 8
d_arreglo_suma2:
.zero 8
.globl arreglo_result
.align 8
.type arreglo_result, @object
.size arreglo_result, 8
arreglo_result:
.zero 8
.globl d_arreglo_suma1
.align 8
.type d_arreglo_suma1, @object
.size d_arreglo_suma1, 8
d_arreglo_suma1:
.zero 8
.globl arreglo_suma1
.align 8
.type arreglo_suma1, @object
.size arreglo_suma1, 8
arreglo_suma1:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1082130432
.align 8
.LC2:
.long 0
.long 1093615616
.align 8
.LC3:
.long 0
.long 1127219200
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1072693248
.set .LC10,.LC4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_test_shared_multi_block_final.hip"
.globl _Z6printii # -- Begin function _Z6printii
.p2align 4, 0x90
.type _Z6printii,@function
_Z6printii: # @_Z6printii
.cfi_startproc
# %bb.0:
movl %edi, %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z6printii, .Lfunc_end0-_Z6printii
.cfi_endproc
# -- End function
.globl _Z14init_CPU_arrayPii # -- Begin function _Z14init_CPU_arrayPii
.p2align 4, 0x90
.type _Z14init_CPU_arrayPii,@function
_Z14init_CPU_arrayPii: # @_Z14init_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_CPU_arrayPii, .Lfunc_end1-_Z14init_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z15print_CPU_arrayPii # -- Begin function _Z15print_CPU_arrayPii
.p2align 4, 0x90
.type _Z15print_CPU_arrayPii,@function
_Z15print_CPU_arrayPii: # @_Z15print_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z15print_CPU_arrayPii, .Lfunc_end2-_Z15print_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sumadorPiS_f # -- Begin function _Z22__device_stub__sumadorPiS_f
.p2align 4, 0x90
.type _Z22__device_stub__sumadorPiS_f,@function
_Z22__device_stub__sumadorPiS_f: # @_Z22__device_stub__sumadorPiS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__sumadorPiS_f, .Lfunc_end3-_Z22__device_stub__sumadorPiS_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412f400000000000 # double 1024000
.LCPI4_1:
.quad 0x4022000000000000 # double 9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, arreglo_suma1(%rip)
movl $d_arreglo_suma1, %edi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, arreglo_result(%rip)
movl $d_arreglo_suma2, %edi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
xorl %eax, %eax
movq arreglo_suma1(%rip), %rsi
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rsi,%rax,4)
incq %rax
cmpq $1024000, %rax # imm = 0xFA000
jne .LBB4_1
# %bb.2: # %_Z14init_CPU_arrayPii.exit
movabsq $4294967296, %r12 # imm = 0x100000000
movq d_arreglo_suma1(%rip), %rdi
movl $1, %r13d
movl $4096000, %edx # imm = 0x3E8000
movl $1, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq exp2@PLT
leaq 512(%r12), %rbx
leaq 80(%rsp), %rbp
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
callq hipDeviceSynchronize
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rcx, d_arreglo_suma1(%rip)
movq %rax, d_arreglo_suma2(%rip)
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq exp2@PLT
incl %r13d
cmpl $4, %r13d
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp2@PLT
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd .LCPI4_1(%rip), %xmm0
callq exp2@PLT
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
movq %r15, %rdi
orq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7sumadorPiS_f, %edi
movq %rbp, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6: # %.lr.ph.i29
movq arreglo_result(%rip), %rdi
movq d_arreglo_suma1(%rip), %rsi
movl $4096000, %edx # imm = 0x3E8000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
callq puts@PLT
movq arreglo_result(%rip), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq arreglo_suma1(%rip), %rdi
callq free
movq d_arreglo_suma1(%rip), %rdi
callq hipFree
movq arreglo_result(%rip), %rdi
callq free
movq d_arreglo_suma2(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumadorPiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type _Z7sumadorPiS_f,@object # @_Z7sumadorPiS_f
.section .rodata,"a",@progbits
.globl _Z7sumadorPiS_f
.p2align 3, 0x0
_Z7sumadorPiS_f:
.quad _Z22__device_stub__sumadorPiS_f
.size _Z7sumadorPiS_f, 8
.type arreglo_suma1,@object # @arreglo_suma1
.bss
.globl arreglo_suma1
.p2align 3, 0x0
arreglo_suma1:
.quad 0
.size arreglo_suma1, 8
.type d_arreglo_suma1,@object # @d_arreglo_suma1
.globl d_arreglo_suma1
.p2align 3, 0x0
d_arreglo_suma1:
.quad 0
.size d_arreglo_suma1, 8
.type arreglo_result,@object # @arreglo_result
.globl arreglo_result
.p2align 3, 0x0
arreglo_result:
.quad 0
.size arreglo_result, 8
.type d_arreglo_suma2,@object # @d_arreglo_suma2
.globl d_arreglo_suma2
.p2align 3, 0x0
d_arreglo_suma2:
.quad 0
.size d_arreglo_suma2, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "elementos restantes: %d \n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "bloques usados: %d \n\n"
.size .L.str.2, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "RESULTADO DE LA SUMA:"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sumadorPiS_f"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumadorPiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumadorPiS_f
.addrsig_sym d_arreglo_suma1
.addrsig_sym d_arreglo_suma2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
cudaMalloc((void **)&d_a,int_size);
cudaMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
cudaStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (cudaStream_t*) new cudaStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
cudaStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
cudaMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
cudaDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
cudaStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); cudaFree(d_a); cudaFree(d_b);
} | code for sm_80
Function : _Z7add_vecPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
cudaMalloc((void **)&d_a,int_size);
cudaMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
cudaStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (cudaStream_t*) new cudaStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
cudaStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
cudaMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
cudaDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
cudaStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); cudaFree(d_a); cudaFree(d_b);
} | .file "tmpxft_000db415_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
.type _Z30__device_stub__Z7add_vecPiS_iiPiS_ii, @function
_Z30__device_stub__Z7add_vecPiS_iiPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_vecPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z7add_vecPiS_iiPiS_ii, .-_Z30__device_stub__Z7add_vecPiS_iiPiS_ii
.globl _Z7add_vecPiS_ii
.type _Z7add_vecPiS_ii, @function
_Z7add_vecPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7add_vecPiS_ii, .-_Z7add_vecPiS_ii
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r14
leaq 1073741824(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1073741824, %edi
call malloc@PLT
movq %rax, (%rsp)
leaq 1073741824(%rax), %rdx
.L13:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $128, %edi
call _Znam@PLT
movq %rax, %r13
movq %rax, %r12
leaq 128(%rax), %r15
movq %rax, %rbx
.L14:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r15, %rbx
jne .L14
movq %r13, %rbp
movl $0, %eax
movl $0, %ebx
movq %r13, 8(%rsp)
movq %r12, 16(%rsp)
movl %eax, %r13d
movq %r15, 24(%rsp)
jmp .L16
.L15:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq (%r15), %r8
movl $2, %ecx
movl $67108864, %edx
movq %r12, %rdi
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $67108864, %rbx
addl $16777216, %r13d
cmpq $1073741824, %rbx
je .L27
.L16:
movq %rbp, %r15
leaq (%r14,%rbx), %r12
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
call cudaMemcpyAsync@PLT
movq (%rsp), %rax
leaq (%rax,%rbx), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $67108864, %edx
call cudaMemcpyAsync@PLT
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $268435456, %ecx
movl %r13d, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
jmp .L15
.L27:
movq 8(%rsp), %r13
movq 16(%rsp), %r12
movq 24(%rsp), %r15
movq %r13, %rbp
movl $0, %ebx
.L17:
movq %rbx, %rsi
addq 32(%rsp), %rsi
leaq (%r14,%rbx), %rdi
movq 0(%rbp), %r8
movl $2, %ecx
movl $67108864, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $67108864, %rbx
cmpq $1073741824, %rbx
jne .L17
call cudaDeviceSynchronize@PLT
.L18:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %r15, %r12
jne .L18
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7add_vecPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_vecPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
cudaMalloc((void **)&d_a,int_size);
cudaMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
cudaStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (cudaStream_t*) new cudaStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
cudaStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
cudaMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,cudaMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
cudaMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,cudaMemcpyDeviceToHost,i_stream[i]);
}
cudaDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
cudaStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); cudaFree(d_a); cudaFree(d_b);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
hipMalloc((void **)&d_a,int_size);
hipMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
hipStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (hipStream_t*) new hipStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
hipStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
hipMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
hipDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
hipStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); hipFree(d_a); hipFree(d_b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
hipMalloc((void **)&d_a,int_size);
hipMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
hipStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (hipStream_t*) new hipStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
hipStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
hipMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
hipDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
hipStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); hipFree(d_a); hipFree(d_b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_vecPiS_ii
.globl _Z7add_vecPiS_ii
.p2align 8
.type _Z7add_vecPiS_ii,@function
_Z7add_vecPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s15, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_vecPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_vecPiS_ii, .Lfunc_end0-_Z7add_vecPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_vecPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_vecPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
__global__
void add_vec(int *a,int *b, int offset,int N)
{
int i = offset + threadIdx.x + blockIdx.x*blockDim.x;
if(i < N){
a[i] = a[i] + b[i];
}
}
template <typename T>
void fill_arr(T *data,T val,int N){
for(int i=0;i<N;++i){
data[i] = val;
}
}
int main(){
int N = 1<<28;
int *a,*b,*d_a,*d_b;
int int_size = N * sizeof(int);
//allocate host memory
a = (int *)malloc(int_size);
fill_arr(a,1,N);
b = (int *)malloc(int_size);
fill_arr(b,2,N);
hipMalloc((void **)&d_a,int_size);
hipMalloc((void **)&d_b,int_size);
int threads = 256;
int blocks = 16;
hipStream_t *i_stream;
int num_stream = 16;
int StreamSize = N/num_stream;
size_t StreamBytes = StreamSize * sizeof(float);
i_stream = (hipStream_t*) new hipStream_t[num_stream];
for (int i = 0; i < num_stream; i++){
hipStreamCreate(&i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&d_a[offset],&a[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
hipMemcpyAsync(&d_b[offset],&b[offset],StreamBytes,hipMemcpyHostToDevice,i_stream[i]);
add_vec<<< threads, blocks, 0, i_stream[i] >>>(d_a,d_b,offset,N);
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
for (int i = 0; i < num_stream; i++){
int offset = i * StreamSize;
hipMemcpyAsync(&a[offset],&d_a[offset],StreamBytes,hipMemcpyDeviceToHost,i_stream[i]);
}
hipDeviceSynchronize();
for (int i = 0; i < num_stream; i++){
hipStreamDestroy(i_stream[i]);
}
delete [] i_stream;
free(a); free(b); hipFree(d_a); hipFree(d_b);
} | .text
.file "vec_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__add_vecPiS_ii # -- Begin function _Z22__device_stub__add_vecPiS_ii
.p2align 4, 0x90
.type _Z22__device_stub__add_vecPiS_ii,@function
_Z22__device_stub__add_vecPiS_ii: # @_Z22__device_stub__add_vecPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_vecPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__add_vecPiS_ii, .Lfunc_end0-_Z22__device_stub__add_vecPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2: # %_Z8fill_arrIiEvPT_S0_i.exit
movl $1073741824, %edi # imm = 0x40000000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i71
# =>This Inner Loop Header: Depth=1
movl $2, (%rax,%rcx,4)
incq %rcx
cmpq $268435456, %rcx # imm = 0x10000000
jne .LBB1_3
# %bb.4: # %_Z8fill_arrIiEvPT_S0_i.exit75
movq %rax, 32(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movl $128, %edi
callq _Znam
movq %rax, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
leaq (%r14,%r13), %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $128, %r14
jne .LBB1_5
# %bb.6: # %.preheader79
movabsq $4294967312, %rax # imm = 0x100000010
xorl %r12d, %r12d
addq $240, %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq %r13, %r15
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rsi
addq %r12, %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpyAsync
addq $16777216, %r14 # imm = 0x1000000
addq $67108864, %r12 # imm = 0x4000000
addq $8, %r15
cmpq $268435456, %r14 # imm = 0x10000000
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
addq %r12, %rdi
leaq (%rbx,%r12), %rbp
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 32(%rsp), %rax # 8-byte Reload
leaq (%rax,%r12), %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r15), %r9
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967312, %rdx # imm = 0x100000010
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r14d, 28(%rsp)
movl $268435456, 24(%rsp) # imm = 0x10000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7add_vecPiS_ii, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10: # %.preheader.preheader
xorl %r14d, %r14d
movq %r13, %r15
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%r14), %rdi
movq 8(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movl $2, %ecx
callq hipMemcpyAsync
addq $67108864, %r14 # imm = 0x4000000
addq $8, %r15
cmpq $1073741824, %r14 # imm = 0x40000000
jne .LBB1_11
# %bb.12:
callq hipDeviceSynchronize
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movq (%r13,%r14,8), %rdi
callq hipStreamDestroy
incq %r14
cmpq $16, %r14
jne .LBB1_13
# %bb.14:
movq %r13, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_vecPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_vecPiS_ii,@object # @_Z7add_vecPiS_ii
.section .rodata,"a",@progbits
.globl _Z7add_vecPiS_ii
.p2align 3, 0x0
_Z7add_vecPiS_ii:
.quad _Z22__device_stub__add_vecPiS_ii
.size _Z7add_vecPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7add_vecPiS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_vecPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_vecPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7add_vecPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_vecPiS_ii
.globl _Z7add_vecPiS_ii
.p2align 8
.type _Z7add_vecPiS_ii,@function
_Z7add_vecPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s15, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_vecPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_vecPiS_ii, .Lfunc_end0-_Z7add_vecPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_vecPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_vecPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000db415_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
.type _Z30__device_stub__Z7add_vecPiS_iiPiS_ii, @function
_Z30__device_stub__Z7add_vecPiS_iiPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_vecPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z7add_vecPiS_iiPiS_ii, .-_Z30__device_stub__Z7add_vecPiS_iiPiS_ii
.globl _Z7add_vecPiS_ii
.type _Z7add_vecPiS_ii, @function
_Z7add_vecPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7add_vecPiS_ii, .-_Z7add_vecPiS_ii
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r14
leaq 1073741824(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1073741824, %edi
call malloc@PLT
movq %rax, (%rsp)
leaq 1073741824(%rax), %rdx
.L13:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $128, %edi
call _Znam@PLT
movq %rax, %r13
movq %rax, %r12
leaq 128(%rax), %r15
movq %rax, %rbx
.L14:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r15, %rbx
jne .L14
movq %r13, %rbp
movl $0, %eax
movl $0, %ebx
movq %r13, 8(%rsp)
movq %r12, 16(%rsp)
movl %eax, %r13d
movq %r15, 24(%rsp)
jmp .L16
.L15:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq (%r15), %r8
movl $2, %ecx
movl $67108864, %edx
movq %r12, %rdi
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $67108864, %rbx
addl $16777216, %r13d
cmpq $1073741824, %rbx
je .L27
.L16:
movq %rbp, %r15
leaq (%r14,%rbx), %r12
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
call cudaMemcpyAsync@PLT
movq (%rsp), %rax
leaq (%rax,%rbx), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $67108864, %edx
call cudaMemcpyAsync@PLT
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $268435456, %ecx
movl %r13d, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7add_vecPiS_iiPiS_ii
jmp .L15
.L27:
movq 8(%rsp), %r13
movq 16(%rsp), %r12
movq 24(%rsp), %r15
movq %r13, %rbp
movl $0, %ebx
.L17:
movq %rbx, %rsi
addq 32(%rsp), %rsi
leaq (%r14,%rbx), %rdi
movq 0(%rbp), %r8
movl $2, %ecx
movl $67108864, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $67108864, %rbx
cmpq $1073741824, %rbx
jne .L17
call cudaDeviceSynchronize@PLT
.L18:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %r15, %r12
jne .L18
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7add_vecPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_vecPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__add_vecPiS_ii # -- Begin function _Z22__device_stub__add_vecPiS_ii
.p2align 4, 0x90
.type _Z22__device_stub__add_vecPiS_ii,@function
_Z22__device_stub__add_vecPiS_ii: # @_Z22__device_stub__add_vecPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_vecPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__add_vecPiS_ii, .Lfunc_end0-_Z22__device_stub__add_vecPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2: # %_Z8fill_arrIiEvPT_S0_i.exit
movl $1073741824, %edi # imm = 0x40000000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i71
# =>This Inner Loop Header: Depth=1
movl $2, (%rax,%rcx,4)
incq %rcx
cmpq $268435456, %rcx # imm = 0x10000000
jne .LBB1_3
# %bb.4: # %_Z8fill_arrIiEvPT_S0_i.exit75
movq %rax, 32(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movl $128, %edi
callq _Znam
movq %rax, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
leaq (%r14,%r13), %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $128, %r14
jne .LBB1_5
# %bb.6: # %.preheader79
movabsq $4294967312, %rax # imm = 0x100000010
xorl %r12d, %r12d
addq $240, %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq %r13, %r15
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rsi
addq %r12, %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpyAsync
addq $16777216, %r14 # imm = 0x1000000
addq $67108864, %r12 # imm = 0x4000000
addq $8, %r15
cmpq $268435456, %r14 # imm = 0x10000000
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
addq %r12, %rdi
leaq (%rbx,%r12), %rbp
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 32(%rsp), %rax # 8-byte Reload
leaq (%rax,%r12), %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r15), %r9
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967312, %rdx # imm = 0x100000010
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r14d, 28(%rsp)
movl $268435456, 24(%rsp) # imm = 0x10000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7add_vecPiS_ii, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10: # %.preheader.preheader
xorl %r14d, %r14d
movq %r13, %r15
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%r14), %rdi
movq 8(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $67108864, %edx # imm = 0x4000000
movl $2, %ecx
callq hipMemcpyAsync
addq $67108864, %r14 # imm = 0x4000000
addq $8, %r15
cmpq $1073741824, %r14 # imm = 0x40000000
jne .LBB1_11
# %bb.12:
callq hipDeviceSynchronize
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movq (%r13,%r14,8), %rdi
callq hipStreamDestroy
incq %r14
cmpq $16, %r14
jne .LBB1_13
# %bb.14:
movq %r13, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_vecPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_vecPiS_ii,@object # @_Z7add_vecPiS_ii
.section .rodata,"a",@progbits
.globl _Z7add_vecPiS_ii
.p2align 3, 0x0
_Z7add_vecPiS_ii:
.quad _Z22__device_stub__add_vecPiS_ii
.size _Z7add_vecPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7add_vecPiS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_vecPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_vecPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Written by : Eric Tan
*/
#include <iostream>
#include <cmath>
#include <array>
#include <cuda.h>
#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4
/*-------------------------------------------------------------------------------------------------
* GLOBAL CONSTANTS
*-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];
/*-------------------------------------------------------------------------------------------------
* FORWARD DECLARATION
*-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);
/*-------------------------------------------------------------------------------------------------
* MAIN
*-----------------------------------------------------------------------------------------------*/
int main(void)
{
const int mask_size = 9;
const int N_data = 1000;
const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};
// Copy to constant memory
cudaMemcpyToSymbol(mask, mask_kernel.data(), mask_size * sizeof(float));
float *input = new float[N_data];
float *cpu_output = new float[N_data];
float *gpu_output = new float[N_data];
for (int i = 0; i < N_data; i++)
input[i] = i + 1.0;
convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);
convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
convolution_cache_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
delete[] input;
delete[] cpu_output;
delete[] gpu_output;
}
/*-------------------------------------------------------------------------------------------------
* KERNELS
*-----------------------------------------------------------------------------------------------*/
/* tiled_convolution_kernel()
* Performs convolution by tiling the input and loading halo elements.
*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int half = N_mask / 2;
__shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];
// Left load
// Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - half)
tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];
// Middle load
tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];
// Right load
// Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if (threadIdx.x < half)
tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];
__syncthreads();
// Convolution calculation
float sum = 0.0;
for (int i = 0; i < N_mask; i++)
sum += tile[threadIdx.x + i] * mask[i];
output[idx] = sum;
}
/* cache_convolution_kernel()
* Performs convolution by loading multiple tiles of the input data and performing the convolution
* operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
* will go to L2 cache to grabe them.
*/
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
__shared__ float tile[N_TILE * TILE_SIZE];
// Load Multiple tiles
#pragma unroll
for (int i = 0; i < N_TILE; i++)
tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];
__syncthreads();
int tile_start = N_TILE * blockDim.x * blockIdx.x;
int tile_end = N_TILE * blockDim.x * (blockIdx.x + 1);
#pragma unroll
for (int i = 0; i < N_TILE; i++) {
int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
int input_idx = start_point + j;
if (input_idx >= 0 && input_idx < N_data) {
// Check if elements needed is in shared memory
if (input_idx >= tile_start && input_idx < tile_end)
sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
else
sum += input[input_idx] * mask[j];
} // Check if element is outside range of input data
} // Loop over Mask elements
output[idx + i * TILE_SIZE] = sum;
} // Loop over multiple tiles
}
/*-------------------------------------------------------------------------------------------------
* FUNCTIONS
*-----------------------------------------------------------------------------------------------*/
/* convolution_tiled_gpu()
* Driver function for tiled convolution which loads halo elements.
*/
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
cudaMalloc((void**)&d_input, size);
cudaMalloc((void**)&d_output, size);
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
cudaEventRecord(stop);
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time_ms = 0.0;
cudaEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";
cudaFree(d_input);
cudaFree(d_output);
}
/* convolution_tiled_gpu()
* Driver function for tiled convolution without loading halo elements.
*/
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
cudaMalloc((void**)&d_input, size);
cudaMalloc((void**)&d_output, size);
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
cudaEventRecord(stop);
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time_ms = 0.0;
cudaEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";
cudaFree(d_input);
cudaFree(d_output);
}
/* convolution_cpu()
* CPU based convolution operation. Used to compare GPU implamentations.
*/
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
int half_point = N_mask / 2;
for (int i = 0; i < N_data; i++) {
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
if (i - half_point + j >= 0 && i - half_point + j < N_data)
sum += input[i - half_point + j] * mask[j];
}
output[i] = sum;
}
}
/* check_convolution()
* Computes the difference between the two outputs of CPU and GPU convolutions.
*/
double check_convolution(const float *A, const float *B, int N)
{
float sum = 0.0;
for (int i = 0; i < N; i++)
sum += fabs(A[i] - B[i]);
return sum;
} | .file "tmpxft_001050ad_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3717:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3717:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15convolution_cpuPKfPfS0_ii
.type _Z15convolution_cpuPKfPfS0_ii, @function
_Z15convolution_cpuPKfPfS0_ii:
.LFB3713:
.cfi_startproc
endbr64
movl %r8d, %eax
shrl $31, %eax
addl %r8d, %eax
sarl %eax
testl %ecx, %ecx
jle .L13
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movq %rdx, %r11
movl %ecx, %edi
movl %r8d, %ebx
movq %rsi, %r9
movl %r8d, %ecx
subl %eax, %ecx
movslq %eax, %rdx
negq %rdx
leaq (%r10,%rdx,4), %rsi
movl %eax, %r10d
negl %r10d
leal (%rdi,%r8), %r8d
subl %eax, %r8d
jmp .L5
.L6:
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
je .L8
.L7:
cmpl %eax, %edi
jle .L6
testl %eax, %eax
js .L6
movss (%rsi,%rdx), %xmm0
mulss (%r11,%rdx), %xmm0
addss %xmm0, %xmm1
jmp .L6
.L8:
movss %xmm1, (%r9)
addq $4, %r9
addl $1, %ecx
addq $4, %rsi
addl $1, %r10d
cmpl %r8d, %ecx
je .L3
.L5:
movl %r10d, %eax
movl $0, %edx
pxor %xmm1, %xmm1
testl %ebx, %ebx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
ret
.cfi_endproc
.LFE3713:
.size _Z15convolution_cpuPKfPfS0_ii, .-_Z15convolution_cpuPKfPfS0_ii
.globl _Z17check_convolutionPKfS0_i
.type _Z17check_convolutionPKfS0_i, @function
_Z17check_convolutionPKfS0_i:
.LFB3714:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L19
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm0, %xmm0
movss .LC1(%rip), %xmm2
.L18:
movss (%rdi,%rax), %xmm1
subss (%rsi,%rax), %xmm1
andps %xmm2, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rax, %rdx
jne .L18
.L17:
cvtss2sd %xmm0, %xmm0
ret
.L19:
pxor %xmm0, %xmm0
jmp .L17
.cfi_endproc
.LFE3714:
.size _Z17check_convolutionPKfS0_i, .-_Z17check_convolutionPKfS0_i
.globl _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
.type _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii:
.LFB3739:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24tiled_convolution_kernelPKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3739:
.size _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
.globl _Z24tiled_convolution_kernelPKfPfii
.type _Z24tiled_convolution_kernelPKfPfii, @function
_Z24tiled_convolution_kernelPKfPfii:
.LFB3740:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3740:
.size _Z24tiled_convolution_kernelPKfPfii, .-_Z24tiled_convolution_kernelPKfPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Convolution with tiling and halo runtime: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "ms "
.text
.globl _Z21convolution_tiled_gpuPKfPfii
.type _Z21convolution_tiled_gpuPKfPfii, @function
_Z21convolution_tiled_gpuPKfPfii:
.LFB3711:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L30
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L30:
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $42, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z21convolution_tiled_gpuPKfPfii, .-_Z21convolution_tiled_gpuPKfPfii
.globl _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
.type _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii:
.LFB3741:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24cache_convolution_kernelPKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3741:
.size _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
.globl _Z24cache_convolution_kernelPKfPfii
.type _Z24cache_convolution_kernelPKfPfii, @function
_Z24cache_convolution_kernelPKfPfii:
.LFB3742:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3742:
.size _Z24cache_convolution_kernelPKfPfii, .-_Z24cache_convolution_kernelPKfPfii
.section .rodata.str1.8
.align 8
.LC9:
.string "Convolution with L2 cache use runtime: "
.text
.globl _Z21convolution_cache_gpuPKfPfii
.type _Z21convolution_cache_gpuPKfPfii, @function
_Z21convolution_cache_gpuPKfPfii:
.LFB3712:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC8(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L45
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L45:
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L46:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
jmp .L46
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3712:
.size _Z21convolution_cache_gpuPKfPfii, .-_Z21convolution_cache_gpuPKfPfii
.section .rodata.str1.1
.LC16:
.string " Error = "
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movss .LC10(%rip), %xmm0
movss %xmm0, (%rsp)
movss .LC11(%rip), %xmm1
movss %xmm1, 4(%rsp)
movss .LC12(%rip), %xmm2
movss %xmm2, 8(%rsp)
movss .LC13(%rip), %xmm3
movss %xmm3, 12(%rsp)
movl $0x40e00000, 16(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm0, 32(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL4mask(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4000, %edi
call _Znam@PLT
movq %rax, %r12
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movsd .LC15(%rip), %xmm1
.L52:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L52
movq %rsp, %rdx
movl $9, %r8d
movl $1000, %ecx
movq %r12, %rsi
movq %rbx, %rdi
call _Z15convolution_cpuPKfPfS0_ii
movl $9, %ecx
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21convolution_tiled_gpuPKfPfii
leaq .LC16(%rip), %r14
movq %r14, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r15
movl $1000, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17check_convolutionPKfS0_i
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $9, %ecx
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21convolution_cache_gpuPKfPfii
movq %r14, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl $1000, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17check_convolutionPKfS0_i
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z24cache_convolution_kernelPKfPfii"
.align 8
.LC18:
.string "_Z24tiled_convolution_kernelPKfPfii"
.section .rodata.str1.1
.LC19:
.string "mask"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3744:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cache_convolution_kernelPKfPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z24tiled_convolution_kernelPKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4mask(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3744:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4mask
.comm _ZL4mask,200,32
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 989855744
.align 4
.LC3:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.set .LC7,.LC1
.align 4
.LC8:
.long 973078528
.align 4
.LC10:
.long 1077936128
.align 4
.LC11:
.long 1082130432
.align 4
.LC12:
.long 1084227584
.align 4
.LC13:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Written by : Eric Tan
*/
#include <iostream>
#include <cmath>
#include <array>
#include <cuda.h>
#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4
/*-------------------------------------------------------------------------------------------------
* GLOBAL CONSTANTS
*-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];
/*-------------------------------------------------------------------------------------------------
* FORWARD DECLARATION
*-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);
/*-------------------------------------------------------------------------------------------------
* MAIN
*-----------------------------------------------------------------------------------------------*/
int main(void)
{
const int mask_size = 9;
const int N_data = 1000;
const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};
// Copy to constant memory
cudaMemcpyToSymbol(mask, mask_kernel.data(), mask_size * sizeof(float));
float *input = new float[N_data];
float *cpu_output = new float[N_data];
float *gpu_output = new float[N_data];
for (int i = 0; i < N_data; i++)
input[i] = i + 1.0;
convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);
convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
convolution_cache_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
delete[] input;
delete[] cpu_output;
delete[] gpu_output;
}
/*-------------------------------------------------------------------------------------------------
* KERNELS
*-----------------------------------------------------------------------------------------------*/
/* tiled_convolution_kernel()
* Performs convolution by tiling the input and loading halo elements.
*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int half = N_mask / 2;
__shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];
// Left load
// Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - half)
tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];
// Middle load
tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];
// Right load
// Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if (threadIdx.x < half)
tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];
__syncthreads();
// Convolution calculation
float sum = 0.0;
for (int i = 0; i < N_mask; i++)
sum += tile[threadIdx.x + i] * mask[i];
output[idx] = sum;
}
/* cache_convolution_kernel()
* Performs convolution by loading multiple tiles of the input data and performing the convolution
* operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
* will go to L2 cache to grabe them.
*/
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
__shared__ float tile[N_TILE * TILE_SIZE];
// Load Multiple tiles
#pragma unroll
for (int i = 0; i < N_TILE; i++)
tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];
__syncthreads();
int tile_start = N_TILE * blockDim.x * blockIdx.x;
int tile_end = N_TILE * blockDim.x * (blockIdx.x + 1);
#pragma unroll
for (int i = 0; i < N_TILE; i++) {
int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
int input_idx = start_point + j;
if (input_idx >= 0 && input_idx < N_data) {
// Check if elements needed is in shared memory
if (input_idx >= tile_start && input_idx < tile_end)
sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
else
sum += input[input_idx] * mask[j];
} // Check if element is outside range of input data
} // Loop over Mask elements
output[idx + i * TILE_SIZE] = sum;
} // Loop over multiple tiles
}
/*-------------------------------------------------------------------------------------------------
* FUNCTIONS
*-----------------------------------------------------------------------------------------------*/
/* convolution_tiled_gpu()
* Driver function for tiled convolution which loads halo elements.
*/
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
cudaMalloc((void**)&d_input, size);
cudaMalloc((void**)&d_output, size);
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
cudaEventRecord(stop);
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time_ms = 0.0;
cudaEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";
cudaFree(d_input);
cudaFree(d_output);
}
/* convolution_tiled_gpu()
* Driver function for tiled convolution without loading halo elements.
*/
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
cudaMalloc((void**)&d_input, size);
cudaMalloc((void**)&d_output, size);
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
cudaEventRecord(stop);
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time_ms = 0.0;
cudaEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";
cudaFree(d_input);
cudaFree(d_output);
}
/* convolution_cpu()
* CPU based convolution operation. Used to compare GPU implamentations.
*/
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
int half_point = N_mask / 2;
for (int i = 0; i < N_data; i++) {
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
if (i - half_point + j >= 0 && i - half_point + j < N_data)
sum += input[i - half_point + j] * mask[j];
}
output[i] = sum;
}
}
/* check_convolution()
* Computes the difference between the two outputs of CPU and GPU convolutions.
*/
double check_convolution(const float *A, const float *B, int N)
{
float sum = 0.0;
for (int i = 0; i < N; i++)
sum += fabs(A[i] - B[i]);
return sum;
} | /* Written by : Eric Tan
*/
#include <iostream>
#include <cmath>
#include <array>
#include <hip/hip_runtime.h>
#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4
/*-------------------------------------------------------------------------------------------------
* GLOBAL CONSTANTS
*-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];
/*-------------------------------------------------------------------------------------------------
* FORWARD DECLARATION
*-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);
/*-------------------------------------------------------------------------------------------------
* MAIN
*-----------------------------------------------------------------------------------------------*/
int main(void)
{
const int mask_size = 9;
const int N_data = 1000;
const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};
// Copy to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(mask), mask_kernel.data(), mask_size * sizeof(float));
float *input = new float[N_data];
float *cpu_output = new float[N_data];
float *gpu_output = new float[N_data];
for (int i = 0; i < N_data; i++)
input[i] = i + 1.0;
convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);
convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
convolution_cache_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
delete[] input;
delete[] cpu_output;
delete[] gpu_output;
}
/*-------------------------------------------------------------------------------------------------
* KERNELS
*-----------------------------------------------------------------------------------------------*/
/* tiled_convolution_kernel()
* Performs convolution by tiling the input and loading halo elements.
*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int half = N_mask / 2;
__shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];
// Left load
// Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - half)
tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];
// Middle load
tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];
// Right load
// Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if (threadIdx.x < half)
tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];
__syncthreads();
// Convolution calculation
float sum = 0.0;
for (int i = 0; i < N_mask; i++)
sum += tile[threadIdx.x + i] * mask[i];
output[idx] = sum;
}
/* cache_convolution_kernel()
* Performs convolution by loading multiple tiles of the input data and performing the convolution
* operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
* will go to L2 cache to grabe them.
*/
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
__shared__ float tile[N_TILE * TILE_SIZE];
// Load Multiple tiles
#pragma unroll
for (int i = 0; i < N_TILE; i++)
tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];
__syncthreads();
int tile_start = N_TILE * blockDim.x * blockIdx.x;
int tile_end = N_TILE * blockDim.x * (blockIdx.x + 1);
#pragma unroll
for (int i = 0; i < N_TILE; i++) {
int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
int input_idx = start_point + j;
if (input_idx >= 0 && input_idx < N_data) {
// Check if elements needed is in shared memory
if (input_idx >= tile_start && input_idx < tile_end)
sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
else
sum += input[input_idx] * mask[j];
} // Check if element is outside range of input data
} // Loop over Mask elements
output[idx + i * TILE_SIZE] = sum;
} // Loop over multiple tiles
}
/*-------------------------------------------------------------------------------------------------
* FUNCTIONS
*-----------------------------------------------------------------------------------------------*/
/* convolution_tiled_gpu()
* Driver function for tiled convolution which loads halo elements.
*/
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_tiled_gpu()
* Driver function for tiled convolution without loading halo elements.
*/
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_cpu()
* CPU based convolution operation. Used to compare GPU implamentations.
*/
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
int half_point = N_mask / 2;
for (int i = 0; i < N_data; i++) {
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
if (i - half_point + j >= 0 && i - half_point + j < N_data)
sum += input[i - half_point + j] * mask[j];
}
output[i] = sum;
}
}
/* check_convolution()
* Computes the difference between the two outputs of CPU and GPU convolutions.
*/
double check_convolution(const float *A, const float *B, int N)
{
float sum = 0.0;
for (int i = 0; i < N; i++)
sum += fabs(A[i] - B[i]);
return sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Written by : Eric Tan
*/
#include <iostream>
#include <cmath>
#include <array>
#include <hip/hip_runtime.h>
#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4
/*-------------------------------------------------------------------------------------------------
* GLOBAL CONSTANTS
*-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];
/*-------------------------------------------------------------------------------------------------
* FORWARD DECLARATION
*-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);
/*-------------------------------------------------------------------------------------------------
* MAIN
*-----------------------------------------------------------------------------------------------*/
int main(void)
{
const int mask_size = 9;
const int N_data = 1000;
const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};
// Copy to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(mask), mask_kernel.data(), mask_size * sizeof(float));
float *input = new float[N_data];
float *cpu_output = new float[N_data];
float *gpu_output = new float[N_data];
for (int i = 0; i < N_data; i++)
input[i] = i + 1.0;
convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);
convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
convolution_cache_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
delete[] input;
delete[] cpu_output;
delete[] gpu_output;
}
/*-------------------------------------------------------------------------------------------------
* KERNELS
*-----------------------------------------------------------------------------------------------*/
/* tiled_convolution_kernel()
* Performs convolution by tiling the input and loading halo elements.
*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int half = N_mask / 2;
__shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];
// Left load
// Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - half)
tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];
// Middle load
tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];
// Right load
// Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if (threadIdx.x < half)
tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];
__syncthreads();
// Convolution calculation
float sum = 0.0;
for (int i = 0; i < N_mask; i++)
sum += tile[threadIdx.x + i] * mask[i];
output[idx] = sum;
}
/* cache_convolution_kernel()
* Performs convolution by loading multiple tiles of the input data and performing the convolution
* operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
* will go to L2 cache to grabe them.
*/
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
__shared__ float tile[N_TILE * TILE_SIZE];
// Load Multiple tiles
#pragma unroll
for (int i = 0; i < N_TILE; i++)
tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];
__syncthreads();
int tile_start = N_TILE * blockDim.x * blockIdx.x;
int tile_end = N_TILE * blockDim.x * (blockIdx.x + 1);
#pragma unroll
for (int i = 0; i < N_TILE; i++) {
int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
int input_idx = start_point + j;
if (input_idx >= 0 && input_idx < N_data) {
// Check if elements needed is in shared memory
if (input_idx >= tile_start && input_idx < tile_end)
sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
else
sum += input[input_idx] * mask[j];
} // Check if element is outside range of input data
} // Loop over Mask elements
output[idx + i * TILE_SIZE] = sum;
} // Loop over multiple tiles
}
/*-------------------------------------------------------------------------------------------------
* FUNCTIONS
*-----------------------------------------------------------------------------------------------*/
/* convolution_tiled_gpu()
* Driver function for tiled convolution which loads halo elements.
*/
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_tiled_gpu()
* Driver function for tiled convolution without loading halo elements.
*/
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_cpu()
* CPU based convolution operation. Used to compare GPU implamentations.
*/
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
int half_point = N_mask / 2;
for (int i = 0; i < N_data; i++) {
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
if (i - half_point + j >= 0 && i - half_point + j < N_data)
sum += input[i - half_point + j] * mask[j];
}
output[i] = sum;
}
}
/* check_convolution()
* Computes the difference between the two outputs of CPU and GPU convolutions.
*/
double check_convolution(const float *A, const float *B, int N)
{
float sum = 0.0;
for (int i = 0; i < N; i++)
sum += fabs(A[i] - B[i]);
return sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24tiled_convolution_kernelPKfPfii
.globl _Z24tiled_convolution_kernelPKfPfii
.p2align 8
.type _Z24tiled_convolution_kernelPKfPfii,@function
_Z24tiled_convolution_kernelPKfPfii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x14
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_sub_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_4
s_add_i32 s8, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s5, v1
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s6, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[0:1], 0x10
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v3, s5, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
v_lshlrev_b32_e32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, mask@rel32@lo+4
s_addc_u32 s3, s3, mask@rel32@hi+12
.LBB0_10:
ds_load_b32 v3, v2
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v2, 4, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v3
s_cbranch_scc0 .LBB0_10
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v0, 0
.LBB0_12:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24tiled_convolution_kernelPKfPfii
.amdhsa_group_segment_fixed_size 2244
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24tiled_convolution_kernelPKfPfii, .Lfunc_end0-_Z24tiled_convolution_kernelPKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24cache_convolution_kernelPKfPfii
.globl _Z24cache_convolution_kernelPKfPfii
.p2align 8
.type _Z24cache_convolution_kernelPKfPfii,@function
_Z24cache_convolution_kernelPKfPfii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s11, s2, 2
s_lshr_b32 s2, s7, 31
s_mul_i32 s10, s11, s15
s_add_i32 s2, s7, s2
v_add_nc_u32_e32 v1, s10, v0
s_add_i32 s15, s15, 1
s_ashr_i32 s12, s2, 1
s_cmp_gt_i32 s7, 0
s_mul_i32 s11, s11, s15
v_ashrrev_i32_e32 v2, 31, v1
s_cselect_b32 s13, -1, 0
s_cmp_lt_i32 s7, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, 0x1000, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_clause 0x3
global_load_b32 v7, v[3:4], off
global_load_b32 v3, v[3:4], off offset:2048
global_load_b32 v4, v[5:6], off
global_load_b32 v6, v[5:6], off offset:2048
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt vmcnt(2)
ds_store_2addr_stride64_b32 v5, v7, v3 offset1:8
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v5, v4, v6 offset0:16 offset1:24
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
v_mov_b32_e32 v4, 0
s_lshl_b32 s2, s12, 2
v_subrev_nc_u32_e32 v3, s12, v1
v_subrev_nc_u32_e32 v5, s2, v5
s_mov_b32 s3, s7
v_mov_b32_e32 v6, v4
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mask@rel32@lo+4
s_addc_u32 s9, s9, mask@rel32@hi+12
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v3, 1, v3
v_add_nc_u32_e32 v5, 4, v5
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_10
.LBB1_4:
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s2, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB1_3
s_waitcnt lgkmcnt(0)
s_load_b32 s15, s[8:9], 0x0
v_cmp_gt_i32_e32 vcc_lo, s10, v3
v_cmp_le_i32_e64 s2, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s16, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s16
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v6, s15, v7
.LBB1_7:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_2
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, s15, v7
s_branch .LBB1_2
.LBB1_9:
v_mov_b32_e32 v6, 0
.LBB1_10:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cndmask_b32_e64 v5, 0, 1, s13
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v3, vcc_lo
v_add_nc_u32_e32 v2, 0x200, v1
s_and_not1_b32 vcc_lo, exec_lo, s13
global_store_b32 v[7:8], v6, off
s_cbranch_vccnz .LBB1_19
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_lshl_b32 s0, s12, 2
s_mov_b32 s1, s7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mask@rel32@lo+4
s_addc_u32 s9, s9, mask@rel32@hi+12
v_subrev_nc_u32_e32 v6, s0, v3
v_subrev_nc_u32_e32 v3, s12, v2
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v7, 0x800, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_14
.p2align 6
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v7, 4, v7
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB1_20
.LBB1_14:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s6, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB1_13
s_waitcnt lgkmcnt(0)
s_load_b32 s14, s[8:9], 0x0
v_cmp_gt_i32_e32 vcc_lo, s10, v3
v_cmp_le_i32_e64 s0, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s15, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s15
s_cbranch_execz .LBB1_17
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v6, s14, v8
.LBB1_17:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB1_12
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, s14, v8
s_branch .LBB1_12
.LBB1_19:
v_mov_b32_e32 v6, 0
.LBB1_20:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_ne_u32_e32 vcc_lo, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_and_b32 vcc_lo, exec_lo, vcc_lo
v_add_co_u32 v7, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s3, v3, s0
v_add_nc_u32_e32 v2, 0x400, v1
global_store_b32 v[7:8], v6, off
s_cbranch_vccnz .LBB1_29
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_lshl_b32 s0, s12, 2
s_mov_b32 s1, s7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mask@rel32@lo+4
s_addc_u32 s9, s9, mask@rel32@hi+12
v_subrev_nc_u32_e32 v6, s0, v3
v_subrev_nc_u32_e32 v3, s12, v2
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v7, 0x1000, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_24
.p2align 6
.LBB1_22:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_23:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v7, 4, v7
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB1_30
.LBB1_24:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s6, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB1_23
s_waitcnt lgkmcnt(0)
s_load_b32 s14, s[8:9], 0x0
v_cmp_gt_i32_e32 vcc_lo, s10, v3
v_cmp_le_i32_e64 s0, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s15, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s15
s_cbranch_execz .LBB1_27
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v6, s14, v8
.LBB1_27:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB1_22
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, s14, v8
s_branch .LBB1_22
.LBB1_29:
v_mov_b32_e32 v6, 0
.LBB1_30:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_add_nc_u32_e32 v1, 0x600, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
global_store_b32 v[2:3], v6, off
s_cbranch_vccnz .LBB1_39
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_lshl_b32 s0, s12, 2
v_subrev_nc_u32_e32 v2, s12, v1
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mask@rel32@lo+4
s_addc_u32 s9, s9, mask@rel32@hi+12
v_subrev_nc_u32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, 0x1800, v0
v_mov_b32_e32 v0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_34
.p2align 6
.LBB1_32:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_33:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s7, s7, -1
v_add_nc_u32_e32 v4, 4, v4
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB1_40
.LBB1_34:
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_33
s_waitcnt lgkmcnt(0)
s_load_b32 s12, s[8:9], 0x0
v_cmp_gt_i32_e32 vcc_lo, s10, v2
v_cmp_le_i32_e64 s0, s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s13, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s13
s_cbranch_execz .LBB1_37
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s12, v5
.LBB1_37:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB1_32
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s12, v5
s_branch .LBB1_32
.LBB1_39:
v_mov_b32_e32 v0, 0
.LBB1_40:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cache_convolution_kernelPKfPfii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z24cache_convolution_kernelPKfPfii, .Lfunc_end1-_Z24cache_convolution_kernelPKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected mask
.type mask,@object
.section .bss,"aw",@nobits
.globl mask
.p2align 4, 0x0
mask:
.zero 200
.size mask, 200
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym mask
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2244
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24tiled_convolution_kernelPKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24tiled_convolution_kernelPKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cache_convolution_kernelPKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z24cache_convolution_kernelPKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Written by : Eric Tan
*/
#include <iostream>
#include <cmath>
#include <array>
#include <hip/hip_runtime.h>
#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4
/*-------------------------------------------------------------------------------------------------
* GLOBAL CONSTANTS
*-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];
/*-------------------------------------------------------------------------------------------------
* FORWARD DECLARATION
*-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);
/*-------------------------------------------------------------------------------------------------
* MAIN
*-----------------------------------------------------------------------------------------------*/
int main(void)
{
const int mask_size = 9;
const int N_data = 1000;
const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};
// Copy to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(mask), mask_kernel.data(), mask_size * sizeof(float));
float *input = new float[N_data];
float *cpu_output = new float[N_data];
float *gpu_output = new float[N_data];
for (int i = 0; i < N_data; i++)
input[i] = i + 1.0;
convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);
convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
convolution_cache_gpu(input, gpu_output, N_data, mask_size);
std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';
delete[] input;
delete[] cpu_output;
delete[] gpu_output;
}
/*-------------------------------------------------------------------------------------------------
* KERNELS
*-----------------------------------------------------------------------------------------------*/
/* tiled_convolution_kernel()
* Performs convolution by tiling the input and loading halo elements.
*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int half = N_mask / 2;
__shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];
// Left load
// Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - half)
tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];
// Middle load
tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];
// Right load
// Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if (threadIdx.x < half)
tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];
__syncthreads();
// Convolution calculation
float sum = 0.0;
for (int i = 0; i < N_mask; i++)
sum += tile[threadIdx.x + i] * mask[i];
output[idx] = sum;
}
/* cache_convolution_kernel()
* Performs convolution by loading multiple tiles of the input data and performing the convolution
* operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
* will go to L2 cache to grabe them.
*/
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
__shared__ float tile[N_TILE * TILE_SIZE];
// Load Multiple tiles
#pragma unroll
for (int i = 0; i < N_TILE; i++)
tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];
__syncthreads();
int tile_start = N_TILE * blockDim.x * blockIdx.x;
int tile_end = N_TILE * blockDim.x * (blockIdx.x + 1);
#pragma unroll
for (int i = 0; i < N_TILE; i++) {
int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
int input_idx = start_point + j;
if (input_idx >= 0 && input_idx < N_data) {
// Check if elements needed is in shared memory
if (input_idx >= tile_start && input_idx < tile_end)
sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
else
sum += input[input_idx] * mask[j];
} // Check if element is outside range of input data
} // Loop over Mask elements
output[idx + i * TILE_SIZE] = sum;
} // Loop over multiple tiles
}
/*-------------------------------------------------------------------------------------------------
* FUNCTIONS
*-----------------------------------------------------------------------------------------------*/
/* convolution_tiled_gpu()
* Driver function for tiled convolution which loads halo elements.
*/
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_tiled_gpu()
* Driver function for tiled convolution without loading halo elements.
*/
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
int size = N_data * sizeof(float);
float *d_input, *d_output;
hipMalloc((void**)&d_input, size);
hipMalloc((void**)&d_output, size);
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
int N_thd = TILE_SIZE;
int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
dim3 blk_dim(N_thd, 1, 1);
dim3 grid_dim(N_blk, 1, 1 );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);
hipEventRecord(stop);
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time_ms = 0.0;
hipEventElapsedTime(&time_ms, start, stop);
std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";
hipFree(d_input);
hipFree(d_output);
}
/* convolution_cpu()
* CPU based convolution operation. Used to compare GPU implamentations.
*/
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
int half_point = N_mask / 2;
for (int i = 0; i < N_data; i++) {
float sum = 0.0;
for (int j = 0; j < N_mask; j++) {
if (i - half_point + j >= 0 && i - half_point + j < N_data)
sum += input[i - half_point + j] * mask[j];
}
output[i] = sum;
}
}
/* check_convolution()
* Computes the difference between the two outputs of CPU and GPU convolutions.
*/
double check_convolution(const float *A, const float *B, int N)
{
float sum = 0.0;
for (int i = 0; i < N; i++)
sum += fabs(A[i] - B[i]);
return sum;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.LCPI0_1:
.long 0x40e00000 # float 7
.long 0x40c00000 # float 6
.long 0x40a00000 # float 5
.long 0x40800000 # float 4
.LCPI0_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3.0E+0,4.0E+0,5.0E+0,6.0E+0]
movups %xmm0, 4(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [7.0E+0,6.0E+0,5.0E+0,4.0E+0]
movups %xmm0, 20(%rsp)
movl $1077936128, 36(%rsp) # imm = 0x40400000
xorl %r12d, %r12d
leaq 4(%rsp), %rsi
movl $mask, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r14
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movq %rax, %r12
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_1
# %bb.2: # %.preheader.i.preheader
xorl %eax, %eax
movq %rbx, %rcx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # %._crit_edge.i
# in Loop: Header=BB0_3 Depth=1
movss %xmm0, (%r14,%rax,4)
incq %rax
addq $4, %rcx
cmpq $1000, %rax # imm = 0x3E8
je .LBB0_8
.LBB0_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorps %xmm0, %xmm0
movq $-4, %rdx
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
incq %rdx
cmpq $5, %rdx
je .LBB0_7
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
cmpl $999, %esi # imm = 0x3E7
ja .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movss (%rcx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 20(%rsp,%rdx,4), %xmm1
addss %xmm1, %xmm0
jmp .LBB0_6
.LBB0_8: # %_Z15convolution_cpuPKfPfS0_ii.exit
movq %rbx, %rdi
movq %r15, %rsi
movl $1000, %edx # imm = 0x3E8
movl $9, %ecx
callq _Z21convolution_tiled_gpuPKfPfii
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r15,%rax,4), %xmm1
andps .LCPI0_2(%rip), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_9
# %bb.10: # %_Z17check_convolutionPKfS0_i.exit
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 3(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_12
# %bb.11:
leaq 3(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_13
.LBB0_12:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq %rbx, %rdi
movq %r15, %rsi
movl $1000, %edx # imm = 0x3E8
movl $9, %ecx
callq _Z21convolution_cache_gpuPKfPfii
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
xorl %eax, %eax
movaps .LCPI0_2(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB0_14: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r15,%rax,4), %xmm1
andps %xmm2, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_14
# %bb.15: # %_Z17check_convolutionPKfS0_i.exit28
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 3(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_17
# %bb.16:
leaq 3(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_18
.LBB0_17:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit31
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z15convolution_cpuPKfPfS0_ii # -- Begin function _Z15convolution_cpuPKfPfS0_ii
.p2align 4, 0x90
.type _Z15convolution_cpuPKfPfS0_ii,@function
_Z15convolution_cpuPKfPfS0_ii: # @_Z15convolution_cpuPKfPfS0_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %r8d, %r10d
shrl $31, %r10d
addl %r8d, %r10d
sarl %r10d
negl %r10d
movl %ecx, %eax
movl %r8d, %r9d
movl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_2 Depth=1
xorps %xmm0, %xmm0
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movss %xmm0, (%rsi,%r11,4)
incq %r11
incq %r10
cmpq %rax, %r11
je .LBB1_5
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
testl %r8d, %r8d
jle .LBB1_3
# %bb.7: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movslq %r10d, %rbx
leaq (%rdi,%rbx,4), %rbx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
incq %r14
cmpq %r14, %r9
je .LBB1_4
.LBB1_8: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r10,%r14), %ebp
cmpl %ecx, %ebp
jae .LBB1_10
# %bb.9: # in Loop: Header=BB1_8 Depth=2
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%r14,4), %xmm1
addss %xmm1, %xmm0
jmp .LBB1_10
.LBB1_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB1_6: # %._crit_edge30
retq
.Lfunc_end1:
.size _Z15convolution_cpuPKfPfS0_ii, .Lfunc_end1-_Z15convolution_cpuPKfPfS0_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21convolution_tiled_gpuPKfPfii
.LCPI2_0:
.long 0x3b000000 # float 0.001953125
.text
.globl _Z21convolution_tiled_gpuPKfPfii
.p2align 4, 0x90
.type _Z21convolution_tiled_gpuPKfPfii,@function
_Z21convolution_tiled_gpuPKfPfii: # @_Z21convolution_tiled_gpuPKfPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24tiled_convolution_kernelPKfPfii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21convolution_tiled_gpuPKfPfii, .Lfunc_end2-_Z21convolution_tiled_gpuPKfPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17check_convolutionPKfS0_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z17check_convolutionPKfS0_i
.p2align 4, 0x90
.type _Z17check_convolutionPKfS0_i,@function
_Z17check_convolutionPKfS0_i: # @_Z17check_convolutionPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rsi,%rcx,4), %xmm2
andps %xmm1, %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
retq
.LBB3_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end3:
.size _Z17check_convolutionPKfS0_i, .Lfunc_end3-_Z17check_convolutionPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21convolution_cache_gpuPKfPfii
.LCPI4_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl _Z21convolution_cache_gpuPKfPfii
.p2align 4, 0x90
.type _Z21convolution_cache_gpuPKfPfii,@function
_Z21convolution_cache_gpuPKfPfii: # @_Z21convolution_cache_gpuPKfPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24cache_convolution_kernelPKfPfii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z21convolution_cache_gpuPKfPfii, .Lfunc_end4-_Z21convolution_cache_gpuPKfPfii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__tiled_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__tiled_convolution_kernelPKfPfii
.p2align 4, 0x90
.type _Z39__device_stub__tiled_convolution_kernelPKfPfii,@function
_Z39__device_stub__tiled_convolution_kernelPKfPfii: # @_Z39__device_stub__tiled_convolution_kernelPKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24tiled_convolution_kernelPKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z39__device_stub__tiled_convolution_kernelPKfPfii, .Lfunc_end5-_Z39__device_stub__tiled_convolution_kernelPKfPfii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__cache_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__cache_convolution_kernelPKfPfii
.p2align 4, 0x90
.type _Z39__device_stub__cache_convolution_kernelPKfPfii,@function
_Z39__device_stub__cache_convolution_kernelPKfPfii: # @_Z39__device_stub__cache_convolution_kernelPKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24cache_convolution_kernelPKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z39__device_stub__cache_convolution_kernelPKfPfii, .Lfunc_end6-_Z39__device_stub__cache_convolution_kernelPKfPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24tiled_convolution_kernelPKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cache_convolution_kernelPKfPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $mask, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $200, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type mask,@object # @mask
.local mask
.comm mask,200,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Error = "
.size .L.str, 10
.type _Z24tiled_convolution_kernelPKfPfii,@object # @_Z24tiled_convolution_kernelPKfPfii
.section .rodata,"a",@progbits
.globl _Z24tiled_convolution_kernelPKfPfii
.p2align 3, 0x0
_Z24tiled_convolution_kernelPKfPfii:
.quad _Z39__device_stub__tiled_convolution_kernelPKfPfii
.size _Z24tiled_convolution_kernelPKfPfii, 8
.type _Z24cache_convolution_kernelPKfPfii,@object # @_Z24cache_convolution_kernelPKfPfii
.globl _Z24cache_convolution_kernelPKfPfii
.p2align 3, 0x0
_Z24cache_convolution_kernelPKfPfii:
.quad _Z39__device_stub__cache_convolution_kernelPKfPfii
.size _Z24cache_convolution_kernelPKfPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Convolution with tiling and halo runtime: "
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Convolution with L2 cache use runtime: "
.size .L.str.3, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24tiled_convolution_kernelPKfPfii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24cache_convolution_kernelPKfPfii"
.size .L__unnamed_2, 36
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mask"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__tiled_convolution_kernelPKfPfii
.addrsig_sym _Z39__device_stub__cache_convolution_kernelPKfPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mask
.addrsig_sym _ZSt4cout
.addrsig_sym _Z24tiled_convolution_kernelPKfPfii
.addrsig_sym _Z24cache_convolution_kernelPKfPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001050ad_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3717:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3717:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15convolution_cpuPKfPfS0_ii
.type _Z15convolution_cpuPKfPfS0_ii, @function
_Z15convolution_cpuPKfPfS0_ii:
.LFB3713:
.cfi_startproc
endbr64
movl %r8d, %eax
shrl $31, %eax
addl %r8d, %eax
sarl %eax
testl %ecx, %ecx
jle .L13
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movq %rdx, %r11
movl %ecx, %edi
movl %r8d, %ebx
movq %rsi, %r9
movl %r8d, %ecx
subl %eax, %ecx
movslq %eax, %rdx
negq %rdx
leaq (%r10,%rdx,4), %rsi
movl %eax, %r10d
negl %r10d
leal (%rdi,%r8), %r8d
subl %eax, %r8d
jmp .L5
.L6:
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
je .L8
.L7:
cmpl %eax, %edi
jle .L6
testl %eax, %eax
js .L6
movss (%rsi,%rdx), %xmm0
mulss (%r11,%rdx), %xmm0
addss %xmm0, %xmm1
jmp .L6
.L8:
movss %xmm1, (%r9)
addq $4, %r9
addl $1, %ecx
addq $4, %rsi
addl $1, %r10d
cmpl %r8d, %ecx
je .L3
.L5:
movl %r10d, %eax
movl $0, %edx
pxor %xmm1, %xmm1
testl %ebx, %ebx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
ret
.cfi_endproc
.LFE3713:
.size _Z15convolution_cpuPKfPfS0_ii, .-_Z15convolution_cpuPKfPfS0_ii
.globl _Z17check_convolutionPKfS0_i
.type _Z17check_convolutionPKfS0_i, @function
_Z17check_convolutionPKfS0_i:
.LFB3714:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L19
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm0, %xmm0
movss .LC1(%rip), %xmm2
.L18:
movss (%rdi,%rax), %xmm1
subss (%rsi,%rax), %xmm1
andps %xmm2, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rax, %rdx
jne .L18
.L17:
cvtss2sd %xmm0, %xmm0
ret
.L19:
pxor %xmm0, %xmm0
jmp .L17
.cfi_endproc
.LFE3714:
.size _Z17check_convolutionPKfS0_i, .-_Z17check_convolutionPKfS0_i
.globl _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
.type _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii:
.LFB3739:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24tiled_convolution_kernelPKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3739:
.size _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
.globl _Z24tiled_convolution_kernelPKfPfii
.type _Z24tiled_convolution_kernelPKfPfii, @function
_Z24tiled_convolution_kernelPKfPfii:
.LFB3740:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3740:
.size _Z24tiled_convolution_kernelPKfPfii, .-_Z24tiled_convolution_kernelPKfPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Convolution with tiling and halo runtime: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "ms "
.text
.globl _Z21convolution_tiled_gpuPKfPfii
.type _Z21convolution_tiled_gpuPKfPfii, @function
_Z21convolution_tiled_gpuPKfPfii:
.LFB3711:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L30
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L30:
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $42, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z21convolution_tiled_gpuPKfPfii, .-_Z21convolution_tiled_gpuPKfPfii
.globl _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
.type _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii:
.LFB3741:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24cache_convolution_kernelPKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3741:
.size _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
.globl _Z24cache_convolution_kernelPKfPfii
.type _Z24cache_convolution_kernelPKfPfii, @function
_Z24cache_convolution_kernelPKfPfii:
.LFB3742:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3742:
.size _Z24cache_convolution_kernelPKfPfii, .-_Z24cache_convolution_kernelPKfPfii
.section .rodata.str1.8
.align 8
.LC9:
.string "Convolution with L2 cache use runtime: "
.text
.globl _Z21convolution_cache_gpuPKfPfii
.type _Z21convolution_cache_gpuPKfPfii, @function
_Z21convolution_cache_gpuPKfPfii:
.LFB3712:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC8(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L45
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L45:
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L46:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
jmp .L46
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3712:
.size _Z21convolution_cache_gpuPKfPfii, .-_Z21convolution_cache_gpuPKfPfii
.section .rodata.str1.1
.LC16:
.string " Error = "
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movss .LC10(%rip), %xmm0
movss %xmm0, (%rsp)
movss .LC11(%rip), %xmm1
movss %xmm1, 4(%rsp)
movss .LC12(%rip), %xmm2
movss %xmm2, 8(%rsp)
movss .LC13(%rip), %xmm3
movss %xmm3, 12(%rsp)
movl $0x40e00000, 16(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm0, 32(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL4mask(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4000, %edi
call _Znam@PLT
movq %rax, %r12
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movsd .LC15(%rip), %xmm1
.L52:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L52
movq %rsp, %rdx
movl $9, %r8d
movl $1000, %ecx
movq %r12, %rsi
movq %rbx, %rdi
call _Z15convolution_cpuPKfPfS0_ii
movl $9, %ecx
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21convolution_tiled_gpuPKfPfii
leaq .LC16(%rip), %r14
movq %r14, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r15
movl $1000, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17check_convolutionPKfS0_i
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $9, %ecx
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21convolution_cache_gpuPKfPfii
movq %r14, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl $1000, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17check_convolutionPKfS0_i
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z24cache_convolution_kernelPKfPfii"
.align 8
.LC18:
.string "_Z24tiled_convolution_kernelPKfPfii"
.section .rodata.str1.1
.LC19:
.string "mask"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3744:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cache_convolution_kernelPKfPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z24tiled_convolution_kernelPKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4mask(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3744:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4mask
.comm _ZL4mask,200,32
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 989855744
.align 4
.LC3:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.set .LC7,.LC1
.align 4
.LC8:
.long 973078528
.align 4
.LC10:
.long 1077936128
.align 4
.LC11:
.long 1082130432
.align 4
.LC12:
.long 1084227584
.align 4
.LC13:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.LCPI0_1:
.long 0x40e00000 # float 7
.long 0x40c00000 # float 6
.long 0x40a00000 # float 5
.long 0x40800000 # float 4
.LCPI0_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3.0E+0,4.0E+0,5.0E+0,6.0E+0]
movups %xmm0, 4(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [7.0E+0,6.0E+0,5.0E+0,4.0E+0]
movups %xmm0, 20(%rsp)
movl $1077936128, 36(%rsp) # imm = 0x40400000
xorl %r12d, %r12d
leaq 4(%rsp), %rsi
movl $mask, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r14
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movq %rax, %r12
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_1
# %bb.2: # %.preheader.i.preheader
xorl %eax, %eax
movq %rbx, %rcx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # %._crit_edge.i
# in Loop: Header=BB0_3 Depth=1
movss %xmm0, (%r14,%rax,4)
incq %rax
addq $4, %rcx
cmpq $1000, %rax # imm = 0x3E8
je .LBB0_8
.LBB0_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorps %xmm0, %xmm0
movq $-4, %rdx
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
incq %rdx
cmpq $5, %rdx
je .LBB0_7
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
cmpl $999, %esi # imm = 0x3E7
ja .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movss (%rcx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 20(%rsp,%rdx,4), %xmm1
addss %xmm1, %xmm0
jmp .LBB0_6
.LBB0_8: # %_Z15convolution_cpuPKfPfS0_ii.exit
movq %rbx, %rdi
movq %r15, %rsi
movl $1000, %edx # imm = 0x3E8
movl $9, %ecx
callq _Z21convolution_tiled_gpuPKfPfii
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r15,%rax,4), %xmm1
andps .LCPI0_2(%rip), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_9
# %bb.10: # %_Z17check_convolutionPKfS0_i.exit
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 3(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_12
# %bb.11:
leaq 3(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_13
.LBB0_12:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq %rbx, %rdi
movq %r15, %rsi
movl $1000, %edx # imm = 0x3E8
movl $9, %ecx
callq _Z21convolution_cache_gpuPKfPfii
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
xorl %eax, %eax
movaps .LCPI0_2(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB0_14: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r15,%rax,4), %xmm1
andps %xmm2, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_14
# %bb.15: # %_Z17check_convolutionPKfS0_i.exit28
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 3(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_17
# %bb.16:
leaq 3(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_18
.LBB0_17:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit31
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z15convolution_cpuPKfPfS0_ii # -- Begin function _Z15convolution_cpuPKfPfS0_ii
.p2align 4, 0x90
.type _Z15convolution_cpuPKfPfS0_ii,@function
_Z15convolution_cpuPKfPfS0_ii: # @_Z15convolution_cpuPKfPfS0_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %r8d, %r10d
shrl $31, %r10d
addl %r8d, %r10d
sarl %r10d
negl %r10d
movl %ecx, %eax
movl %r8d, %r9d
movl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_2 Depth=1
xorps %xmm0, %xmm0
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movss %xmm0, (%rsi,%r11,4)
incq %r11
incq %r10
cmpq %rax, %r11
je .LBB1_5
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
testl %r8d, %r8d
jle .LBB1_3
# %bb.7: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movslq %r10d, %rbx
leaq (%rdi,%rbx,4), %rbx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
incq %r14
cmpq %r14, %r9
je .LBB1_4
.LBB1_8: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r10,%r14), %ebp
cmpl %ecx, %ebp
jae .LBB1_10
# %bb.9: # in Loop: Header=BB1_8 Depth=2
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%r14,4), %xmm1
addss %xmm1, %xmm0
jmp .LBB1_10
.LBB1_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB1_6: # %._crit_edge30
retq
.Lfunc_end1:
.size _Z15convolution_cpuPKfPfS0_ii, .Lfunc_end1-_Z15convolution_cpuPKfPfS0_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21convolution_tiled_gpuPKfPfii
.LCPI2_0:
.long 0x3b000000 # float 0.001953125
.text
.globl _Z21convolution_tiled_gpuPKfPfii
.p2align 4, 0x90
.type _Z21convolution_tiled_gpuPKfPfii,@function
_Z21convolution_tiled_gpuPKfPfii: # @_Z21convolution_tiled_gpuPKfPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24tiled_convolution_kernelPKfPfii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21convolution_tiled_gpuPKfPfii, .Lfunc_end2-_Z21convolution_tiled_gpuPKfPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17check_convolutionPKfS0_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z17check_convolutionPKfS0_i
.p2align 4, 0x90
.type _Z17check_convolutionPKfS0_i,@function
_Z17check_convolutionPKfS0_i: # @_Z17check_convolutionPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rsi,%rcx,4), %xmm2
andps %xmm1, %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
retq
.LBB3_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end3:
.size _Z17check_convolutionPKfS0_i, .Lfunc_end3-_Z17check_convolutionPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21convolution_cache_gpuPKfPfii
.LCPI4_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl _Z21convolution_cache_gpuPKfPfii
.p2align 4, 0x90
.type _Z21convolution_cache_gpuPKfPfii,@function
_Z21convolution_cache_gpuPKfPfii: # @_Z21convolution_cache_gpuPKfPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24cache_convolution_kernelPKfPfii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z21convolution_cache_gpuPKfPfii, .Lfunc_end4-_Z21convolution_cache_gpuPKfPfii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__tiled_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__tiled_convolution_kernelPKfPfii
.p2align 4, 0x90
.type _Z39__device_stub__tiled_convolution_kernelPKfPfii,@function
_Z39__device_stub__tiled_convolution_kernelPKfPfii: # @_Z39__device_stub__tiled_convolution_kernelPKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24tiled_convolution_kernelPKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z39__device_stub__tiled_convolution_kernelPKfPfii, .Lfunc_end5-_Z39__device_stub__tiled_convolution_kernelPKfPfii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__cache_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__cache_convolution_kernelPKfPfii
.p2align 4, 0x90
.type _Z39__device_stub__cache_convolution_kernelPKfPfii,@function
_Z39__device_stub__cache_convolution_kernelPKfPfii: # @_Z39__device_stub__cache_convolution_kernelPKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24cache_convolution_kernelPKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z39__device_stub__cache_convolution_kernelPKfPfii, .Lfunc_end6-_Z39__device_stub__cache_convolution_kernelPKfPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24tiled_convolution_kernelPKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cache_convolution_kernelPKfPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $mask, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $200, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type mask,@object # @mask
.local mask
.comm mask,200,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Error = "
.size .L.str, 10
.type _Z24tiled_convolution_kernelPKfPfii,@object # @_Z24tiled_convolution_kernelPKfPfii
.section .rodata,"a",@progbits
.globl _Z24tiled_convolution_kernelPKfPfii
.p2align 3, 0x0
_Z24tiled_convolution_kernelPKfPfii:
.quad _Z39__device_stub__tiled_convolution_kernelPKfPfii
.size _Z24tiled_convolution_kernelPKfPfii, 8
.type _Z24cache_convolution_kernelPKfPfii,@object # @_Z24cache_convolution_kernelPKfPfii
.globl _Z24cache_convolution_kernelPKfPfii
.p2align 3, 0x0
_Z24cache_convolution_kernelPKfPfii:
.quad _Z39__device_stub__cache_convolution_kernelPKfPfii
.size _Z24cache_convolution_kernelPKfPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Convolution with tiling and halo runtime: "
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Convolution with L2 cache use runtime: "
.size .L.str.3, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24tiled_convolution_kernelPKfPfii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24cache_convolution_kernelPKfPfii"
.size .L__unnamed_2, 36
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mask"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__tiled_convolution_kernelPKfPfii
.addrsig_sym _Z39__device_stub__cache_convolution_kernelPKfPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mask
.addrsig_sym _ZSt4cout
.addrsig_sym _Z24tiled_convolution_kernelPKfPfii
.addrsig_sym _Z24cache_convolution_kernelPKfPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} | code for sm_80
Function : _Z13sum_reductionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0080*/ ULEA.HI UR4, UR4, UR5, URZ, 0x2 ; /* 0x0000000504047291 */
/* 0x000fe2000f8f103f */
/*0090*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e660000002300 */
/*00a0*/ USHF.R.S32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fe20008011404 */
/*00b0*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00e0*/ @P0 BRA 0x190 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x006fe400000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1d00 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*0160*/ IADD3 R8, R4, R5, R8 ; /* 0x0000000504087210 */
/* 0x004fc80007ffe008 */
/*0170*/ IADD3 R8, R7, R8, R6 ; /* 0x0000000807087210 */
/* 0x000fce0007ffe006 */
/*0180*/ @!P0 BRA 0x100 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x006fea0003800000 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ IMAD R0, R2, c[0x0][0x4], R9 ; /* 0x0000010002007a24 */
/* 0x000fe200078e0209 */
/*01c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*01d0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fe40007ffe1ff */
/*01e0*/ ULDC UR5, c[0x0][0x8] ; /* 0x0000020000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0200*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0210*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0220*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fca0003f05270 */
/*0230*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0240*/ @!P1 BRA 0x330 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0260*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ SHF.L.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057819 */
/* 0x000fe400000006ff */
/*0280*/ ISETP.GT.AND P1, PT, R0.reuse, R3, PT ; /* 0x000000030000720c */
/* 0x040fe20003f24270 */
/*0290*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*02b0*/ ISETP.GT.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f44270 */
/*02c0*/ @P1 IMAD R2, R0.reuse, 0x4, R5 ; /* 0x0000000400021824 */
/* 0x040fe200078e0205 */
/*02d0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*02e0*/ @P1 LDS R7, [R2] ; /* 0x0000000002071984 */
/* 0x000e220000000800 */
/*02f0*/ SHF.R.S32.HI R0, RZ, 0x1, R4 ; /* 0x00000001ff007819 */
/* 0x000fe20000011404 */
/*0300*/ @P1 IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108081824 */
/* 0x001fe400078e0207 */
/*0310*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*0320*/ @P2 BRA 0x280 ; /* 0xffffff5000002947 */
/* 0x000fea000383ffff */
/*0330*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0340*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0350*/ REDUX.SUM UR5, R8 ; /* 0x00000000080573c4 */
/* 0x000e62000000c000 */
/*0360*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0370*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0380*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*03b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*03c0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} | .file "tmpxft_000f73db_00000000-6_sum_reduction_cooperative_groups.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6872:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6872:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.type _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, @function
_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, .-_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.globl _Z10thread_sumPii
.type _Z10thread_sumPii, @function
_Z10thread_sumPii:
.LFB6867:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6867:
.size _Z10thread_sumPii, .-_Z10thread_sumPii
.globl _Z17initialize_vectorPii
.type _Z17initialize_vectorPii, @function
_Z17initialize_vectorPii:
.LFB6868:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L9:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE6868:
.size _Z17initialize_vectorPii, .-_Z17initialize_vectorPii
.globl _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.type _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, @function
_Z36__device_stub__Z13sum_reductionPiS_iPiS_i:
.LFB6894:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_reductionPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6894:
.size _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, .-_Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.globl _Z13sum_reductionPiS_i
.type _Z13sum_reductionPiS_i, @function
_Z13sum_reductionPiS_i:
.LFB6895:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6895:
.size _Z13sum_reductionPiS_i, .-_Z13sum_reductionPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "COMPLTED SUCCESSFULLY\n"
.text
.globl main
.type main, @function
main:
.LFB6869:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32768, %esi
call cudaMallocManaged@PLT
movl $8192, %esi
movq 8(%rsp), %rdi
call _Z17initialize_vectorPii
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $8192, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6869:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13sum_reductionPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std3__419piecewise_constructE"
.align 8
.LC3:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC4:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6897:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_reductionPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6897:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
hipDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
hipDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_reductionPiS_i
.globl _Z13sum_reductionPiS_i
.p2align 8
.type _Z13sum_reductionPiS_i,@function
_Z13sum_reductionPiS_i:
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s8
s_cselect_b32 s4, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_load_b32 s4, s[0:1], 0x10
global_load_u16 v5, v1, s[2:3]
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 30
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s7, s4, 2
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, v5, v[1:2]
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v5, s8, v5
v_mov_b32_e32 v4, 0
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_add_nc_u32_e32 v2, v2, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s7, v2
global_load_b128 v[6:9], v[6:7], off
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add3_u32 v3, v6, v4, v7
v_add3_u32 v4, v3, v8, v9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[2:3], 0xc
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s5, 0xffff
s_mul_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s4
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_10
v_mad_u32_u24 v6, v0, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
v_lshl_add_u32 v3, v2, 2, 0
.p2align 6
.LBB0_6:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, s5, 2, v3
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v6, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
s_mov_b32 s4, s5
s_branch .LBB0_6
.LBB0_10:
v_mad_u32_u24 v0, v0, s3, v5
v_sub_nc_u32_e32 v1, 0, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
s_mov_b32 s2, 0
v_cmpx_eq_u32_e64 v0, v1
s_cbranch_execz .LBB0_15
s_mov_b32 s3, exec_lo
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s4, s3
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_reductionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_reductionPiS_i, .Lfunc_end0-_Z13sum_reductionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_reductionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_reductionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include <iostream>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum( thread_group g, int *temp, int val)
{
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane + i]
for(int i = g.size()/2; i > 0 ; i /= 2)
{
temp[lane] = val;
// wait for all threads to store
g.sync();
if(lane < i)
{
val += temp[lane + i];
}
// wait for all threads to laod
g.sync();
}
// only thread 0 will return full sum
return val;
}
// Create partial sums from the original array
__device__ int thread_sum(int *input, int n)
{
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = tid; i < n / 4; i += blockDim.x * gridDim.x)
{ // cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction( int *sum, int *input, int n )
{
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a Thread Block
auto g = this_thread_block();
// Reduce each Thread Block
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each Thread Block
if (g.thread_rank() == 0)
{
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main()
{ // Vector size
int n = 1<<13;
size_t bytes = n * sizeof(int);
// Original vector and result vector
int *sum;
int *data;
// Allocate using unified memory
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
// Initialize vector
initialize_vector(data, n);
// Thread Block size
int TB_SIZE = 256;
// Grid size ( cut in half )
int GRID_SIZE = (n + TB_SIZE - 1) / TB_SIZE;
// Call kernel with dynamic shared memory ( Could decrease this to fit larger data)
sum_reduction<<< GRID_SIZE, TB_SIZE, n * sizeof(int)>>> (sum, data, n);
// Synchronize the kernel
hipDeviceSynchronize();
assert(*sum == 8192);
printf("COMPLTED SUCCESSFULLY\n");
return 0;
} | .text
.file "sum_reduction_cooperative_groups.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__sum_reductionPiS_i # -- Begin function _Z28__device_stub__sum_reductionPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_reductionPiS_i,@function
_Z28__device_stub__sum_reductionPiS_i: # @_Z28__device_stub__sum_reductionPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_reductionPiS_i, .Lfunc_end0-_Z28__device_stub__sum_reductionPiS_i
.cfi_endproc
# -- End function
.globl _Z17initialize_vectorPii # -- Begin function _Z17initialize_vectorPii
.p2align 4, 0x90
.type _Z17initialize_vectorPii,@function
_Z17initialize_vectorPii: # @_Z17initialize_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17initialize_vectorPii, .Lfunc_end1-_Z17initialize_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rcx,%rax,4)
incq %rax
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_1
# %bb.2: # %_Z17initialize_vectorPii.exit
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $8192, 12(%rsp) # imm = 0x2000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_reductionPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_reductionPiS_i,@object # @_Z13sum_reductionPiS_i
.section .rodata,"a",@progbits
.globl _Z13sum_reductionPiS_i
.p2align 3, 0x0
_Z13sum_reductionPiS_i:
.quad _Z28__device_stub__sum_reductionPiS_i
.size _Z13sum_reductionPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_reductionPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "COMPLTED SUCCESSFULLY"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_reductionPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_reductionPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13sum_reductionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0080*/ ULEA.HI UR4, UR4, UR5, URZ, 0x2 ; /* 0x0000000504047291 */
/* 0x000fe2000f8f103f */
/*0090*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e660000002300 */
/*00a0*/ USHF.R.S32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fe20008011404 */
/*00b0*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00e0*/ @P0 BRA 0x190 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x006fe400000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1d00 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*0160*/ IADD3 R8, R4, R5, R8 ; /* 0x0000000504087210 */
/* 0x004fc80007ffe008 */
/*0170*/ IADD3 R8, R7, R8, R6 ; /* 0x0000000807087210 */
/* 0x000fce0007ffe006 */
/*0180*/ @!P0 BRA 0x100 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x006fea0003800000 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ IMAD R0, R2, c[0x0][0x4], R9 ; /* 0x0000010002007a24 */
/* 0x000fe200078e0209 */
/*01c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*01d0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fe40007ffe1ff */
/*01e0*/ ULDC UR5, c[0x0][0x8] ; /* 0x0000020000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0200*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0210*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0220*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fca0003f05270 */
/*0230*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0240*/ @!P1 BRA 0x330 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0260*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ SHF.L.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057819 */
/* 0x000fe400000006ff */
/*0280*/ ISETP.GT.AND P1, PT, R0.reuse, R3, PT ; /* 0x000000030000720c */
/* 0x040fe20003f24270 */
/*0290*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*02b0*/ ISETP.GT.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f44270 */
/*02c0*/ @P1 IMAD R2, R0.reuse, 0x4, R5 ; /* 0x0000000400021824 */
/* 0x040fe200078e0205 */
/*02d0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*02e0*/ @P1 LDS R7, [R2] ; /* 0x0000000002071984 */
/* 0x000e220000000800 */
/*02f0*/ SHF.R.S32.HI R0, RZ, 0x1, R4 ; /* 0x00000001ff007819 */
/* 0x000fe20000011404 */
/*0300*/ @P1 IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108081824 */
/* 0x001fe400078e0207 */
/*0310*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*0320*/ @P2 BRA 0x280 ; /* 0xffffff5000002947 */
/* 0x000fea000383ffff */
/*0330*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0340*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0350*/ REDUX.SUM UR5, R8 ; /* 0x00000000080573c4 */
/* 0x000e62000000c000 */
/*0360*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0370*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0380*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*03b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*03c0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_reductionPiS_i
.globl _Z13sum_reductionPiS_i
.p2align 8
.type _Z13sum_reductionPiS_i,@function
_Z13sum_reductionPiS_i:
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s8
s_cselect_b32 s4, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_load_b32 s4, s[0:1], 0x10
global_load_u16 v5, v1, s[2:3]
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 30
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s7, s4, 2
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, v5, v[1:2]
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v5, s8, v5
v_mov_b32_e32 v4, 0
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_add_nc_u32_e32 v2, v2, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s7, v2
global_load_b128 v[6:9], v[6:7], off
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add3_u32 v3, v6, v4, v7
v_add3_u32 v4, v3, v8, v9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[2:3], 0xc
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s5, 0xffff
s_mul_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s4
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_10
v_mad_u32_u24 v6, v0, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
v_lshl_add_u32 v3, v2, 2, 0
.p2align 6
.LBB0_6:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, s5, 2, v3
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v6, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
s_mov_b32 s4, s5
s_branch .LBB0_6
.LBB0_10:
v_mad_u32_u24 v0, v0, s3, v5
v_sub_nc_u32_e32 v1, 0, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
s_mov_b32 s2, 0
v_cmpx_eq_u32_e64 v0, v1
s_cbranch_execz .LBB0_15
s_mov_b32 s3, exec_lo
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s4, s3
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_reductionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_reductionPiS_i, .Lfunc_end0-_Z13sum_reductionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_reductionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_reductionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f73db_00000000-6_sum_reduction_cooperative_groups.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6872:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6872:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.type _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, @function
_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, .-_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.globl _Z10thread_sumPii
.type _Z10thread_sumPii, @function
_Z10thread_sumPii:
.LFB6867:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6867:
.size _Z10thread_sumPii, .-_Z10thread_sumPii
.globl _Z17initialize_vectorPii
.type _Z17initialize_vectorPii, @function
_Z17initialize_vectorPii:
.LFB6868:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L9:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE6868:
.size _Z17initialize_vectorPii, .-_Z17initialize_vectorPii
.globl _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.type _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, @function
_Z36__device_stub__Z13sum_reductionPiS_iPiS_i:
.LFB6894:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_reductionPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6894:
.size _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, .-_Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.globl _Z13sum_reductionPiS_i
.type _Z13sum_reductionPiS_i, @function
_Z13sum_reductionPiS_i:
.LFB6895:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6895:
.size _Z13sum_reductionPiS_i, .-_Z13sum_reductionPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "COMPLTED SUCCESSFULLY\n"
.text
.globl main
.type main, @function
main:
.LFB6869:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32768, %esi
call cudaMallocManaged@PLT
movl $8192, %esi
movq 8(%rsp), %rdi
call _Z17initialize_vectorPii
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $8192, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6869:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13sum_reductionPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std3__419piecewise_constructE"
.align 8
.LC3:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC4:
.string "_ZN66_INTERNAL_46bb29b4_35_sum_reduction_cooperative_groups_cu_115040b94cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6897:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_reductionPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6897:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_reduction_cooperative_groups.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__sum_reductionPiS_i # -- Begin function _Z28__device_stub__sum_reductionPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_reductionPiS_i,@function
_Z28__device_stub__sum_reductionPiS_i: # @_Z28__device_stub__sum_reductionPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_reductionPiS_i, .Lfunc_end0-_Z28__device_stub__sum_reductionPiS_i
.cfi_endproc
# -- End function
.globl _Z17initialize_vectorPii # -- Begin function _Z17initialize_vectorPii
.p2align 4, 0x90
.type _Z17initialize_vectorPii,@function
_Z17initialize_vectorPii: # @_Z17initialize_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17initialize_vectorPii, .Lfunc_end1-_Z17initialize_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rcx,%rax,4)
incq %rax
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_1
# %bb.2: # %_Z17initialize_vectorPii.exit
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $8192, 12(%rsp) # imm = 0x2000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_reductionPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_reductionPiS_i,@object # @_Z13sum_reductionPiS_i
.section .rodata,"a",@progbits
.globl _Z13sum_reductionPiS_i
.p2align 3, 0x0
_Z13sum_reductionPiS_i:
.quad _Z28__device_stub__sum_reductionPiS_i
.size _Z13sum_reductionPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_reductionPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "COMPLTED SUCCESSFULLY"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_reductionPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_reductionPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
__device__ double dist(double x1, double y1, double x2, double y2){
return sqrt((x1-x2)*(x1-x2) + (y1-y2)*(y1-y2));
}
__global__ void testKernel(double *xs, double *ys, double *b){
b[blockIdx.x] = dist(xs[blockIdx.x], 1.0, ys[blockIdx.x], 1.0);
}
/* r^3 */
__device__ double rbf(double x1, double y1, double x2, double y2){
return pow(dist(x1, y1, x2, y2),3);
}
/* 6*r */
__device__ double rbfd2(double x1, double y1, double x2, double y2){
return 6*dist(x1, y1, x2, y2);
}
/* Gaussian Elimination */
__device__ void gauss_elim(double *A, double *b, double *x, int n){
int i, j, k;
int idxi, idxj, idxij, idxik, idxjk;
double m, diff;
// Swap first and second rows
int r1 = 0;
int r2 = 1;
double mtemp, vtemp;
int idx1;
int idx2;
for (i = 0; i < n; ++i)
{
// matrix swap
idx1 = r1*n + i;
idx2 = r2*n + i;
mtemp = A[idx1];
A[idx1] = A[idx2];
A[idx2] = mtemp;
}
// RHS vector swap
vtemp = b[1];
b[1] = b[0];
b[0] = vtemp;
// Gauss-Jordan Forward Elimination to Upper triangular matrix
for (j = 0; j < n-1; j++){
for (i = j+1; i < n; i++){
idxij = i*n + j;
idxj = j*n + j;
m = A[idxij]/A[idxj];
for (k = 0; k < n; k++){
idxik = i*n + k;
idxjk = j*n + k;
A[idxik] = A[idxik] - m*A[idxjk];
}
b[i] = b[i] - m*b[j];
}
}
// Back substituion
for (i = n-1; i >= 0; i--){
diff = b[i];
for (j = i+1; j < n; j++){
idxij = i*n + j;
diff = diff - x[j]*A[idxij];
}
idxi = i*n + i;
x[i] = diff/A[idxi];
}
}
__device__ void build_stencil_matrix(double* xs, double* ys,
int* nn, double* full_mat1, double* RHS1,
int l_max, int l, int deg, int k){
int pdim = (deg+1)*(deg+2)/2;
int i, j;
// Make matrix 0
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
// Build A and O matrices
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
if(i < l && j < l){
full_mat1[i*(l+pdim)+j] = rbf(
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]],
xs[nn[k*l_max+j]], ys[nn[k*l_max+j]]);
}
else if(i >= l && j>= l){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
}
// Build P matrix
int d = deg;
int xp = 0;
int yp = d;
for(j = l+pdim - 1; j >= l; j--){
for(i = 0; i < l; i++){
full_mat1[i*(l+pdim) + j] =
pow(xs[nn[k*l_max+i]] - xs[nn[k*l_max+0]], xp) *
pow(ys[nn[k*l_max+i]] - ys[nn[k+l_max+0]], yp);
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// Build P transpose matrix
d = deg;
xp = 0;
yp = d;
for(i = l+pdim - 1; i >= l; i--){
for(j = 0; j < l; j++){
//full_mat1[i*(l+pdim) + j] = pow(xs[nn[k*l+j]],xp)*pow(ys[nn[k*l+j]],yp);
full_mat1[i*(l+pdim) + j] = full_mat1[j*(l+pdim) + i];
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// RHS vector
for(i = 0; i < l + pdim; i++){
if(i < l){
RHS1[i] = rbfd2(
xs[nn[k*l_max+0]], ys[nn[k*l_max+0]],
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]]);
}
else if(i==l+3 || i==l+5){
RHS1[i] = 2.0;
}
else{
RHS1[i] = 0.0;
}
}
}
__global__ void genDMatrix(int n, double* xs, double* ys,
int* nn, double* weights_root,
double* full_mat1_root, double* RHS1_root,
int l_max, int l, int deg){
int my_id = blockDim.x*blockIdx.x + threadIdx.x;
int pdim = (deg+1)*(deg+2)/2;
if(my_id <n){
double* full_mat1 = &full_mat1_root[my_id * (l+pdim)*(l+pdim)];
double* RHS1 = &RHS1_root[my_id * (l+pdim)];
double* weights = &weights_root[my_id * (l+pdim)];
build_stencil_matrix(xs, ys, nn, full_mat1, RHS1, l_max, l, deg, my_id);
gauss_elim(full_mat1, RHS1, weights, l+pdim);
}
} | .file "tmpxft_0015aace_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4distdddd
.type _Z4distdddd, @function
_Z4distdddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4distdddd, .-_Z4distdddd
.globl _Z3rbfdddd
.type _Z3rbfdddd, @function
_Z3rbfdddd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3rbfdddd, .-_Z3rbfdddd
.globl _Z5rbfd2dddd
.type _Z5rbfd2dddd, @function
_Z5rbfd2dddd:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5rbfd2dddd, .-_Z5rbfd2dddd
.globl _Z10gauss_elimPdS_S_i
.type _Z10gauss_elimPdS_S_i, @function
_Z10gauss_elimPdS_S_i:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z10gauss_elimPdS_S_i, .-_Z10gauss_elimPdS_S_i
.globl _Z20build_stencil_matrixPdS_PiS_S_iiii
.type _Z20build_stencil_matrixPdS_PiS_S_iiii, @function
_Z20build_stencil_matrixPdS_PiS_S_iiii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z20build_stencil_matrixPdS_PiS_S_iiii, .-_Z20build_stencil_matrixPdS_PiS_S_iiii
.globl _Z34__device_stub__Z10testKernelPdS_S_PdS_S_
.type _Z34__device_stub__Z10testKernelPdS_S_PdS_S_, @function
_Z34__device_stub__Z10testKernelPdS_S_PdS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10testKernelPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z34__device_stub__Z10testKernelPdS_S_PdS_S_, .-_Z34__device_stub__Z10testKernelPdS_S_PdS_S_
.globl _Z10testKernelPdS_S_
.type _Z10testKernelPdS_S_, @function
_Z10testKernelPdS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10testKernelPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10testKernelPdS_S_, .-_Z10testKernelPdS_S_
.globl _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
.type _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii, @function
_Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10genDMatrixiPdS_PiS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii, .-_Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
.globl _Z10genDMatrixiPdS_PiS_S_S_iii
.type _Z10genDMatrixiPdS_PiS_S_S_iii, @function
_Z10genDMatrixiPdS_PiS_S_S_iii:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10genDMatrixiPdS_PiS_S_S_iii, .-_Z10genDMatrixiPdS_PiS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10genDMatrixiPdS_PiS_S_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10testKernelPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10genDMatrixiPdS_PiS_S_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKernelPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
__device__ double dist(double x1, double y1, double x2, double y2){
return sqrt((x1-x2)*(x1-x2) + (y1-y2)*(y1-y2));
}
__global__ void testKernel(double *xs, double *ys, double *b){
b[blockIdx.x] = dist(xs[blockIdx.x], 1.0, ys[blockIdx.x], 1.0);
}
/* r^3 */
__device__ double rbf(double x1, double y1, double x2, double y2){
return pow(dist(x1, y1, x2, y2),3);
}
/* 6*r */
__device__ double rbfd2(double x1, double y1, double x2, double y2){
return 6*dist(x1, y1, x2, y2);
}
/* Gaussian Elimination */
__device__ void gauss_elim(double *A, double *b, double *x, int n){
int i, j, k;
int idxi, idxj, idxij, idxik, idxjk;
double m, diff;
// Swap first and second rows
int r1 = 0;
int r2 = 1;
double mtemp, vtemp;
int idx1;
int idx2;
for (i = 0; i < n; ++i)
{
// matrix swap
idx1 = r1*n + i;
idx2 = r2*n + i;
mtemp = A[idx1];
A[idx1] = A[idx2];
A[idx2] = mtemp;
}
// RHS vector swap
vtemp = b[1];
b[1] = b[0];
b[0] = vtemp;
// Gauss-Jordan Forward Elimination to Upper triangular matrix
for (j = 0; j < n-1; j++){
for (i = j+1; i < n; i++){
idxij = i*n + j;
idxj = j*n + j;
m = A[idxij]/A[idxj];
for (k = 0; k < n; k++){
idxik = i*n + k;
idxjk = j*n + k;
A[idxik] = A[idxik] - m*A[idxjk];
}
b[i] = b[i] - m*b[j];
}
}
// Back substituion
for (i = n-1; i >= 0; i--){
diff = b[i];
for (j = i+1; j < n; j++){
idxij = i*n + j;
diff = diff - x[j]*A[idxij];
}
idxi = i*n + i;
x[i] = diff/A[idxi];
}
}
__device__ void build_stencil_matrix(double* xs, double* ys,
int* nn, double* full_mat1, double* RHS1,
int l_max, int l, int deg, int k){
int pdim = (deg+1)*(deg+2)/2;
int i, j;
// Make matrix 0
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
// Build A and O matrices
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
if(i < l && j < l){
full_mat1[i*(l+pdim)+j] = rbf(
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]],
xs[nn[k*l_max+j]], ys[nn[k*l_max+j]]);
}
else if(i >= l && j>= l){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
}
// Build P matrix
int d = deg;
int xp = 0;
int yp = d;
for(j = l+pdim - 1; j >= l; j--){
for(i = 0; i < l; i++){
full_mat1[i*(l+pdim) + j] =
pow(xs[nn[k*l_max+i]] - xs[nn[k*l_max+0]], xp) *
pow(ys[nn[k*l_max+i]] - ys[nn[k+l_max+0]], yp);
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// Build P transpose matrix
d = deg;
xp = 0;
yp = d;
for(i = l+pdim - 1; i >= l; i--){
for(j = 0; j < l; j++){
//full_mat1[i*(l+pdim) + j] = pow(xs[nn[k*l+j]],xp)*pow(ys[nn[k*l+j]],yp);
full_mat1[i*(l+pdim) + j] = full_mat1[j*(l+pdim) + i];
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// RHS vector
for(i = 0; i < l + pdim; i++){
if(i < l){
RHS1[i] = rbfd2(
xs[nn[k*l_max+0]], ys[nn[k*l_max+0]],
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]]);
}
else if(i==l+3 || i==l+5){
RHS1[i] = 2.0;
}
else{
RHS1[i] = 0.0;
}
}
}
__global__ void genDMatrix(int n, double* xs, double* ys,
int* nn, double* weights_root,
double* full_mat1_root, double* RHS1_root,
int l_max, int l, int deg){
int my_id = blockDim.x*blockIdx.x + threadIdx.x;
int pdim = (deg+1)*(deg+2)/2;
if(my_id <n){
double* full_mat1 = &full_mat1_root[my_id * (l+pdim)*(l+pdim)];
double* RHS1 = &RHS1_root[my_id * (l+pdim)];
double* weights = &weights_root[my_id * (l+pdim)];
build_stencil_matrix(xs, ys, nn, full_mat1, RHS1, l_max, l, deg, my_id);
gauss_elim(full_mat1, RHS1, weights, l+pdim);
}
} | #include <hip/hip_runtime.h>
#include <math.h>
__device__ double dist(double x1, double y1, double x2, double y2){
return sqrt((x1-x2)*(x1-x2) + (y1-y2)*(y1-y2));
}
__global__ void testKernel(double *xs, double *ys, double *b){
b[blockIdx.x] = dist(xs[blockIdx.x], 1.0, ys[blockIdx.x], 1.0);
}
/* r^3 */
__device__ double rbf(double x1, double y1, double x2, double y2){
return pow(dist(x1, y1, x2, y2),3);
}
/* 6*r */
__device__ double rbfd2(double x1, double y1, double x2, double y2){
return 6*dist(x1, y1, x2, y2);
}
/* Gaussian Elimination */
__device__ void gauss_elim(double *A, double *b, double *x, int n){
int i, j, k;
int idxi, idxj, idxij, idxik, idxjk;
double m, diff;
// Swap first and second rows
int r1 = 0;
int r2 = 1;
double mtemp, vtemp;
int idx1;
int idx2;
for (i = 0; i < n; ++i)
{
// matrix swap
idx1 = r1*n + i;
idx2 = r2*n + i;
mtemp = A[idx1];
A[idx1] = A[idx2];
A[idx2] = mtemp;
}
// RHS vector swap
vtemp = b[1];
b[1] = b[0];
b[0] = vtemp;
// Gauss-Jordan Forward Elimination to Upper triangular matrix
for (j = 0; j < n-1; j++){
for (i = j+1; i < n; i++){
idxij = i*n + j;
idxj = j*n + j;
m = A[idxij]/A[idxj];
for (k = 0; k < n; k++){
idxik = i*n + k;
idxjk = j*n + k;
A[idxik] = A[idxik] - m*A[idxjk];
}
b[i] = b[i] - m*b[j];
}
}
// Back substituion
for (i = n-1; i >= 0; i--){
diff = b[i];
for (j = i+1; j < n; j++){
idxij = i*n + j;
diff = diff - x[j]*A[idxij];
}
idxi = i*n + i;
x[i] = diff/A[idxi];
}
}
__device__ void build_stencil_matrix(double* xs, double* ys,
int* nn, double* full_mat1, double* RHS1,
int l_max, int l, int deg, int k){
int pdim = (deg+1)*(deg+2)/2;
int i, j;
// Make matrix 0
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
// Build A and O matrices
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
if(i < l && j < l){
full_mat1[i*(l+pdim)+j] = rbf(
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]],
xs[nn[k*l_max+j]], ys[nn[k*l_max+j]]);
}
else if(i >= l && j>= l){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
}
// Build P matrix
int d = deg;
int xp = 0;
int yp = d;
for(j = l+pdim - 1; j >= l; j--){
for(i = 0; i < l; i++){
full_mat1[i*(l+pdim) + j] =
pow(xs[nn[k*l_max+i]] - xs[nn[k*l_max+0]], xp) *
pow(ys[nn[k*l_max+i]] - ys[nn[k+l_max+0]], yp);
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// Build P transpose matrix
d = deg;
xp = 0;
yp = d;
for(i = l+pdim - 1; i >= l; i--){
for(j = 0; j < l; j++){
//full_mat1[i*(l+pdim) + j] = pow(xs[nn[k*l+j]],xp)*pow(ys[nn[k*l+j]],yp);
full_mat1[i*(l+pdim) + j] = full_mat1[j*(l+pdim) + i];
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// RHS vector
for(i = 0; i < l + pdim; i++){
if(i < l){
RHS1[i] = rbfd2(
xs[nn[k*l_max+0]], ys[nn[k*l_max+0]],
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]]);
}
else if(i==l+3 || i==l+5){
RHS1[i] = 2.0;
}
else{
RHS1[i] = 0.0;
}
}
}
__global__ void genDMatrix(int n, double* xs, double* ys,
int* nn, double* weights_root,
double* full_mat1_root, double* RHS1_root,
int l_max, int l, int deg){
int my_id = blockDim.x*blockIdx.x + threadIdx.x;
int pdim = (deg+1)*(deg+2)/2;
if(my_id <n){
double* full_mat1 = &full_mat1_root[my_id * (l+pdim)*(l+pdim)];
double* RHS1 = &RHS1_root[my_id * (l+pdim)];
double* weights = &weights_root[my_id * (l+pdim)];
build_stencil_matrix(xs, ys, nn, full_mat1, RHS1, l_max, l, deg, my_id);
gauss_elim(full_mat1, RHS1, weights, l+pdim);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
__device__ double dist(double x1, double y1, double x2, double y2){
return sqrt((x1-x2)*(x1-x2) + (y1-y2)*(y1-y2));
}
__global__ void testKernel(double *xs, double *ys, double *b){
b[blockIdx.x] = dist(xs[blockIdx.x], 1.0, ys[blockIdx.x], 1.0);
}
/* r^3 */
__device__ double rbf(double x1, double y1, double x2, double y2){
return pow(dist(x1, y1, x2, y2),3);
}
/* 6*r */
__device__ double rbfd2(double x1, double y1, double x2, double y2){
return 6*dist(x1, y1, x2, y2);
}
/* Gaussian Elimination */
__device__ void gauss_elim(double *A, double *b, double *x, int n){
int i, j, k;
int idxi, idxj, idxij, idxik, idxjk;
double m, diff;
// Swap first and second rows
int r1 = 0;
int r2 = 1;
double mtemp, vtemp;
int idx1;
int idx2;
for (i = 0; i < n; ++i)
{
// matrix swap
idx1 = r1*n + i;
idx2 = r2*n + i;
mtemp = A[idx1];
A[idx1] = A[idx2];
A[idx2] = mtemp;
}
// RHS vector swap
vtemp = b[1];
b[1] = b[0];
b[0] = vtemp;
// Gauss-Jordan Forward Elimination to Upper triangular matrix
for (j = 0; j < n-1; j++){
for (i = j+1; i < n; i++){
idxij = i*n + j;
idxj = j*n + j;
m = A[idxij]/A[idxj];
for (k = 0; k < n; k++){
idxik = i*n + k;
idxjk = j*n + k;
A[idxik] = A[idxik] - m*A[idxjk];
}
b[i] = b[i] - m*b[j];
}
}
// Back substituion
for (i = n-1; i >= 0; i--){
diff = b[i];
for (j = i+1; j < n; j++){
idxij = i*n + j;
diff = diff - x[j]*A[idxij];
}
idxi = i*n + i;
x[i] = diff/A[idxi];
}
}
__device__ void build_stencil_matrix(double* xs, double* ys,
int* nn, double* full_mat1, double* RHS1,
int l_max, int l, int deg, int k){
int pdim = (deg+1)*(deg+2)/2;
int i, j;
// Make matrix 0
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
// Build A and O matrices
for(i = 0; i < l + pdim; i++){
for(j = 0; j < l + pdim; j++){
if(i < l && j < l){
full_mat1[i*(l+pdim)+j] = rbf(
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]],
xs[nn[k*l_max+j]], ys[nn[k*l_max+j]]);
}
else if(i >= l && j>= l){
full_mat1[i*(l+pdim) + j] = 0.0;
}
}
}
// Build P matrix
int d = deg;
int xp = 0;
int yp = d;
for(j = l+pdim - 1; j >= l; j--){
for(i = 0; i < l; i++){
full_mat1[i*(l+pdim) + j] =
pow(xs[nn[k*l_max+i]] - xs[nn[k*l_max+0]], xp) *
pow(ys[nn[k*l_max+i]] - ys[nn[k+l_max+0]], yp);
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// Build P transpose matrix
d = deg;
xp = 0;
yp = d;
for(i = l+pdim - 1; i >= l; i--){
for(j = 0; j < l; j++){
//full_mat1[i*(l+pdim) + j] = pow(xs[nn[k*l+j]],xp)*pow(ys[nn[k*l+j]],yp);
full_mat1[i*(l+pdim) + j] = full_mat1[j*(l+pdim) + i];
}
if(yp - 1 < 0){
--d;
yp = d;
xp = 0;
}
else{
xp++;
yp--;
}
}
// RHS vector
for(i = 0; i < l + pdim; i++){
if(i < l){
RHS1[i] = rbfd2(
xs[nn[k*l_max+0]], ys[nn[k*l_max+0]],
xs[nn[k*l_max+i]], ys[nn[k*l_max+i]]);
}
else if(i==l+3 || i==l+5){
RHS1[i] = 2.0;
}
else{
RHS1[i] = 0.0;
}
}
}
__global__ void genDMatrix(int n, double* xs, double* ys,
int* nn, double* weights_root,
double* full_mat1_root, double* RHS1_root,
int l_max, int l, int deg){
int my_id = blockDim.x*blockIdx.x + threadIdx.x;
int pdim = (deg+1)*(deg+2)/2;
if(my_id <n){
double* full_mat1 = &full_mat1_root[my_id * (l+pdim)*(l+pdim)];
double* RHS1 = &RHS1_root[my_id * (l+pdim)];
double* weights = &weights_root[my_id * (l+pdim)];
build_stencil_matrix(xs, ys, nn, full_mat1, RHS1, l_max, l, deg, my_id);
gauss_elim(full_mat1, RHS1, weights, l+pdim);
}
} | .text
.file "kernels.hip"
.globl _Z25__device_stub__testKernelPdS_S_ # -- Begin function _Z25__device_stub__testKernelPdS_S_
.p2align 4, 0x90
.type _Z25__device_stub__testKernelPdS_S_,@function
_Z25__device_stub__testKernelPdS_S_: # @_Z25__device_stub__testKernelPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10testKernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__testKernelPdS_S_, .Lfunc_end0-_Z25__device_stub__testKernelPdS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii # -- Begin function _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii,@function
_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii: # @_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10genDMatrixiPdS_PiS_S_S_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii, .Lfunc_end1-_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKernelPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10genDMatrixiPdS_PiS_S_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKernelPdS_S_,@object # @_Z10testKernelPdS_S_
.section .rodata,"a",@progbits
.globl _Z10testKernelPdS_S_
.p2align 3, 0x0
_Z10testKernelPdS_S_:
.quad _Z25__device_stub__testKernelPdS_S_
.size _Z10testKernelPdS_S_, 8
.type _Z10genDMatrixiPdS_PiS_S_S_iii,@object # @_Z10genDMatrixiPdS_PiS_S_S_iii
.globl _Z10genDMatrixiPdS_PiS_S_S_iii
.p2align 3, 0x0
_Z10genDMatrixiPdS_PiS_S_S_iii:
.quad _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.size _Z10genDMatrixiPdS_PiS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKernelPdS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10genDMatrixiPdS_PiS_S_S_iii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKernelPdS_S_
.addrsig_sym _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKernelPdS_S_
.addrsig_sym _Z10genDMatrixiPdS_PiS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015aace_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4distdddd
.type _Z4distdddd, @function
_Z4distdddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4distdddd, .-_Z4distdddd
.globl _Z3rbfdddd
.type _Z3rbfdddd, @function
_Z3rbfdddd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3rbfdddd, .-_Z3rbfdddd
.globl _Z5rbfd2dddd
.type _Z5rbfd2dddd, @function
_Z5rbfd2dddd:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5rbfd2dddd, .-_Z5rbfd2dddd
.globl _Z10gauss_elimPdS_S_i
.type _Z10gauss_elimPdS_S_i, @function
_Z10gauss_elimPdS_S_i:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z10gauss_elimPdS_S_i, .-_Z10gauss_elimPdS_S_i
.globl _Z20build_stencil_matrixPdS_PiS_S_iiii
.type _Z20build_stencil_matrixPdS_PiS_S_iiii, @function
_Z20build_stencil_matrixPdS_PiS_S_iiii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z20build_stencil_matrixPdS_PiS_S_iiii, .-_Z20build_stencil_matrixPdS_PiS_S_iiii
.globl _Z34__device_stub__Z10testKernelPdS_S_PdS_S_
.type _Z34__device_stub__Z10testKernelPdS_S_PdS_S_, @function
_Z34__device_stub__Z10testKernelPdS_S_PdS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10testKernelPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z34__device_stub__Z10testKernelPdS_S_PdS_S_, .-_Z34__device_stub__Z10testKernelPdS_S_PdS_S_
.globl _Z10testKernelPdS_S_
.type _Z10testKernelPdS_S_, @function
_Z10testKernelPdS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10testKernelPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10testKernelPdS_S_, .-_Z10testKernelPdS_S_
.globl _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
.type _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii, @function
_Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10genDMatrixiPdS_PiS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii, .-_Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
.globl _Z10genDMatrixiPdS_PiS_S_S_iii
.type _Z10genDMatrixiPdS_PiS_S_S_iii, @function
_Z10genDMatrixiPdS_PiS_S_S_iii:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z10genDMatrixiPdS_PiS_S_S_iiiiPdS_PiS_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10genDMatrixiPdS_PiS_S_S_iii, .-_Z10genDMatrixiPdS_PiS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10genDMatrixiPdS_PiS_S_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10testKernelPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10genDMatrixiPdS_PiS_S_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKernelPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z25__device_stub__testKernelPdS_S_ # -- Begin function _Z25__device_stub__testKernelPdS_S_
.p2align 4, 0x90
.type _Z25__device_stub__testKernelPdS_S_,@function
_Z25__device_stub__testKernelPdS_S_: # @_Z25__device_stub__testKernelPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10testKernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__testKernelPdS_S_, .Lfunc_end0-_Z25__device_stub__testKernelPdS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii # -- Begin function _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii,@function
_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii: # @_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10genDMatrixiPdS_PiS_S_S_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii, .Lfunc_end1-_Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKernelPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10genDMatrixiPdS_PiS_S_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKernelPdS_S_,@object # @_Z10testKernelPdS_S_
.section .rodata,"a",@progbits
.globl _Z10testKernelPdS_S_
.p2align 3, 0x0
_Z10testKernelPdS_S_:
.quad _Z25__device_stub__testKernelPdS_S_
.size _Z10testKernelPdS_S_, 8
.type _Z10genDMatrixiPdS_PiS_S_S_iii,@object # @_Z10genDMatrixiPdS_PiS_S_S_iii
.globl _Z10genDMatrixiPdS_PiS_S_S_iii
.p2align 3, 0x0
_Z10genDMatrixiPdS_PiS_S_S_iii:
.quad _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.size _Z10genDMatrixiPdS_PiS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKernelPdS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10genDMatrixiPdS_PiS_S_S_iii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKernelPdS_S_
.addrsig_sym _Z25__device_stub__genDMatrixiPdS_PiS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKernelPdS_S_
.addrsig_sym _Z10genDMatrixiPdS_PiS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} | code for sm_80
Function : _Z21kernelSetDoubleBufferPffm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x040fe200078010ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} | .file "tmpxft_0008cf3c_00000000-6_kernelSetDoubleBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
.type _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm, @function
_Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernelSetDoubleBufferPffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm, .-_Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
.globl _Z21kernelSetDoubleBufferPffm
.type _Z21kernelSetDoubleBufferPffm, @function
_Z21kernelSetDoubleBufferPffm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21kernelSetDoubleBufferPffm, .-_Z21kernelSetDoubleBufferPffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21kernelSetDoubleBufferPffm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernelSetDoubleBufferPffm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21kernelSetDoubleBufferPffm
.globl _Z21kernelSetDoubleBufferPffm
.p2align 8
.type _Z21kernelSetDoubleBufferPffm,@function
_Z21kernelSetDoubleBufferPffm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21kernelSetDoubleBufferPffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21kernelSetDoubleBufferPffm, .Lfunc_end0-_Z21kernelSetDoubleBufferPffm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21kernelSetDoubleBufferPffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21kernelSetDoubleBufferPffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* @brief cudaCreateBuffer Allocates a cuda buffer and stops the programm on error.
* @param size
* @return
*/
__global__ void kernelSetDoubleBuffer(float* gpuBuffPtr, float v, size_t size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < size)
gpuBuffPtr[index] = v;
} | .text
.file "kernelSetDoubleBuffer.hip"
.globl _Z36__device_stub__kernelSetDoubleBufferPffm # -- Begin function _Z36__device_stub__kernelSetDoubleBufferPffm
.p2align 4, 0x90
.type _Z36__device_stub__kernelSetDoubleBufferPffm,@function
_Z36__device_stub__kernelSetDoubleBufferPffm: # @_Z36__device_stub__kernelSetDoubleBufferPffm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernelSetDoubleBufferPffm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__kernelSetDoubleBufferPffm, .Lfunc_end0-_Z36__device_stub__kernelSetDoubleBufferPffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernelSetDoubleBufferPffm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21kernelSetDoubleBufferPffm,@object # @_Z21kernelSetDoubleBufferPffm
.section .rodata,"a",@progbits
.globl _Z21kernelSetDoubleBufferPffm
.p2align 3, 0x0
_Z21kernelSetDoubleBufferPffm:
.quad _Z36__device_stub__kernelSetDoubleBufferPffm
.size _Z21kernelSetDoubleBufferPffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernelSetDoubleBufferPffm"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernelSetDoubleBufferPffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernelSetDoubleBufferPffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21kernelSetDoubleBufferPffm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x040fe200078010ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21kernelSetDoubleBufferPffm
.globl _Z21kernelSetDoubleBufferPffm
.p2align 8
.type _Z21kernelSetDoubleBufferPffm,@function
_Z21kernelSetDoubleBufferPffm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21kernelSetDoubleBufferPffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21kernelSetDoubleBufferPffm, .Lfunc_end0-_Z21kernelSetDoubleBufferPffm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21kernelSetDoubleBufferPffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21kernelSetDoubleBufferPffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008cf3c_00000000-6_kernelSetDoubleBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
.type _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm, @function
_Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernelSetDoubleBufferPffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm, .-_Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
.globl _Z21kernelSetDoubleBufferPffm
.type _Z21kernelSetDoubleBufferPffm, @function
_Z21kernelSetDoubleBufferPffm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21kernelSetDoubleBufferPffmPffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21kernelSetDoubleBufferPffm, .-_Z21kernelSetDoubleBufferPffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21kernelSetDoubleBufferPffm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernelSetDoubleBufferPffm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelSetDoubleBuffer.hip"
.globl _Z36__device_stub__kernelSetDoubleBufferPffm # -- Begin function _Z36__device_stub__kernelSetDoubleBufferPffm
.p2align 4, 0x90
.type _Z36__device_stub__kernelSetDoubleBufferPffm,@function
_Z36__device_stub__kernelSetDoubleBufferPffm: # @_Z36__device_stub__kernelSetDoubleBufferPffm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernelSetDoubleBufferPffm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__kernelSetDoubleBufferPffm, .Lfunc_end0-_Z36__device_stub__kernelSetDoubleBufferPffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernelSetDoubleBufferPffm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21kernelSetDoubleBufferPffm,@object # @_Z21kernelSetDoubleBufferPffm
.section .rodata,"a",@progbits
.globl _Z21kernelSetDoubleBufferPffm
.p2align 3, 0x0
_Z21kernelSetDoubleBufferPffm:
.quad _Z36__device_stub__kernelSetDoubleBufferPffm
.size _Z21kernelSetDoubleBufferPffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernelSetDoubleBufferPffm"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernelSetDoubleBufferPffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernelSetDoubleBufferPffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/fill.h>
struct saxpy_functor
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
int main()
{
// initial values
std::vector<float> h_x = { 1.0, 2.0, 3.0 };
std::vector<float> h_y = { 4.0, 5.0, 6.0 };
// init device
float A = 2.0;
thrust::device_vector<float> X;
thrust::device_vector<float> Y;
X = h_x;
Y = h_y;
saxpy_slow(A, X, Y);
// move data from device to host
thrust::host_vector<float> result;
result = Y;
// print result ( A*X + Y )
std::cout << "A = " << A << std::endl;
std::cout << "X = ";
for (auto x : h_x) {
std::cout << x << ", ";
}
std::cout << std::endl;
std::cout << "Y = ";
for (auto y : h_y) {
std::cout << y << ", ";
}
std::cout << std::endl;
std::cout << "A * X + Y = ";
for (int i = 0; i < result.size(); i++) {
std::cout << result[i] << ", ";
}
std::cout << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagENS7_4plusIfEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R9, R6, R5 ; /* 0x0000000506097221 */
/* 0x005fca0000000000 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagENS7_10multipliesIfEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x004fca0000400000 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FMUL R9, R6, R5 ; /* 0x0000000506097220 */
/* 0x005fca0000400000 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x004fca0000400000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x004fca0000400000 */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagE13saxpy_functorNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R6, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R4, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R7, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R5, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000057a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R9, R6, c[0x0][0x180], R5 ; /* 0x0000600006097a23 */
/* 0x005fca0000000005 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FFMA R11, R0, c[0x0][0x180], R11 ; /* 0x00006000000b7a23 */
/* 0x004fca000000000b */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/fill.h>
struct saxpy_functor
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
int main()
{
// initial values
std::vector<float> h_x = { 1.0, 2.0, 3.0 };
std::vector<float> h_y = { 4.0, 5.0, 6.0 };
// init device
float A = 2.0;
thrust::device_vector<float> X;
thrust::device_vector<float> Y;
X = h_x;
Y = h_y;
saxpy_slow(A, X, Y);
// move data from device to host
thrust::host_vector<float> result;
result = Y;
// print result ( A*X + Y )
std::cout << "A = " << A << std::endl;
std::cout << "X = ";
for (auto x : h_x) {
std::cout << x << ", ";
}
std::cout << std::endl;
std::cout << "Y = ";
for (auto y : h_y) {
std::cout << y << ", ";
}
std::cout << std::endl;
std::cout << "A * X + Y = ";
for (int i = 0; i < result.size(); i++) {
std::cout << result[i] << ", ";
}
std::cout << std::endl;
return 0;
} |
#include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/fill.h>
struct saxpy_functor
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
int main()
{
// initial values
std::vector<float> h_x = { 1.0, 2.0, 3.0 };
std::vector<float> h_y = { 4.0, 5.0, 6.0 };
// init device
float A = 2.0;
thrust::device_vector<float> X;
thrust::device_vector<float> Y;
X = h_x;
Y = h_y;
saxpy_slow(A, X, Y);
// move data from device to host
thrust::host_vector<float> result;
result = Y;
// print result ( A*X + Y )
std::cout << "A = " << A << std::endl;
std::cout << "X = ";
for (auto x : h_x) {
std::cout << x << ", ";
}
std::cout << std::endl;
std::cout << "Y = ";
for (auto y : h_y) {
std::cout << y << ", ";
}
std::cout << std::endl;
std::cout << "A * X + Y = ";
for (int i = 0; i < result.size(); i++) {
std::cout << result[i] << ", ";
}
std::cout << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. |
#include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/fill.h>
struct saxpy_functor
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
int main()
{
// initial values
std::vector<float> h_x = { 1.0, 2.0, 3.0 };
std::vector<float> h_y = { 4.0, 5.0, 6.0 };
// init device
float A = 2.0;
thrust::device_vector<float> X;
thrust::device_vector<float> Y;
X = h_x;
Y = h_y;
saxpy_slow(A, X, Y);
// move data from device to host
thrust::host_vector<float> result;
result = Y;
// print result ( A*X + Y )
std::cout << "A = " << A << std::endl;
std::cout << "X = ";
for (auto x : h_x) {
std::cout << x << ", ";
}
std::cout << std::endl;
std::cout << "Y = ";
for (auto y : h_y) {
std::cout << y << ", ";
}
std::cout << std::endl;
std::cout << "A * X + Y = ";
for (int i = 0; i < result.size(); i++) {
std::cout << result[i] << ", ";
}
std::cout << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s0, v2
flat_store_b32 v[0:1], v3
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB3_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end3:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB4_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB4_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end4:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end4-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define nPerThread 32
/* Simple Cuda Program: Shared memory
* - Use dynamic shared memory
* - bank conflicts
* - synchronization
*/
// no bank conflicts
__global__ void addOneShared(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
for (int j=0; j<nPerThread; j++)
smem[j*nt + t]++;
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
// bank conflicts
__global__ void addOneShared_bankConflits(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
__syncthreads();
for (int j=0; j<nPerThread; j++)
smem[t*nPerThread + j]++;
__syncthreads();
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
int main() {
time_t sTime = time(NULL);
struct timeval tt1, tt2;
int ms;
double fms;
int nBlocks = 256;
int nThreads = 128;
int n = nPerThread*nThreads*nBlocks;
double *data = (double*) malloc(n * sizeof(double));
for (int i=0; i<n; i++) {
data[i] = i;
}
double *data_dev;
cudaMalloc((void**) &data_dev, n * sizeof(double));
cudaMemcpy(data_dev, data, n * sizeof(double) , cudaMemcpyHostToDevice);
cudaError_t error = cudaGetLastError();
cout << "copy to device = " << error << " : " << cudaGetErrorString(error) << endl;
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
int sharedMem = nThreads * nPerThread * sizeof(double);
// (*) Add shared memory size to execution configuration parameters
//cudaFuncSetCacheConfig(addOneShared, cudaFuncCachePreferL1);
addOneShared <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
//addOneShared_bankConflits <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
error = cudaGetLastError();
cout << "run kernel = " << error << " : " << cudaGetErrorString(error) << endl;
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
cudaMemcpy(data, data_dev, n * sizeof(double) , cudaMemcpyDeviceToHost);
error = cudaGetLastError();
cout << "copy from device = " << error << " : " << cudaGetErrorString(error) << endl;
cudaFree(data_dev);
cout << "data[n-1] = " << data[n-1] << endl;
free(data);
} | .file "tmpxft_000a8322_00000000-6_sol6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12addOneSharediPdiPd
.type _Z33__device_stub__Z12addOneSharediPdiPd, @function
_Z33__device_stub__Z12addOneSharediPdiPd:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12addOneSharediPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z12addOneSharediPdiPd, .-_Z33__device_stub__Z12addOneSharediPdiPd
.globl _Z12addOneSharediPd
.type _Z12addOneSharediPd, @function
_Z12addOneSharediPd:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12addOneSharediPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12addOneSharediPd, .-_Z12addOneSharediPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copy to device = "
.LC1:
.string " : "
.LC2:
.string "run kernel = "
.LC4:
.string "Comp time = "
.LC5:
.string "copy from device = "
.LC6:
.string "data[n-1] = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1048576, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebp
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaGetLastError@PLT
movl %eax, %r13d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r14
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaThreadSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subl 32(%rsp), %eax
imull $1000000, %eax, %eax
subl 40(%rsp), %eax
addl 56(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
movq %xmm0, %r13
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $8388608, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %r13d
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8388600(%rbx), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movl $1048576, %edi
call _Z33__device_stub__Z12addOneSharediPdiPd
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
.type _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd, @function
_Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25addOneShared_bankConflitsiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd, .-_Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
.globl _Z25addOneShared_bankConflitsiPd
.type _Z25addOneShared_bankConflitsiPd, @function
_Z25addOneShared_bankConflitsiPd:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z25addOneShared_bankConflitsiPd, .-_Z25addOneShared_bankConflitsiPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z25addOneShared_bankConflitsiPd"
.section .rodata.str1.1
.LC8:
.string "_Z12addOneSharediPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z25addOneShared_bankConflitsiPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addOneSharediPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define nPerThread 32
/* Simple Cuda Program: Shared memory
* - Use dynamic shared memory
* - bank conflicts
* - synchronization
*/
// no bank conflicts
__global__ void addOneShared(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
for (int j=0; j<nPerThread; j++)
smem[j*nt + t]++;
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
// bank conflicts
__global__ void addOneShared_bankConflits(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
__syncthreads();
for (int j=0; j<nPerThread; j++)
smem[t*nPerThread + j]++;
__syncthreads();
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
int main() {
time_t sTime = time(NULL);
struct timeval tt1, tt2;
int ms;
double fms;
int nBlocks = 256;
int nThreads = 128;
int n = nPerThread*nThreads*nBlocks;
double *data = (double*) malloc(n * sizeof(double));
for (int i=0; i<n; i++) {
data[i] = i;
}
double *data_dev;
cudaMalloc((void**) &data_dev, n * sizeof(double));
cudaMemcpy(data_dev, data, n * sizeof(double) , cudaMemcpyHostToDevice);
cudaError_t error = cudaGetLastError();
cout << "copy to device = " << error << " : " << cudaGetErrorString(error) << endl;
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
int sharedMem = nThreads * nPerThread * sizeof(double);
// (*) Add shared memory size to execution configuration parameters
//cudaFuncSetCacheConfig(addOneShared, cudaFuncCachePreferL1);
addOneShared <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
//addOneShared_bankConflits <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
error = cudaGetLastError();
cout << "run kernel = " << error << " : " << cudaGetErrorString(error) << endl;
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
cudaMemcpy(data, data_dev, n * sizeof(double) , cudaMemcpyDeviceToHost);
error = cudaGetLastError();
cout << "copy from device = " << error << " : " << cudaGetErrorString(error) << endl;
cudaFree(data_dev);
cout << "data[n-1] = " << data[n-1] << endl;
free(data);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define nPerThread 32
/* Simple Cuda Program: Shared memory
* - Use dynamic shared memory
* - bank conflicts
* - synchronization
*/
// no bank conflicts
__global__ void addOneShared(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
for (int j=0; j<nPerThread; j++)
smem[j*nt + t]++;
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
// bank conflicts
__global__ void addOneShared_bankConflits(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
__syncthreads();
for (int j=0; j<nPerThread; j++)
smem[t*nPerThread + j]++;
__syncthreads();
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
int main() {
time_t sTime = time(NULL);
struct timeval tt1, tt2;
int ms;
double fms;
int nBlocks = 256;
int nThreads = 128;
int n = nPerThread*nThreads*nBlocks;
double *data = (double*) malloc(n * sizeof(double));
for (int i=0; i<n; i++) {
data[i] = i;
}
double *data_dev;
hipMalloc((void**) &data_dev, n * sizeof(double));
hipMemcpy(data_dev, data, n * sizeof(double) , hipMemcpyHostToDevice);
hipError_t error = hipGetLastError();
cout << "copy to device = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
int sharedMem = nThreads * nPerThread * sizeof(double);
// (*) Add shared memory size to execution configuration parameters
//cudaFuncSetCacheConfig(addOneShared, cudaFuncCachePreferL1);
addOneShared <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
//addOneShared_bankConflits <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
error = hipGetLastError();
cout << "run kernel = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
hipMemcpy(data, data_dev, n * sizeof(double) , hipMemcpyDeviceToHost);
error = hipGetLastError();
cout << "copy from device = " << error << " : " << hipGetErrorString(error) << endl;
hipFree(data_dev);
cout << "data[n-1] = " << data[n-1] << endl;
free(data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define nPerThread 32
/* Simple Cuda Program: Shared memory
* - Use dynamic shared memory
* - bank conflicts
* - synchronization
*/
// no bank conflicts
__global__ void addOneShared(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
for (int j=0; j<nPerThread; j++)
smem[j*nt + t]++;
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
// bank conflicts
__global__ void addOneShared_bankConflits(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
__syncthreads();
for (int j=0; j<nPerThread; j++)
smem[t*nPerThread + j]++;
__syncthreads();
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
int main() {
time_t sTime = time(NULL);
struct timeval tt1, tt2;
int ms;
double fms;
int nBlocks = 256;
int nThreads = 128;
int n = nPerThread*nThreads*nBlocks;
double *data = (double*) malloc(n * sizeof(double));
for (int i=0; i<n; i++) {
data[i] = i;
}
double *data_dev;
hipMalloc((void**) &data_dev, n * sizeof(double));
hipMemcpy(data_dev, data, n * sizeof(double) , hipMemcpyHostToDevice);
hipError_t error = hipGetLastError();
cout << "copy to device = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
int sharedMem = nThreads * nPerThread * sizeof(double);
// (*) Add shared memory size to execution configuration parameters
//cudaFuncSetCacheConfig(addOneShared, cudaFuncCachePreferL1);
addOneShared <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
//addOneShared_bankConflits <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
error = hipGetLastError();
cout << "run kernel = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
hipMemcpy(data, data_dev, n * sizeof(double) , hipMemcpyDeviceToHost);
error = hipGetLastError();
cout << "copy from device = " << error << " : " << hipGetErrorString(error) << endl;
hipFree(data_dev);
cout << "data[n-1] = " << data[n-1] << endl;
free(data);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12addOneSharediPd
.globl _Z12addOneSharediPd
.p2align 8
.type _Z12addOneSharediPd,@function
_Z12addOneSharediPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v3, v0, 3, 0
s_mov_b32 s5, 32
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s2, s15
s_lshl_b32 s4, s2, 3
s_lshl_b32 s3, s3, 5
v_add_nc_u32_e32 v1, s3, v0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b64 v3, v[4:5]
v_add_nc_u32_e32 v3, s4, v3
s_cbranch_scc1 .LBB0_1
v_lshl_add_u32 v1, v0, 3, 0
s_lshl_b32 s4, s2, 3
s_mov_b32 s5, 32
.LBB0_3:
ds_load_b64 v[2:3], v1
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], 1.0
ds_store_b64 v1, v[2:3]
v_add_nc_u32_e32 v1, s4, v1
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v1, s3, v0
v_lshl_add_u32 v0, v0, 3, 0
s_lshl_b32 s3, s2, 3
s_mov_b32 s4, 32
.LBB0_5:
ds_load_b64 v[3:4], v0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, s3, v0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s4, 0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB0_5
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12addOneSharediPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12addOneSharediPd, .Lfunc_end0-_Z12addOneSharediPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25addOneShared_bankConflitsiPd
.globl _Z25addOneShared_bankConflitsiPd
.p2align 8
.type _Z25addOneShared_bankConflitsiPd,@function
_Z25addOneShared_bankConflitsiPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v3, v0, 3, 0
s_mov_b32 s5, 32
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s2, s15
s_lshl_b32 s4, s2, 3
s_lshl_b32 s3, s3, 5
v_add_nc_u32_e32 v1, s3, v0
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b64 v3, v[4:5]
v_add_nc_u32_e32 v3, s4, v3
s_cbranch_scc0 .LBB1_1
v_lshl_add_u32 v1, v0, 8, 0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v4, s4, v1
s_add_i32 s4, s4, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s4, 0x100
ds_load_b64 v[2:3], v4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], 1.0
ds_store_b64 v4, v[2:3]
s_cbranch_scc0 .LBB1_3
v_add_nc_u32_e32 v1, s3, v0
v_lshl_add_u32 v0, v0, 3, 0
s_lshl_b32 s3, s2, 3
s_mov_b32 s4, 32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_5:
ds_load_b64 v[3:4], v0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, s3, v0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s4, 0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB1_5
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25addOneShared_bankConflitsiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25addOneShared_bankConflitsiPd, .Lfunc_end1-_Z25addOneShared_bankConflitsiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12addOneSharediPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12addOneSharediPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25addOneShared_bankConflitsiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25addOneShared_bankConflitsiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define nPerThread 32
/* Simple Cuda Program: Shared memory
* - Use dynamic shared memory
* - bank conflicts
* - synchronization
*/
// no bank conflicts
__global__ void addOneShared(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
for (int j=0; j<nPerThread; j++)
smem[j*nt + t]++;
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
// bank conflicts
__global__ void addOneShared_bankConflits(const int n, double *data) {
extern __shared__ double smem[];
int nt = blockDim.x;
int t = threadIdx.x;
int b = blockIdx.x;
int i = b*(nt*nPerThread);
for (int j=0; j<nPerThread; j++)
smem[j*nt + t] = data[i + j*nt + t];
__syncthreads();
for (int j=0; j<nPerThread; j++)
smem[t*nPerThread + j]++;
__syncthreads();
for (int j=0; j<nPerThread; j++)
data[i + j*nt + t] = smem[j*nt + t];
}
int main() {
time_t sTime = time(NULL);
struct timeval tt1, tt2;
int ms;
double fms;
int nBlocks = 256;
int nThreads = 128;
int n = nPerThread*nThreads*nBlocks;
double *data = (double*) malloc(n * sizeof(double));
for (int i=0; i<n; i++) {
data[i] = i;
}
double *data_dev;
hipMalloc((void**) &data_dev, n * sizeof(double));
hipMemcpy(data_dev, data, n * sizeof(double) , hipMemcpyHostToDevice);
hipError_t error = hipGetLastError();
cout << "copy to device = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
int sharedMem = nThreads * nPerThread * sizeof(double);
// (*) Add shared memory size to execution configuration parameters
//cudaFuncSetCacheConfig(addOneShared, cudaFuncCachePreferL1);
addOneShared <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
//addOneShared_bankConflits <<< nBlocks, nThreads, sharedMem >>>(n, data_dev);
error = hipGetLastError();
cout << "run kernel = " << error << " : " << hipGetErrorString(error) << endl;
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
hipMemcpy(data, data_dev, n * sizeof(double) , hipMemcpyDeviceToHost);
error = hipGetLastError();
cout << "copy from device = " << error << " : " << hipGetErrorString(error) << endl;
hipFree(data_dev);
cout << "data[n-1] = " << data[n-1] << endl;
free(data);
} | .text
.file "sol6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__addOneSharediPd # -- Begin function _Z27__device_stub__addOneSharediPd
.p2align 4, 0x90
.type _Z27__device_stub__addOneSharediPd,@function
_Z27__device_stub__addOneSharediPd: # @_Z27__device_stub__addOneSharediPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12addOneSharediPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__addOneSharediPd, .Lfunc_end0-_Z27__device_stub__addOneSharediPd
.cfi_endproc
# -- End function
.globl _Z40__device_stub__addOneShared_bankConflitsiPd # -- Begin function _Z40__device_stub__addOneShared_bankConflitsiPd
.p2align 4, 0x90
.type _Z40__device_stub__addOneShared_bankConflitsiPd,@function
_Z40__device_stub__addOneShared_bankConflitsiPd: # @_Z40__device_stub__addOneShared_bankConflitsiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25addOneShared_bankConflitsiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z40__device_stub__addOneShared_bankConflitsiPd, .Lfunc_end1-_Z40__device_stub__addOneShared_bankConflitsiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq %rsp, %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq (%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_3
# %bb.4:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_5
.LBB2_3:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_8
# %bb.7:
movzbl 67(%r15), %eax
jmp .LBB2_9
.LBB2_8:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 128(%rdx), %rdi
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq (%rsp), %rax
movl $1048576, 12(%rsp) # imm = 0x100000
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12addOneSharediPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_12
# %bb.13:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_14
.LBB2_12:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit34
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%r15)
je .LBB2_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB2_18
.LBB2_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq 104(%rsp), %rax
movabsq $4294967296000000, %rcx # imm = 0xF424000000000
imulq %rax, %rcx
shrq $32, %rcx
movl 24(%rsp), %eax
subl 112(%rsp), %eax
addl %eax, %ecx
cvtsi2sd %ecx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i43
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %ecx
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit46
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_23
# %bb.24:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_25
.LBB2_23:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%r15)
je .LBB2_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB2_29
.LBB2_28:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 8388600(%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%r14)
je .LBB2_32
# %bb.31:
movzbl 67(%r14), %ecx
jmp .LBB2_33
.LBB2_32:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addOneSharediPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25addOneShared_bankConflitsiPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12addOneSharediPd,@object # @_Z12addOneSharediPd
.section .rodata,"a",@progbits
.globl _Z12addOneSharediPd
.p2align 3, 0x0
_Z12addOneSharediPd:
.quad _Z27__device_stub__addOneSharediPd
.size _Z12addOneSharediPd, 8
.type _Z25addOneShared_bankConflitsiPd,@object # @_Z25addOneShared_bankConflitsiPd
.globl _Z25addOneShared_bankConflitsiPd
.p2align 3, 0x0
_Z25addOneShared_bankConflitsiPd:
.quad _Z40__device_stub__addOneShared_bankConflitsiPd
.size _Z25addOneShared_bankConflitsiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "copy to device = "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "run kernel = "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Comp time = "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "copy from device = "
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "data[n-1] = "
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12addOneSharediPd"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25addOneShared_bankConflitsiPd"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__addOneSharediPd
.addrsig_sym _Z40__device_stub__addOneShared_bankConflitsiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12addOneSharediPd
.addrsig_sym _Z25addOneShared_bankConflitsiPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8322_00000000-6_sol6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12addOneSharediPdiPd
.type _Z33__device_stub__Z12addOneSharediPdiPd, @function
_Z33__device_stub__Z12addOneSharediPdiPd:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12addOneSharediPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z12addOneSharediPdiPd, .-_Z33__device_stub__Z12addOneSharediPdiPd
.globl _Z12addOneSharediPd
.type _Z12addOneSharediPd, @function
_Z12addOneSharediPd:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12addOneSharediPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12addOneSharediPd, .-_Z12addOneSharediPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copy to device = "
.LC1:
.string " : "
.LC2:
.string "run kernel = "
.LC4:
.string "Comp time = "
.LC5:
.string "copy from device = "
.LC6:
.string "data[n-1] = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1048576, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebp
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaGetLastError@PLT
movl %eax, %r13d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r14
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaThreadSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subl 32(%rsp), %eax
imull $1000000, %eax, %eax
subl 40(%rsp), %eax
addl 56(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
movq %xmm0, %r13
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $8388608, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %r13d
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8388600(%rbx), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movl $1048576, %edi
call _Z33__device_stub__Z12addOneSharediPdiPd
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
.type _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd, @function
_Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25addOneShared_bankConflitsiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd, .-_Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
.globl _Z25addOneShared_bankConflitsiPd
.type _Z25addOneShared_bankConflitsiPd, @function
_Z25addOneShared_bankConflitsiPd:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25addOneShared_bankConflitsiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z25addOneShared_bankConflitsiPd, .-_Z25addOneShared_bankConflitsiPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z25addOneShared_bankConflitsiPd"
.section .rodata.str1.1
.LC8:
.string "_Z12addOneSharediPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z25addOneShared_bankConflitsiPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addOneSharediPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sol6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__addOneSharediPd # -- Begin function _Z27__device_stub__addOneSharediPd
.p2align 4, 0x90
.type _Z27__device_stub__addOneSharediPd,@function
_Z27__device_stub__addOneSharediPd: # @_Z27__device_stub__addOneSharediPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12addOneSharediPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__addOneSharediPd, .Lfunc_end0-_Z27__device_stub__addOneSharediPd
.cfi_endproc
# -- End function
.globl _Z40__device_stub__addOneShared_bankConflitsiPd # -- Begin function _Z40__device_stub__addOneShared_bankConflitsiPd
.p2align 4, 0x90
.type _Z40__device_stub__addOneShared_bankConflitsiPd,@function
_Z40__device_stub__addOneShared_bankConflitsiPd: # @_Z40__device_stub__addOneShared_bankConflitsiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25addOneShared_bankConflitsiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z40__device_stub__addOneShared_bankConflitsiPd, .Lfunc_end1-_Z40__device_stub__addOneShared_bankConflitsiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq %rsp, %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq (%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_3
# %bb.4:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_5
.LBB2_3:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_8
# %bb.7:
movzbl 67(%r15), %eax
jmp .LBB2_9
.LBB2_8:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 128(%rdx), %rdi
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq (%rsp), %rax
movl $1048576, 12(%rsp) # imm = 0x100000
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12addOneSharediPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_12
# %bb.13:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_14
.LBB2_12:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit34
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%r15)
je .LBB2_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB2_18
.LBB2_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq 104(%rsp), %rax
movabsq $4294967296000000, %rcx # imm = 0xF424000000000
imulq %rax, %rcx
shrq $32, %rcx
movl 24(%rsp), %eax
subl 112(%rsp), %eax
addl %eax, %ecx
cvtsi2sd %ecx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i43
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %ecx
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit46
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_23
# %bb.24:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_25
.LBB2_23:
movq (%r14), %rax
movq -24(%rax), %rax
movq %r14, %rdi
addq %rax, %rdi
movl 32(%r14,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_34
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%r15)
je .LBB2_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB2_29
.LBB2_28:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 8388600(%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%r14)
je .LBB2_32
# %bb.31:
movzbl 67(%r14), %ecx
jmp .LBB2_33
.LBB2_32:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addOneSharediPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25addOneShared_bankConflitsiPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12addOneSharediPd,@object # @_Z12addOneSharediPd
.section .rodata,"a",@progbits
.globl _Z12addOneSharediPd
.p2align 3, 0x0
_Z12addOneSharediPd:
.quad _Z27__device_stub__addOneSharediPd
.size _Z12addOneSharediPd, 8
.type _Z25addOneShared_bankConflitsiPd,@object # @_Z25addOneShared_bankConflitsiPd
.globl _Z25addOneShared_bankConflitsiPd
.p2align 3, 0x0
_Z25addOneShared_bankConflitsiPd:
.quad _Z40__device_stub__addOneShared_bankConflitsiPd
.size _Z25addOneShared_bankConflitsiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "copy to device = "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "run kernel = "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Comp time = "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "copy from device = "
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "data[n-1] = "
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12addOneSharediPd"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25addOneShared_bankConflitsiPd"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__addOneSharediPd
.addrsig_sym _Z40__device_stub__addOneShared_bankConflitsiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12addOneSharediPd
.addrsig_sym _Z25addOneShared_bankConflitsiPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} | code for sm_80
Function : _Z12MatMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e640000002100 */
/*0070*/ @!P0 MOV R24, RZ ; /* 0x000000ff00188202 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe20000011400 */
/*00c0*/ @!P0 BRA 0xc30 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe40000011403 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd60000000f00 */
/*0140*/ @!P0 BRA 0xad0 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*0150*/ LEA R12, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800000c7a11 */
/* 0x040fe400078010ff */
/*0160*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe40007ffe1ff */
/*0170*/ LEA.HI.X R5, R0, c[0x0][0x164], R2, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe400000f1402 */
/*0180*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R12, P2, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe40007f5e0ff */
/*01a0*/ LEA R28, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a00031c7a11 */
/* 0x000fc400078210ff */
/*01b0*/ IADD3.X R13, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0d7210 */
/* 0x000fe400017fe4ff */
/*01c0*/ LEA.HI.X R29, R3, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b00031d7a11 */
/* 0x000fe400008f1406 */
/*01d0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*01f0*/ @!P0 BRA 0x950 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x6a0 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ LDG.E R27, [R28.64] ; /* 0x000000041c1b7981 */
/* 0x0000a2000c1e1900 */
/*0250*/ IMAD.WIDE R16, R4, 0x4, R28 ; /* 0x0000000404107825 */
/* 0x000fc600078e021c */
/*0260*/ LDG.E R9, [R12.64+-0x8] ; /* 0xfffff8040c097981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R12.64+-0x4] ; /* 0xfffffc040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x0002e8000c1e1900 */
/*0290*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R12.64+0x4] ; /* 0x000004040c0f7981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x002fc600078e0210 */
/*02c0*/ LDG.E R26, [R12.64+0x8] ; /* 0x000008040c1a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000322000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x000fc600078e0210 */
/*02f0*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000164000c1e1900 */
/*0310*/ IMAD.WIDE R20, R4, 0x4, R20 ; /* 0x0000000404147825 */
/* 0x001fca00078e0214 */
/*0320*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R28, R4, 0x4, R20 ; /* 0x00000004041c7825 */
/* 0x000fca00078e0214 */
/*0340*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD.WIDE R16, R4, 0x4, R28 ; /* 0x0000000404107825 */
/* 0x002fc800078e021c */
/*0360*/ FFMA R27, R27, R9, R24 ; /* 0x000000091b1b7223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a8000c1e1900 */
/*0380*/ LDG.E R24, [R12.64+0x10] ; /* 0x000010040c187981 */
/* 0x000ea2000c1e1900 */
/*0390*/ FFMA R27, R18, R11, R27 ; /* 0x0000000b121b7223 */
/* 0x008fc6000000001b */
/*03a0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x002fca00078e0210 */
/*03c0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x001fca00078e0210 */
/*03e0*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x0000e2000c1e1900 */
/*03f0*/ FFMA R29, R23, R22, R27 ; /* 0x00000016171d7223 */
/* 0x010fe4000000001b */
/*0400*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fe200078e0214 */
/*0410*/ LDG.E R27, [R12.64+0x18] ; /* 0x000018040c1b7981 */
/* 0x000f26000c1e1900 */
/*0420*/ FFMA R16, R14, R15, R29 ; /* 0x0000000f0e107223 */
/* 0x020fe2000000001d */
/*0430*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x001f68000c1e1900 */
/*0440*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*0450*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0216 */
/*0460*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000f62000c1e1900 */
/*0470*/ FFMA R25, R25, R26, R16 ; /* 0x0000001a19197223 */
/* 0x000fe40000000010 */
/*0480*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe400078e020e */
/*0490*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*04a0*/ FFMA R10, R19, R10, R25 ; /* 0x0000000a130a7223 */
/* 0x000fe40000000019 */
/*04b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R25, [R12.64+0x2c] ; /* 0x00002c040c197981 */
/* 0x000362000c1e1900 */
/*04d0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x001fcc00078e0210 */
/*04e0*/ IMAD.WIDE R22, R4, 0x4, R16 ; /* 0x0000000404167825 */
/* 0x000fca00078e0210 */
/*04f0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x002f62000c1e1900 */
/*0500*/ FFMA R10, R9, R24, R10 ; /* 0x00000018090a7223 */
/* 0x004fc6000000000a */
/*0510*/ LDG.E R24, [R12.64+0x24] ; /* 0x000024040c187981 */
/* 0x0000a8000c1e1900 */
/*0520*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0530*/ FFMA R26, R11, R18, R10 ; /* 0x000000120b1a7223 */
/* 0x008fc6000000000a */
/*0540*/ LDG.E R18, [R12.64+0x28] ; /* 0x000028040c127981 */
/* 0x0000e2000c1e1900 */
/*0550*/ IMAD.WIDE R10, R4, 0x4, R22 ; /* 0x00000004040a7825 */
/* 0x000fc600078e0216 */
/*0560*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x0020e2000c1e1900 */
/*0570*/ FFMA R16, R28, R27, R26 ; /* 0x0000001b1c107223 */
/* 0x010fe4000000001a */
/*0580*/ IMAD.WIDE R26, R4, 0x4, R10 ; /* 0x00000004041a7825 */
/* 0x000fe200078e020a */
/*0590*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000f26000c1e1900 */
/*05a0*/ FFMA R20, R29, R20, R16 ; /* 0x000000141d147223 */
/* 0x020fe40000000010 */
/*05b0*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000f62000c1e1900 */
/*05d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ FFMA R14, R14, R21, R20 ; /* 0x000000150e0e7223 */
/* 0x000fc60000000014 */
/*05f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0600*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x001fe40007f5e0ff */
/*0610*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0630*/ FFMA R14, R19, R24, R14 ; /* 0x00000018130e7223 */
/* 0x004fc8000000000e */
/*0640*/ FFMA R14, R9, R18, R14 ; /* 0x00000012090e7223 */
/* 0x008fc8000000000e */
/*0650*/ FFMA R14, R15, R25, R14 ; /* 0x000000190f0e7223 */
/* 0x000fc8000000000e */
/*0660*/ FFMA R14, R28, R17, R14 ; /* 0x000000111c0e7223 */
/* 0x010fc8000000000e */
/*0670*/ FFMA R24, R16, R29, R14 ; /* 0x0000001d10187223 */
/* 0x020fe4000000000e */
/*0680*/ IMAD.WIDE R28, R4, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x000fe200078e021a */
/*0690*/ @P1 BRA 0x240 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x930 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x0000a8000c1e1900 */
/*06d0*/ LDG.E R23, [R12.64+-0x8] ; /* 0xfffff8040c177981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE R20, R4, 0x4, R28 ; /* 0x0000000404147825 */
/* 0x000fc600078e021c */
/*06f0*/ LDG.E R9, [R12.64+-0x4] ; /* 0xfffffc040c097981 */
/* 0x000ee8000c1e1900 */
/*0700*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x0002e2000c1e1900 */
/*0710*/ IMAD.WIDE R14, R4, 0x4, R20 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0214 */
/*0720*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000f26000c1e1900 */
/*0730*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0740*/ LDG.E R26, [R12.64+0x4] ; /* 0x000004040c1a7981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000122000c1e1900 */
/*0760*/ IMAD.WIDE R10, R4, 0x4, R16 ; /* 0x00000004040a7825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000166000c1e1900 */
/*0780*/ IMAD.WIDE R18, R4.reuse, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x040fe400078e020a */
/*0790*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R16, [R12.64+0x8] ; /* 0x000008040c107981 */
/* 0x001f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x002fc600078e0212 */
/*07c0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f66000c1e1900 */
/*07d0*/ IMAD.WIDE R28, R4, 0x4, R20 ; /* 0x00000004041c7825 */
/* 0x000fe200078e0214 */
/*07e0*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000f66000c1e1900 */
/*07f0*/ FFMA R25, R25, R23, R24 ; /* 0x0000001719197223 */
/* 0x004fe40000000018 */
/*0800*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R24, [R12.64+0x10] ; /* 0x000010040c187981 */
/* 0x000ea2000c1e1900 */
/*0820*/ FFMA R25, R22, R9, R25 ; /* 0x0000000916197223 */
/* 0x008fc60000000019 */
/*0830*/ LDG.E R22, [R12.64+0x14] ; /* 0x000014040c167981 */
/* 0x0000e8000c1e1900 */
/*0840*/ LDG.E R9, [R28.64] ; /* 0x000000041c097981 */
/* 0x0002e2000c1e1900 */
/*0850*/ FFMA R14, R14, R27, R25 ; /* 0x0000001b0e0e7223 */
/* 0x010fc80000000019 */
/*0860*/ FFMA R14, R17, R26, R14 ; /* 0x0000001a110e7223 */
/* 0x020fc8000000000e */
/*0870*/ FFMA R11, R11, R16, R14 ; /* 0x000000100b0b7223 */
/* 0x000fe2000000000e */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0890*/ IMAD.WIDE R28, R4, 0x4, R28 ; /* 0x00000004041c7825 */
/* 0x002fe200078e021c */
/*08a0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FFMA R10, R10, R23, R11 ; /* 0x000000170a0a7223 */
/* 0x004fe2000000000b */
/*08d0*/ IADD3 R11, P1, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fc60007f3e0ff */
/*08e0*/ FFMA R24, R15, R24, R10 ; /* 0x000000180f187223 */
/* 0x000fe2000000000a */
/*08f0*/ IADD3.X R10, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0a7210 */
/* 0x000fe40000ffe4ff */
/*0900*/ MOV R12, R11 ; /* 0x0000000b000c7202 */
/* 0x001fe40000000f00 */
/*0910*/ MOV R13, R10 ; /* 0x0000000a000d7202 */
/* 0x000fe20000000f00 */
/*0920*/ FFMA R24, R9, R22, R24 ; /* 0x0000001609187223 */
/* 0x008fe40000000018 */
/*0930*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0940*/ @!P0 BRA 0xad0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.WIDE R10, R4.reuse, 0x4, R28 ; /* 0x00000004040a7825 */
/* 0x040fe200078e021c */
/*0960*/ LDG.E R9, [R12.64+-0x8] ; /* 0xfffff8040c097981 */
/* 0x0000a8000c1e1900 */
/*0970*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ea2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4, 0x4, R10 ; /* 0x0000000404107825 */
/* 0x000fc600078e020a */
/*0990*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x0002e8000c1e1900 */
/*09a0*/ LDG.E R19, [R12.64+-0x4] ; /* 0xfffffc040c137981 */
/* 0x0000e2000c1e1900 */
/*09b0*/ IMAD.WIDE R14, R4, 0x4, R16 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0210 */
/*09c0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000128000c1e1900 */
/*09d0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000168000c1e1900 */
/*09f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f62000c1e1900 */
/*0a00*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0a20*/ IADD3 R10, P1, R12, 0x10, RZ ; /* 0x000000100c0a7810 */
/* 0x002fc80007f3e0ff */
/*0a30*/ IADD3.X R11, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0b7210 */
/* 0x000fe40000ffe4ff */
/*0a40*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x001fe40000000f00 */
/*0a60*/ MOV R13, R11 ; /* 0x0000000b000d7202 */
/* 0x000fe20000000f00 */
/*0a70*/ FFMA R9, R29, R9, R24 ; /* 0x000000091d097223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R9, R18, R19, R9 ; /* 0x0000001312097223 */
/* 0x008fe40000000009 */
/*0a90*/ IMAD.WIDE R28, R4, 0x4, R14 ; /* 0x00000004041c7825 */
/* 0x000fc800078e020e */
/*0aa0*/ FFMA R9, R20, R21, R9 ; /* 0x0000001514097223 */
/* 0x010fc80000000009 */
/*0ab0*/ FFMA R24, R22, R23, R9 ; /* 0x0000001716187223 */
/* 0x020fe20000000009 */
/*0ac0*/ @P0 BRA 0x950 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xc30 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0af0*/ IMAD R8, R5, c[0x0][0x178], RZ ; /* 0x00005e0005087a24 */
/* 0x000fe200078e02ff */
/*0b00*/ IADD3 R13, P2, R0, R5, RZ ; /* 0x00000005000d7210 */
/* 0x000fc80007f5e0ff */
/*0b10*/ IADD3 R9, P0, R3, R8, RZ ; /* 0x0000000803097210 */
/* 0x000fe40007f1e0ff */
/*0b20*/ LEA R12, P3, R13, c[0x0][0x160], 0x2 ; /* 0x000058000d0c7a11 */
/* 0x000fe400078610ff */
/*0b30*/ LEA R10, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a00090a7a11 */
/* 0x000fe400078210ff */
/*0b40*/ LEA.HI.X.SX32 R14, R5, R2, 0x1, P2 ; /* 0x00000002050e7211 */
/* 0x000fe400010f0eff */
/*0b50*/ LEA.HI.X.SX32 R6, R8, R6, 0x1, P0 ; /* 0x0000000608067211 */
/* 0x000fe400000f0eff */
/*0b60*/ LEA.HI.X R13, R13, c[0x0][0x164], R14, 0x2, P3 ; /* 0x000059000d0d7a11 */
/* 0x000fc400018f140e */
/*0b70*/ LEA.HI.X R9, R9, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b0009097a11 */
/* 0x000fc800008f1406 */
/*0b80*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0b90*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ IMAD.WIDE R8, R4, 0x4, R10 ; /* 0x0000000404087825 */
/* 0x000fc600078e020a */
/*0bd0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0be0*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x001fe40007f3e0ff */
/*0bf0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x002fe40000000f00 */
/*0c00*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ FFMA R24, R5, R6, R24 ; /* 0x0000000605187223 */
/* 0x004fcc0000000018 */
/*0c20*/ @P0 BRA 0xb80 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c30*/ IADD3 R0, P0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x000fc80007f1e0ff */
/*0c40*/ LEA.HI.X.SX32 R3, R3, R2, 0x1, P0 ; /* 0x0000000203037211 */
/* 0x000fe400000f0eff */
/*0c50*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*0c60*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1403 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} | .file "tmpxft_00096b52_00000000-6_MatMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12MatMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
.globl _Z12MatMulKernelPfS_S_i
.type _Z12MatMulKernelPfS_S_i, @function
_Z12MatMulKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12MatMulKernelPfS_S_i, .-_Z12MatMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12MatMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernelPfS_S_i
.globl _Z12MatMulKernelPfS_S_i
.p2align 8
.type _Z12MatMulKernelPfS_S_i,@function
_Z12MatMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s3, v[1:2]
s_cmp_lt_i32 s4, 1
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mul_lo_u32 v2, v3, s4
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v5, 0
s_mov_b32 s3, 0
s_mov_b32 s5, s4
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.p2align 6
.LBB0_2:
s_lshl_b64 s[6:7], s[2:3], 2
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s5, 0
global_load_b32 v10, v[3:4], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v10, v8
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v5, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernelPfS_S_i, .Lfunc_end0-_Z12MatMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatMulKernel(float *Md, float *Nd, float *Pd, int width)
{
// Thread row and column within matrix
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread computes one element of P
// by accumulating results into Pvalue
float Pvalue = 0;
// Multiply M and N
for (int k = 0; k < width; ++k) {
float Melement = *(Md + row*width + k);
float Nelement = *(Nd + k*width + col);
Pvalue += Melement * Nelement;
}
// Write Pvalue to device memory
// Each thread writes one element
*(Pd + row*width + col) = Pvalue;
} | .text
.file "MatMulKernel.hip"
.globl _Z27__device_stub__MatMulKernelPfS_S_i # -- Begin function _Z27__device_stub__MatMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernelPfS_S_i,@function
_Z27__device_stub__MatMulKernelPfS_S_i: # @_Z27__device_stub__MatMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatMulKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__MatMulKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernelPfS_S_i,@object # @_Z12MatMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12MatMulKernelPfS_S_i
.p2align 3, 0x0
_Z12MatMulKernelPfS_S_i:
.quad _Z27__device_stub__MatMulKernelPfS_S_i
.size _Z12MatMulKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12MatMulKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e640000002100 */
/*0070*/ @!P0 MOV R24, RZ ; /* 0x000000ff00188202 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe20000011400 */
/*00c0*/ @!P0 BRA 0xc30 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe40000011403 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd60000000f00 */
/*0140*/ @!P0 BRA 0xad0 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*0150*/ LEA R12, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800000c7a11 */
/* 0x040fe400078010ff */
/*0160*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe40007ffe1ff */
/*0170*/ LEA.HI.X R5, R0, c[0x0][0x164], R2, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe400000f1402 */
/*0180*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R12, P2, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe40007f5e0ff */
/*01a0*/ LEA R28, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a00031c7a11 */
/* 0x000fc400078210ff */
/*01b0*/ IADD3.X R13, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0d7210 */
/* 0x000fe400017fe4ff */
/*01c0*/ LEA.HI.X R29, R3, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b00031d7a11 */
/* 0x000fe400008f1406 */
/*01d0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*01f0*/ @!P0 BRA 0x950 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x6a0 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ LDG.E R27, [R28.64] ; /* 0x000000041c1b7981 */
/* 0x0000a2000c1e1900 */
/*0250*/ IMAD.WIDE R16, R4, 0x4, R28 ; /* 0x0000000404107825 */
/* 0x000fc600078e021c */
/*0260*/ LDG.E R9, [R12.64+-0x8] ; /* 0xfffff8040c097981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R12.64+-0x4] ; /* 0xfffffc040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x0002e8000c1e1900 */
/*0290*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R12.64+0x4] ; /* 0x000004040c0f7981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x002fc600078e0210 */
/*02c0*/ LDG.E R26, [R12.64+0x8] ; /* 0x000008040c1a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000322000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x000fc600078e0210 */
/*02f0*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000164000c1e1900 */
/*0310*/ IMAD.WIDE R20, R4, 0x4, R20 ; /* 0x0000000404147825 */
/* 0x001fca00078e0214 */
/*0320*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R28, R4, 0x4, R20 ; /* 0x00000004041c7825 */
/* 0x000fca00078e0214 */
/*0340*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD.WIDE R16, R4, 0x4, R28 ; /* 0x0000000404107825 */
/* 0x002fc800078e021c */
/*0360*/ FFMA R27, R27, R9, R24 ; /* 0x000000091b1b7223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a8000c1e1900 */
/*0380*/ LDG.E R24, [R12.64+0x10] ; /* 0x000010040c187981 */
/* 0x000ea2000c1e1900 */
/*0390*/ FFMA R27, R18, R11, R27 ; /* 0x0000000b121b7223 */
/* 0x008fc6000000001b */
/*03a0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x002fca00078e0210 */
/*03c0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x001fca00078e0210 */
/*03e0*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x0000e2000c1e1900 */
/*03f0*/ FFMA R29, R23, R22, R27 ; /* 0x00000016171d7223 */
/* 0x010fe4000000001b */
/*0400*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fe200078e0214 */
/*0410*/ LDG.E R27, [R12.64+0x18] ; /* 0x000018040c1b7981 */
/* 0x000f26000c1e1900 */
/*0420*/ FFMA R16, R14, R15, R29 ; /* 0x0000000f0e107223 */
/* 0x020fe2000000001d */
/*0430*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x001f68000c1e1900 */
/*0440*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*0450*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0216 */
/*0460*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000f62000c1e1900 */
/*0470*/ FFMA R25, R25, R26, R16 ; /* 0x0000001a19197223 */
/* 0x000fe40000000010 */
/*0480*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe400078e020e */
/*0490*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*04a0*/ FFMA R10, R19, R10, R25 ; /* 0x0000000a130a7223 */
/* 0x000fe40000000019 */
/*04b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R25, [R12.64+0x2c] ; /* 0x00002c040c197981 */
/* 0x000362000c1e1900 */
/*04d0*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x001fcc00078e0210 */
/*04e0*/ IMAD.WIDE R22, R4, 0x4, R16 ; /* 0x0000000404167825 */
/* 0x000fca00078e0210 */
/*04f0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x002f62000c1e1900 */
/*0500*/ FFMA R10, R9, R24, R10 ; /* 0x00000018090a7223 */
/* 0x004fc6000000000a */
/*0510*/ LDG.E R24, [R12.64+0x24] ; /* 0x000024040c187981 */
/* 0x0000a8000c1e1900 */
/*0520*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0530*/ FFMA R26, R11, R18, R10 ; /* 0x000000120b1a7223 */
/* 0x008fc6000000000a */
/*0540*/ LDG.E R18, [R12.64+0x28] ; /* 0x000028040c127981 */
/* 0x0000e2000c1e1900 */
/*0550*/ IMAD.WIDE R10, R4, 0x4, R22 ; /* 0x00000004040a7825 */
/* 0x000fc600078e0216 */
/*0560*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x0020e2000c1e1900 */
/*0570*/ FFMA R16, R28, R27, R26 ; /* 0x0000001b1c107223 */
/* 0x010fe4000000001a */
/*0580*/ IMAD.WIDE R26, R4, 0x4, R10 ; /* 0x00000004041a7825 */
/* 0x000fe200078e020a */
/*0590*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000f26000c1e1900 */
/*05a0*/ FFMA R20, R29, R20, R16 ; /* 0x000000141d147223 */
/* 0x020fe40000000010 */
/*05b0*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000f62000c1e1900 */
/*05d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ FFMA R14, R14, R21, R20 ; /* 0x000000150e0e7223 */
/* 0x000fc60000000014 */
/*05f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0600*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x001fe40007f5e0ff */
/*0610*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0630*/ FFMA R14, R19, R24, R14 ; /* 0x00000018130e7223 */
/* 0x004fc8000000000e */
/*0640*/ FFMA R14, R9, R18, R14 ; /* 0x00000012090e7223 */
/* 0x008fc8000000000e */
/*0650*/ FFMA R14, R15, R25, R14 ; /* 0x000000190f0e7223 */
/* 0x000fc8000000000e */
/*0660*/ FFMA R14, R28, R17, R14 ; /* 0x000000111c0e7223 */
/* 0x010fc8000000000e */
/*0670*/ FFMA R24, R16, R29, R14 ; /* 0x0000001d10187223 */
/* 0x020fe4000000000e */
/*0680*/ IMAD.WIDE R28, R4, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x000fe200078e021a */
/*0690*/ @P1 BRA 0x240 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x930 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x0000a8000c1e1900 */
/*06d0*/ LDG.E R23, [R12.64+-0x8] ; /* 0xfffff8040c177981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE R20, R4, 0x4, R28 ; /* 0x0000000404147825 */
/* 0x000fc600078e021c */
/*06f0*/ LDG.E R9, [R12.64+-0x4] ; /* 0xfffffc040c097981 */
/* 0x000ee8000c1e1900 */
/*0700*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x0002e2000c1e1900 */
/*0710*/ IMAD.WIDE R14, R4, 0x4, R20 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0214 */
/*0720*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000f26000c1e1900 */
/*0730*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0740*/ LDG.E R26, [R12.64+0x4] ; /* 0x000004040c1a7981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000122000c1e1900 */
/*0760*/ IMAD.WIDE R10, R4, 0x4, R16 ; /* 0x00000004040a7825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000166000c1e1900 */
/*0780*/ IMAD.WIDE R18, R4.reuse, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x040fe400078e020a */
/*0790*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R16, [R12.64+0x8] ; /* 0x000008040c107981 */
/* 0x001f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x002fc600078e0212 */
/*07c0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f66000c1e1900 */
/*07d0*/ IMAD.WIDE R28, R4, 0x4, R20 ; /* 0x00000004041c7825 */
/* 0x000fe200078e0214 */
/*07e0*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000f66000c1e1900 */
/*07f0*/ FFMA R25, R25, R23, R24 ; /* 0x0000001719197223 */
/* 0x004fe40000000018 */
/*0800*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R24, [R12.64+0x10] ; /* 0x000010040c187981 */
/* 0x000ea2000c1e1900 */
/*0820*/ FFMA R25, R22, R9, R25 ; /* 0x0000000916197223 */
/* 0x008fc60000000019 */
/*0830*/ LDG.E R22, [R12.64+0x14] ; /* 0x000014040c167981 */
/* 0x0000e8000c1e1900 */
/*0840*/ LDG.E R9, [R28.64] ; /* 0x000000041c097981 */
/* 0x0002e2000c1e1900 */
/*0850*/ FFMA R14, R14, R27, R25 ; /* 0x0000001b0e0e7223 */
/* 0x010fc80000000019 */
/*0860*/ FFMA R14, R17, R26, R14 ; /* 0x0000001a110e7223 */
/* 0x020fc8000000000e */
/*0870*/ FFMA R11, R11, R16, R14 ; /* 0x000000100b0b7223 */
/* 0x000fe2000000000e */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0890*/ IMAD.WIDE R28, R4, 0x4, R28 ; /* 0x00000004041c7825 */
/* 0x002fe200078e021c */
/*08a0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FFMA R10, R10, R23, R11 ; /* 0x000000170a0a7223 */
/* 0x004fe2000000000b */
/*08d0*/ IADD3 R11, P1, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fc60007f3e0ff */
/*08e0*/ FFMA R24, R15, R24, R10 ; /* 0x000000180f187223 */
/* 0x000fe2000000000a */
/*08f0*/ IADD3.X R10, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0a7210 */
/* 0x000fe40000ffe4ff */
/*0900*/ MOV R12, R11 ; /* 0x0000000b000c7202 */
/* 0x001fe40000000f00 */
/*0910*/ MOV R13, R10 ; /* 0x0000000a000d7202 */
/* 0x000fe20000000f00 */
/*0920*/ FFMA R24, R9, R22, R24 ; /* 0x0000001609187223 */
/* 0x008fe40000000018 */
/*0930*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0940*/ @!P0 BRA 0xad0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.WIDE R10, R4.reuse, 0x4, R28 ; /* 0x00000004040a7825 */
/* 0x040fe200078e021c */
/*0960*/ LDG.E R9, [R12.64+-0x8] ; /* 0xfffff8040c097981 */
/* 0x0000a8000c1e1900 */
/*0970*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ea2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4, 0x4, R10 ; /* 0x0000000404107825 */
/* 0x000fc600078e020a */
/*0990*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x0002e8000c1e1900 */
/*09a0*/ LDG.E R19, [R12.64+-0x4] ; /* 0xfffffc040c137981 */
/* 0x0000e2000c1e1900 */
/*09b0*/ IMAD.WIDE R14, R4, 0x4, R16 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0210 */
/*09c0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000128000c1e1900 */
/*09d0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000168000c1e1900 */
/*09f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f62000c1e1900 */
/*0a00*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0a20*/ IADD3 R10, P1, R12, 0x10, RZ ; /* 0x000000100c0a7810 */
/* 0x002fc80007f3e0ff */
/*0a30*/ IADD3.X R11, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0b7210 */
/* 0x000fe40000ffe4ff */
/*0a40*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x001fe40000000f00 */
/*0a60*/ MOV R13, R11 ; /* 0x0000000b000d7202 */
/* 0x000fe20000000f00 */
/*0a70*/ FFMA R9, R29, R9, R24 ; /* 0x000000091d097223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R9, R18, R19, R9 ; /* 0x0000001312097223 */
/* 0x008fe40000000009 */
/*0a90*/ IMAD.WIDE R28, R4, 0x4, R14 ; /* 0x00000004041c7825 */
/* 0x000fc800078e020e */
/*0aa0*/ FFMA R9, R20, R21, R9 ; /* 0x0000001514097223 */
/* 0x010fc80000000009 */
/*0ab0*/ FFMA R24, R22, R23, R9 ; /* 0x0000001716187223 */
/* 0x020fe20000000009 */
/*0ac0*/ @P0 BRA 0x950 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xc30 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0af0*/ IMAD R8, R5, c[0x0][0x178], RZ ; /* 0x00005e0005087a24 */
/* 0x000fe200078e02ff */
/*0b00*/ IADD3 R13, P2, R0, R5, RZ ; /* 0x00000005000d7210 */
/* 0x000fc80007f5e0ff */
/*0b10*/ IADD3 R9, P0, R3, R8, RZ ; /* 0x0000000803097210 */
/* 0x000fe40007f1e0ff */
/*0b20*/ LEA R12, P3, R13, c[0x0][0x160], 0x2 ; /* 0x000058000d0c7a11 */
/* 0x000fe400078610ff */
/*0b30*/ LEA R10, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a00090a7a11 */
/* 0x000fe400078210ff */
/*0b40*/ LEA.HI.X.SX32 R14, R5, R2, 0x1, P2 ; /* 0x00000002050e7211 */
/* 0x000fe400010f0eff */
/*0b50*/ LEA.HI.X.SX32 R6, R8, R6, 0x1, P0 ; /* 0x0000000608067211 */
/* 0x000fe400000f0eff */
/*0b60*/ LEA.HI.X R13, R13, c[0x0][0x164], R14, 0x2, P3 ; /* 0x000059000d0d7a11 */
/* 0x000fc400018f140e */
/*0b70*/ LEA.HI.X R9, R9, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b0009097a11 */
/* 0x000fc800008f1406 */
/*0b80*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0b90*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ IMAD.WIDE R8, R4, 0x4, R10 ; /* 0x0000000404087825 */
/* 0x000fc600078e020a */
/*0bd0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0be0*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x001fe40007f3e0ff */
/*0bf0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x002fe40000000f00 */
/*0c00*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ FFMA R24, R5, R6, R24 ; /* 0x0000000605187223 */
/* 0x004fcc0000000018 */
/*0c20*/ @P0 BRA 0xb80 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c30*/ IADD3 R0, P0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x000fc80007f1e0ff */
/*0c40*/ LEA.HI.X.SX32 R3, R3, R2, 0x1, P0 ; /* 0x0000000203037211 */
/* 0x000fe400000f0eff */
/*0c50*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*0c60*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1403 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernelPfS_S_i
.globl _Z12MatMulKernelPfS_S_i
.p2align 8
.type _Z12MatMulKernelPfS_S_i,@function
_Z12MatMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s3, v[1:2]
s_cmp_lt_i32 s4, 1
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mul_lo_u32 v2, v3, s4
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v5, 0
s_mov_b32 s3, 0
s_mov_b32 s5, s4
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.p2align 6
.LBB0_2:
s_lshl_b64 s[6:7], s[2:3], 2
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s5, 0
global_load_b32 v10, v[3:4], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v10, v8
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v5, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernelPfS_S_i, .Lfunc_end0-_Z12MatMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096b52_00000000-6_MatMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12MatMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
.globl _Z12MatMulKernelPfS_S_i
.type _Z12MatMulKernelPfS_S_i, @function
_Z12MatMulKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12MatMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12MatMulKernelPfS_S_i, .-_Z12MatMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12MatMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatMulKernel.hip"
.globl _Z27__device_stub__MatMulKernelPfS_S_i # -- Begin function _Z27__device_stub__MatMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernelPfS_S_i,@function
_Z27__device_stub__MatMulKernelPfS_S_i: # @_Z27__device_stub__MatMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatMulKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__MatMulKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernelPfS_S_i,@object # @_Z12MatMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12MatMulKernelPfS_S_i
.p2align 3, 0x0
_Z12MatMulKernelPfS_S_i:
.quad _Z27__device_stub__MatMulKernelPfS_S_i
.size _Z12MatMulKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12MatMulKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
#include <math_constants.h>
extern "C"
{
__global__ void
rtruncnorm_kernel(
float *x, int n,
float *mu, float *sigma,
float *lo, float *hi,
int maxtries, int rng_a,
int rng_b, int rng_c)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < n){
// Setup the RNG:
curandState_t rng;
curand_init(rng_a+rng_b*idx,rng_c,0,&rng);
// Draw sample
int ntries = 0;
int accepted = 0;
float ran;
while(!accepted and ntries < maxtries){
ran = mu[idx]+sigma[idx]*curand_normal(&rng);
ntries += 1;
if(ran >= lo[idx] and ran <= hi[idx]){
accepted = 1;
}
}
// Use Robert Method if that didn't work
if(!accepted){
// my code is set up to sample only (a,infty), so if it's a (-infty,b) sample we want, then we sample from (-b,infty) and reverse the sign after
int rev_sign = 0;
float lower;
if(isfinite(hi[idx])){
lower = lo[idx]-mu[idx];
}else{
lower = mu[idx]-hi[idx];
rev_sign = 1;
}
float alpha = (lower+sqrtf(lower*lower+4))/2;
float z;
int ntries = 0;
// I may well have done something wrong...but for some datasets, this while loop never ended if I didn't set a max # of tries.
while(!accepted and ntries < 10000L){
ntries += 1;
float psi;
// sample uniform, then use inverse cdf to get sample from exponential distribution:
z = lower-logf(curand_uniform(&rng))/alpha;
if(lower<alpha){
psi = expf(-powf((alpha-z),2)/2);
}else{
psi = expf(-powf((alpha-z),2)/2)*expf(powf((lower-alpha),2)/2);
}
float u = curand_uniform(&rng);
if(u<psi){
accepted = 1;
}
}
if(rev_sign){
ran = mu[idx]-z;
}else{
ran = mu[idx]+z;
}
// If the Robert method failed to accept in 10000 tries:
if(!accepted){
ran = CUDART_NAN_F;
}
}
x[idx] = ran;
}
return;
}
} // END extern "C" | .file "tmpxft_00165306_00000000-6_rtruncnorm2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
.type _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii, @function
_Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii:
.LFB2295:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rtruncnorm_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii, .-_Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
.globl rtruncnorm_kernel
.type rtruncnorm_kernel, @function
rtruncnorm_kernel:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size rtruncnorm_kernel, .-rtruncnorm_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rtruncnorm_kernel"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq rtruncnorm_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
#include <math_constants.h>
extern "C"
{
__global__ void
rtruncnorm_kernel(
float *x, int n,
float *mu, float *sigma,
float *lo, float *hi,
int maxtries, int rng_a,
int rng_b, int rng_c)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < n){
// Setup the RNG:
curandState_t rng;
curand_init(rng_a+rng_b*idx,rng_c,0,&rng);
// Draw sample
int ntries = 0;
int accepted = 0;
float ran;
while(!accepted and ntries < maxtries){
ran = mu[idx]+sigma[idx]*curand_normal(&rng);
ntries += 1;
if(ran >= lo[idx] and ran <= hi[idx]){
accepted = 1;
}
}
// Use Robert Method if that didn't work
if(!accepted){
// my code is set up to sample only (a,infty), so if it's a (-infty,b) sample we want, then we sample from (-b,infty) and reverse the sign after
int rev_sign = 0;
float lower;
if(isfinite(hi[idx])){
lower = lo[idx]-mu[idx];
}else{
lower = mu[idx]-hi[idx];
rev_sign = 1;
}
float alpha = (lower+sqrtf(lower*lower+4))/2;
float z;
int ntries = 0;
// I may well have done something wrong...but for some datasets, this while loop never ended if I didn't set a max # of tries.
while(!accepted and ntries < 10000L){
ntries += 1;
float psi;
// sample uniform, then use inverse cdf to get sample from exponential distribution:
z = lower-logf(curand_uniform(&rng))/alpha;
if(lower<alpha){
psi = expf(-powf((alpha-z),2)/2);
}else{
psi = expf(-powf((alpha-z),2)/2)*expf(powf((lower-alpha),2)/2);
}
float u = curand_uniform(&rng);
if(u<psi){
accepted = 1;
}
}
if(rev_sign){
ran = mu[idx]-z;
}else{
ran = mu[idx]+z;
}
// If the Robert method failed to accept in 10000 tries:
if(!accepted){
ran = CUDART_NAN_F;
}
}
x[idx] = ran;
}
return;
}
} // END extern "C" | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/hip_math_constants.h>
extern "C"
{
__global__ void
rtruncnorm_kernel(
float *x, int n,
float *mu, float *sigma,
float *lo, float *hi,
int maxtries, int rng_a,
int rng_b, int rng_c)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < n){
// Setup the RNG:
hiprandState_t rng;
hiprand_init(rng_a+rng_b*idx,rng_c,0,&rng);
// Draw sample
int ntries = 0;
int accepted = 0;
float ran;
while(!accepted and ntries < maxtries){
ran = mu[idx]+sigma[idx]*hiprand_normal(&rng);
ntries += 1;
if(ran >= lo[idx] and ran <= hi[idx]){
accepted = 1;
}
}
// Use Robert Method if that didn't work
if(!accepted){
// my code is set up to sample only (a,infty), so if it's a (-infty,b) sample we want, then we sample from (-b,infty) and reverse the sign after
int rev_sign = 0;
float lower;
if(isfinite(hi[idx])){
lower = lo[idx]-mu[idx];
}else{
lower = mu[idx]-hi[idx];
rev_sign = 1;
}
float alpha = (lower+sqrtf(lower*lower+4))/2;
float z;
int ntries = 0;
// I may well have done something wrong...but for some datasets, this while loop never ended if I didn't set a max # of tries.
while(!accepted and ntries < 10000L){
ntries += 1;
float psi;
// sample uniform, then use inverse cdf to get sample from exponential distribution:
z = lower-logf(hiprand_uniform(&rng))/alpha;
if(lower<alpha){
psi = expf(-powf((alpha-z),2)/2);
}else{
psi = expf(-powf((alpha-z),2)/2)*expf(powf((lower-alpha),2)/2);
}
float u = hiprand_uniform(&rng);
if(u<psi){
accepted = 1;
}
}
if(rev_sign){
ran = mu[idx]-z;
}else{
ran = mu[idx]+z;
}
// If the Robert method failed to accept in 10000 tries:
if(!accepted){
ran = HIP_NAN_F;
}
}
x[idx] = ran;
}
return;
}
} // END extern "C" |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/hip_math_constants.h>
extern "C"
{
__global__ void
rtruncnorm_kernel(
float *x, int n,
float *mu, float *sigma,
float *lo, float *hi,
int maxtries, int rng_a,
int rng_b, int rng_c)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < n){
// Setup the RNG:
hiprandState_t rng;
hiprand_init(rng_a+rng_b*idx,rng_c,0,&rng);
// Draw sample
int ntries = 0;
int accepted = 0;
float ran;
while(!accepted and ntries < maxtries){
ran = mu[idx]+sigma[idx]*hiprand_normal(&rng);
ntries += 1;
if(ran >= lo[idx] and ran <= hi[idx]){
accepted = 1;
}
}
// Use Robert Method if that didn't work
if(!accepted){
// my code is set up to sample only (a,infty), so if it's a (-infty,b) sample we want, then we sample from (-b,infty) and reverse the sign after
int rev_sign = 0;
float lower;
if(isfinite(hi[idx])){
lower = lo[idx]-mu[idx];
}else{
lower = mu[idx]-hi[idx];
rev_sign = 1;
}
float alpha = (lower+sqrtf(lower*lower+4))/2;
float z;
int ntries = 0;
// I may well have done something wrong...but for some datasets, this while loop never ended if I didn't set a max # of tries.
while(!accepted and ntries < 10000L){
ntries += 1;
float psi;
// sample uniform, then use inverse cdf to get sample from exponential distribution:
z = lower-logf(hiprand_uniform(&rng))/alpha;
if(lower<alpha){
psi = expf(-powf((alpha-z),2)/2);
}else{
psi = expf(-powf((alpha-z),2)/2)*expf(powf((lower-alpha),2)/2);
}
float u = hiprand_uniform(&rng);
if(u<psi){
accepted = 1;
}
}
if(rev_sign){
ran = mu[idx]-z;
}else{
ran = mu[idx]+z;
}
// If the Robert method failed to accept in 10000 tries:
if(!accepted){
ran = HIP_NAN_F;
}
}
x[idx] = ran;
}
return;
}
} // END extern "C" | .text
.file "rtruncnorm2.hip"
.globl __device_stub__rtruncnorm_kernel # -- Begin function __device_stub__rtruncnorm_kernel
.p2align 4, 0x90
.type __device_stub__rtruncnorm_kernel,@function
__device_stub__rtruncnorm_kernel: # @__device_stub__rtruncnorm_kernel
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rtruncnorm_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size __device_stub__rtruncnorm_kernel, .Lfunc_end0-__device_stub__rtruncnorm_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rtruncnorm_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type rtruncnorm_kernel,@object # @rtruncnorm_kernel
.section .rodata,"a",@progbits
.globl rtruncnorm_kernel
.p2align 3, 0x0
rtruncnorm_kernel:
.quad __device_stub__rtruncnorm_kernel
.size rtruncnorm_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "rtruncnorm_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__rtruncnorm_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rtruncnorm_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00165306_00000000-6_rtruncnorm2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
.type _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii, @function
_Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii:
.LFB2295:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rtruncnorm_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii, .-_Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
.globl rtruncnorm_kernel
.type rtruncnorm_kernel, @function
rtruncnorm_kernel:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17rtruncnorm_kernelPfiS_S_S_S_iiiiPfiS_S_S_S_iiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size rtruncnorm_kernel, .-rtruncnorm_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rtruncnorm_kernel"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq rtruncnorm_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rtruncnorm2.hip"
.globl __device_stub__rtruncnorm_kernel # -- Begin function __device_stub__rtruncnorm_kernel
.p2align 4, 0x90
.type __device_stub__rtruncnorm_kernel,@function
__device_stub__rtruncnorm_kernel: # @__device_stub__rtruncnorm_kernel
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rtruncnorm_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size __device_stub__rtruncnorm_kernel, .Lfunc_end0-__device_stub__rtruncnorm_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rtruncnorm_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type rtruncnorm_kernel,@object # @rtruncnorm_kernel
.section .rodata,"a",@progbits
.globl rtruncnorm_kernel
.p2align 3, 0x0
rtruncnorm_kernel:
.quad __device_stub__rtruncnorm_kernel
.size rtruncnorm_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "rtruncnorm_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__rtruncnorm_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rtruncnorm_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //first cuda program
//Hitender Prakash
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
cudaMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= cudaGetLastError();
cudaMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
cudaMemcpy(d_in, h_in, siz*sizeof(double), cudaMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
cudaMemcpy(h_out, d_out, siz*sizeof(double), cudaMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} | code for sm_80
Function : _Z6squarePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0070*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*0080*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //first cuda program
//Hitender Prakash
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
cudaMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= cudaGetLastError();
cudaMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
cudaMemcpy(d_in, h_in, siz*sizeof(double), cudaMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
cudaMemcpy(h_out, d_out, siz*sizeof(double), cudaMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} | .file "tmpxft_000baf90_00000000-6_cuda_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePdS_PdS_
.type _Z27__device_stub__Z6squarePdS_PdS_, @function
_Z27__device_stub__Z6squarePdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePdS_PdS_, .-_Z27__device_stub__Z6squarePdS_PdS_
.globl _Z6squarePdS_
.type _Z6squarePdS_, @function
_Z6squarePdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePdS_, .-_Z6squarePdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nUsage: sqaure <size of array>"
.align 8
.LC3:
.string "\nBelow is the processed square values: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n%lf ----> %lf"
.section .rodata.str1.8
.align 8
.LC5:
.string "\nLast cuda error in malloc: %d"
.section .rodata.str1.1
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movslq %eax, %r13
salq $3, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L13
leal -1(%rbx), %ecx
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movq $0x000000000, (%r12,%rax,8)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L14
.L13:
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %r14d
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L15:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L16
movl %ebx, %r13d
movl $0, %ebx
leaq .LC4(%rip), %r15
.L17:
movsd 0(%rbp,%rbx,8), %xmm0
movsd (%r12,%rbx,8), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L17
.L16:
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6squarePdS_PdS_
jmp .L15
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6squarePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //first cuda program
//Hitender Prakash
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
cudaMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= cudaGetLastError();
cudaMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
cudaMemcpy(d_in, h_in, siz*sizeof(double), cudaMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
cudaMemcpy(h_out, d_out, siz*sizeof(double), cudaMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} | //first cuda program
//Hitender Prakash
#include <hip/hip_runtime.h>
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
hipMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= hipGetLastError();
hipMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
hipMemcpy(d_in, h_in, siz*sizeof(double), hipMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
hipMemcpy(h_out, d_out, siz*sizeof(double), hipMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //first cuda program
//Hitender Prakash
#include <hip/hip_runtime.h>
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
hipMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= hipGetLastError();
hipMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
hipMemcpy(d_in, h_in, siz*sizeof(double), hipMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
hipMemcpy(h_out, d_out, siz*sizeof(double), hipMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePdS_
.globl _Z6squarePdS_
.p2align 8
.type _Z6squarePdS_,@function
_Z6squarePdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v2, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePdS_, .Lfunc_end0-_Z6squarePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePdS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //first cuda program
//Hitender Prakash
#include <hip/hip_runtime.h>
#include <stdio.h>
//define gpu kernel
__global__ void square(double *d_out, double *d_in){
int pos=threadIdx.x;
d_out[pos]=d_in[pos]*d_in[pos];
}
int main(int argc, char **argv){
if(argc <2 ||argc >2){
printf("\nUsage: sqaure <size of array>");
exit(0);
}
int siz=atoi(argv[1]);
double *d_in, *d_out, *h_in, *h_out;
h_in=(double *)malloc(siz*sizeof(double));
h_out=(double *)malloc(siz*sizeof(double));
for(int i=0;i<siz;i++){
h_in[i]=i+1.0;
h_out[i]=0.0;
}
//allocate space on GPU
hipMalloc((void**)&d_in, (size_t)siz*sizeof(double));
int err= hipGetLastError();
hipMalloc((void**)&d_out, (size_t)siz*sizeof(double));
//copy from host to device
hipMemcpy(d_in, h_in, siz*sizeof(double), hipMemcpyHostToDevice);
square<<<1,siz>>>(d_out,d_in);
hipMemcpy(h_out, d_out, siz*sizeof(double), hipMemcpyDeviceToHost);
printf("\nBelow is the processed square values: ");
for(int i=0;i<siz;i++){
printf("\n%lf ----> %lf",h_in[i],h_out[i]);
}
printf("\nLast cuda error in malloc: %d",err);
printf("\n");
return 0;
} | .text
.file "cuda_square.hip"
.globl _Z21__device_stub__squarePdS_ # -- Begin function _Z21__device_stub__squarePdS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePdS_,@function
_Z21__device_stub__squarePdS_: # @_Z21__device_stub__squarePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePdS_, .Lfunc_end0-_Z21__device_stub__squarePdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_10
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %r13d
leaq (,%r13,8), %rdx
xorl %ebp, %ebp
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ebp, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
testl %r15d, %r15d
jle .LBB1_9
# %bb.7: # %.lr.ph38.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph38
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.2, %edi
movb $2, %al
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB1_8
.LBB1_9: # %._crit_edge39
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 160
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePdS_,@object # @_Z6squarePdS_
.section .rodata,"a",@progbits
.globl _Z6squarePdS_
.p2align 3, 0x0
_Z6squarePdS_:
.quad _Z21__device_stub__squarePdS_
.size _Z6squarePdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nUsage: sqaure <size of array>"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nBelow is the processed square values: "
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%lf ----> %lf"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nLast cuda error in malloc: %d"
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0070*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*0080*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePdS_
.globl _Z6squarePdS_
.p2align 8
.type _Z6squarePdS_,@function
_Z6squarePdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v2, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePdS_, .Lfunc_end0-_Z6squarePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePdS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000baf90_00000000-6_cuda_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePdS_PdS_
.type _Z27__device_stub__Z6squarePdS_PdS_, @function
_Z27__device_stub__Z6squarePdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePdS_PdS_, .-_Z27__device_stub__Z6squarePdS_PdS_
.globl _Z6squarePdS_
.type _Z6squarePdS_, @function
_Z6squarePdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePdS_, .-_Z6squarePdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nUsage: sqaure <size of array>"
.align 8
.LC3:
.string "\nBelow is the processed square values: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n%lf ----> %lf"
.section .rodata.str1.8
.align 8
.LC5:
.string "\nLast cuda error in malloc: %d"
.section .rodata.str1.1
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movslq %eax, %r13
salq $3, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L13
leal -1(%rbx), %ecx
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movq $0x000000000, (%r12,%rax,8)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L14
.L13:
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %r14d
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L15:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L16
movl %ebx, %r13d
movl $0, %ebx
leaq .LC4(%rip), %r15
.L17:
movsd 0(%rbp,%rbx,8), %xmm0
movsd (%r12,%rbx,8), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L17
.L16:
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6squarePdS_PdS_
jmp .L15
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6squarePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_square.hip"
.globl _Z21__device_stub__squarePdS_ # -- Begin function _Z21__device_stub__squarePdS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePdS_,@function
_Z21__device_stub__squarePdS_: # @_Z21__device_stub__squarePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePdS_, .Lfunc_end0-_Z21__device_stub__squarePdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_10
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %r13d
leaq (,%r13,8), %rdx
xorl %ebp, %ebp
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ebp, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
testl %r15d, %r15d
jle .LBB1_9
# %bb.7: # %.lr.ph38.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph38
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.2, %edi
movb $2, %al
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB1_8
.LBB1_9: # %._crit_edge39
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 160
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePdS_,@object # @_Z6squarePdS_
.section .rodata,"a",@progbits
.globl _Z6squarePdS_
.p2align 3, 0x0
_Z6squarePdS_:
.quad _Z21__device_stub__squarePdS_
.size _Z6squarePdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nUsage: sqaure <size of array>"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nBelow is the processed square values: "
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%lf ----> %lf"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nLast cuda error in malloc: %d"
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// TauSelection.cpp
// HiggsAnalysis_new
//
// Created by Joona Havukainen on 5/14/19.
// Copyright © 2019 Joona Havukainen. All rights reserved.
//
//#include "TauSelection.cuh"
__device__
float deltaR(float eta1, float eta2, float phi1, float phi2)
{
float deta = eta2-eta1;
float dphi = phi2-phi1;
if(dphi>=M_PI)
{
dphi=dphi-2*M_PI;
}else if(dphi<-M_PI)
{
dphi=dphi+2*M_PI;
}
return std::sqrt(deta*deta + dphi*dphi);
}
//Check that tau matches HLT tau
__device__
bool passTriggerMatching(int tauInd, int firstHLTTauInd, int nHLTTaus, float triggerTauMatchingCone, float *inputArray, float *numericalArray, int processIndex)
{
float myMinDeltaR = 9999.0;
for(int i=0; i<nHLTTaus; i++)
{
myMinDeltaR = fminf(deltaR(inputArray[tauInd+1], inputArray[firstHLTTauInd+(i*4)+1],inputArray[tauInd+2], inputArray[firstHLTTauInd+(i*4)+2]),myMinDeltaR);
}
return myMinDeltaR<triggerTauMatchingCone;
}
//Check tau prongs
//Useless at the moment, just accept any number of prongs
__device__
bool passNProngsCut(int tauNProngs, int tauDecayMode)
{
return true;
}
//Just the bool in tauDecayModeFinding, made into function for consistency
__device__
bool passDecayModeFinding(int tauDecayModeFinding)
{
return tauDecayModeFinding;
}
//Find out what are generic discriminators
__device__
bool passGenericDiscriminators()
{
return true;
}
__device__
bool passElectronDiscriminator(int tauElectronDiscriminator)
{
return tauElectronDiscriminator;
}
__device__
bool passMuonDiscriminator(int tauMuonDiscriminator)
{
return tauMuonDiscriminator;
}
__device__
bool passTauIsolation(int tauIsolationDiscriminator)
{
return tauIsolationDiscriminator;
}
__global__
void tauSelection(float *inputArray, bool *passedArray, bool *passed, bool *selectedTaus, float *numericalResults, int variablesPerEvent, int tauIndex, int hltIndex, int nTaus, int nEvents)
{
//Index of the processed event
int processIndex = blockIdx.x * blockDim.x + threadIdx.x;
if(processIndex<nEvents)
{
//Index of the first variable of the event processed in the inputArray
int localIndex = processIndex * variablesPerEvent;
bool _passed = false;
//Tau loop
for(int j=0; j<inputArray[processIndex*variablesPerEvent+0]; j++)
{
int thisTau = processIndex*nTaus+j;
selectedTaus[thisTau]=passTriggerMatching(localIndex+tauIndex+j*11, localIndex+hltIndex, nTaus, 0.4, inputArray, numericalResults, processIndex);
selectedTaus[thisTau]=passNProngsCut(inputArray[localIndex+tauIndex+j*11+5], inputArray[localIndex+tauIndex+j*11+6])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passDecayModeFinding(inputArray[localIndex+tauIndex+j*11+7])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passGenericDiscriminators()&&selectedTaus[thisTau];
selectedTaus[thisTau]=passElectronDiscriminator(inputArray[localIndex+tauIndex+j*11+8])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passMuonDiscriminator(inputArray[localIndex+tauIndex+j*11+9])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passTauIsolation(inputArray[localIndex+tauIndex+j*11+10])&&selectedTaus[thisTau];
_passed = (_passed || selectedTaus[thisTau]);
}
passed[processIndex]=passed[processIndex] && _passed;
}
} | .file "tmpxft_00105d82_00000000-6_TauSelection.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6deltaRffff
.type _Z6deltaRffff, @function
_Z6deltaRffff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z6deltaRffff, .-_Z6deltaRffff
.globl _Z19passTriggerMatchingiiifPfS_i
.type _Z19passTriggerMatchingiiifPfS_i, @function
_Z19passTriggerMatchingiiifPfS_i:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z19passTriggerMatchingiiifPfS_i, .-_Z19passTriggerMatchingiiifPfS_i
.globl _Z14passNProngsCutii
.type _Z14passNProngsCutii, @function
_Z14passNProngsCutii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14passNProngsCutii, .-_Z14passNProngsCutii
.globl _Z20passDecayModeFindingi
.type _Z20passDecayModeFindingi, @function
_Z20passDecayModeFindingi:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z20passDecayModeFindingi, .-_Z20passDecayModeFindingi
.globl _Z25passGenericDiscriminatorsv
.type _Z25passGenericDiscriminatorsv, @function
_Z25passGenericDiscriminatorsv:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z25passGenericDiscriminatorsv, .-_Z25passGenericDiscriminatorsv
.globl _Z25passElectronDiscriminatori
.type _Z25passElectronDiscriminatori, @function
_Z25passElectronDiscriminatori:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z25passElectronDiscriminatori, .-_Z25passElectronDiscriminatori
.globl _Z21passMuonDiscriminatori
.type _Z21passMuonDiscriminatori, @function
_Z21passMuonDiscriminatori:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z21passMuonDiscriminatori, .-_Z21passMuonDiscriminatori
.globl _Z16passTauIsolationi
.type _Z16passTauIsolationi, @function
_Z16passTauIsolationi:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z16passTauIsolationi, .-_Z16passTauIsolationi
.globl _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
.type _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii, @function
_Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii:
.LFB2059:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12tauSelectionPfPbS0_S0_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii, .-_Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
.globl _Z12tauSelectionPfPbS0_S0_S_iiiii
.type _Z12tauSelectionPfPbS0_S0_S_iiiii, @function
_Z12tauSelectionPfPbS0_S0_S_iiiii:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12tauSelectionPfPbS0_S0_S_iiiii, .-_Z12tauSelectionPfPbS0_S0_S_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12tauSelectionPfPbS0_S0_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12tauSelectionPfPbS0_S0_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// TauSelection.cpp
// HiggsAnalysis_new
//
// Created by Joona Havukainen on 5/14/19.
// Copyright © 2019 Joona Havukainen. All rights reserved.
//
//#include "TauSelection.cuh"
__device__
float deltaR(float eta1, float eta2, float phi1, float phi2)
{
float deta = eta2-eta1;
float dphi = phi2-phi1;
if(dphi>=M_PI)
{
dphi=dphi-2*M_PI;
}else if(dphi<-M_PI)
{
dphi=dphi+2*M_PI;
}
return std::sqrt(deta*deta + dphi*dphi);
}
//Check that tau matches HLT tau
__device__
bool passTriggerMatching(int tauInd, int firstHLTTauInd, int nHLTTaus, float triggerTauMatchingCone, float *inputArray, float *numericalArray, int processIndex)
{
float myMinDeltaR = 9999.0;
for(int i=0; i<nHLTTaus; i++)
{
myMinDeltaR = fminf(deltaR(inputArray[tauInd+1], inputArray[firstHLTTauInd+(i*4)+1],inputArray[tauInd+2], inputArray[firstHLTTauInd+(i*4)+2]),myMinDeltaR);
}
return myMinDeltaR<triggerTauMatchingCone;
}
//Check tau prongs
//Useless at the moment, just accept any number of prongs
__device__
bool passNProngsCut(int tauNProngs, int tauDecayMode)
{
return true;
}
//Just the bool in tauDecayModeFinding, made into function for consistency
__device__
bool passDecayModeFinding(int tauDecayModeFinding)
{
return tauDecayModeFinding;
}
//Find out what are generic discriminators
__device__
bool passGenericDiscriminators()
{
return true;
}
__device__
bool passElectronDiscriminator(int tauElectronDiscriminator)
{
return tauElectronDiscriminator;
}
__device__
bool passMuonDiscriminator(int tauMuonDiscriminator)
{
return tauMuonDiscriminator;
}
__device__
bool passTauIsolation(int tauIsolationDiscriminator)
{
return tauIsolationDiscriminator;
}
__global__
void tauSelection(float *inputArray, bool *passedArray, bool *passed, bool *selectedTaus, float *numericalResults, int variablesPerEvent, int tauIndex, int hltIndex, int nTaus, int nEvents)
{
//Index of the processed event
int processIndex = blockIdx.x * blockDim.x + threadIdx.x;
if(processIndex<nEvents)
{
//Index of the first variable of the event processed in the inputArray
int localIndex = processIndex * variablesPerEvent;
bool _passed = false;
//Tau loop
for(int j=0; j<inputArray[processIndex*variablesPerEvent+0]; j++)
{
int thisTau = processIndex*nTaus+j;
selectedTaus[thisTau]=passTriggerMatching(localIndex+tauIndex+j*11, localIndex+hltIndex, nTaus, 0.4, inputArray, numericalResults, processIndex);
selectedTaus[thisTau]=passNProngsCut(inputArray[localIndex+tauIndex+j*11+5], inputArray[localIndex+tauIndex+j*11+6])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passDecayModeFinding(inputArray[localIndex+tauIndex+j*11+7])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passGenericDiscriminators()&&selectedTaus[thisTau];
selectedTaus[thisTau]=passElectronDiscriminator(inputArray[localIndex+tauIndex+j*11+8])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passMuonDiscriminator(inputArray[localIndex+tauIndex+j*11+9])&&selectedTaus[thisTau];
selectedTaus[thisTau]=passTauIsolation(inputArray[localIndex+tauIndex+j*11+10])&&selectedTaus[thisTau];
_passed = (_passed || selectedTaus[thisTau]);
}
passed[processIndex]=passed[processIndex] && _passed;
}
} | #pragma once
#include <hip/hip_runtime.h>
extern __global__ void tauSelection(float *array, bool *passedArray, bool *passed, bool *selectedTaus, float *numericalArray, int variablesPerEvent, int tauIndex, int hltIndex, int nTaus, int nEvents); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
extern __global__ void tauSelection(float *array, bool *passedArray, bool *passed, bool *selectedTaus, float *numericalArray, int variablesPerEvent, int tauIndex, int hltIndex, int nTaus, int nEvents); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
extern __global__ void tauSelection(float *array, bool *passedArray, bool *passed, bool *selectedTaus, float *numericalArray, int variablesPerEvent, int tauIndex, int hltIndex, int nTaus, int nEvents); | .text
.file "TauSelection.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00105d82_00000000-6_TauSelection.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6deltaRffff
.type _Z6deltaRffff, @function
_Z6deltaRffff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z6deltaRffff, .-_Z6deltaRffff
.globl _Z19passTriggerMatchingiiifPfS_i
.type _Z19passTriggerMatchingiiifPfS_i, @function
_Z19passTriggerMatchingiiifPfS_i:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z19passTriggerMatchingiiifPfS_i, .-_Z19passTriggerMatchingiiifPfS_i
.globl _Z14passNProngsCutii
.type _Z14passNProngsCutii, @function
_Z14passNProngsCutii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14passNProngsCutii, .-_Z14passNProngsCutii
.globl _Z20passDecayModeFindingi
.type _Z20passDecayModeFindingi, @function
_Z20passDecayModeFindingi:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z20passDecayModeFindingi, .-_Z20passDecayModeFindingi
.globl _Z25passGenericDiscriminatorsv
.type _Z25passGenericDiscriminatorsv, @function
_Z25passGenericDiscriminatorsv:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z25passGenericDiscriminatorsv, .-_Z25passGenericDiscriminatorsv
.globl _Z25passElectronDiscriminatori
.type _Z25passElectronDiscriminatori, @function
_Z25passElectronDiscriminatori:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z25passElectronDiscriminatori, .-_Z25passElectronDiscriminatori
.globl _Z21passMuonDiscriminatori
.type _Z21passMuonDiscriminatori, @function
_Z21passMuonDiscriminatori:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z21passMuonDiscriminatori, .-_Z21passMuonDiscriminatori
.globl _Z16passTauIsolationi
.type _Z16passTauIsolationi, @function
_Z16passTauIsolationi:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z16passTauIsolationi, .-_Z16passTauIsolationi
.globl _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
.type _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii, @function
_Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii:
.LFB2059:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12tauSelectionPfPbS0_S0_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii, .-_Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
.globl _Z12tauSelectionPfPbS0_S0_S_iiiii
.type _Z12tauSelectionPfPbS0_S0_S_iiiii, @function
_Z12tauSelectionPfPbS0_S0_S_iiiii:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z12tauSelectionPfPbS0_S0_S_iiiiiPfPbS0_S0_S_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12tauSelectionPfPbS0_S0_S_iiiii, .-_Z12tauSelectionPfPbS0_S0_S_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12tauSelectionPfPbS0_S0_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12tauSelectionPfPbS0_S0_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TauSelection.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
int l, m, n, R, displacement;
if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
else displacement = 1;
int row_index = blockIdx.y * blockDim.y + threadIdx.y;
int col_index = blockIdx.x * blockDim.x + threadIdx.x;
if(row_index < matrix_size && col_index < matrix_size){
for(m = 0; m < displacement; m++){
for(n = 0; n < displacement; n++){
R = 0;
for(l = 0; l < matrix_size; l++){
int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
R += A * B;
}
gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
}
}
}
}
int main(int argc, char** argv){
srand(time(NULL));
double runtime;
struct timespec begin, end;
// Inisialisasi parameter dari user input
int mode = atoi(argv[1]);
int matrix_size = atoi(argv[2]);
int igrid = atoi(argv[3]);
int iblock = atoi(argv[4]);
//Debug print variabel user input
//printf("Mode: %d\n", mode);
//printf("Size %d x %d\n", matrix_size, matrix_size);
//printf("Grid: %d\n", igrid);
//printf("Block:%d\n", iblock);
// Inisailiasai pada Host
int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
int *matrixA = (int *)malloc(matrixBytes);
int *matrixB = (int *)malloc(matrixBytes);
int *result = (int *)malloc(matrixBytes);
int i, j, k;
//Inisialisasi martrix
for(i = 0; i < matrix_size * matrix_size; i++){
matrixA[i] = rand() % 99 + 1;
matrixB[i] = rand() % 99 + 1;
}
//Operasi dengan 1 GPU
//if(mode < 2){
clock_gettime(CLOCK_REALTIME, &begin);
//Inisialisasi pada GPU
int *gpu_matrixA, *gpu_matrixB, *gpu_result;
cudaMalloc((void **) &gpu_matrixA, matrixBytes);
cudaMalloc((void **) &gpu_matrixB, matrixBytes);
cudaMalloc((void **) &gpu_result, matrixBytes);
cudaMemcpy(gpu_matrixA, matrixA, matrixBytes, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_matrixB, matrixB, matrixBytes, cudaMemcpyHostToDevice);
//Mulai operasi pada device
dim3 grid(igrid, igrid);
dim3 block(iblock, iblock);
matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);
//Return hasil perkalian
cudaMemcpy(result, gpu_result, matrixBytes, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
/*}else{
//Operasi pada multiple GPU
//Check Device
clock_gettime(CLOCK_REALTIME, &begin);
int device_count;
cudaGetDeviceCount(&device_count);
printf("Device: %d\n", device_count);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
}*/
//Operasi sekuensial
if(mode == 1 || mode == 3){
int right_answer = 0;
int *seqresult = (int *)malloc(matrixBytes);
for (i = 0; i < matrix_size; i++){
for (j = 0; j < matrix_size; j++){
seqresult[i * matrix_size + j] = 0;
for (k = 0; k < matrix_size; k++)
seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
//printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
}
}
if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
free(seqresult);
}
//Membebaskan Device
cudaFree(gpu_matrixB);
cudaFree(gpu_matrixB);
cudaFree(gpu_result);
//Membebaskan Host
free(matrixA);
free(matrixB);
free(result);
} | .file "tmpxft_0015d03a_00000000-6_mm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
.type _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, @function
_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16matrixmul_kernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, .-_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
.globl _Z16matrixmul_kernelPiS_S_iii
.type _Z16matrixmul_kernelPiS_S_iii, @function
_Z16matrixmul_kernelPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16matrixmul_kernelPiS_S_iii, .-_Z16matrixmul_kernelPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Running Time: %f\n\n"
.LC2:
.string "The answer is matched.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 28(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 48(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %r14d, %r15d
imull %r14d, %r15d
leal 0(,%r15,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
testl %r15d, %r15d
jle .L12
movslq %r15d, %r13
leaq (%rbx,%r13,4), %r13
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r13, %rbx
jne .L13
.L12:
leaq 112(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movl %eax, 88(%rsp)
movl %eax, 92(%rsp)
movq 16(%rsp), %rax
movl %eax, 100(%rsp)
movl %eax, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 80(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 56(%rsp), %eax
andl $-3, %eax
cmpl $1, %eax
je .L30
.L15:
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl 16(%rsp), %r9d
movl 48(%rsp), %r8d
movl 28(%rsp), %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
jmp .L14
.L30:
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r14d, %r14d
jle .L23
movslq %r14d, %rdi
salq $2, %rdi
movq 40(%rsp), %r12
movq 32(%rsp), %rax
movq %rax, %rbp
leal -1(%r14), %r13d
leaq 4(%rax,%r13,4), %r8
movq %rbx, %rdx
movl $0, %r14d
movl $0, %eax
movl %r15d, 48(%rsp)
movq %rbx, 56(%rsp)
movl %eax, %r9d
jmp .L17
.L33:
addl $1, %r14d
.L19:
leaq 1(%r10), %rax
addq $4, %r11
addq $4, %rbx
cmpq %r13, %r10
je .L32
movq %rax, %r10
.L20:
movq %r11, %r15
movq %rbx, %rsi
movq %rbp, %rax
movl $0, %r9d
.L18:
movl (%rax), %ecx
imull (%rsi), %ecx
addl %ecx, %r9d
addq $4, %rax
addq %rdi, %rsi
cmpq %r8, %rax
jne .L18
movl %r9d, (%r15)
cmpl (%r12,%r10,4), %r9d
jne .L19
jmp .L33
.L32:
movl 16(%rsp), %r9d
addl $1, %r9d
addq %rdi, %r12
addq %rdi, %rbp
addq %rdi, %r8
addq %rdi, %rdx
movl 28(%rsp), %eax
cmpl %eax, %r9d
je .L27
.L17:
movq 8(%rsp), %rbx
movq %rdx, %r11
movl $0, %r10d
movl %r9d, 16(%rsp)
jmp .L20
.L23:
movl $0, %r14d
jmp .L16
.L27:
movl 48(%rsp), %r15d
movq 56(%rsp), %rbx
.L16:
cmpl %r14d, %r15d
je .L34
.L21:
movq %rbx, %rdi
call free@PLT
jmp .L15
.L34:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16matrixmul_kernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixmul_kernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
int l, m, n, R, displacement;
if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
else displacement = 1;
int row_index = blockIdx.y * blockDim.y + threadIdx.y;
int col_index = blockIdx.x * blockDim.x + threadIdx.x;
if(row_index < matrix_size && col_index < matrix_size){
for(m = 0; m < displacement; m++){
for(n = 0; n < displacement; n++){
R = 0;
for(l = 0; l < matrix_size; l++){
int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
R += A * B;
}
gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
}
}
}
}
int main(int argc, char** argv){
srand(time(NULL));
double runtime;
struct timespec begin, end;
// Inisialisasi parameter dari user input
int mode = atoi(argv[1]);
int matrix_size = atoi(argv[2]);
int igrid = atoi(argv[3]);
int iblock = atoi(argv[4]);
//Debug print variabel user input
//printf("Mode: %d\n", mode);
//printf("Size %d x %d\n", matrix_size, matrix_size);
//printf("Grid: %d\n", igrid);
//printf("Block:%d\n", iblock);
// Inisailiasai pada Host
int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
int *matrixA = (int *)malloc(matrixBytes);
int *matrixB = (int *)malloc(matrixBytes);
int *result = (int *)malloc(matrixBytes);
int i, j, k;
//Inisialisasi martrix
for(i = 0; i < matrix_size * matrix_size; i++){
matrixA[i] = rand() % 99 + 1;
matrixB[i] = rand() % 99 + 1;
}
//Operasi dengan 1 GPU
//if(mode < 2){
clock_gettime(CLOCK_REALTIME, &begin);
//Inisialisasi pada GPU
int *gpu_matrixA, *gpu_matrixB, *gpu_result;
cudaMalloc((void **) &gpu_matrixA, matrixBytes);
cudaMalloc((void **) &gpu_matrixB, matrixBytes);
cudaMalloc((void **) &gpu_result, matrixBytes);
cudaMemcpy(gpu_matrixA, matrixA, matrixBytes, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_matrixB, matrixB, matrixBytes, cudaMemcpyHostToDevice);
//Mulai operasi pada device
dim3 grid(igrid, igrid);
dim3 block(iblock, iblock);
matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);
//Return hasil perkalian
cudaMemcpy(result, gpu_result, matrixBytes, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
/*}else{
//Operasi pada multiple GPU
//Check Device
clock_gettime(CLOCK_REALTIME, &begin);
int device_count;
cudaGetDeviceCount(&device_count);
printf("Device: %d\n", device_count);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
}*/
//Operasi sekuensial
if(mode == 1 || mode == 3){
int right_answer = 0;
int *seqresult = (int *)malloc(matrixBytes);
for (i = 0; i < matrix_size; i++){
for (j = 0; j < matrix_size; j++){
seqresult[i * matrix_size + j] = 0;
for (k = 0; k < matrix_size; k++)
seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
//printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
}
}
if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
free(seqresult);
}
//Membebaskan Device
cudaFree(gpu_matrixB);
cudaFree(gpu_matrixB);
cudaFree(gpu_result);
//Membebaskan Host
free(matrixA);
free(matrixB);
free(result);
} | //Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
int l, m, n, R, displacement;
if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
else displacement = 1;
int row_index = blockIdx.y * blockDim.y + threadIdx.y;
int col_index = blockIdx.x * blockDim.x + threadIdx.x;
if(row_index < matrix_size && col_index < matrix_size){
for(m = 0; m < displacement; m++){
for(n = 0; n < displacement; n++){
R = 0;
for(l = 0; l < matrix_size; l++){
int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
R += A * B;
}
gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
}
}
}
}
int main(int argc, char** argv){
srand(time(NULL));
double runtime;
struct timespec begin, end;
// Inisialisasi parameter dari user input
int mode = atoi(argv[1]);
int matrix_size = atoi(argv[2]);
int igrid = atoi(argv[3]);
int iblock = atoi(argv[4]);
//Debug print variabel user input
//printf("Mode: %d\n", mode);
//printf("Size %d x %d\n", matrix_size, matrix_size);
//printf("Grid: %d\n", igrid);
//printf("Block:%d\n", iblock);
// Inisailiasai pada Host
int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
int *matrixA = (int *)malloc(matrixBytes);
int *matrixB = (int *)malloc(matrixBytes);
int *result = (int *)malloc(matrixBytes);
int i, j, k;
//Inisialisasi martrix
for(i = 0; i < matrix_size * matrix_size; i++){
matrixA[i] = rand() % 99 + 1;
matrixB[i] = rand() % 99 + 1;
}
//Operasi dengan 1 GPU
//if(mode < 2){
clock_gettime(CLOCK_REALTIME, &begin);
//Inisialisasi pada GPU
int *gpu_matrixA, *gpu_matrixB, *gpu_result;
hipMalloc((void **) &gpu_matrixA, matrixBytes);
hipMalloc((void **) &gpu_matrixB, matrixBytes);
hipMalloc((void **) &gpu_result, matrixBytes);
hipMemcpy(gpu_matrixA, matrixA, matrixBytes, hipMemcpyHostToDevice);
hipMemcpy(gpu_matrixB, matrixB, matrixBytes, hipMemcpyHostToDevice);
//Mulai operasi pada device
dim3 grid(igrid, igrid);
dim3 block(iblock, iblock);
matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);
//Return hasil perkalian
hipMemcpy(result, gpu_result, matrixBytes, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
/*}else{
//Operasi pada multiple GPU
//Check Device
clock_gettime(CLOCK_REALTIME, &begin);
int device_count;
cudaGetDeviceCount(&device_count);
printf("Device: %d\n", device_count);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
}*/
//Operasi sekuensial
if(mode == 1 || mode == 3){
int right_answer = 0;
int *seqresult = (int *)malloc(matrixBytes);
for (i = 0; i < matrix_size; i++){
for (j = 0; j < matrix_size; j++){
seqresult[i * matrix_size + j] = 0;
for (k = 0; k < matrix_size; k++)
seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
//printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
}
}
if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
free(seqresult);
}
//Membebaskan Device
hipFree(gpu_matrixB);
hipFree(gpu_matrixB);
hipFree(gpu_result);
//Membebaskan Host
free(matrixA);
free(matrixB);
free(result);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
int l, m, n, R, displacement;
if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
else displacement = 1;
int row_index = blockIdx.y * blockDim.y + threadIdx.y;
int col_index = blockIdx.x * blockDim.x + threadIdx.x;
if(row_index < matrix_size && col_index < matrix_size){
for(m = 0; m < displacement; m++){
for(n = 0; n < displacement; n++){
R = 0;
for(l = 0; l < matrix_size; l++){
int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
R += A * B;
}
gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
}
}
}
}
int main(int argc, char** argv){
srand(time(NULL));
double runtime;
struct timespec begin, end;
// Inisialisasi parameter dari user input
int mode = atoi(argv[1]);
int matrix_size = atoi(argv[2]);
int igrid = atoi(argv[3]);
int iblock = atoi(argv[4]);
//Debug print variabel user input
//printf("Mode: %d\n", mode);
//printf("Size %d x %d\n", matrix_size, matrix_size);
//printf("Grid: %d\n", igrid);
//printf("Block:%d\n", iblock);
// Inisailiasai pada Host
int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
int *matrixA = (int *)malloc(matrixBytes);
int *matrixB = (int *)malloc(matrixBytes);
int *result = (int *)malloc(matrixBytes);
int i, j, k;
//Inisialisasi martrix
for(i = 0; i < matrix_size * matrix_size; i++){
matrixA[i] = rand() % 99 + 1;
matrixB[i] = rand() % 99 + 1;
}
//Operasi dengan 1 GPU
//if(mode < 2){
clock_gettime(CLOCK_REALTIME, &begin);
//Inisialisasi pada GPU
int *gpu_matrixA, *gpu_matrixB, *gpu_result;
hipMalloc((void **) &gpu_matrixA, matrixBytes);
hipMalloc((void **) &gpu_matrixB, matrixBytes);
hipMalloc((void **) &gpu_result, matrixBytes);
hipMemcpy(gpu_matrixA, matrixA, matrixBytes, hipMemcpyHostToDevice);
hipMemcpy(gpu_matrixB, matrixB, matrixBytes, hipMemcpyHostToDevice);
//Mulai operasi pada device
dim3 grid(igrid, igrid);
dim3 block(iblock, iblock);
matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);
//Return hasil perkalian
hipMemcpy(result, gpu_result, matrixBytes, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
/*}else{
//Operasi pada multiple GPU
//Check Device
clock_gettime(CLOCK_REALTIME, &begin);
int device_count;
cudaGetDeviceCount(&device_count);
printf("Device: %d\n", device_count);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
}*/
//Operasi sekuensial
if(mode == 1 || mode == 3){
int right_answer = 0;
int *seqresult = (int *)malloc(matrixBytes);
for (i = 0; i < matrix_size; i++){
for (j = 0; j < matrix_size; j++){
seqresult[i * matrix_size + j] = 0;
for (k = 0; k < matrix_size; k++)
seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
//printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
}
}
if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
free(seqresult);
}
//Membebaskan Device
hipFree(gpu_matrixB);
hipFree(gpu_matrixB);
hipFree(gpu_result);
//Membebaskan Host
free(matrixA);
free(matrixB);
free(result);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixmul_kernelPiS_S_iii
.globl _Z16matrixmul_kernelPiS_S_iii
.p2align 8
.type _Z16matrixmul_kernelPiS_S_iii,@function
_Z16matrixmul_kernelPiS_S_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
s_mov_b32 s10, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s3, s2
s_cbranch_scc1 .LBB0_2
s_ashr_i32 s4, s3, 31
s_ashr_i32 s7, s2, 31
s_add_i32 s3, s3, s4
s_add_i32 s8, s2, s7
s_xor_b32 s3, s3, s4
s_xor_b32 s8, s8, s7
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_xor_b32 s4, s7, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s5, s6
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s8, s5
s_mul_i32 s6, s5, s3
s_add_i32 s7, s5, 1
s_sub_i32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s5, s7, s5
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s5, 1
s_cmp_ge_u32 s6, s3
s_cselect_b32 s3, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s4
s_sub_i32 s10, s3, s4
.LBB0_2:
s_load_b32 s3, s[0:1], 0x34
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_gt_i32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
s_cselect_b32 s3, -1, 0
v_max_i32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s3, s10, s2
v_mul_lo_u32 v0, v2, s10
v_mul_lo_u32 v11, v1, s10
v_mul_lo_u32 v1, s3, v1
s_cmp_gt_i32 s2, 0
s_cselect_b32 s12, -1, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s2, v1
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s11, s10
s_cbranch_scc0 .LBB0_11
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s11, v11
s_mov_b32 s3, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v6, s2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v5, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_6:
v_mov_b32_e32 v6, 0
.LBB0_7:
v_add_nc_u32_e32 v7, s3, v2
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s3, s10
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_store_b32 v[7:8], v6, off
s_cbranch_scc0 .LBB0_4
.LBB0_8:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
v_mov_b32_e32 v10, v4
s_mov_b32 s13, s2
v_mov_b32_e32 v9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_mov_b32_e32 v6, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.p2align 6
.LBB0_10:
global_load_b32 v14, v[9:10], off
global_load_b32 v15, v[7:8], off
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[12:13], null, v15, v14, v[6:7]
v_add_co_u32 v7, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_mov_b32_e32 v6, v12
s_cbranch_scc1 .LBB0_10
s_branch .LBB0_7
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrixmul_kernelPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrixmul_kernelPiS_S_iii, .Lfunc_end0-_Z16matrixmul_kernelPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrixmul_kernelPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrixmul_kernelPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block) | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
int l, m, n, R, displacement;
if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
else displacement = 1;
int row_index = blockIdx.y * blockDim.y + threadIdx.y;
int col_index = blockIdx.x * blockDim.x + threadIdx.x;
if(row_index < matrix_size && col_index < matrix_size){
for(m = 0; m < displacement; m++){
for(n = 0; n < displacement; n++){
R = 0;
for(l = 0; l < matrix_size; l++){
int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
R += A * B;
}
gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
}
}
}
}
int main(int argc, char** argv){
srand(time(NULL));
double runtime;
struct timespec begin, end;
// Inisialisasi parameter dari user input
int mode = atoi(argv[1]);
int matrix_size = atoi(argv[2]);
int igrid = atoi(argv[3]);
int iblock = atoi(argv[4]);
//Debug print variabel user input
//printf("Mode: %d\n", mode);
//printf("Size %d x %d\n", matrix_size, matrix_size);
//printf("Grid: %d\n", igrid);
//printf("Block:%d\n", iblock);
// Inisailiasai pada Host
int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
int *matrixA = (int *)malloc(matrixBytes);
int *matrixB = (int *)malloc(matrixBytes);
int *result = (int *)malloc(matrixBytes);
int i, j, k;
//Inisialisasi martrix
for(i = 0; i < matrix_size * matrix_size; i++){
matrixA[i] = rand() % 99 + 1;
matrixB[i] = rand() % 99 + 1;
}
//Operasi dengan 1 GPU
//if(mode < 2){
clock_gettime(CLOCK_REALTIME, &begin);
//Inisialisasi pada GPU
int *gpu_matrixA, *gpu_matrixB, *gpu_result;
hipMalloc((void **) &gpu_matrixA, matrixBytes);
hipMalloc((void **) &gpu_matrixB, matrixBytes);
hipMalloc((void **) &gpu_result, matrixBytes);
hipMemcpy(gpu_matrixA, matrixA, matrixBytes, hipMemcpyHostToDevice);
hipMemcpy(gpu_matrixB, matrixB, matrixBytes, hipMemcpyHostToDevice);
//Mulai operasi pada device
dim3 grid(igrid, igrid);
dim3 block(iblock, iblock);
matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);
//Return hasil perkalian
hipMemcpy(result, gpu_result, matrixBytes, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
/*}else{
//Operasi pada multiple GPU
//Check Device
clock_gettime(CLOCK_REALTIME, &begin);
int device_count;
cudaGetDeviceCount(&device_count);
printf("Device: %d\n", device_count);
clock_gettime(CLOCK_REALTIME, &end);
runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
printf("Running Time: %f\n\n", runtime);
}*/
//Operasi sekuensial
if(mode == 1 || mode == 3){
int right_answer = 0;
int *seqresult = (int *)malloc(matrixBytes);
for (i = 0; i < matrix_size; i++){
for (j = 0; j < matrix_size; j++){
seqresult[i * matrix_size + j] = 0;
for (k = 0; k < matrix_size; k++)
seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
//printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
}
}
if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
free(seqresult);
}
//Membebaskan Device
hipFree(gpu_matrixB);
hipFree(gpu_matrixB);
hipFree(gpu_result);
//Membebaskan Host
free(matrixA);
free(matrixB);
free(result);
} | .text
.file "mm.hip"
.globl _Z31__device_stub__matrixmul_kernelPiS_S_iii # -- Begin function _Z31__device_stub__matrixmul_kernelPiS_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__matrixmul_kernelPiS_S_iii,@function
_Z31__device_stub__matrixmul_kernelPiS_S_iii: # @_Z31__device_stub__matrixmul_kernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16matrixmul_kernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixmul_kernelPiS_S_iii, .Lfunc_end0-_Z31__device_stub__matrixmul_kernelPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 80(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movl %ebx, %eax
imull %eax, %eax
movq %rax, 48(%rsp) # 8-byte Spill
leal (,%rax,4), %eax
movslq %eax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbx, (%rsp) # 8-byte Spill
testl %ebx, %ebx
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq 48(%rsp), %r13 # 8-byte Reload
cmpl $1, %r13d
# kill: def $r13d killed $r13d killed $r13 def $r13
adcl $0, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 216(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rbx # 8-byte Reload
movl %ebx, %eax
movq %rbx, %rdi
shlq $32, %rdi
orq %rax, %rdi
movq 64(%rsp), %r12 # 8-byte Reload
movl %r12d, %eax
movq %r12, %rdx
shlq $32, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq (%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
movl %ebx, 40(%rsp)
movl %r12d, 36(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z16matrixmul_kernelPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
subq 216(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 224(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 80(%rsp), %rax # 8-byte Reload
andl $-3, %eax
cmpl $1, %eax
jne .LBB1_15
# %bb.6:
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_13
# %bb.7: # %.preheader.lr.ph
movl (%rsp), %eax # 4-byte Reload
leaq (,%rax,4), %rcx
xorl %edx, %edx
xorl %esi, %esi
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
# Child Loop BB1_10 Depth 3
movl %edx, %edi
leaq (%r14,%rdi,4), %rdi
movq %rsi, %r8
imulq %rax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %r15, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph96
# Parent Loop BB1_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_10 Depth 3
xorl %r11d, %r11d
movq %r9, %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_8 Depth=1
# Parent Loop BB1_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %ebx
imull (%rdi,%r11,4), %ebx
addl %ebx, %r12d
incq %r11
addq %rcx, %r13
cmpq %r11, %rax
jne .LBB1_10
# %bb.11: # %._crit_edge97
# in Loop: Header=BB1_9 Depth=2
xorl %r11d, %r11d
cmpl (%r8,%r10,4), %r12d
sete %r11b
addl %r11d, %ebp
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB1_9
# %bb.12: # %._crit_edge101
# in Loop: Header=BB1_8 Depth=1
incq %rsi
addl (%rsp), %edx # 4-byte Folded Reload
cmpq %rax, %rsi
jne .LBB1_8
.LBB1_13: # %._crit_edge104
cmpl 48(%rsp), %ebp # 4-byte Folded Reload
jne .LBB1_15
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_15:
movq 8(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixmul_kernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixmul_kernelPiS_S_iii,@object # @_Z16matrixmul_kernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z16matrixmul_kernelPiS_S_iii
.p2align 3, 0x0
_Z16matrixmul_kernelPiS_S_iii:
.quad _Z31__device_stub__matrixmul_kernelPiS_S_iii
.size _Z16matrixmul_kernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running Time: %f\n\n"
.size .L.str, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrixmul_kernelPiS_S_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The answer is matched."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixmul_kernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixmul_kernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015d03a_00000000-6_mm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
.type _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, @function
_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16matrixmul_kernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, .-_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
.globl _Z16matrixmul_kernelPiS_S_iii
.type _Z16matrixmul_kernelPiS_S_iii, @function
_Z16matrixmul_kernelPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16matrixmul_kernelPiS_S_iii, .-_Z16matrixmul_kernelPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Running Time: %f\n\n"
.LC2:
.string "The answer is matched.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 28(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 48(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %r14d, %r15d
imull %r14d, %r15d
leal 0(,%r15,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
testl %r15d, %r15d
jle .L12
movslq %r15d, %r13
leaq (%rbx,%r13,4), %r13
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r13, %rbx
jne .L13
.L12:
leaq 112(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movl %eax, 88(%rsp)
movl %eax, 92(%rsp)
movq 16(%rsp), %rax
movl %eax, 100(%rsp)
movl %eax, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 80(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 56(%rsp), %eax
andl $-3, %eax
cmpl $1, %eax
je .L30
.L15:
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl 16(%rsp), %r9d
movl 48(%rsp), %r8d
movl 28(%rsp), %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
jmp .L14
.L30:
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r14d, %r14d
jle .L23
movslq %r14d, %rdi
salq $2, %rdi
movq 40(%rsp), %r12
movq 32(%rsp), %rax
movq %rax, %rbp
leal -1(%r14), %r13d
leaq 4(%rax,%r13,4), %r8
movq %rbx, %rdx
movl $0, %r14d
movl $0, %eax
movl %r15d, 48(%rsp)
movq %rbx, 56(%rsp)
movl %eax, %r9d
jmp .L17
.L33:
addl $1, %r14d
.L19:
leaq 1(%r10), %rax
addq $4, %r11
addq $4, %rbx
cmpq %r13, %r10
je .L32
movq %rax, %r10
.L20:
movq %r11, %r15
movq %rbx, %rsi
movq %rbp, %rax
movl $0, %r9d
.L18:
movl (%rax), %ecx
imull (%rsi), %ecx
addl %ecx, %r9d
addq $4, %rax
addq %rdi, %rsi
cmpq %r8, %rax
jne .L18
movl %r9d, (%r15)
cmpl (%r12,%r10,4), %r9d
jne .L19
jmp .L33
.L32:
movl 16(%rsp), %r9d
addl $1, %r9d
addq %rdi, %r12
addq %rdi, %rbp
addq %rdi, %r8
addq %rdi, %rdx
movl 28(%rsp), %eax
cmpl %eax, %r9d
je .L27
.L17:
movq 8(%rsp), %rbx
movq %rdx, %r11
movl $0, %r10d
movl %r9d, 16(%rsp)
jmp .L20
.L23:
movl $0, %r14d
jmp .L16
.L27:
movl 48(%rsp), %r15d
movq 56(%rsp), %rbx
.L16:
cmpl %r14d, %r15d
je .L34
.L21:
movq %rbx, %rdi
call free@PLT
jmp .L15
.L34:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16matrixmul_kernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixmul_kernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm.hip"
.globl _Z31__device_stub__matrixmul_kernelPiS_S_iii # -- Begin function _Z31__device_stub__matrixmul_kernelPiS_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__matrixmul_kernelPiS_S_iii,@function
_Z31__device_stub__matrixmul_kernelPiS_S_iii: # @_Z31__device_stub__matrixmul_kernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16matrixmul_kernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixmul_kernelPiS_S_iii, .Lfunc_end0-_Z31__device_stub__matrixmul_kernelPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 80(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movl %ebx, %eax
imull %eax, %eax
movq %rax, 48(%rsp) # 8-byte Spill
leal (,%rax,4), %eax
movslq %eax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbx, (%rsp) # 8-byte Spill
testl %ebx, %ebx
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq 48(%rsp), %r13 # 8-byte Reload
cmpl $1, %r13d
# kill: def $r13d killed $r13d killed $r13 def $r13
adcl $0, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 216(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rbx # 8-byte Reload
movl %ebx, %eax
movq %rbx, %rdi
shlq $32, %rdi
orq %rax, %rdi
movq 64(%rsp), %r12 # 8-byte Reload
movl %r12d, %eax
movq %r12, %rdx
shlq $32, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq (%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
movl %ebx, 40(%rsp)
movl %r12d, 36(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z16matrixmul_kernelPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
subq 216(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 224(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 80(%rsp), %rax # 8-byte Reload
andl $-3, %eax
cmpl $1, %eax
jne .LBB1_15
# %bb.6:
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_13
# %bb.7: # %.preheader.lr.ph
movl (%rsp), %eax # 4-byte Reload
leaq (,%rax,4), %rcx
xorl %edx, %edx
xorl %esi, %esi
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
# Child Loop BB1_10 Depth 3
movl %edx, %edi
leaq (%r14,%rdi,4), %rdi
movq %rsi, %r8
imulq %rax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %r15, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph96
# Parent Loop BB1_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_10 Depth 3
xorl %r11d, %r11d
movq %r9, %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_8 Depth=1
# Parent Loop BB1_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %ebx
imull (%rdi,%r11,4), %ebx
addl %ebx, %r12d
incq %r11
addq %rcx, %r13
cmpq %r11, %rax
jne .LBB1_10
# %bb.11: # %._crit_edge97
# in Loop: Header=BB1_9 Depth=2
xorl %r11d, %r11d
cmpl (%r8,%r10,4), %r12d
sete %r11b
addl %r11d, %ebp
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB1_9
# %bb.12: # %._crit_edge101
# in Loop: Header=BB1_8 Depth=1
incq %rsi
addl (%rsp), %edx # 4-byte Folded Reload
cmpq %rax, %rsi
jne .LBB1_8
.LBB1_13: # %._crit_edge104
cmpl 48(%rsp), %ebp # 4-byte Folded Reload
jne .LBB1_15
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_15:
movq 8(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixmul_kernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixmul_kernelPiS_S_iii,@object # @_Z16matrixmul_kernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z16matrixmul_kernelPiS_S_iii
.p2align 3, 0x0
_Z16matrixmul_kernelPiS_S_iii:
.quad _Z31__device_stub__matrixmul_kernelPiS_S_iii
.size _Z16matrixmul_kernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running Time: %f\n\n"
.size .L.str, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrixmul_kernelPiS_S_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The answer is matched."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixmul_kernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixmul_kernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
cudaFree(key);
cudaFree(bucket);
} | code for sm_80
Function : _Z10bucketsortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
cudaFree(key);
cudaFree(bucket);
} | .file "tmpxft_0018e55c_00000000-6_12_bucket_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10bucketsortPiS_iPiS_i
.type _Z33__device_stub__Z10bucketsortPiS_iPiS_i, @function
_Z33__device_stub__Z10bucketsortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10bucketsortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z33__device_stub__Z10bucketsortPiS_iPiS_i, .-_Z33__device_stub__Z10bucketsortPiS_iPiS_i
.globl _Z10bucketsortPiS_i
.type _Z10bucketsortPiS_i, @function
_Z10bucketsortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10bucketsortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z10bucketsortPiS_i, .-_Z10bucketsortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $5, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10bucketsortPiS_iPiS_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bucketsortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bucketsortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
cudaFree(key);
cudaFree(bucket);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
hipFree(key);
hipFree(bucket);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
hipFree(key);
hipFree(bucket);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bucketsortPiS_i
.globl _Z10bucketsortPiS_i
.p2align 8
.type _Z10bucketsortPiS_i,@function
_Z10bucketsortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bucketsortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bucketsortPiS_i, .Lfunc_end0-_Z10bucketsortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bucketsortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10bucketsortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketsort(int *key, int *bucket, int n){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>=n) return;
int a = key[i];
atomicAdd(&bucket[a],1);
__syncthreads();
for(int j = 0, k = 0; j <= i; k++){
key[i] = k;
j += bucket[k];
}
}
int main() {
int n = 50;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
const int X = 32;
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
bucketsort<<<(n+X-1)/X,X,range>>>(key,bucket,n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ", key[i]);
}
printf("\n");
// for (int i=0; i<range; i++){
// printf("%d ", bucket[i]);
// }
// printf("\n");
hipFree(key);
hipFree(bucket);
} | .text
.file "12_bucket_sort.hip"
.globl _Z25__device_stub__bucketsortPiS_i # -- Begin function _Z25__device_stub__bucketsortPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__bucketsortPiS_i,@function
_Z25__device_stub__bucketsortPiS_i: # @_Z25__device_stub__bucketsortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bucketsortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__bucketsortPiS_i, .Lfunc_end0-_Z25__device_stub__bucketsortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $5, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bucketsortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bucketsortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bucketsortPiS_i,@object # @_Z10bucketsortPiS_i
.section .rodata,"a",@progbits
.globl _Z10bucketsortPiS_i
.p2align 3, 0x0
_Z10bucketsortPiS_i:
.quad _Z25__device_stub__bucketsortPiS_i
.size _Z10bucketsortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bucketsortPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bucketsortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bucketsortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10bucketsortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bucketsortPiS_i
.globl _Z10bucketsortPiS_i
.p2align 8
.type _Z10bucketsortPiS_i,@function
_Z10bucketsortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bucketsortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bucketsortPiS_i, .Lfunc_end0-_Z10bucketsortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bucketsortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10bucketsortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018e55c_00000000-6_12_bucket_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10bucketsortPiS_iPiS_i
.type _Z33__device_stub__Z10bucketsortPiS_iPiS_i, @function
_Z33__device_stub__Z10bucketsortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10bucketsortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z33__device_stub__Z10bucketsortPiS_iPiS_i, .-_Z33__device_stub__Z10bucketsortPiS_iPiS_i
.globl _Z10bucketsortPiS_i
.type _Z10bucketsortPiS_i, @function
_Z10bucketsortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10bucketsortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z10bucketsortPiS_i, .-_Z10bucketsortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $5, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10bucketsortPiS_iPiS_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bucketsortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bucketsortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "12_bucket_sort.hip"
.globl _Z25__device_stub__bucketsortPiS_i # -- Begin function _Z25__device_stub__bucketsortPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__bucketsortPiS_i,@function
_Z25__device_stub__bucketsortPiS_i: # @_Z25__device_stub__bucketsortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bucketsortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__bucketsortPiS_i, .Lfunc_end0-_Z25__device_stub__bucketsortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $5, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bucketsortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bucketsortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bucketsortPiS_i,@object # @_Z10bucketsortPiS_i
.section .rodata,"a",@progbits
.globl _Z10bucketsortPiS_i
.p2align 3, 0x0
_Z10bucketsortPiS_i:
.quad _Z25__device_stub__bucketsortPiS_i
.size _Z10bucketsortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bucketsortPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bucketsortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bucketsortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
cudaError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMemcpy(dev_data, data, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
cudaMemcpy(dev_data, dev_final, N*sizeof(int), cudaMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = cudaMemcpy(data, dev_data, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
Error:
cudaFree(dev_data);
cudaFree(dev_final);
return cudaStatus;
} | code for sm_80
Function : _Z5mergePjS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fda0003f05270 */
/*0020*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0030*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0040*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc8000f8e023f */
/*0070*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc8000800063f */
/*0080*/ UIADD3 UR6, UR4, UR5, URZ ; /* 0x0000000504067290 */
/* 0x000fe4000fffe03f */
/*0090*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fe4000f8e00ff */
/*00a0*/ UIADD3 UR5, UR6, UR5, URZ ; /* 0x0000000506057290 */
/* 0x000fe4000fffe03f */
/*00b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe4000f8e00ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0000 */
/*00d0*/ ISETP.GE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf06270 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*00f0*/ ISETP.EQ.AND P1, PT, R9, UR6, PT ; /* 0x0000000609007c0c */
/* 0x000fc6000bf22270 */
/*0100*/ IMAD.WIDE R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0207 */
/*0110*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0207 */
/*0120*/ @!P0 BRA P1, 0x240 ; /* 0x0000011000008947 */
/* 0x000fea0000800000 */
/*0130*/ ISETP.NE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf05270 */
/*0140*/ IMAD.WIDE R6, R9.reuse, R7, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x040fe200078e0207 */
/*0150*/ ISETP.LT.AND P1, PT, R9, UR6, PT ; /* 0x0000000609007c0c */
/* 0x000fda000bf21270 */
/*0160*/ @!P0 BRA P1, 0x1f0 ; /* 0x0000008000008947 */
/* 0x000fea0000800000 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea4000c1e1900 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f06070 */
/*01a0*/ @P0 STG.E [R4.64], R2 ; /* 0x0000000204000986 */
/* 0x0001e2000c101908 */
/*01b0*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109098810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ @!P0 STG.E [R4.64], R7 ; /* 0x0000000704008986 */
/* 0x0001e2000c101908 */
/*01e0*/ BRA 0x280 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */
/* 0x000fe4000f8e00ff */
/*0220*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e2000c101908 */
/*0230*/ BRA 0x280 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.U32 R9, RZ, RZ, UR6 ; /* 0x00000006ff097e24 */
/* 0x000fc4000f8e00ff */
/*0270*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e8000c101908 */
/*0280*/ ISETP.NE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe4000bf05270 */
/*0290*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.OR P0, PT, R9, UR6, P0 ; /* 0x0000000609007c0c */
/* 0x000fda0008705670 */
/*02b0*/ @P0 BRA 0xd0 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4sortPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x330 ; /* 0x000002f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x001fc800078ec0ff */
/*0060*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05070 */
/*0070*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fd800078e0200 */
/*0080*/ @!P0 BRA 0x320 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R12, R2.reuse, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*00b0*/ IADD3 R14, R2, 0x2, RZ ; /* 0x00000002020e7810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0002 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000c */
/*00e0*/ ISETP.GE.AND P0, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fe20003f06270 */
/*00f0*/ BSSY B1, 0x2c0 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0100*/ ISETP.EQ.AND P1, PT, R9, R12, PT ; /* 0x0000000c0900720c */
/* 0x000fda0003f22270 */
/*0110*/ @!P0 BRA P1, 0x260 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0120*/ ISETP.NE.AND P0, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fe40003f05270 */
/*0130*/ ISETP.LE.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f23270 */
/*0140*/ @!P0 BRA P1, 0x200 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R6, R9, R4, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fc800078e0204 */
/*0170*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*0180*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x004fda0003f06070 */
/*01b0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0006 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0007 */
/*01e0*/ @!P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109098810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ BRA 0x2b0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R6, R9.reuse, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x040fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000e */
/*0230*/ IMAD.WIDE R4, R9, R4, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fc800078e0204 */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0250*/ BRA 0x2b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R6, R3.reuse, 0x1, RZ ; /* 0x0000000103067810 */
/* 0x040fe20007ffe0ff */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000c */
/*0290*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*02a0*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fc60000000f00 */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ ISETP.NE.AND P0, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fc80003f05270 */
/*02e0*/ ISETP.NE.OR P0, PT, R9, R12, P0 ; /* 0x0000000c0900720c */
/* 0x000fe20000705670 */
/*02f0*/ STS [R8.X4], R5 ; /* 0x0000000508007388 */
/* 0x0041e40000004800 */
/*0300*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x001fd40007ffe0ff */
/*0310*/ @P0 BRA 0xe0 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0340*/ IMAD.SHL.U32 R3, R0.reuse, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x040fe200078e00ff */
/*0350*/ LOP3.LUT P0, RZ, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300ff7812 */
/* 0x000fe2000780c0ff */
/*0360*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0370*/ BSSY B0, 0x670 ; /* 0x000002f000007945 */
/* 0x000fe20003800000 */
/*0380*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fe200078e0005 */
/*0390*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x000e280000000800 */
/*03a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101904 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ @P0 BRA 0x660 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R17, R2.reuse, 0x2, RZ ; /* 0x0000000202117810 */
/* 0x040fe20007ffe0ff */
/*03e0*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*03f0*/ IADD3 R15, R2, 0x4, RZ ; /* 0x00000004020f7810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0002 */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0011 */
/*0420*/ ISETP.GE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe20003f06270 */
/*0430*/ BSSY B1, 0x600 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0440*/ ISETP.EQ.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f22270 */
/*0450*/ @!P0 BRA P1, 0x5a0 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0460*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe40003f05270 */
/*0470*/ ISETP.LT.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f21270 */
/*0480*/ @!P0 BRA P1, 0x540 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fc800078e00ff */
/*04a0*/ IMAD.WIDE R8, R12, R7, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e0207 */
/*04b0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fe200078e0207 */
/*04c0*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fda0003f06070 */
/*04f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*0500*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe20007ffe0ff */
/*0510*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff078224 */
/* 0x000fe200078e0009 */
/*0520*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fe20007ffe0ff */
/*0530*/ BRA 0x5f0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0550*/ IADD3 R8, R12.reuse, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x040fe40007ffe0ff */
/*0560*/ MOV R10, R15 ; /* 0x0000000f000a7202 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.WIDE R6, R12, R7, c[0x0][0x160] ; /* 0x000058000c067625 */
/* 0x000fc800078e0207 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0590*/ BRA 0x5f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*05b0*/ IADD3 R8, R10.reuse, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x040fe20007ffe0ff */
/*05c0*/ IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0011 */
/*05d0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0207 */
/*05e0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0610*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fc80003f05270 */
/*0620*/ ISETP.NE.OR P0, PT, R12, R17, P0 ; /* 0x000000110c00720c */
/* 0x000fe20000705670 */
/*0630*/ STS [R11.X4], R6 ; /* 0x000000060b007388 */
/* 0x0041e40000004800 */
/*0640*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x001fd40007ffe0ff */
/*0650*/ @P0 BRA 0x420 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0680*/ LOP3.LUT P0, RZ, R0, 0x7, RZ, 0xc0, !PT ; /* 0x0000000700ff7812 */
/* 0x000fca000780c0ff */
/*0690*/ BSSY B0, 0x980 ; /* 0x000002e000007945 */
/* 0x000fe20003800000 */
/*06a0*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x001e280000000800 */
/*06b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101904 */
/*06c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06d0*/ @P0 BRA 0x970 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R17, R2.reuse, 0x4, RZ ; /* 0x0000000402117810 */
/* 0x040fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*0700*/ IADD3 R15, R2, 0x8, RZ ; /* 0x00000008020f7810 */
/* 0x000fe20007ffe0ff */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0002 */
/*0720*/ IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0011 */
/*0730*/ ISETP.GE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe20003f06270 */
/*0740*/ BSSY B1, 0x910 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0750*/ ISETP.EQ.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f22270 */
/*0760*/ @!P0 BRA P1, 0x8b0 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0770*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe40003f05270 */
/*0780*/ ISETP.LT.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f21270 */
/*0790*/ @!P0 BRA P1, 0x850 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*07a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fc800078e00ff */
/*07b0*/ IMAD.WIDE R8, R12, R7, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e0207 */
/*07c0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fe200078e0207 */
/*07d0*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea4000c1e1900 */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fda0003f06070 */
/*0800*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*0810*/ @!P0 MOV R7, R9 ; /* 0x0000000900078202 */
/* 0x000fe40000000f00 */
/*0820*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe40007ffe0ff */
/*0830*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fe20007ffe0ff */
/*0840*/ BRA 0x900 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0860*/ IADD3 R8, R12.reuse, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x040fe20007ffe0ff */
/*0870*/ IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000f */
/*0880*/ IMAD.WIDE R6, R12, R7, c[0x0][0x160] ; /* 0x000058000c067625 */
/* 0x000fc800078e0207 */
/*0890*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*08a0*/ BRA 0x900 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*08c0*/ IADD3 R8, R10.reuse, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x040fe20007ffe0ff */
/*08d0*/ IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0011 */
/*08e0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0900*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0920*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fc80003f05270 */
/*0930*/ ISETP.NE.OR P0, PT, R12, R17, P0 ; /* 0x000000110c00720c */
/* 0x000fe20000705670 */
/*0940*/ STS [R11.X4], R6 ; /* 0x000000060b007388 */
/* 0x0041e40000004800 */
/*0950*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x001fd40007ffe0ff */
/*0960*/ @P0 BRA 0x730 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0990*/ LOP3.LUT P0, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fca000780c0ff */
/*09a0*/ BSSY B0, 0xc90 ; /* 0x000002e000007945 */
/* 0x000fe20003800000 */
/*09b0*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x001e280000000800 */
/*09c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101904 */
/*09d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09e0*/ @P0 BRA 0xc80 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R17, R2.reuse, 0x8, RZ ; /* 0x0000000802117810 */
/* 0x040fe20007ffe0ff */
/*0a00*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*0a10*/ IADD3 R15, R2, 0x10, RZ ; /* 0x00000010020f7810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0002 */
/*0a30*/ IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0011 */
/*0a40*/ ISETP.GE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe20003f06270 */
/*0a50*/ BSSY B1, 0xc20 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0a60*/ ISETP.EQ.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f22270 */
/*0a70*/ @!P0 BRA P1, 0xbc0 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0a80*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fe40003f05270 */
/*0a90*/ ISETP.LT.AND P1, PT, R12, R17, PT ; /* 0x000000110c00720c */
/* 0x000fda0003f21270 */
/*0aa0*/ @!P0 BRA P1, 0xb60 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*0ab0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0ac0*/ IMAD.WIDE R8, R12, R7, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e0207 */
/*0ad0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fe200078e0207 */
/*0ae0*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fda0003f06070 */
/*0b10*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*0b20*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe20007ffe0ff */
/*0b30*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff078224 */
/* 0x000fe200078e0009 */
/*0b40*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ BRA 0xc10 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0b70*/ IADD3 R8, R12.reuse, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x040fe20007ffe0ff */
/*0b80*/ IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000f */
/*0b90*/ IMAD.WIDE R6, R12, R7, c[0x0][0x160] ; /* 0x000058000c067625 */
/* 0x000fc800078e0207 */
/*0ba0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0bb0*/ BRA 0xc10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0bc0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0bd0*/ IADD3 R8, R10.reuse, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x040fe20007ffe0ff */
/*0be0*/ IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0011 */
/*0bf0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0207 */
/*0c00*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0c10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fc80003f05270 */
/*0c40*/ ISETP.NE.OR P0, PT, R12, R17, P0 ; /* 0x000000110c00720c */
/* 0x000fe20000705670 */
/*0c50*/ STS [R11.X4], R6 ; /* 0x000000060b007388 */
/* 0x0041e40000004800 */
/*0c60*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x001fd40007ffe0ff */
/*0c70*/ @P0 BRA 0xa40 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0c80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ca0*/ LOP3.LUT P0, RZ, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00ff7812 */
/* 0x000fca000780c0ff */
/*0cb0*/ BSSY B0, 0xf80 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0cc0*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x001e280000000800 */
/*0cd0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101904 */
/*0ce0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0cf0*/ @P0 BRA 0xf70 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0d00*/ IADD3 R15, R2.reuse, 0x10, RZ ; /* 0x00000010020f7810 */
/* 0x040fe40007ffe0ff */
/*0d10*/ IADD3 R13, R2, 0x20, RZ ; /* 0x00000020020d7810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e000f */
/*0d30*/ ISETP.GE.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe20003f06270 */
/*0d40*/ BSSY B1, 0xf10 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0d50*/ ISETP.EQ.AND P1, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fda0003f22270 */
/*0d60*/ @!P0 BRA P1, 0xeb0 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0d70*/ ISETP.NE.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe40003f05270 */
/*0d80*/ ISETP.LT.AND P1, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fda0003f21270 */
/*0d90*/ @!P0 BRA P1, 0xe50 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*0da0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x001fca0000000f00 */
/*0db0*/ IMAD.WIDE R8, R2, R7, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fc800078e0207 */
/*0dc0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fe200078e0207 */
/*0dd0*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1900 */
/*0de0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ ISETP.GE.U32.AND P0, PT, R12, R11, PT ; /* 0x0000000b0c00720c */
/* 0x004fda0003f06070 */
/*0e00*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*0e10*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe20007ffe0ff */
/*0e20*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff078224 */
/* 0x000fe200078e0009 */
/*0e30*/ @!P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102028810 */
/* 0x000fe20007ffe0ff */
/*0e40*/ BRA 0xf00 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0e50*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0e60*/ IADD3 R8, R2.reuse, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x040fe20007ffe0ff */
/*0e70*/ IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000d */
/*0e80*/ IMAD.WIDE R6, R2, R7, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fc800078e0207 */
/*0e90*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0ea0*/ BRA 0xf00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0eb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0ec0*/ IADD3 R8, R10.reuse, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x040fe20007ffe0ff */
/*0ed0*/ IMAD.MOV.U32 R2, RZ, RZ, R15 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000f */
/*0ee0*/ IMAD.WIDE R6, R10, R7, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0207 */
/*0ef0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0f00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f10*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0f20*/ ISETP.NE.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fc80003f05270 */
/*0f30*/ ISETP.NE.OR P0, PT, R2, R15, P0 ; /* 0x0000000f0200720c */
/* 0x000fe20000705670 */
/*0f40*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e40000004800 */
/*0f50*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fd40007ffe0ff */
/*0f60*/ @P0 BRA 0xd30 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0f70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0f90*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e680000000800 */
/*0fa0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x002fe8000c101904 */
/*0fb0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0fc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fd0*/ BRA 0xfd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
cudaError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMemcpy(dev_data, data, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
cudaMemcpy(dev_data, dev_final, N*sizeof(int), cudaMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = cudaMemcpy(data, dev_data, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
Error:
cudaFree(dev_data);
cudaFree(dev_final);
return cudaStatus;
} | .file "tmpxft_001b0a72_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9init_dataPjj
.type _Z9init_dataPjj, @function
_Z9init_dataPjj:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movl %esi, %eax
leaq (%rdi,%rax,4), %r12
.L5:
call rand@PLT
movl $0, %edx
divl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3669:
.size _Z9init_dataPjj, .-_Z9init_dataPjj
.globl _Z23__device_stub__Z4sortPjPj
.type _Z23__device_stub__Z4sortPjPj, @function
_Z23__device_stub__Z4sortPjPj:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z23__device_stub__Z4sortPjPj, .-_Z23__device_stub__Z4sortPjPj
.globl _Z4sortPj
.type _Z4sortPj, @function
_Z4sortPj:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4sortPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z4sortPj, .-_Z4sortPj
.globl _Z27__device_stub__Z5mergePjS_iPjS_i
.type _Z27__device_stub__Z5mergePjS_iPjS_i, @function
_Z27__device_stub__Z5mergePjS_iPjS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mergePjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z27__device_stub__Z5mergePjS_iPjS_i, .-_Z27__device_stub__Z5mergePjS_iPjS_i
.globl _Z5mergePjS_i
.type _Z5mergePjS_i, @function
_Z5mergePjS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5mergePjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z5mergePjS_i, .-_Z5mergePjS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "Launching kernel on the GPU"
.LC4:
.string "sortKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaDeviceSynchronize returned error code %d after launching sortKernel!\n"
.text
.globl _Z8sortCudaPji
.type _Z8sortCudaPji, @function
_Z8sortCudaPji:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L45
.L28:
movslq %r13d, %r13
salq $2, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
.L29:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
.L30:
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
.L31:
movl $27, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L49
cmpb $0, 56(%rbx)
je .L34
movzbl 67(%rbx), %esi
.L35:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L36:
movl $5, %ebp
movl $32, %r12d
movl $16, %ebx
jmp .L38
.L45:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L28
.L46:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L29
.L47:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L48:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L31
.L49:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L34:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L50:
movq (%rsp), %rdi
call _Z23__device_stub__Z4sortPjPj
jmp .L36
.L37:
movl $3, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
addl %r12d, %r12d
subl $1, %ebp
je .L52
.L38:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z5mergePjS_iPjS_i
jmp .L37
.L52:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
.L39:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L54
.L40:
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
.L41:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L39
.L54:
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L40
.L55:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L41
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z8sortCudaPji, .-_Z8sortCudaPji
.section .rodata.str1.1
.LC6:
.string "Initializing data:"
.LC7:
.string "sortCuda failed!"
.LC8:
.string "Results after sorting:"
.LC9:
.string "Data ["
.LC10:
.string "]: "
.LC11:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %esi
movq %rax, %rdi
call _Z9init_dataPjj
movl $1024, %esi
movq %r14, %rdi
call _Z8sortCudaPji
testl %eax, %eax
jne .L67
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC9(%rip), %r15
leaq _ZSt4cout(%rip), %r13
jmp .L63
.L67:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L57
.L69:
call _ZSt16__throw_bad_castv@PLT
.L61:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L62:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $1024, %rbp
je .L68
.L63:
movl $6, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC10(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L69
cmpb $0, 56(%r12)
je .L61
movzbl 67(%r12), %esi
jmp .L62
.L68:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L70
.L57:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L57
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5mergePjS_i"
.LC13:
.string "_Z4sortPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mergePjS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
cudaError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
// goto Error;
}
cudaStatus = cudaMemcpy(dev_data, data, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
cudaMemcpy(dev_data, dev_final, N*sizeof(int), cudaMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = cudaMemcpy(data, dev_data, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
}
Error:
cudaFree(dev_data);
cudaFree(dev_final);
return cudaStatus;
} | #ifndef __HIPCC__
#define __HIPCC__
#endif
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
hipError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
hipError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMemcpy(dev_data, data, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
hipMemcpy(dev_data, dev_final, N*sizeof(int), hipMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = hipMemcpy(data, dev_data, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
Error:
hipFree(dev_data);
hipFree(dev_final);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __HIPCC__
#define __HIPCC__
#endif
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
hipError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
hipError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMemcpy(dev_data, data, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
hipMemcpy(dev_data, dev_final, N*sizeof(int), hipMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = hipMemcpy(data, dev_data, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
Error:
hipFree(dev_data);
hipFree(dev_final);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPj
.globl _Z4sortPj
.p2align 8
.type _Z4sortPj,@function
_Z4sortPj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
v_lshlrev_b32_e32 v7, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v7
s_lshl_b32 s5, s4, 1
s_cmp_lt_u32 s4, 17
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v3, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_17
.LBB0_2:
s_add_i32 s5, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, s5, v0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_1
s_load_b32 s6, s[0:1], 0xc
s_mov_b32 s7, -1
s_mov_b32 s8, -1
v_mov_b32_e32 v9, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_lshr_b32 s6, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v8 :: v_dual_add_nc_u32 v10, s6, v8
s_mov_b32 s6, 0
s_branch .LBB0_7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s7
v_cmp_ne_u32_e64 s7, v3, v8
v_cmp_ne_u32_e64 s8, v5, v10
v_add_nc_u32_e32 v9, 4, v9
s_or_b32 s9, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s9, s9, -1
s_and_b32 s9, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s9, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_1
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, v5, v10
s_xor_b32 s7, s7, -1
s_and_b32 s7, s7, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s7
s_xor_b32 s7, exec_lo, s9
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[5:6]
v_add_nc_u32_e32 v5, 1, v5
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v4
.LBB0_9:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_6
v_cmp_lt_i32_e32 vcc_lo, v3, v8
v_ashrrev_i32_e32 v4, 31, v3
s_xor_b32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s8
s_and_saveexec_b32 s9, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s9
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v4
.LBB0_12:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v4, v[11:12], off
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_ge_u32_e64 v4, v6
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v5, 1, v5
ds_store_b32 v9, v6
.LBB0_15:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v3, 1, v3
ds_store_b32 v9, v4
s_branch .LBB0_4
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPj
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPj, .Lfunc_end0-_Z4sortPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5mergePjS_i
.globl _Z5mergePjS_i
.p2align 8
.type _Z5mergePjS_i,@function
_Z5mergePjS_i:
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 0
s_cselect_b32 s7, -1, 0
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_15
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s15, s15, s6
v_mov_b32_e32 v0, 0
s_lshl_b32 s4, s15, 1
s_mov_b32 s10, -1
s_ashr_i32 s5, s4, 31
s_add_i32 s8, s4, s6
s_lshl_b64 s[12:13], s[4:5], 2
s_add_i32 s9, s8, s6
s_mov_b32 s6, s8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s12
s_addc_u32 s3, s3, s13
s_branch .LBB1_5
.LBB1_2:
s_mov_b32 s7, s4
s_mov_b32 s6, s5
.LBB1_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, s6
s_mov_b32 s4, s7
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s4, s8
s_cselect_b32 s7, -1, 0
s_cmp_lg_u32 s5, s9
s_cselect_b32 s10, -1, 0
s_or_b32 s6, s7, s10
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_and_b32 vcc_lo, exec_lo, s6
s_mov_b32 s6, s5
s_cbranch_vccz .LBB1_15
.LBB1_5:
s_cmp_ge_i32 s6, s9
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s7, s5
s_mov_b32 s7, -1
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB1_7
s_ashr_i32 s7, s6, 31
s_add_i32 s5, s6, 1
s_lshl_b64 s[12:13], s[6:7], 2
s_mov_b32 s7, 0
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
global_load_b32 v1, v0, s[12:13]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB1_7:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_4
s_cmp_ge_i32 s4, s8
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s10, s5
s_and_b32 vcc_lo, exec_lo, s5
s_mov_b32 s5, -1
s_cbranch_vccnz .LBB1_10
s_ashr_i32 s5, s4, 31
s_add_i32 s7, s4, 1
s_lshl_b64 s[10:11], s[4:5], 2
s_mov_b32 s5, 0
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
global_load_b32 v1, v0, s[10:11]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB1_10:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB1_3
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[6:7], 2
s_mov_b32 s7, -1
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_clause 0x1
global_load_b32 v1, v0, s[10:11]
global_load_b32 v2, v0, s[12:13]
s_waitcnt vmcnt(0)
v_cmp_ge_u32_e32 vcc_lo, v1, v2
s_cbranch_vccz .LBB1_13
s_add_i32 s5, s6, 1
s_mov_b32 s7, 0
global_store_b32 v0, v2, s[2:3]
.LBB1_13:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_2
s_add_i32 s4, s4, 1
s_mov_b32 s5, s6
global_store_b32 v0, v1, s[2:3]
s_branch .LBB1_2
.LBB1_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5mergePjS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5mergePjS_i, .Lfunc_end1-_Z5mergePjS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5mergePjS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5mergePjS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __HIPCC__
#define __HIPCC__
#endif
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <iostream>
#include <cstdio>
#define N 1024
#define THREADS 32
#define BLOCKS 32
hipError_t sortCuda(unsigned int *data, const int size);
__global__ void sort(unsigned int *data) {
int i = 2;
__shared__ int temp[THREADS];
while (i <= THREADS) {
if ((threadIdx.x % i) == 0) {
int index1 = threadIdx.x + (blockIdx.x * blockDim.x);
int targetIndex = threadIdx.x;
int endIndex1 = index1 + i/2;
int index2 = endIndex1;
int endIndex2 = index2 + i/2;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
temp[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
temp[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
temp[targetIndex++] = data[index1++];
else
temp[targetIndex++] = data[index2++];
}
}
__syncthreads();
data[threadIdx.x + (blockIdx.x*blockDim.x)] = temp[threadIdx.x];
__syncthreads();
i *= 2;
}
}
__global__ void merge(unsigned int *data, unsigned int *final, int sortedsize) {
int index1 = blockIdx.x * 2 * sortedsize;
int targetIndex = blockIdx.x * 2 * sortedsize;
int endIndex1 = index1 + sortedsize;
int index2 = endIndex1;
int endIndex2 = index2 + sortedsize;
while (!((index1==endIndex1) && (index2==endIndex2))) {
if ((index1 == endIndex1) && (index2 < endIndex2))
final[targetIndex++] = data[index2++];
else if ((index2 == endIndex2) && (index1 < endIndex1))
final[targetIndex++] = data[index1++];
else if (data[index1] < data[index2])
final[targetIndex++] = data[index1++];
else
final[targetIndex++] = data[index2++];
}
}
void init_data(unsigned int *data, unsigned int nitems) {
for (unsigned i = 0 ; i < nitems ; i++)
data[i] = rand() % nitems ;
}
int main() {
unsigned int *h_data = 0;
std::cout << "Initializing data:" << std::endl;
h_data =(unsigned int *)malloc( N*sizeof(unsigned int));
init_data(h_data, N);
//for(int i=0 ; i<N ; i++)
// std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
hipError_t cudaStatus = sortCuda(h_data, N);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortCuda failed!");
return 1;
}
std::cout << "Results after sorting:" << std::endl;
for(int i=0 ; i<N ; i++)
std::cout << "Data [" << i << "]: " << h_data[i] << std::endl;
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t sortCuda(unsigned int *data, const int size) {
unsigned int *dev_data = 0;
unsigned int *dev_final = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_data, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMalloc((void**)&dev_final, size * sizeof(unsigned int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
// goto Error;
}
cudaStatus = hipMemcpy(dev_data, data, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
std::cout << "Launching kernel on the GPU" << std::endl;
//quicksort<<< 1, size >>>(dev_data);
sort<<<BLOCKS,THREADS>>>(dev_data);
int blocks = BLOCKS/2;
int sortedsize = THREADS;
while (blocks > 0) {
merge<<<blocks,1>>>(dev_data, dev_final, sortedsize);
hipMemcpy(dev_data, dev_final, N*sizeof(int), hipMemcpyDeviceToDevice);
blocks /= 2;
sortedsize *= 2;
}
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "sortKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching sortKernel!\n", cudaStatus);
// goto Error;
}
cudaStatus = hipMemcpy(data, dev_data, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
// goto Error;
}
Error:
hipFree(dev_data);
hipFree(dev_final);
return cudaStatus;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__sortPj # -- Begin function _Z19__device_stub__sortPj
.p2align 4, 0x90
.type _Z19__device_stub__sortPj,@function
_Z19__device_stub__sortPj: # @_Z19__device_stub__sortPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4sortPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__sortPj, .Lfunc_end0-_Z19__device_stub__sortPj
.cfi_endproc
# -- End function
.globl _Z20__device_stub__mergePjS_i # -- Begin function _Z20__device_stub__mergePjS_i
.p2align 4, 0x90
.type _Z20__device_stub__mergePjS_i,@function
_Z20__device_stub__mergePjS_i: # @_Z20__device_stub__mergePjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mergePjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__mergePjS_i, .Lfunc_end1-_Z20__device_stub__mergePjS_i
.cfi_endproc
# -- End function
.globl _Z9init_dataPjj # -- Begin function _Z9init_dataPjj
.p2align 4, 0x90
.type _Z9init_dataPjj,@function
_Z9init_dataPjj: # @_Z9init_dataPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9init_dataPjj, .Lfunc_end2-_Z9init_dataPjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_22
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
andl $1023, %eax # imm = 0x3FF
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB3_5
# %bb.6: # %_Z9init_dataPjj.exit
movq %rbx, %rdi
movl $1024, %esi # imm = 0x400
callq _Z8sortCudaPji
testl %eax, %eax
jne .LBB3_7
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_22
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%r14)
je .LBB3_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB3_12
.LBB3_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
movzbl 67(%r15), %ecx
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
# in Loop: Header=BB3_13 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $1024, %r14 # imm = 0x400
je .LBB3_18
.LBB3_13: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_22
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
# in Loop: Header=BB3_13 Depth=1
cmpb $0, 56(%r15)
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_13 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
jmp .LBB3_17
.LBB3_18:
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB3_19
.LBB3_21:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $16, %esi
jmp .LBB3_20
.LBB3_19:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
.LBB3_20:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB3_21
.LBB3_22:
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z8sortCudaPji # -- Begin function _Z8sortCudaPji
.p2align 4, 0x90
.type _Z8sortCudaPji,@function
_Z8sortCudaPji: # @_Z8sortCudaPji
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movq $0, (%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_1
.LBB4_2:
movslq %ebx, %r15
shlq $2, %r15
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_3
.LBB4_4:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_5
.LBB4_6:
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_7
.LBB4_8:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_25
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
movq %r15, 112(%rsp) # 8-byte Spill
je .LBB4_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB4_12
.LBB4_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movq %r14, 120(%rsp) # 8-byte Spill
movabsq $4294967328, %r15 # imm = 0x100000020
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
leaq 64(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4sortPj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movl $32, %ebp
movl $16, %ebx
leaq -31(%r15), %r12
leaq 128(%rsp), %r14
leaq 80(%rsp), %r13
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_15 Depth=1
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $3, %ecx
callq hipMemcpy
movl %ebx, %eax
shrl %eax
addl %ebp, %ebp
cmpl $1, %ebx
movl %eax, %ebx
jbe .LBB4_18
.LBB4_15: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
leaq (%r15,%rax), %rdi
addq $-32, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_15 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movl %ebp, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5mergePjS_i, %edi
movq %r13, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_19
.LBB4_20:
callq hipDeviceSynchronize
testl %eax, %eax
movq 120(%rsp), %rdi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
jne .LBB4_21
.LBB4_22:
movq (%rsp), %rsi
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebx
testl %eax, %eax
jne .LBB4_23
.LBB4_24:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $63, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_2
.LBB4_3:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_4
.LBB4_5:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_6
.LBB4_7:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_8
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_20
.LBB4_21:
movq %rdi, %rbx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movq %rdx, %r14
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdx
movq %rbx, %rdi
jmp .LBB4_22
.LBB4_23:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_24
.LBB4_25:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z8sortCudaPji, .Lfunc_end4-_Z8sortCudaPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mergePjS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sortPj,@object # @_Z4sortPj
.section .rodata,"a",@progbits
.globl _Z4sortPj
.p2align 3, 0x0
_Z4sortPj:
.quad _Z19__device_stub__sortPj
.size _Z4sortPj, 8
.type _Z5mergePjS_i,@object # @_Z5mergePjS_i
.globl _Z5mergePjS_i
.p2align 3, 0x0
_Z5mergePjS_i:
.quad _Z20__device_stub__mergePjS_i
.size _Z5mergePjS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Initializing data:"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sortCuda failed!"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results after sorting:"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Data ["
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "]: "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipDeviceReset failed!"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.6, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy failed!"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Launching kernel on the GPU"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "sortKernel launch failed: %s\n"
.size .L.str.10, 30
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching sortKernel!\n"
.size .L.str.11, 73
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPj"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5mergePjS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPj
.addrsig_sym _Z20__device_stub__mergePjS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPj
.addrsig_sym _Z5mergePjS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0a72_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9init_dataPjj
.type _Z9init_dataPjj, @function
_Z9init_dataPjj:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movl %esi, %eax
leaq (%rdi,%rax,4), %r12
.L5:
call rand@PLT
movl $0, %edx
divl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3669:
.size _Z9init_dataPjj, .-_Z9init_dataPjj
.globl _Z23__device_stub__Z4sortPjPj
.type _Z23__device_stub__Z4sortPjPj, @function
_Z23__device_stub__Z4sortPjPj:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z23__device_stub__Z4sortPjPj, .-_Z23__device_stub__Z4sortPjPj
.globl _Z4sortPj
.type _Z4sortPj, @function
_Z4sortPj:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4sortPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z4sortPj, .-_Z4sortPj
.globl _Z27__device_stub__Z5mergePjS_iPjS_i
.type _Z27__device_stub__Z5mergePjS_iPjS_i, @function
_Z27__device_stub__Z5mergePjS_iPjS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mergePjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z27__device_stub__Z5mergePjS_iPjS_i, .-_Z27__device_stub__Z5mergePjS_iPjS_i
.globl _Z5mergePjS_i
.type _Z5mergePjS_i, @function
_Z5mergePjS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5mergePjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z5mergePjS_i, .-_Z5mergePjS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "Launching kernel on the GPU"
.LC4:
.string "sortKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaDeviceSynchronize returned error code %d after launching sortKernel!\n"
.text
.globl _Z8sortCudaPji
.type _Z8sortCudaPji, @function
_Z8sortCudaPji:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L45
.L28:
movslq %r13d, %r13
salq $2, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
.L29:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
.L30:
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
.L31:
movl $27, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L49
cmpb $0, 56(%rbx)
je .L34
movzbl 67(%rbx), %esi
.L35:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L36:
movl $5, %ebp
movl $32, %r12d
movl $16, %ebx
jmp .L38
.L45:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L28
.L46:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L29
.L47:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L48:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L31
.L49:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L34:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L50:
movq (%rsp), %rdi
call _Z23__device_stub__Z4sortPjPj
jmp .L36
.L37:
movl $3, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
addl %r12d, %r12d
subl $1, %ebp
je .L52
.L38:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z5mergePjS_iPjS_i
jmp .L37
.L52:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
.L39:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L54
.L40:
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
.L41:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L39
.L54:
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L40
.L55:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L41
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z8sortCudaPji, .-_Z8sortCudaPji
.section .rodata.str1.1
.LC6:
.string "Initializing data:"
.LC7:
.string "sortCuda failed!"
.LC8:
.string "Results after sorting:"
.LC9:
.string "Data ["
.LC10:
.string "]: "
.LC11:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %esi
movq %rax, %rdi
call _Z9init_dataPjj
movl $1024, %esi
movq %r14, %rdi
call _Z8sortCudaPji
testl %eax, %eax
jne .L67
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC9(%rip), %r15
leaq _ZSt4cout(%rip), %r13
jmp .L63
.L67:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L57
.L69:
call _ZSt16__throw_bad_castv@PLT
.L61:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L62:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $1024, %rbp
je .L68
.L63:
movl $6, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC10(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L69
cmpb $0, 56(%r12)
je .L61
movzbl 67(%r12), %esi
jmp .L62
.L68:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L70
.L57:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L57
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5mergePjS_i"
.LC13:
.string "_Z4sortPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mergePjS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__sortPj # -- Begin function _Z19__device_stub__sortPj
.p2align 4, 0x90
.type _Z19__device_stub__sortPj,@function
_Z19__device_stub__sortPj: # @_Z19__device_stub__sortPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4sortPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__sortPj, .Lfunc_end0-_Z19__device_stub__sortPj
.cfi_endproc
# -- End function
.globl _Z20__device_stub__mergePjS_i # -- Begin function _Z20__device_stub__mergePjS_i
.p2align 4, 0x90
.type _Z20__device_stub__mergePjS_i,@function
_Z20__device_stub__mergePjS_i: # @_Z20__device_stub__mergePjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mergePjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__mergePjS_i, .Lfunc_end1-_Z20__device_stub__mergePjS_i
.cfi_endproc
# -- End function
.globl _Z9init_dataPjj # -- Begin function _Z9init_dataPjj
.p2align 4, 0x90
.type _Z9init_dataPjj,@function
_Z9init_dataPjj: # @_Z9init_dataPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9init_dataPjj, .Lfunc_end2-_Z9init_dataPjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_22
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
andl $1023, %eax # imm = 0x3FF
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB3_5
# %bb.6: # %_Z9init_dataPjj.exit
movq %rbx, %rdi
movl $1024, %esi # imm = 0x400
callq _Z8sortCudaPji
testl %eax, %eax
jne .LBB3_7
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_22
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%r14)
je .LBB3_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB3_12
.LBB3_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
movzbl 67(%r15), %ecx
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
# in Loop: Header=BB3_13 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $1024, %r14 # imm = 0x400
je .LBB3_18
.LBB3_13: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_22
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
# in Loop: Header=BB3_13 Depth=1
cmpb $0, 56(%r15)
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_13 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
jmp .LBB3_17
.LBB3_18:
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB3_19
.LBB3_21:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $16, %esi
jmp .LBB3_20
.LBB3_19:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
.LBB3_20:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB3_21
.LBB3_22:
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z8sortCudaPji # -- Begin function _Z8sortCudaPji
.p2align 4, 0x90
.type _Z8sortCudaPji,@function
_Z8sortCudaPji: # @_Z8sortCudaPji
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movq $0, (%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_1
.LBB4_2:
movslq %ebx, %r15
shlq $2, %r15
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_3
.LBB4_4:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_5
.LBB4_6:
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_7
.LBB4_8:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_25
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
movq %r15, 112(%rsp) # 8-byte Spill
je .LBB4_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB4_12
.LBB4_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movq %r14, 120(%rsp) # 8-byte Spill
movabsq $4294967328, %r15 # imm = 0x100000020
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
leaq 64(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4sortPj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movl $32, %ebp
movl $16, %ebx
leaq -31(%r15), %r12
leaq 128(%rsp), %r14
leaq 80(%rsp), %r13
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_15 Depth=1
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $3, %ecx
callq hipMemcpy
movl %ebx, %eax
shrl %eax
addl %ebp, %ebp
cmpl $1, %ebx
movl %eax, %ebx
jbe .LBB4_18
.LBB4_15: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
leaq (%r15,%rax), %rdi
addq $-32, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_15 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movl %ebp, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5mergePjS_i, %edi
movq %r13, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_19
.LBB4_20:
callq hipDeviceSynchronize
testl %eax, %eax
movq 120(%rsp), %rdi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
jne .LBB4_21
.LBB4_22:
movq (%rsp), %rsi
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebx
testl %eax, %eax
jne .LBB4_23
.LBB4_24:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $63, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_2
.LBB4_3:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_4
.LBB4_5:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_6
.LBB4_7:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_8
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_20
.LBB4_21:
movq %rdi, %rbx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movq %rdx, %r14
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdx
movq %rbx, %rdi
jmp .LBB4_22
.LBB4_23:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_24
.LBB4_25:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z8sortCudaPji, .Lfunc_end4-_Z8sortCudaPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mergePjS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sortPj,@object # @_Z4sortPj
.section .rodata,"a",@progbits
.globl _Z4sortPj
.p2align 3, 0x0
_Z4sortPj:
.quad _Z19__device_stub__sortPj
.size _Z4sortPj, 8
.type _Z5mergePjS_i,@object # @_Z5mergePjS_i
.globl _Z5mergePjS_i
.p2align 3, 0x0
_Z5mergePjS_i:
.quad _Z20__device_stub__mergePjS_i
.size _Z5mergePjS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Initializing data:"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sortCuda failed!"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results after sorting:"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Data ["
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "]: "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipDeviceReset failed!"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.6, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy failed!"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Launching kernel on the GPU"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "sortKernel launch failed: %s\n"
.size .L.str.10, 30
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching sortKernel!\n"
.size .L.str.11, 73
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPj"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5mergePjS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPj
.addrsig_sym _Z20__device_stub__mergePjS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPj
.addrsig_sym _Z5mergePjS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} | .file "tmpxft_000f46ad_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "basic/hello initialized!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
std::cout << "basic/hello initialized!" << std::endl;
} | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "basic/hello initialized!"
.size .L.str, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f46ad_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "basic/hello initialized!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "basic/hello initialized!"
.size .L.str, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11) {
for (int i=0; i < var_1; ++i) {
comp = (+1.5305E34f + -1.1993E13f + +1.7273E-44f);
comp += -0.0f + var_2 + var_3;
comp += (-1.8399E-36f * var_4);
if (comp >= (-1.4667E28f - +1.2950E-43f - +0.0f)) {
comp += powf(expf((var_5 - coshf((var_6 / +0.0f - log10f(var_7 * var_8))))), +1.0475E-43f / (-1.8649E-37f / (+1.5649E-28f / +0.0f)));
comp += -1.5571E-35f * (var_9 + asinf((-1.1575E-36f - var_10 - var_11)));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000d780b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z36__device_stub__Z7computefifffffffffffiffffffffff
.type _Z36__device_stub__Z7computefifffffffffffiffffffffff, @function
_Z36__device_stub__Z7computefifffffffffffiffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z7computefifffffffffffiffffffffff, .-_Z36__device_stub__Z7computefifffffffffffiffffffffff
.globl _Z7computefiffffffffff
.type _Z7computefiffffffffff, @function
_Z7computefiffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movss 64(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 56(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 48(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z36__device_stub__Z7computefifffffffffffiffffffffff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffffff, .-_Z7computefiffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 88(%rsp), %xmm0
subq $32, %rsp
.cfi_def_cfa_offset 192
pxor %xmm1, %xmm1
cvtsd2ss 40(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 48(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 64(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 72(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 80(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 88(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 96(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 104(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movl %ebp, %edi
call _Z36__device_stub__Z7computefifffffffffffiffffffffff
addq $32, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11) {
for (int i=0; i < var_1; ++i) {
comp = (+1.5305E34f + -1.1993E13f + +1.7273E-44f);
comp += -0.0f + var_2 + var_3;
comp += (-1.8399E-36f * var_4);
if (comp >= (-1.4667E28f - +1.2950E-43f - +0.0f)) {
comp += powf(expf((var_5 - coshf((var_6 / +0.0f - log10f(var_7 * var_8))))), +1.0475E-43f / (-1.8649E-37f / (+1.5649E-28f / +0.0f)));
comp += -1.5571E-35f * (var_9 + asinf((-1.1575E-36f - var_10 - var_11)));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11) {
for (int i=0; i < var_1; ++i) {
comp = (+1.5305E34f + -1.1993E13f + +1.7273E-44f);
comp += -0.0f + var_2 + var_3;
comp += (-1.8399E-36f * var_4);
if (comp >= (-1.4667E28f - +1.2950E-43f - +0.0f)) {
comp += powf(expf((var_5 - coshf((var_6 / +0.0f - log10f(var_7 * var_8))))), +1.0475E-43f / (-1.8649E-37f / (+1.5649E-28f / +0.0f)));
comp += -1.5571E-35f * (var_9 + asinf((-1.1575E-36f - var_10 - var_11)));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11) {
for (int i=0; i < var_1; ++i) {
comp = (+1.5305E34f + -1.1993E13f + +1.7273E-44f);
comp += -0.0f + var_2 + var_3;
comp += (-1.8399E-36f * var_4);
if (comp >= (-1.4667E28f - +1.2950E-43f - +0.0f)) {
comp += powf(expf((var_5 - coshf((var_6 / +0.0f - log10f(var_7 * var_8))))), +1.0475E-43f / (-1.8649E-37f / (+1.5649E-28f / +0.0f)));
comp += -1.5571E-35f * (var_9 + asinf((-1.1575E-36f - var_10 - var_11)));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffffff # -- Begin function _Z22__device_stub__computefiffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffffff,@function
_Z22__device_stub__computefiffffffffff: # @_Z22__device_stub__computefiffffffffff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 128(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 136(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movss %xmm10, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm9, 44(%rsp)
movss %xmm8, 40(%rsp)
movss %xmm7, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 36(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rax
movq %rax, 232(%rsp)
leaq 28(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 20(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 12(%rsp), %rax
movq %rax, 272(%rsp)
leaq 8(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z7computefiffffffffff, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffffff,@object # @_Z7computefiffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffffff
.p2align 3, 0x0
_Z7computefiffffffffff:
.quad _Z22__device_stub__computefiffffffffff
.size _Z7computefiffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffffff"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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