system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d780b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z36__device_stub__Z7computefifffffffffffiffffffffff
.type _Z36__device_stub__Z7computefifffffffffffiffffffffff, @function
_Z36__device_stub__Z7computefifffffffffffiffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z7computefifffffffffffiffffffffff, .-_Z36__device_stub__Z7computefifffffffffffiffffffffff
.globl _Z7computefiffffffffff
.type _Z7computefiffffffffff, @function
_Z7computefiffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movss 64(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 56(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 48(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z36__device_stub__Z7computefifffffffffffiffffffffff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffffff, .-_Z7computefiffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 88(%rsp), %xmm0
subq $32, %rsp
.cfi_def_cfa_offset 192
pxor %xmm1, %xmm1
cvtsd2ss 40(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 48(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 64(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 72(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 80(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 88(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 96(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 104(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movl %ebp, %edi
call _Z36__device_stub__Z7computefifffffffffffiffffffffff
addq $32, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffffff # -- Begin function _Z22__device_stub__computefiffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffffff,@function
_Z22__device_stub__computefiffffffffff: # @_Z22__device_stub__computefiffffffffff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 128(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 136(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movss %xmm10, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm9, 44(%rsp)
movss %xmm8, 40(%rsp)
movss %xmm7, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 36(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rax
movq %rax, 232(%rsp)
leaq 28(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 20(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 12(%rsp), %rax
movq %rax, 272(%rsp)
leaq 8(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z7computefiffffffffff, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffffff,@object # @_Z7computefiffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffffff
.p2align 3, 0x0
_Z7computefiffffffffff:
.quad _Z22__device_stub__computefiffffffffff
.size _Z7computefiffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffffff"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define INF 1073741824
#define BLOCK_SZ 16
int m; // nodes
int n; // dimensions
int k; // k-nearest
// input sample file
int* load(const char *input)
{
FILE *file = fopen(input, "r");
if (!file) {
fprintf(stderr, "Error: no such input file \"%s\"\n", input);
exit(1);
}
// load m, n, k
fscanf(file, "%d%d%d", &m, &n, &k);
// allocate memory
int *data = (int*)malloc(sizeof(int) * m * n);
// load data
for (int i = 0; i < m * n; i++) {
fscanf(file, "%d", data + i);
}
fclose(file);
return data;
}
__global__ void distances(int *data, int *dis, int m, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i > j || i >= m || j >= m) return;
if (i == j) {
dis[i * m + i] = INF;
} else {
int tmp1;
int tmp2 = 0;
for (int l = 0; l < n; l++) { // for each dimension
tmp1 = data[i * n + l] - data[j * n + l];
tmp2 += tmp1 * tmp1;
}
dis[i * m + j] = dis[j * m + i] = tmp2;
}
}
__global__ void sort(int *dis, int *result, int m, int k)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= m) return;
int tmp, idx;
for (int j = 0; j < k; j++) { // find j-th nearest neighbor
tmp = INF;
for (int l = i * m; l < (i + 1) * m; l++) {
if (dis[l] < tmp) {
tmp = dis[l];
idx = l;
}
}
result[i * k + j] = idx % m;
dis[idx] = INF;
}
}
void knn(int *data, int *result)
{
int *d_data, *d_result, *d_dis;
int block = ceil(m / (double)BLOCK_SZ);
float timer1, timer2;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMalloc((void**)&d_data, sizeof(int) * m * n);
cudaMalloc((void**)&d_result, sizeof(int) * m * k);
cudaMalloc((void**)&d_dis, sizeof(int) * m * m);
cudaMemcpy(d_data, data, sizeof(int) * m * n, cudaMemcpyHostToDevice);
cudaEventRecord(start);
distances<<<dim3(block, block, 1), dim3(BLOCK_SZ, BLOCK_SZ, 1)>>>(d_data, d_dis, m, n);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer1, start, stop);
cudaEventRecord(start);
sort<<<block, BLOCK_SZ>>>(d_dis, d_result, m, k);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer2, start, stop);
cudaMemcpy(result, d_result, sizeof(int) * m * k, cudaMemcpyDeviceToHost);
fprintf(stderr, "distance: %.4lf ms\n", timer1);
fprintf(stderr, "sort: %.4lf ms\n", timer2);
cudaFree(d_data);
cudaFree(d_result);
cudaFree(d_dis);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
int main(int argc, char **argv)
{
if (argc != 2) {
fprintf(stderr, "Usage: %s input_file\n", argv[0]);
exit(1);
}
// input
int *data = load(argv[1]);
int *result = (int*)malloc(sizeof(int) * m * k);
// compute
knn(data, result);
// output
for (int i = 0; i < m; i++) {
for (int j = 0; j < k; j++) {
printf("%d ", result[i * k + j]);
}
printf("\n");
}
free(data);
free(result);
return 0;
} | .file "tmpxft_000e03aa_00000000-6_knn_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error: no such input file \"%s\"\n"
.section .rodata.str1.1
.LC2:
.string "%d%d%d"
.LC3:
.string "%d"
.text
.globl _Z4loadPKc
.type _Z4loadPKc, @function
_Z4loadPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L9
movq %rax, %r12
leaq k(%rip), %r8
leaq n(%rip), %rcx
leaq m(%rip), %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl m(%rip), %ebx
movl n(%rip), %ebp
movslq %ebx, %rdi
movslq %ebp, %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
imull %ebp, %ebx
testl %ebx, %ebx
jle .L5
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r13
.L6:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
movl m(%rip), %eax
imull n(%rip), %eax
cmpl %ebx, %eax
jg .L6
.L5:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4loadPKc, .-_Z4loadPKc
.globl _Z32__device_stub__Z9distancesPiS_iiPiS_ii
.type _Z32__device_stub__Z9distancesPiS_iiPiS_ii, @function
_Z32__device_stub__Z9distancesPiS_iiPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9distancesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z9distancesPiS_iiPiS_ii, .-_Z32__device_stub__Z9distancesPiS_iiPiS_ii
.globl _Z9distancesPiS_ii
.type _Z9distancesPiS_ii, @function
_Z9distancesPiS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9distancesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9distancesPiS_ii, .-_Z9distancesPiS_ii
.globl _Z27__device_stub__Z4sortPiS_iiPiS_ii
.type _Z27__device_stub__Z4sortPiS_iiPiS_ii, @function
_Z27__device_stub__Z4sortPiS_iiPiS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sortPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z4sortPiS_iiPiS_ii, .-_Z27__device_stub__Z4sortPiS_iiPiS_ii
.globl _Z4sortPiS_ii
.type _Z4sortPiS_ii, @function
_Z4sortPiS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4sortPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4sortPiS_ii, .-_Z4sortPiS_ii
.section .rodata.str1.1
.LC8:
.string "distance: %.4lf ms\n"
.LC9:
.string "sort: %.4lf ms\n"
.text
.globl _Z3knnPiS_
.type _Z3knnPiS_, @function
_Z3knnPiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl m(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC5(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L27
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movapd %xmm0, %xmm3
cmpnlesd %xmm1, %xmm3
movsd .LC7(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm3, %xmm1
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm1
movsd %xmm1, 8(%rsp)
.L27:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movslq m(%rip), %rsi
movslq n(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rsi
movslq k(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rsi
imulq %rsi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rdx
movslq n(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
cvttsd2sil 8(%rsp), %ebp
movl %ebp, 64(%rsp)
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebp, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movslq m(%rip), %rdx
movslq k(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl n(%rip), %ecx
movl m(%rip), %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z9distancesPiS_iiPiS_ii
jmp .L28
.L33:
movl k(%rip), %ecx
movl m(%rip), %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z4sortPiS_iiPiS_ii
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z3knnPiS_, .-_Z3knnPiS_
.section .rodata.str1.1
.LC11:
.string "Usage: %s input_file\n"
.LC12:
.string "%d "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
cmpl $2, %edi
jne .L47
movq 8(%rsi), %rdi
call _Z4loadPKc
movq %rax, %r15
movslq m(%rip), %rdi
movslq k(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, %rsi
movq %r15, %rdi
call _Z3knnPiS_
movl $0, %ebp
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r14
cmpl $0, m(%rip)
jg .L37
.L38:
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl k(%rip), %eax
cmpl %ebx, %eax
jg .L39
.L40:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, m(%rip)
jle .L38
.L37:
movl k(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L39
jmp .L40
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z4sortPiS_ii"
.LC15:
.string "_Z9distancesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9distancesPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl k
.bss
.align 4
.type k, @object
.size k, 4
k:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl m
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1068498944
.align 8
.LC5:
.long 0
.long 1127219200
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define INF 1073741824
#define BLOCK_SZ 16
int m; // nodes
int n; // dimensions
int k; // k-nearest
// input sample file
int* load(const char *input)
{
FILE *file = fopen(input, "r");
if (!file) {
fprintf(stderr, "Error: no such input file \"%s\"\n", input);
exit(1);
}
// load m, n, k
fscanf(file, "%d%d%d", &m, &n, &k);
// allocate memory
int *data = (int*)malloc(sizeof(int) * m * n);
// load data
for (int i = 0; i < m * n; i++) {
fscanf(file, "%d", data + i);
}
fclose(file);
return data;
}
__global__ void distances(int *data, int *dis, int m, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i > j || i >= m || j >= m) return;
if (i == j) {
dis[i * m + i] = INF;
} else {
int tmp1;
int tmp2 = 0;
for (int l = 0; l < n; l++) { // for each dimension
tmp1 = data[i * n + l] - data[j * n + l];
tmp2 += tmp1 * tmp1;
}
dis[i * m + j] = dis[j * m + i] = tmp2;
}
}
__global__ void sort(int *dis, int *result, int m, int k)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= m) return;
int tmp, idx;
for (int j = 0; j < k; j++) { // find j-th nearest neighbor
tmp = INF;
for (int l = i * m; l < (i + 1) * m; l++) {
if (dis[l] < tmp) {
tmp = dis[l];
idx = l;
}
}
result[i * k + j] = idx % m;
dis[idx] = INF;
}
}
void knn(int *data, int *result)
{
int *d_data, *d_result, *d_dis;
int block = ceil(m / (double)BLOCK_SZ);
float timer1, timer2;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMalloc((void**)&d_data, sizeof(int) * m * n);
cudaMalloc((void**)&d_result, sizeof(int) * m * k);
cudaMalloc((void**)&d_dis, sizeof(int) * m * m);
cudaMemcpy(d_data, data, sizeof(int) * m * n, cudaMemcpyHostToDevice);
cudaEventRecord(start);
distances<<<dim3(block, block, 1), dim3(BLOCK_SZ, BLOCK_SZ, 1)>>>(d_data, d_dis, m, n);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer1, start, stop);
cudaEventRecord(start);
sort<<<block, BLOCK_SZ>>>(d_dis, d_result, m, k);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer2, start, stop);
cudaMemcpy(result, d_result, sizeof(int) * m * k, cudaMemcpyDeviceToHost);
fprintf(stderr, "distance: %.4lf ms\n", timer1);
fprintf(stderr, "sort: %.4lf ms\n", timer2);
cudaFree(d_data);
cudaFree(d_result);
cudaFree(d_dis);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
int main(int argc, char **argv)
{
if (argc != 2) {
fprintf(stderr, "Usage: %s input_file\n", argv[0]);
exit(1);
}
// input
int *data = load(argv[1]);
int *result = (int*)malloc(sizeof(int) * m * k);
// compute
knn(data, result);
// output
for (int i = 0; i < m; i++) {
for (int j = 0; j < k; j++) {
printf("%d ", result[i * k + j]);
}
printf("\n");
}
free(data);
free(result);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define INF 1073741824
#define BLOCK_SZ 16
int m; // nodes
int n; // dimensions
int k; // k-nearest
// input sample file
int* load(const char *input)
{
FILE *file = fopen(input, "r");
if (!file) {
fprintf(stderr, "Error: no such input file \"%s\"\n", input);
exit(1);
}
// load m, n, k
fscanf(file, "%d%d%d", &m, &n, &k);
// allocate memory
int *data = (int*)malloc(sizeof(int) * m * n);
// load data
for (int i = 0; i < m * n; i++) {
fscanf(file, "%d", data + i);
}
fclose(file);
return data;
}
__global__ void distances(int *data, int *dis, int m, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i > j || i >= m || j >= m) return;
if (i == j) {
dis[i * m + i] = INF;
} else {
int tmp1;
int tmp2 = 0;
for (int l = 0; l < n; l++) { // for each dimension
tmp1 = data[i * n + l] - data[j * n + l];
tmp2 += tmp1 * tmp1;
}
dis[i * m + j] = dis[j * m + i] = tmp2;
}
}
__global__ void sort(int *dis, int *result, int m, int k)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= m) return;
int tmp, idx;
for (int j = 0; j < k; j++) { // find j-th nearest neighbor
tmp = INF;
for (int l = i * m; l < (i + 1) * m; l++) {
if (dis[l] < tmp) {
tmp = dis[l];
idx = l;
}
}
result[i * k + j] = idx % m;
dis[idx] = INF;
}
}
void knn(int *data, int *result)
{
int *d_data, *d_result, *d_dis;
int block = ceil(m / (double)BLOCK_SZ);
float timer1, timer2;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void**)&d_data, sizeof(int) * m * n);
hipMalloc((void**)&d_result, sizeof(int) * m * k);
hipMalloc((void**)&d_dis, sizeof(int) * m * m);
hipMemcpy(d_data, data, sizeof(int) * m * n, hipMemcpyHostToDevice);
hipEventRecord(start);
distances<<<dim3(block, block, 1), dim3(BLOCK_SZ, BLOCK_SZ, 1)>>>(d_data, d_dis, m, n);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer1, start, stop);
hipEventRecord(start);
sort<<<block, BLOCK_SZ>>>(d_dis, d_result, m, k);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer2, start, stop);
hipMemcpy(result, d_result, sizeof(int) * m * k, hipMemcpyDeviceToHost);
fprintf(stderr, "distance: %.4lf ms\n", timer1);
fprintf(stderr, "sort: %.4lf ms\n", timer2);
hipFree(d_data);
hipFree(d_result);
hipFree(d_dis);
hipEventDestroy(start);
hipEventDestroy(stop);
}
int main(int argc, char **argv)
{
if (argc != 2) {
fprintf(stderr, "Usage: %s input_file\n", argv[0]);
exit(1);
}
// input
int *data = load(argv[1]);
int *result = (int*)malloc(sizeof(int) * m * k);
// compute
knn(data, result);
// output
for (int i = 0; i < m; i++) {
for (int j = 0; j < k; j++) {
printf("%d ", result[i * k + j]);
}
printf("\n");
}
free(data);
free(result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define INF 1073741824
#define BLOCK_SZ 16
int m; // nodes
int n; // dimensions
int k; // k-nearest
// input sample file
int* load(const char *input)
{
FILE *file = fopen(input, "r");
if (!file) {
fprintf(stderr, "Error: no such input file \"%s\"\n", input);
exit(1);
}
// load m, n, k
fscanf(file, "%d%d%d", &m, &n, &k);
// allocate memory
int *data = (int*)malloc(sizeof(int) * m * n);
// load data
for (int i = 0; i < m * n; i++) {
fscanf(file, "%d", data + i);
}
fclose(file);
return data;
}
__global__ void distances(int *data, int *dis, int m, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i > j || i >= m || j >= m) return;
if (i == j) {
dis[i * m + i] = INF;
} else {
int tmp1;
int tmp2 = 0;
for (int l = 0; l < n; l++) { // for each dimension
tmp1 = data[i * n + l] - data[j * n + l];
tmp2 += tmp1 * tmp1;
}
dis[i * m + j] = dis[j * m + i] = tmp2;
}
}
__global__ void sort(int *dis, int *result, int m, int k)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= m) return;
int tmp, idx;
for (int j = 0; j < k; j++) { // find j-th nearest neighbor
tmp = INF;
for (int l = i * m; l < (i + 1) * m; l++) {
if (dis[l] < tmp) {
tmp = dis[l];
idx = l;
}
}
result[i * k + j] = idx % m;
dis[idx] = INF;
}
}
void knn(int *data, int *result)
{
int *d_data, *d_result, *d_dis;
int block = ceil(m / (double)BLOCK_SZ);
float timer1, timer2;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void**)&d_data, sizeof(int) * m * n);
hipMalloc((void**)&d_result, sizeof(int) * m * k);
hipMalloc((void**)&d_dis, sizeof(int) * m * m);
hipMemcpy(d_data, data, sizeof(int) * m * n, hipMemcpyHostToDevice);
hipEventRecord(start);
distances<<<dim3(block, block, 1), dim3(BLOCK_SZ, BLOCK_SZ, 1)>>>(d_data, d_dis, m, n);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer1, start, stop);
hipEventRecord(start);
sort<<<block, BLOCK_SZ>>>(d_dis, d_result, m, k);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer2, start, stop);
hipMemcpy(result, d_result, sizeof(int) * m * k, hipMemcpyDeviceToHost);
fprintf(stderr, "distance: %.4lf ms\n", timer1);
fprintf(stderr, "sort: %.4lf ms\n", timer2);
hipFree(d_data);
hipFree(d_result);
hipFree(d_dis);
hipEventDestroy(start);
hipEventDestroy(stop);
}
int main(int argc, char **argv)
{
if (argc != 2) {
fprintf(stderr, "Usage: %s input_file\n", argv[0]);
exit(1);
}
// input
int *data = load(argv[1]);
int *result = (int*)malloc(sizeof(int) * m * k);
// compute
knn(data, result);
// output
for (int i = 0; i < m; i++) {
for (int j = 0; j < k; j++) {
printf("%d ", result[i * k + j]);
}
printf("\n");
}
free(data);
free(result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9distancesPiS_ii
.globl _Z9distancesPiS_ii
.p2align 8
.type _Z9distancesPiS_ii,@function
_Z9distancesPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_max_i32_e32 v2, v0, v1
v_cmp_le_i32_e32 vcc_lo, v0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v2
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e64 v0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_7
s_load_b32 s6, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s6
v_mul_lo_u32 v4, v0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v9, vcc_lo
.p2align 6
.LBB0_4:
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v[3:4], off
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v9, v7, v8
v_mad_u64_u32 v[7:8], null, v9, v9, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s5
v_mad_u64_u32 v[3:4], null, v0, s4, v[0:1]
v_mov_b32_e32 v2, 2.0
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9distancesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9distancesPiS_ii, .Lfunc_end0-_Z9distancesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4sortPiS_ii
.globl _Z4sortPiS_ii
.p2align 8
.type _Z4sortPiS_ii,@function
_Z4sortPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_6
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s2, s4
s_xor_b32 s9, s5, s4
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s0, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v0
v_mul_lo_u32 v0, v2, s2
v_cvt_u32_f32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_mul_lo_u32 v6, s0, v5
v_add_nc_u32_e32 v7, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, v0, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mul_hi_u32 v8, v5, v6
v_mul_lo_u32 v6, v2, s3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v2, s0, s5, v4, s0
v_dual_mov_b32 v8, 2.0 :: v_dual_add_nc_u32 v7, v5, v8
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s1
v_ashrrev_i32_e32 v11, 31, v3
v_add_nc_u32_e32 v9, s8, v6
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, s3
v_add_nc_u32_e32 v4, v3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_xor_b32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_mul_hi_u32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s9
v_sub_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e64 s0, s9, v4
v_cndmask_b32_e64 v5, v4, v5, s0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v12, s9, v5
v_cmp_le_u32_e64 s0, s9, v5
v_cndmask_b32_e64 v12, v5, v12, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v9, s0, s6, v9
v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v12, v12, v11
v_add_co_u32 v4, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
v_sub_nc_u32_e32 v11, v12, v11
global_store_b32 v[9:10], v11, off
global_store_b32 v[4:5], v8, off
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB1_2
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v10, v0
v_dual_mov_b32 v9, 2.0 :: v_dual_mov_b32 v4, v1
s_mov_b32 s10, s2
.LBB1_5:
global_load_b32 v11, v[4:5], off
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, v11, v9
v_min_i32_e32 v9, v11, v9
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v10, s0
v_add_nc_u32_e32 v10, 1, v10
s_cbranch_scc0 .LBB1_5
s_branch .LBB1_2
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4sortPiS_ii, .Lfunc_end1-_Z4sortPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9distancesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9distancesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define INF 1073741824
#define BLOCK_SZ 16
int m; // nodes
int n; // dimensions
int k; // k-nearest
// input sample file
int* load(const char *input)
{
FILE *file = fopen(input, "r");
if (!file) {
fprintf(stderr, "Error: no such input file \"%s\"\n", input);
exit(1);
}
// load m, n, k
fscanf(file, "%d%d%d", &m, &n, &k);
// allocate memory
int *data = (int*)malloc(sizeof(int) * m * n);
// load data
for (int i = 0; i < m * n; i++) {
fscanf(file, "%d", data + i);
}
fclose(file);
return data;
}
__global__ void distances(int *data, int *dis, int m, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i > j || i >= m || j >= m) return;
if (i == j) {
dis[i * m + i] = INF;
} else {
int tmp1;
int tmp2 = 0;
for (int l = 0; l < n; l++) { // for each dimension
tmp1 = data[i * n + l] - data[j * n + l];
tmp2 += tmp1 * tmp1;
}
dis[i * m + j] = dis[j * m + i] = tmp2;
}
}
__global__ void sort(int *dis, int *result, int m, int k)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= m) return;
int tmp, idx;
for (int j = 0; j < k; j++) { // find j-th nearest neighbor
tmp = INF;
for (int l = i * m; l < (i + 1) * m; l++) {
if (dis[l] < tmp) {
tmp = dis[l];
idx = l;
}
}
result[i * k + j] = idx % m;
dis[idx] = INF;
}
}
void knn(int *data, int *result)
{
int *d_data, *d_result, *d_dis;
int block = ceil(m / (double)BLOCK_SZ);
float timer1, timer2;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void**)&d_data, sizeof(int) * m * n);
hipMalloc((void**)&d_result, sizeof(int) * m * k);
hipMalloc((void**)&d_dis, sizeof(int) * m * m);
hipMemcpy(d_data, data, sizeof(int) * m * n, hipMemcpyHostToDevice);
hipEventRecord(start);
distances<<<dim3(block, block, 1), dim3(BLOCK_SZ, BLOCK_SZ, 1)>>>(d_data, d_dis, m, n);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer1, start, stop);
hipEventRecord(start);
sort<<<block, BLOCK_SZ>>>(d_dis, d_result, m, k);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer2, start, stop);
hipMemcpy(result, d_result, sizeof(int) * m * k, hipMemcpyDeviceToHost);
fprintf(stderr, "distance: %.4lf ms\n", timer1);
fprintf(stderr, "sort: %.4lf ms\n", timer2);
hipFree(d_data);
hipFree(d_result);
hipFree(d_dis);
hipEventDestroy(start);
hipEventDestroy(stop);
}
int main(int argc, char **argv)
{
if (argc != 2) {
fprintf(stderr, "Usage: %s input_file\n", argv[0]);
exit(1);
}
// input
int *data = load(argv[1]);
int *result = (int*)malloc(sizeof(int) * m * k);
// compute
knn(data, result);
// output
for (int i = 0; i < m; i++) {
for (int j = 0; j < k; j++) {
printf("%d ", result[i * k + j]);
}
printf("\n");
}
free(data);
free(result);
return 0;
} | .text
.file "knn_naive.hip"
.globl _Z4loadPKc # -- Begin function _Z4loadPKc
.p2align 4, 0x90
.type _Z4loadPKc,@function
_Z4loadPKc: # @_Z4loadPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_5
# %bb.1:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $m, %edx
movl $n, %ecx
movl $k, %r8d
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq m(%rip), %rdi
movslq n(%rip), %r15
imulq %r15, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movl m(%rip), %eax
imull %r15d, %eax
testl %eax, %eax
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq m(%rip), %rax
movslq n(%rip), %rcx
imulq %rax, %rcx
addq $4, %r15
cmpq %rcx, %r12
jl .LBB0_3
.LBB0_4: # %._crit_edge
movq %rbx, %rdi
callq fclose
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %r14, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z4loadPKc, .Lfunc_end0-_Z4loadPKc
.cfi_endproc
# -- End function
.globl _Z24__device_stub__distancesPiS_ii # -- Begin function _Z24__device_stub__distancesPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__distancesPiS_ii,@function
_Z24__device_stub__distancesPiS_ii: # @_Z24__device_stub__distancesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9distancesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__distancesPiS_ii, .Lfunc_end1-_Z24__device_stub__distancesPiS_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPiS_ii # -- Begin function _Z19__device_stub__sortPiS_ii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiS_ii,@function
_Z19__device_stub__sortPiS_ii: # @_Z19__device_stub__sortPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sortPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z19__device_stub__sortPiS_ii, .Lfunc_end2-_Z19__device_stub__sortPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3knnPiS_
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl _Z3knnPiS_
.p2align 4, 0x90
.type _Z3knnPiS_,@function
_Z3knnPiS_: # @_Z3knnPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r12
movabsq $4294967296, %r14 # imm = 0x100000000
cvtsi2sdl m(%rip), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq m(%rip), %rax
movslq n(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq m(%rip), %rax
movslq k(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq m(%rip), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 48(%rsp), %rdi
movslq m(%rip), %rax
movslq n(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 1(%r14), %rdi
imulq %r15, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 48(%rsp), %rax
movq 32(%rsp), %rcx
movl m(%rip), %edx
movl n(%rip), %esi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
movl %esi, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9distancesPiS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq %r14, %r15
addq $16, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movl m(%rip), %edx
movl k(%rip), %esi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
movl %esi, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4sortPiS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rsi
movslq m(%rip), %rax
movslq k(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq stderr(%rip), %rdi
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movq stderr(%rip), %rdi
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %esi
movb $1, %al
callq fprintf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z3knnPiS_, .Lfunc_end3-_Z3knnPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_8
# %bb.1:
movq 8(%rsi), %rdi
callq _Z4loadPKc
movq %rax, %rbx
movslq m(%rip), %rax
movslq k(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq _Z3knnPiS_
cmpl $0, m(%rip)
jle .LBB4_7
# %bb.2: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl m(%rip), %ebp
jge .LBB4_7
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movl k(%rip), %eax
testl %eax, %eax
jle .LBB4_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB4_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%r14,%rax,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl k(%rip), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB4_5
jmp .LBB4_6
.LBB4_7: # %._crit_edge18
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9distancesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type m,@object # @m
.bss
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type k,@object # @k
.globl k
.p2align 2, 0x0
k:
.long 0 # 0x0
.size k, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: no such input file \"%s\"\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d%d%d"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type _Z9distancesPiS_ii,@object # @_Z9distancesPiS_ii
.section .rodata,"a",@progbits
.globl _Z9distancesPiS_ii
.p2align 3, 0x0
_Z9distancesPiS_ii:
.quad _Z24__device_stub__distancesPiS_ii
.size _Z9distancesPiS_ii, 8
.type _Z4sortPiS_ii,@object # @_Z4sortPiS_ii
.globl _Z4sortPiS_ii
.p2align 3, 0x0
_Z4sortPiS_ii:
.quad _Z19__device_stub__sortPiS_ii
.size _Z4sortPiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "distance: %.4lf ms\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sort: %.4lf ms\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s input_file\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9distancesPiS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4sortPiS_ii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__distancesPiS_ii
.addrsig_sym _Z19__device_stub__sortPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym m
.addrsig_sym n
.addrsig_sym k
.addrsig_sym _Z9distancesPiS_ii
.addrsig_sym _Z4sortPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e03aa_00000000-6_knn_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error: no such input file \"%s\"\n"
.section .rodata.str1.1
.LC2:
.string "%d%d%d"
.LC3:
.string "%d"
.text
.globl _Z4loadPKc
.type _Z4loadPKc, @function
_Z4loadPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L9
movq %rax, %r12
leaq k(%rip), %r8
leaq n(%rip), %rcx
leaq m(%rip), %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl m(%rip), %ebx
movl n(%rip), %ebp
movslq %ebx, %rdi
movslq %ebp, %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
imull %ebp, %ebx
testl %ebx, %ebx
jle .L5
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r13
.L6:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
movl m(%rip), %eax
imull n(%rip), %eax
cmpl %ebx, %eax
jg .L6
.L5:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4loadPKc, .-_Z4loadPKc
.globl _Z32__device_stub__Z9distancesPiS_iiPiS_ii
.type _Z32__device_stub__Z9distancesPiS_iiPiS_ii, @function
_Z32__device_stub__Z9distancesPiS_iiPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9distancesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z9distancesPiS_iiPiS_ii, .-_Z32__device_stub__Z9distancesPiS_iiPiS_ii
.globl _Z9distancesPiS_ii
.type _Z9distancesPiS_ii, @function
_Z9distancesPiS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9distancesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9distancesPiS_ii, .-_Z9distancesPiS_ii
.globl _Z27__device_stub__Z4sortPiS_iiPiS_ii
.type _Z27__device_stub__Z4sortPiS_iiPiS_ii, @function
_Z27__device_stub__Z4sortPiS_iiPiS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sortPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z4sortPiS_iiPiS_ii, .-_Z27__device_stub__Z4sortPiS_iiPiS_ii
.globl _Z4sortPiS_ii
.type _Z4sortPiS_ii, @function
_Z4sortPiS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4sortPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4sortPiS_ii, .-_Z4sortPiS_ii
.section .rodata.str1.1
.LC8:
.string "distance: %.4lf ms\n"
.LC9:
.string "sort: %.4lf ms\n"
.text
.globl _Z3knnPiS_
.type _Z3knnPiS_, @function
_Z3knnPiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl m(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC5(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L27
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movapd %xmm0, %xmm3
cmpnlesd %xmm1, %xmm3
movsd .LC7(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm3, %xmm1
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm1
movsd %xmm1, 8(%rsp)
.L27:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movslq m(%rip), %rsi
movslq n(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rsi
movslq k(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rsi
imulq %rsi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq m(%rip), %rdx
movslq n(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
cvttsd2sil 8(%rsp), %ebp
movl %ebp, 64(%rsp)
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebp, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movslq m(%rip), %rdx
movslq k(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl n(%rip), %ecx
movl m(%rip), %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z9distancesPiS_iiPiS_ii
jmp .L28
.L33:
movl k(%rip), %ecx
movl m(%rip), %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z4sortPiS_iiPiS_ii
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z3knnPiS_, .-_Z3knnPiS_
.section .rodata.str1.1
.LC11:
.string "Usage: %s input_file\n"
.LC12:
.string "%d "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
cmpl $2, %edi
jne .L47
movq 8(%rsi), %rdi
call _Z4loadPKc
movq %rax, %r15
movslq m(%rip), %rdi
movslq k(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, %rsi
movq %r15, %rdi
call _Z3knnPiS_
movl $0, %ebp
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r14
cmpl $0, m(%rip)
jg .L37
.L38:
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl k(%rip), %eax
cmpl %ebx, %eax
jg .L39
.L40:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, m(%rip)
jle .L38
.L37:
movl k(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L39
jmp .L40
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z4sortPiS_ii"
.LC15:
.string "_Z9distancesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9distancesPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl k
.bss
.align 4
.type k, @object
.size k, 4
k:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl m
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1068498944
.align 8
.LC5:
.long 0
.long 1127219200
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "knn_naive.hip"
.globl _Z4loadPKc # -- Begin function _Z4loadPKc
.p2align 4, 0x90
.type _Z4loadPKc,@function
_Z4loadPKc: # @_Z4loadPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_5
# %bb.1:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $m, %edx
movl $n, %ecx
movl $k, %r8d
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq m(%rip), %rdi
movslq n(%rip), %r15
imulq %r15, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movl m(%rip), %eax
imull %r15d, %eax
testl %eax, %eax
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq m(%rip), %rax
movslq n(%rip), %rcx
imulq %rax, %rcx
addq $4, %r15
cmpq %rcx, %r12
jl .LBB0_3
.LBB0_4: # %._crit_edge
movq %rbx, %rdi
callq fclose
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %r14, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z4loadPKc, .Lfunc_end0-_Z4loadPKc
.cfi_endproc
# -- End function
.globl _Z24__device_stub__distancesPiS_ii # -- Begin function _Z24__device_stub__distancesPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__distancesPiS_ii,@function
_Z24__device_stub__distancesPiS_ii: # @_Z24__device_stub__distancesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9distancesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__distancesPiS_ii, .Lfunc_end1-_Z24__device_stub__distancesPiS_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPiS_ii # -- Begin function _Z19__device_stub__sortPiS_ii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiS_ii,@function
_Z19__device_stub__sortPiS_ii: # @_Z19__device_stub__sortPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sortPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z19__device_stub__sortPiS_ii, .Lfunc_end2-_Z19__device_stub__sortPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3knnPiS_
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl _Z3knnPiS_
.p2align 4, 0x90
.type _Z3knnPiS_,@function
_Z3knnPiS_: # @_Z3knnPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r12
movabsq $4294967296, %r14 # imm = 0x100000000
cvtsi2sdl m(%rip), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq m(%rip), %rax
movslq n(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq m(%rip), %rax
movslq k(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq m(%rip), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 48(%rsp), %rdi
movslq m(%rip), %rax
movslq n(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 1(%r14), %rdi
imulq %r15, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 48(%rsp), %rax
movq 32(%rsp), %rcx
movl m(%rip), %edx
movl n(%rip), %esi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
movl %esi, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9distancesPiS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq %r14, %r15
addq $16, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movl m(%rip), %edx
movl k(%rip), %esi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
movl %esi, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4sortPiS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rsi
movslq m(%rip), %rax
movslq k(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq stderr(%rip), %rdi
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movq stderr(%rip), %rdi
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %esi
movb $1, %al
callq fprintf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z3knnPiS_, .Lfunc_end3-_Z3knnPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_8
# %bb.1:
movq 8(%rsi), %rdi
callq _Z4loadPKc
movq %rax, %rbx
movslq m(%rip), %rax
movslq k(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq _Z3knnPiS_
cmpl $0, m(%rip)
jle .LBB4_7
# %bb.2: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl m(%rip), %ebp
jge .LBB4_7
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movl k(%rip), %eax
testl %eax, %eax
jle .LBB4_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB4_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%r14,%rax,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl k(%rip), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB4_5
jmp .LBB4_6
.LBB4_7: # %._crit_edge18
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9distancesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type m,@object # @m
.bss
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type k,@object # @k
.globl k
.p2align 2, 0x0
k:
.long 0 # 0x0
.size k, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: no such input file \"%s\"\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d%d%d"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type _Z9distancesPiS_ii,@object # @_Z9distancesPiS_ii
.section .rodata,"a",@progbits
.globl _Z9distancesPiS_ii
.p2align 3, 0x0
_Z9distancesPiS_ii:
.quad _Z24__device_stub__distancesPiS_ii
.size _Z9distancesPiS_ii, 8
.type _Z4sortPiS_ii,@object # @_Z4sortPiS_ii
.globl _Z4sortPiS_ii
.p2align 3, 0x0
_Z4sortPiS_ii:
.quad _Z19__device_stub__sortPiS_ii
.size _Z4sortPiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "distance: %.4lf ms\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sort: %.4lf ms\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s input_file\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9distancesPiS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4sortPiS_ii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__distancesPiS_ii
.addrsig_sym _Z19__device_stub__sortPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym m
.addrsig_sym n
.addrsig_sym k
.addrsig_sym _Z9distancesPiS_ii
.addrsig_sym _Z4sortPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} | .file "tmpxft_0008a13a_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4179:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4179:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[-] Sum: "
.LC1:
.string "[-] Duration: "
.LC2:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB4170:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4170
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $16777216, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
leaq 16777216(%rax), %rdx
.L4:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq %rbp, %rax
leaq 16777216(%rbp), %rcx
movl $0, %edx
.L5:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L5
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r12
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
jmp .L13
.L7:
endbr64
movq %rax, %rbx
movl $16777216, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L13:
movl $16777216, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4170:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4170-.LLSDACSB4170
.LLSDACSB4170:
.uleb128 .LEHB0-.LFB4170
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4170
.uleb128 .LEHE1-.LEHB1
.uleb128 .L7-.LFB4170
.uleb128 0
.uleb128 .LEHB2-.LFB4170
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4170:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4202:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4202:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* In his exalted name
*
* Reduction - Sequential Code
* Written by Ahmad Siavashi (siavashi@aut.ac.ir)
* Date: June, 2018
* Language: C++11
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <vector>
#include <chrono>
#include <iostream>>
#include <cmath>
#include <numeric>
// N = 2^22
#define N pow(2, 22)
using namespace std;
int main(int argc, char *argv[]) {
// initialize a vector of size N with 1
vector<int> v(N, 1);
// capture start time
auto start_time = chrono::high_resolution_clock::now();
// reduction
auto sum = accumulate(begin(v), end(v), 0);
// capture end time
auto end_time = chrono::high_resolution_clock::now();
// elapsed time in milliseconds
auto duration = chrono::duration_cast<chrono::microseconds>(end_time - start_time);
// print sum and elapsed time
cout << "[-] Sum: " << sum << endl;
cout << "[-] Duration: " << duration.count() << "ms" << endl;
return EXIT_SUCCESS;
} | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEE17_S_check_init_lenEmRKS0_.exit.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB0_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
xorl %r15d, %r15d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax), %r15d
addq $4, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB0_3
# %bb.4: # %_ZSt10accumulateIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET0_T_S8_S7_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
.Ltmp0:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp2:
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
.Ltmp3:
# %bb.6:
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB0_9
# %bb.8:
movzbl 67(%r12), %eax
jmp .LBB0_11
.LBB0_9:
.Ltmp4:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.10: # %.noexc22
movq (%r12), %rax
.Ltmp6:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB0_11: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp9:
# %bb.12: # %.noexc24
.Ltmp10:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp11:
# %bb.13: # %_ZNSolsEPFRSoS_E.exit
.Ltmp12:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit12
.Ltmp14:
movq %r14, %rax
shrq $63, %rax
sarq $7, %r14
addq %rax, %r14
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp15:
# %bb.15: # %_ZNSolsEl.exit
.Ltmp16:
movq %rax, %r14
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit15
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r15)
je .LBB0_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_21:
.Ltmp18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.22: # %.noexc32
movq (%r15), %rax
.Ltmp20:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i29
.Ltmp22:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp23:
# %bb.24: # %.noexc34
.Ltmp24:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit17
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_17: # %.invoke
.cfi_def_cfa_offset 48
.Ltmp26:
callq _ZSt16__throw_bad_castv
.Ltmp27:
# %bb.18: # %.cont
.LBB0_26: # %_ZNSt6vectorIiSaIiEED2Ev.exit19
.Ltmp28:
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp27-.Ltmp0 # Call between .Ltmp0 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end0-.Ltmp27 # Call between .Ltmp27 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[-] Sum: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[-] Duration: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a13a_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4179:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4179:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[-] Sum: "
.LC1:
.string "[-] Duration: "
.LC2:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB4170:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4170
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $16777216, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
leaq 16777216(%rax), %rdx
.L4:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq %rbp, %rax
leaq 16777216(%rbp), %rcx
movl $0, %edx
.L5:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L5
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r12
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
jmp .L13
.L7:
endbr64
movq %rax, %rbx
movl $16777216, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L13:
movl $16777216, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4170:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4170-.LLSDACSB4170
.LLSDACSB4170:
.uleb128 .LEHB0-.LFB4170
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4170
.uleb128 .LEHE1-.LEHB1
.uleb128 .L7-.LFB4170
.uleb128 0
.uleb128 .LEHB2-.LFB4170
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4170:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4202:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4202:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEE17_S_check_init_lenEmRKS0_.exit.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB0_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
xorl %r15d, %r15d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax), %r15d
addq $4, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB0_3
# %bb.4: # %_ZSt10accumulateIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET0_T_S8_S7_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
.Ltmp0:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp2:
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
.Ltmp3:
# %bb.6:
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB0_9
# %bb.8:
movzbl 67(%r12), %eax
jmp .LBB0_11
.LBB0_9:
.Ltmp4:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.10: # %.noexc22
movq (%r12), %rax
.Ltmp6:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB0_11: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp9:
# %bb.12: # %.noexc24
.Ltmp10:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp11:
# %bb.13: # %_ZNSolsEPFRSoS_E.exit
.Ltmp12:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit12
.Ltmp14:
movq %r14, %rax
shrq $63, %rax
sarq $7, %r14
addq %rax, %r14
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp15:
# %bb.15: # %_ZNSolsEl.exit
.Ltmp16:
movq %rax, %r14
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit15
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r15)
je .LBB0_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_21:
.Ltmp18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.22: # %.noexc32
movq (%r15), %rax
.Ltmp20:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i29
.Ltmp22:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp23:
# %bb.24: # %.noexc34
.Ltmp24:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit17
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_17: # %.invoke
.cfi_def_cfa_offset 48
.Ltmp26:
callq _ZSt16__throw_bad_castv
.Ltmp27:
# %bb.18: # %.cont
.LBB0_26: # %_ZNSt6vectorIiSaIiEED2Ev.exit19
.Ltmp28:
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp27-.Ltmp0 # Call between .Ltmp0 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end0-.Ltmp27 # Call between .Ltmp27 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[-] Sum: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[-] Duration: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} | code for sm_80
Function : _Z20matrixMultiplySharedPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x184], R0 ; /* 0x000061000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x184], P1 ; /* 0x0000610000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x184], R12 ; /* 0x00006100050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} | .file "tmpxft_000f5996_00000000-6_matrixMultiplyShared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.type _Z20matrixMultiplySharedPfS_S_iiiiii, @function
_Z20matrixMultiplySharedPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20matrixMultiplySharedPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20matrixMultiplySharedPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 8
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@function
_Z20matrixMultiplySharedPfS_S_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s8, -14
v_cmp_gt_i32_e32 vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s3, s8, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v7, 6, v3
s_ashr_i32 s11, s3, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mad_u64_u32 v[5:6], null, v0, s8, v[4:5]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s10, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v6, v8, v7
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s8, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v3
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v6, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s10, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplySharedPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplySharedPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplySharedPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiplyShared(float *A, float *B, float *C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
//@@ You have to use shared memory for this MP
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int m = numARows;
int n = numBRows;
int k = numBColumns;
int numRows = blockIdx.y * blockDim.y + ty;
int numColumns = blockIdx.x * blockDim.x + tx;
float Cval = 0.0;
//Loading A and B elements and doing Boundary Check
for(int t = 0; t < (n-1)/TILE_WIDTH + 1; t++) {
if((numRows < numARows) && (t*TILE_WIDTH+tx < n)) {
ds_A[ty][tx] = A[numRows*n + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if((numColumns < k) && (t*TILE_WIDTH+ty < n)) {
ds_B[ty][tx] = B[(t*TILE_WIDTH+ty)*k + numColumns];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH; i++) {
Cval += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if(numRows < m && numColumns < k) {
C[numRows*k + numColumns] = Cval;
}
} | .text
.file "matrixMultiplyShared.hip"
.globl _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii # -- Begin function _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii,@function
_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii: # @_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@object # @_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 3, 0x0
_Z20matrixMultiplySharedPfS_S_iiiiii:
.quad _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.size _Z20matrixMultiplySharedPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20matrixMultiplySharedPfS_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20matrixMultiplySharedPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x184], R0 ; /* 0x000061000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x184], P1 ; /* 0x0000610000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x184], R12 ; /* 0x00006100050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20matrixMultiplySharedPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 8
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@function
_Z20matrixMultiplySharedPfS_S_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s8, -14
v_cmp_gt_i32_e32 vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s3, s8, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v7, 6, v3
s_ashr_i32 s11, s3, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mad_u64_u32 v[5:6], null, v0, s8, v[4:5]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s10, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v6, v8, v7
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s8, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v3
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v6, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s10, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplySharedPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplySharedPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplySharedPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5996_00000000-6_matrixMultiplyShared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.type _Z20matrixMultiplySharedPfS_S_iiiiii, @function
_Z20matrixMultiplySharedPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20matrixMultiplySharedPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiplyShared.hip"
.globl _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii # -- Begin function _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii,@function
_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii: # @_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@object # @_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 3, 0x0
_Z20matrixMultiplySharedPfS_S_iiiiii:
.quad _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.size _Z20matrixMultiplySharedPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20matrixMultiplySharedPfS_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
cudaMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
cudaDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
cudaFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} | code for sm_80
Function : _Z3addPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
cudaMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
cudaDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
cudaFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} | .file "tmpxft_000df37d_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10add_serialPKfS0_Pfi
.type _Z10add_serialPKfS0_Pfi, @function
_Z10add_serialPKfS0_Pfi:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z10add_serialPKfS0_Pfi, .-_Z10add_serialPKfS0_Pfi
.globl _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
.globl _Z3addPKfS0_Pfi
.type _Z3addPKfS0_Pfi, @function
_Z3addPKfS0_Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPKfS0_Pfi, .-_Z3addPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Calc error..."
.LC6:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
movq 24(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L16
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1048576, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 40(%rsp), %rbx
leaq 1073741824(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L18:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $268435456, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3addPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
cudaMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
cudaDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
cudaFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
hipMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
hipDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
hipFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
hipMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
hipDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
hipFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKfS0_Pfi
.globl _Z3addPKfS0_Pfi
.p2align 8
.type _Z3addPKfS0_Pfi,@function
_Z3addPKfS0_Pfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKfS0_Pfi, .Lfunc_end0-_Z3addPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__
void add(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
res[i] = x[i] + y[i];
}
void add_serial(
const float *const x,
const float *const y,
float *const res,
const int n
)
{
for (int i = 0; i < n; ++i)
res[i] = x[i] + y[i];
}
int main()
{
int N = 1 << 28; // 1M elements
float *x, *y, *res;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
hipMallocManaged(&res, N * sizeof(float));
// x = new float[N];
// y = new float[N];
// res = new float[N];
for (int i = 0; i < N; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add <<< numBlocks, blockSize >>> (x, y, res, N);
hipDeviceSynchronize();
// add_serial(x, y, res, N);
std::cout << "Calc error...";
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(res[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
hipFree(res);
// delete[] x;
// delete[] y;
// delete[] res;
return 0;
} | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPKfS0_Pfi # -- Begin function _Z18__device_stub__addPKfS0_Pfi
.p2align 4, 0x90
.type _Z18__device_stub__addPKfS0_Pfi,@function
_Z18__device_stub__addPKfS0_Pfi: # @_Z18__device_stub__addPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPKfS0_Pfi, .Lfunc_end0-_Z18__device_stub__addPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z10add_serialPKfS0_Pfi # -- Begin function _Z10add_serialPKfS0_Pfi
.p2align 4, 0x90
.type _Z10add_serialPKfS0_Pfi,@function
_Z10add_serialPKfS0_Pfi: # @_Z10add_serialPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10add_serialPKfS0_Pfi, .Lfunc_end1-_Z10add_serialPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $268435456, %rcx # imm = 0x10000000
jne .LBB2_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $268435456, 36(%rsp) # imm = 0x10000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKfS0_Pfi,@object # @_Z3addPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z3addPKfS0_Pfi
.p2align 3, 0x0
_Z3addPKfS0_Pfi:
.quad _Z18__device_stub__addPKfS0_Pfi
.size _Z3addPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calc error..."
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKfS0_Pfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKfS0_Pfi
.globl _Z3addPKfS0_Pfi
.p2align 8
.type _Z3addPKfS0_Pfi,@function
_Z3addPKfS0_Pfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKfS0_Pfi, .Lfunc_end0-_Z3addPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df37d_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10add_serialPKfS0_Pfi
.type _Z10add_serialPKfS0_Pfi, @function
_Z10add_serialPKfS0_Pfi:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z10add_serialPKfS0_Pfi, .-_Z10add_serialPKfS0_Pfi
.globl _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
.globl _Z3addPKfS0_Pfi
.type _Z3addPKfS0_Pfi, @function
_Z3addPKfS0_Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPKfS0_Pfi, .-_Z3addPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Calc error..."
.LC6:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
movq 24(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L16
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1048576, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 40(%rsp), %rbx
leaq 1073741824(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L18:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $268435456, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z3addPKfS0_PfiPKfS0_Pfi
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3addPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPKfS0_Pfi # -- Begin function _Z18__device_stub__addPKfS0_Pfi
.p2align 4, 0x90
.type _Z18__device_stub__addPKfS0_Pfi,@function
_Z18__device_stub__addPKfS0_Pfi: # @_Z18__device_stub__addPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPKfS0_Pfi, .Lfunc_end0-_Z18__device_stub__addPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z10add_serialPKfS0_Pfi # -- Begin function _Z10add_serialPKfS0_Pfi
.p2align 4, 0x90
.type _Z10add_serialPKfS0_Pfi,@function
_Z10add_serialPKfS0_Pfi: # @_Z10add_serialPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10add_serialPKfS0_Pfi, .Lfunc_end1-_Z10add_serialPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $268435456, %rcx # imm = 0x10000000
jne .LBB2_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $268435456, 36(%rsp) # imm = 0x10000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKfS0_Pfi,@object # @_Z3addPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z3addPKfS0_Pfi
.p2align 3, 0x0
_Z3addPKfS0_Pfi:
.quad _Z18__device_stub__addPKfS0_Pfi
.size _Z3addPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calc error..."
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKfS0_Pfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define TPB2D 8
__global__ void ldc_D3Q15_LBGK_ts(float * fOut, const float * fIn,
const int * snl,
const int * lnl, const float u_bc,
const float omega,const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
int X=threadIdx.x+blockIdx.x*blockDim.x;
int Y=threadIdx.y+blockIdx.y*blockDim.y;
int Z=threadIdx.z+blockIdx.z*blockDim.z;
if((X<Nx)&&(Y<Ny)&&(Z<Nz)){
int tid=X+Y*Nx+Z*Nx*Ny;
int dof;
//load fIn data into shared memory
__shared__ float fIns[TPB2D][TPB2D][15];
for(int spd=0;spd<15;spd++){
for(int y=0;y<TPB2D;y++){
for(int x=0;x<TPB2D;x++){
dof=(blockIdx.x*blockDim.x+x)+
(blockIdx.y*blockDim.y+y)*Nx+
(blockIdx.z*blockDim.z)*Nx*Ny;
fIns[y][x][spd]=fIn[spd*(Nx*Ny*Nz)+dof];
}
}
}
//compute density and velocity
float rho=0.; float ux=0.; float uy=0.; float uz=0.; float f_tmp;
for(int spd=0;spd<15;spd++){
f_tmp=fIns[threadIdx.y][threadIdx.x][spd];
rho+=f_tmp;
ux+=f_tmp*ex[spd];
uy+=f_tmp*ey[spd];
uz+=f_tmp*ez[spd];
}
ux/=rho; uy/=rho; uz/=rho;
//check for boundary condition and update
if(lnl[tid]==1){
for(int spd=1;spd<15;spd++){
f_tmp=3.0*(ex[spd]*(-ux)+ey[spd]*(u_bc-uy)+ez[spd]*(-uz));
fIns[threadIdx.y][threadIdx.x][spd]+=w[spd]*rho*f_tmp;
}
ux=0.; uy=u_bc;uz=0.;
}
if(snl[tid]==1){
ux=0.;uy=0.;uz=0.;
//-- bounce-back here as well..
// 1--2
f_tmp=fIns[threadIdx.y][threadIdx.x][2];
fIns[threadIdx.y][threadIdx.x][2]=fIns[threadIdx.y][threadIdx.x][1];
fIns[threadIdx.y][threadIdx.x][1]=f_tmp;
//3 -- 4
f_tmp=fIns[threadIdx.y][threadIdx.x][4];
fIns[threadIdx.y][threadIdx.x][4]=fIns[threadIdx.y][threadIdx.x][3];
fIns[threadIdx.y][threadIdx.x][3]=f_tmp;
//5 -- 6
f_tmp=fIns[threadIdx.y][threadIdx.x][6];
fIns[threadIdx.y][threadIdx.x][6]=fIns[threadIdx.y][threadIdx.x][5];
fIns[threadIdx.y][threadIdx.x][5]=f_tmp;
//7 -- 14
f_tmp=fIns[threadIdx.y][threadIdx.x][14];
fIns[threadIdx.y][threadIdx.x][14]=fIns[threadIdx.y][threadIdx.x][7];
fIns[threadIdx.y][threadIdx.x][7]=f_tmp;
//8--13
f_tmp=fIns[threadIdx.y][threadIdx.x][13];
fIns[threadIdx.y][threadIdx.x][13]=fIns[threadIdx.y][threadIdx.x][8];
fIns[threadIdx.y][threadIdx.x][8]=f_tmp;
//9--12
f_tmp=fIns[threadIdx.y][threadIdx.x][12];
fIns[threadIdx.y][threadIdx.x][12]=fIns[threadIdx.y][threadIdx.x][9];
fIns[threadIdx.y][threadIdx.x][9]=f_tmp;
//10--11
f_tmp=fIns[threadIdx.y][threadIdx.x][11];
fIns[threadIdx.y][threadIdx.x][11]=fIns[threadIdx.y][threadIdx.x][10];
fIns[threadIdx.y][threadIdx.x][10]=f_tmp;
//do not do relaxation on solid nodes since the result
//is annulled with the bounce-back.
}else{
//not a solid node, relaxation
float cu, fEq;
for(int spd=0;spd<15;spd++){
cu = 3.0*(ex[spd]*ux+ey[spd]*uy+ez[spd]*uz);
fEq=rho*w[spd]*(1.+cu+0.5*(cu*cu)-
(1.5)*(ux*ux+uy*uy+uz*uz));
fIns[threadIdx.y][threadIdx.x][spd]-=
omega*(fIns[threadIdx.y][threadIdx.x][spd]-fEq);
}
}
//now, everybody streams....
int X_t,Y_t,Z_t;
for(int spd=0;spd<15;spd++){
X_t=X+ex[spd];
Y_t=Y+ey[spd];
Z_t=Z+ez[spd];
if(X_t==Nx)
X_t=0;
if(Y_t==Ny)
Y_t=0;
if(Z_t==Nz)
Z_t=0;
if(X_t<0)
X_t=(Nx-1);
if(Y_t<0)
Y_t=(Ny-1);
if(Z_t<0)
Z_t=(Nz-1);
dof=X_t+Y_t*Nx+Z_t*Nx*Ny;
fOut[spd*Nx*Ny*Nz+dof]=fIns[threadIdx.y][threadIdx.x][spd];
}
}//if (X<Nx...
}
void ldc_D3Q15_LBGK_ts_cuda(float * fOut, const float * fIn, const int * snl,
const int * lnl, const float u_bc,
const float omega, const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
dim3 BLOCKS(TPB2D,TPB2D,1);
dim3 GRIDS((Nx+TPB2D-1)/TPB2D,(Ny+TPB2D-1)/TPB2D,Nz);
ldc_D3Q15_LBGK_ts<<<GRIDS,BLOCKS>>>(fOut,fIn,snl,lnl,u_bc,
omega,ex,ey,ez,w,Nx,Ny,Nz);
} | .file "tmpxft_000df1b6_00000000-6_ldc_3D_LBGK_ts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 272(%rsp), %rax
movq %rax, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
leaq 296(%rsp), %rax
movq %rax, 232(%rsp)
leaq 304(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
.globl _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.globl _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, %r12
movq %rcx, %r13
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movq %r8, %r14
movq %r9, %r15
movl 144(%rsp), %ebx
movl 152(%rsp), %ebp
movl $8, 40(%rsp)
movl $8, 44(%rsp)
leal 14(%rbx), %eax
movl %ebx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 52(%rsp)
leal 14(%rbp), %eax
movl %ebp, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl 160(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq %rbp
.cfi_def_cfa_offset 152
pushq %rbx
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %r14, %r8
movss 76(%rsp), %xmm1
movss 72(%rsp), %xmm0
movq %r13, %rcx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
addq $48, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define TPB2D 8
__global__ void ldc_D3Q15_LBGK_ts(float * fOut, const float * fIn,
const int * snl,
const int * lnl, const float u_bc,
const float omega,const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
int X=threadIdx.x+blockIdx.x*blockDim.x;
int Y=threadIdx.y+blockIdx.y*blockDim.y;
int Z=threadIdx.z+blockIdx.z*blockDim.z;
if((X<Nx)&&(Y<Ny)&&(Z<Nz)){
int tid=X+Y*Nx+Z*Nx*Ny;
int dof;
//load fIn data into shared memory
__shared__ float fIns[TPB2D][TPB2D][15];
for(int spd=0;spd<15;spd++){
for(int y=0;y<TPB2D;y++){
for(int x=0;x<TPB2D;x++){
dof=(blockIdx.x*blockDim.x+x)+
(blockIdx.y*blockDim.y+y)*Nx+
(blockIdx.z*blockDim.z)*Nx*Ny;
fIns[y][x][spd]=fIn[spd*(Nx*Ny*Nz)+dof];
}
}
}
//compute density and velocity
float rho=0.; float ux=0.; float uy=0.; float uz=0.; float f_tmp;
for(int spd=0;spd<15;spd++){
f_tmp=fIns[threadIdx.y][threadIdx.x][spd];
rho+=f_tmp;
ux+=f_tmp*ex[spd];
uy+=f_tmp*ey[spd];
uz+=f_tmp*ez[spd];
}
ux/=rho; uy/=rho; uz/=rho;
//check for boundary condition and update
if(lnl[tid]==1){
for(int spd=1;spd<15;spd++){
f_tmp=3.0*(ex[spd]*(-ux)+ey[spd]*(u_bc-uy)+ez[spd]*(-uz));
fIns[threadIdx.y][threadIdx.x][spd]+=w[spd]*rho*f_tmp;
}
ux=0.; uy=u_bc;uz=0.;
}
if(snl[tid]==1){
ux=0.;uy=0.;uz=0.;
//-- bounce-back here as well..
// 1--2
f_tmp=fIns[threadIdx.y][threadIdx.x][2];
fIns[threadIdx.y][threadIdx.x][2]=fIns[threadIdx.y][threadIdx.x][1];
fIns[threadIdx.y][threadIdx.x][1]=f_tmp;
//3 -- 4
f_tmp=fIns[threadIdx.y][threadIdx.x][4];
fIns[threadIdx.y][threadIdx.x][4]=fIns[threadIdx.y][threadIdx.x][3];
fIns[threadIdx.y][threadIdx.x][3]=f_tmp;
//5 -- 6
f_tmp=fIns[threadIdx.y][threadIdx.x][6];
fIns[threadIdx.y][threadIdx.x][6]=fIns[threadIdx.y][threadIdx.x][5];
fIns[threadIdx.y][threadIdx.x][5]=f_tmp;
//7 -- 14
f_tmp=fIns[threadIdx.y][threadIdx.x][14];
fIns[threadIdx.y][threadIdx.x][14]=fIns[threadIdx.y][threadIdx.x][7];
fIns[threadIdx.y][threadIdx.x][7]=f_tmp;
//8--13
f_tmp=fIns[threadIdx.y][threadIdx.x][13];
fIns[threadIdx.y][threadIdx.x][13]=fIns[threadIdx.y][threadIdx.x][8];
fIns[threadIdx.y][threadIdx.x][8]=f_tmp;
//9--12
f_tmp=fIns[threadIdx.y][threadIdx.x][12];
fIns[threadIdx.y][threadIdx.x][12]=fIns[threadIdx.y][threadIdx.x][9];
fIns[threadIdx.y][threadIdx.x][9]=f_tmp;
//10--11
f_tmp=fIns[threadIdx.y][threadIdx.x][11];
fIns[threadIdx.y][threadIdx.x][11]=fIns[threadIdx.y][threadIdx.x][10];
fIns[threadIdx.y][threadIdx.x][10]=f_tmp;
//do not do relaxation on solid nodes since the result
//is annulled with the bounce-back.
}else{
//not a solid node, relaxation
float cu, fEq;
for(int spd=0;spd<15;spd++){
cu = 3.0*(ex[spd]*ux+ey[spd]*uy+ez[spd]*uz);
fEq=rho*w[spd]*(1.+cu+0.5*(cu*cu)-
(1.5)*(ux*ux+uy*uy+uz*uz));
fIns[threadIdx.y][threadIdx.x][spd]-=
omega*(fIns[threadIdx.y][threadIdx.x][spd]-fEq);
}
}
//now, everybody streams....
int X_t,Y_t,Z_t;
for(int spd=0;spd<15;spd++){
X_t=X+ex[spd];
Y_t=Y+ey[spd];
Z_t=Z+ez[spd];
if(X_t==Nx)
X_t=0;
if(Y_t==Ny)
Y_t=0;
if(Z_t==Nz)
Z_t=0;
if(X_t<0)
X_t=(Nx-1);
if(Y_t<0)
Y_t=(Ny-1);
if(Z_t<0)
Z_t=(Nz-1);
dof=X_t+Y_t*Nx+Z_t*Nx*Ny;
fOut[spd*Nx*Ny*Nz+dof]=fIns[threadIdx.y][threadIdx.x][spd];
}
}//if (X<Nx...
}
void ldc_D3Q15_LBGK_ts_cuda(float * fOut, const float * fIn, const int * snl,
const int * lnl, const float u_bc,
const float omega, const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
dim3 BLOCKS(TPB2D,TPB2D,1);
dim3 GRIDS((Nx+TPB2D-1)/TPB2D,(Ny+TPB2D-1)/TPB2D,Nz);
ldc_D3Q15_LBGK_ts<<<GRIDS,BLOCKS>>>(fOut,fIn,snl,lnl,u_bc,
omega,ex,ey,ez,w,Nx,Ny,Nz);
} | #include <hip/hip_runtime.h>
#define TPB2D 8
__global__ void ldc_D3Q15_LBGK_ts(float * fOut, const float * fIn,
const int * snl,
const int * lnl, const float u_bc,
const float omega,const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
int X=threadIdx.x+blockIdx.x*blockDim.x;
int Y=threadIdx.y+blockIdx.y*blockDim.y;
int Z=threadIdx.z+blockIdx.z*blockDim.z;
if((X<Nx)&&(Y<Ny)&&(Z<Nz)){
int tid=X+Y*Nx+Z*Nx*Ny;
int dof;
//load fIn data into shared memory
__shared__ float fIns[TPB2D][TPB2D][15];
for(int spd=0;spd<15;spd++){
for(int y=0;y<TPB2D;y++){
for(int x=0;x<TPB2D;x++){
dof=(blockIdx.x*blockDim.x+x)+
(blockIdx.y*blockDim.y+y)*Nx+
(blockIdx.z*blockDim.z)*Nx*Ny;
fIns[y][x][spd]=fIn[spd*(Nx*Ny*Nz)+dof];
}
}
}
//compute density and velocity
float rho=0.; float ux=0.; float uy=0.; float uz=0.; float f_tmp;
for(int spd=0;spd<15;spd++){
f_tmp=fIns[threadIdx.y][threadIdx.x][spd];
rho+=f_tmp;
ux+=f_tmp*ex[spd];
uy+=f_tmp*ey[spd];
uz+=f_tmp*ez[spd];
}
ux/=rho; uy/=rho; uz/=rho;
//check for boundary condition and update
if(lnl[tid]==1){
for(int spd=1;spd<15;spd++){
f_tmp=3.0*(ex[spd]*(-ux)+ey[spd]*(u_bc-uy)+ez[spd]*(-uz));
fIns[threadIdx.y][threadIdx.x][spd]+=w[spd]*rho*f_tmp;
}
ux=0.; uy=u_bc;uz=0.;
}
if(snl[tid]==1){
ux=0.;uy=0.;uz=0.;
//-- bounce-back here as well..
// 1--2
f_tmp=fIns[threadIdx.y][threadIdx.x][2];
fIns[threadIdx.y][threadIdx.x][2]=fIns[threadIdx.y][threadIdx.x][1];
fIns[threadIdx.y][threadIdx.x][1]=f_tmp;
//3 -- 4
f_tmp=fIns[threadIdx.y][threadIdx.x][4];
fIns[threadIdx.y][threadIdx.x][4]=fIns[threadIdx.y][threadIdx.x][3];
fIns[threadIdx.y][threadIdx.x][3]=f_tmp;
//5 -- 6
f_tmp=fIns[threadIdx.y][threadIdx.x][6];
fIns[threadIdx.y][threadIdx.x][6]=fIns[threadIdx.y][threadIdx.x][5];
fIns[threadIdx.y][threadIdx.x][5]=f_tmp;
//7 -- 14
f_tmp=fIns[threadIdx.y][threadIdx.x][14];
fIns[threadIdx.y][threadIdx.x][14]=fIns[threadIdx.y][threadIdx.x][7];
fIns[threadIdx.y][threadIdx.x][7]=f_tmp;
//8--13
f_tmp=fIns[threadIdx.y][threadIdx.x][13];
fIns[threadIdx.y][threadIdx.x][13]=fIns[threadIdx.y][threadIdx.x][8];
fIns[threadIdx.y][threadIdx.x][8]=f_tmp;
//9--12
f_tmp=fIns[threadIdx.y][threadIdx.x][12];
fIns[threadIdx.y][threadIdx.x][12]=fIns[threadIdx.y][threadIdx.x][9];
fIns[threadIdx.y][threadIdx.x][9]=f_tmp;
//10--11
f_tmp=fIns[threadIdx.y][threadIdx.x][11];
fIns[threadIdx.y][threadIdx.x][11]=fIns[threadIdx.y][threadIdx.x][10];
fIns[threadIdx.y][threadIdx.x][10]=f_tmp;
//do not do relaxation on solid nodes since the result
//is annulled with the bounce-back.
}else{
//not a solid node, relaxation
float cu, fEq;
for(int spd=0;spd<15;spd++){
cu = 3.0*(ex[spd]*ux+ey[spd]*uy+ez[spd]*uz);
fEq=rho*w[spd]*(1.+cu+0.5*(cu*cu)-
(1.5)*(ux*ux+uy*uy+uz*uz));
fIns[threadIdx.y][threadIdx.x][spd]-=
omega*(fIns[threadIdx.y][threadIdx.x][spd]-fEq);
}
}
//now, everybody streams....
int X_t,Y_t,Z_t;
for(int spd=0;spd<15;spd++){
X_t=X+ex[spd];
Y_t=Y+ey[spd];
Z_t=Z+ez[spd];
if(X_t==Nx)
X_t=0;
if(Y_t==Ny)
Y_t=0;
if(Z_t==Nz)
Z_t=0;
if(X_t<0)
X_t=(Nx-1);
if(Y_t<0)
Y_t=(Ny-1);
if(Z_t<0)
Z_t=(Nz-1);
dof=X_t+Y_t*Nx+Z_t*Nx*Ny;
fOut[spd*Nx*Ny*Nz+dof]=fIns[threadIdx.y][threadIdx.x][spd];
}
}//if (X<Nx...
}
void ldc_D3Q15_LBGK_ts_cuda(float * fOut, const float * fIn, const int * snl,
const int * lnl, const float u_bc,
const float omega, const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
dim3 BLOCKS(TPB2D,TPB2D,1);
dim3 GRIDS((Nx+TPB2D-1)/TPB2D,(Ny+TPB2D-1)/TPB2D,Nz);
ldc_D3Q15_LBGK_ts<<<GRIDS,BLOCKS>>>(fOut,fIn,snl,lnl,u_bc,
omega,ex,ey,ez,w,Nx,Ny,Nz);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define TPB2D 8
__global__ void ldc_D3Q15_LBGK_ts(float * fOut, const float * fIn,
const int * snl,
const int * lnl, const float u_bc,
const float omega,const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
int X=threadIdx.x+blockIdx.x*blockDim.x;
int Y=threadIdx.y+blockIdx.y*blockDim.y;
int Z=threadIdx.z+blockIdx.z*blockDim.z;
if((X<Nx)&&(Y<Ny)&&(Z<Nz)){
int tid=X+Y*Nx+Z*Nx*Ny;
int dof;
//load fIn data into shared memory
__shared__ float fIns[TPB2D][TPB2D][15];
for(int spd=0;spd<15;spd++){
for(int y=0;y<TPB2D;y++){
for(int x=0;x<TPB2D;x++){
dof=(blockIdx.x*blockDim.x+x)+
(blockIdx.y*blockDim.y+y)*Nx+
(blockIdx.z*blockDim.z)*Nx*Ny;
fIns[y][x][spd]=fIn[spd*(Nx*Ny*Nz)+dof];
}
}
}
//compute density and velocity
float rho=0.; float ux=0.; float uy=0.; float uz=0.; float f_tmp;
for(int spd=0;spd<15;spd++){
f_tmp=fIns[threadIdx.y][threadIdx.x][spd];
rho+=f_tmp;
ux+=f_tmp*ex[spd];
uy+=f_tmp*ey[spd];
uz+=f_tmp*ez[spd];
}
ux/=rho; uy/=rho; uz/=rho;
//check for boundary condition and update
if(lnl[tid]==1){
for(int spd=1;spd<15;spd++){
f_tmp=3.0*(ex[spd]*(-ux)+ey[spd]*(u_bc-uy)+ez[spd]*(-uz));
fIns[threadIdx.y][threadIdx.x][spd]+=w[spd]*rho*f_tmp;
}
ux=0.; uy=u_bc;uz=0.;
}
if(snl[tid]==1){
ux=0.;uy=0.;uz=0.;
//-- bounce-back here as well..
// 1--2
f_tmp=fIns[threadIdx.y][threadIdx.x][2];
fIns[threadIdx.y][threadIdx.x][2]=fIns[threadIdx.y][threadIdx.x][1];
fIns[threadIdx.y][threadIdx.x][1]=f_tmp;
//3 -- 4
f_tmp=fIns[threadIdx.y][threadIdx.x][4];
fIns[threadIdx.y][threadIdx.x][4]=fIns[threadIdx.y][threadIdx.x][3];
fIns[threadIdx.y][threadIdx.x][3]=f_tmp;
//5 -- 6
f_tmp=fIns[threadIdx.y][threadIdx.x][6];
fIns[threadIdx.y][threadIdx.x][6]=fIns[threadIdx.y][threadIdx.x][5];
fIns[threadIdx.y][threadIdx.x][5]=f_tmp;
//7 -- 14
f_tmp=fIns[threadIdx.y][threadIdx.x][14];
fIns[threadIdx.y][threadIdx.x][14]=fIns[threadIdx.y][threadIdx.x][7];
fIns[threadIdx.y][threadIdx.x][7]=f_tmp;
//8--13
f_tmp=fIns[threadIdx.y][threadIdx.x][13];
fIns[threadIdx.y][threadIdx.x][13]=fIns[threadIdx.y][threadIdx.x][8];
fIns[threadIdx.y][threadIdx.x][8]=f_tmp;
//9--12
f_tmp=fIns[threadIdx.y][threadIdx.x][12];
fIns[threadIdx.y][threadIdx.x][12]=fIns[threadIdx.y][threadIdx.x][9];
fIns[threadIdx.y][threadIdx.x][9]=f_tmp;
//10--11
f_tmp=fIns[threadIdx.y][threadIdx.x][11];
fIns[threadIdx.y][threadIdx.x][11]=fIns[threadIdx.y][threadIdx.x][10];
fIns[threadIdx.y][threadIdx.x][10]=f_tmp;
//do not do relaxation on solid nodes since the result
//is annulled with the bounce-back.
}else{
//not a solid node, relaxation
float cu, fEq;
for(int spd=0;spd<15;spd++){
cu = 3.0*(ex[spd]*ux+ey[spd]*uy+ez[spd]*uz);
fEq=rho*w[spd]*(1.+cu+0.5*(cu*cu)-
(1.5)*(ux*ux+uy*uy+uz*uz));
fIns[threadIdx.y][threadIdx.x][spd]-=
omega*(fIns[threadIdx.y][threadIdx.x][spd]-fEq);
}
}
//now, everybody streams....
int X_t,Y_t,Z_t;
for(int spd=0;spd<15;spd++){
X_t=X+ex[spd];
Y_t=Y+ey[spd];
Z_t=Z+ez[spd];
if(X_t==Nx)
X_t=0;
if(Y_t==Ny)
Y_t=0;
if(Z_t==Nz)
Z_t=0;
if(X_t<0)
X_t=(Nx-1);
if(Y_t<0)
Y_t=(Ny-1);
if(Z_t<0)
Z_t=(Nz-1);
dof=X_t+Y_t*Nx+Z_t*Nx*Ny;
fOut[spd*Nx*Ny*Nz+dof]=fIns[threadIdx.y][threadIdx.x][spd];
}
}//if (X<Nx...
}
void ldc_D3Q15_LBGK_ts_cuda(float * fOut, const float * fIn, const int * snl,
const int * lnl, const float u_bc,
const float omega, const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
dim3 BLOCKS(TPB2D,TPB2D,1);
dim3 GRIDS((Nx+TPB2D-1)/TPB2D,(Ny+TPB2D-1)/TPB2D,Nz);
ldc_D3Q15_LBGK_ts<<<GRIDS,BLOCKS>>>(fOut,fIn,snl,lnl,u_bc,
omega,ex,ey,ez,w,Nx,Ny,Nz);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.globl _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 8
.type _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii,@function
_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x64
s_load_b64 s[8:9], s[0:1], 0x48
s_load_b32 s16, s[0:1], 0x50
v_bfe_u32 v2, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_and_b32 s4, s3, 0xffff
s_mul_i32 s13, s13, s5
s_mul_i32 s14, s14, s2
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_add_nc_u32_e32 v2, s13, v6
v_add_nc_u32_e32 v1, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_cmp_gt_i32_e64 s2, s9, v1
v_cmp_gt_i32_e64 s3, s16, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s5, s15, s9
s_mul_i32 s7, s16, s9
s_mul_i32 s4, s5, s4
s_mul_i32 s7, s7, s8
s_add_i32 s4, s4, s14
s_mov_b32 s10, 0
s_mul_i32 s4, s8, s4
s_mov_b32 s11, 0
s_add_i32 s6, s4, s13
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, s6
s_mov_b32 s13, s10
s_mov_b32 s14, 0
.p2align 6
.LBB0_3:
s_mov_b32 s15, 0
s_mov_b32 s4, s12
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[18:19], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s18, s2, s18
s_addc_u32 s19, s3, s19
s_add_i32 s17, s13, s15
s_load_b32 s5, s[18:19], 0x0
v_mov_b32_e32 v3, s17
s_add_i32 s15, s15, 60
s_add_i32 s4, s4, 1
s_cmpk_eq_i32 s15, 0x1e0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v4, s5
ds_store_b32 v3, v4
s_cbranch_scc0 .LBB0_4
s_add_i32 s14, s14, 1
s_addk_i32 s13, 0x1e0
s_add_i32 s12, s12, s8
s_cmp_eq_u32 s14, 8
s_cbranch_scc0 .LBB0_3
s_add_i32 s11, s11, 1
s_add_i32 s10, s10, 4
s_add_i32 s6, s6, s7
s_cmp_lg_u32 s11, 15
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[10:11], s[0:1], 0x38
v_mul_u32_u24_e32 v3, 60, v6
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u32_u24 v3, v5, 0x1e0, v3
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_8:
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s4, s2
s_addc_u32 s13, s5, s3
s_add_u32 s14, s6, s2
s_addc_u32 s15, s7, s3
s_load_b32 s17, s[12:13], 0x0
s_add_u32 s12, s10, s2
s_addc_u32 s13, s11, s3
ds_load_b32 v4, v3
s_load_b32 s14, s[14:15], 0x0
s_load_b32 s12, s[12:13], 0x0
v_add_nc_u32_e32 v3, 4, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 60
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v10, s14, v4
v_add_f32_e32 v7, v7, v4
v_fmac_f32_e32 v9, s17, v4
v_fmac_f32_e32 v8, s12, v4
s_cbranch_scc0 .LBB0_8
v_mad_u64_u32 v[11:12], null, v0, s9, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0x40
v_div_scale_f32 v13, null, v7, v7, v10
v_div_scale_f32 v15, null, v7, v7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v11, s8, v[2:3]
v_rcp_f32_e32 v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v17, v15
s_mov_b32 s14, exec_lo
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v19, -v13, v16, 1.0
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_fma_f32 v20, -v15, v17, 1.0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v20, v17
v_div_scale_f32 v20, s3, v8, v7, v8
global_load_b32 v11, v[11:12], off
v_div_scale_f32 v12, null, v7, v7, v9
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v12, v14, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v18, v14
v_div_scale_f32 v18, vcc_lo, v9, v7, v9
v_fmac_f32_e32 v16, v19, v16
v_div_scale_f32 v19, s2, v10, v7, v10
v_dual_mul_f32 v21, v18, v14 :: v_dual_mul_f32 v22, v19, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v23, -v12, v21, v18
v_mul_f32_e32 v24, v20, v17
v_fma_f32 v25, -v13, v22, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v21, v23, v14
v_fma_f32 v23, -v15, v24, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v22, v25, v16
v_fma_f32 v12, -v12, v21, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v24, v23, v17
v_fma_f32 v13, -v13, v22, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v12, v12, v14, v21
v_fma_f32 v14, -v15, v24, v20
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f32 v13, v13, v16, v22
s_mov_b32 vcc_lo, s3
v_div_fixup_f32 v9, v12, v7, v9
v_div_fmas_f32 v14, v14, v17, v24
v_div_fixup_f32 v10, v13, v7, v10
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v8, v14, v7, v8
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v11
s_cbranch_execz .LBB0_13
s_load_b32 s15, s[0:1], 0x20
v_mul_u32_u24_e32 v11, 0x1e0, v5
v_mul_u32_u24_e32 v12, 60, v6
s_mov_b64 s[2:3], 4
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v11, v11, v12, 4
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v10, s15, v10
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_11:
s_add_u32 s18, s4, s2
s_addc_u32 s19, s5, s3
ds_load_b32 v12, v11
s_load_b32 s17, s[18:19], 0x0
s_add_u32 s18, s6, s2
s_addc_u32 s19, s7, s3
s_load_b32 s22, s[18:19], 0x0
s_add_u32 s18, s10, s2
s_addc_u32 s19, s11, s3
s_add_u32 s20, s12, s2
s_addc_u32 s21, s13, s3
s_load_b32 s18, s[18:19], 0x0
s_load_b32 s19, s[20:21], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 60
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v13, s17, v9 :: v_dual_mul_f32 v14, s19, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v10, s22, -v13
v_fma_f32 v13, -v8, s18, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, 0x40400000, v13
v_fmac_f32_e32 v12, v14, v13
ds_store_b32 v11, v12
v_add_nc_u32_e32 v11, 4, v11
s_cbranch_scc1 .LBB0_11
s_set_inst_prefetch_distance 0x2
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v10, s15
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s14
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 1, v3
s_xor_b32 s14, exec_lo, s2
s_cbranch_execz .LBB0_16
v_mul_f32_e32 v3, v10, v10
s_load_b32 s15, s[0:1], 0x24
v_mul_u32_u24_e32 v11, 60, v6
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, v9, v9
v_mad_u32_u24 v11, v5, 0x1e0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v8, v8
v_cvt_f64_f32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0x3ff80000
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
s_add_u32 s18, s4, s2
s_addc_u32 s19, s5, s3
s_add_u32 s20, s6, s2
s_addc_u32 s21, s7, s3
s_load_b32 s17, s[20:21], 0x0
s_load_b32 s20, s[18:19], 0x0
s_add_u32 s18, s10, s2
s_addc_u32 s19, s11, s3
s_load_b32 s18, s[18:19], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v12, s17, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, s20, v9
v_fmac_f32_e32 v12, s18, v8
s_add_u32 s18, s12, s2
s_addc_u32 s19, s13, s3
s_add_u32 s2, s2, 4
s_load_b32 s17, s[18:19], 0x0
v_mul_f32_e32 v14, 0x40400000, v12
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 60
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[12:13], v14
v_mul_f32_e32 v14, v14, v14
v_cvt_f64_f32_e32 v[14:15], v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], 1.0
v_fma_f64 v[12:13], v[14:15], 0.5, v[12:13]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v14, s17, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[14:15], v14
v_add_f64 v[12:13], v[12:13], -v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], v[14:15]
v_cvt_f32_f64_e32 v12, v[12:13]
ds_load_b32 v13, v11
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v12, v13, v12
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v12, -v12, s15, v13
ds_store_b32 v11, v12
v_add_nc_u32_e32 v11, 4, v11
s_cbranch_scc1 .LBB0_15
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_and_not1_saveexec_b32 s2, s14
s_cbranch_execz .LBB0_18
v_mul_u32_u24_e32 v3, 60, v6
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v19, v5, 0x1e0, v3
ds_load_2addr_b32 v[3:4], v19 offset0:1 offset1:2
ds_load_2addr_b32 v[7:8], v19 offset0:3 offset1:4
ds_load_2addr_b32 v[9:10], v19 offset0:5 offset1:6
ds_load_2addr_b32 v[11:12], v19 offset0:13 offset1:14
ds_load_2addr_b32 v[13:14], v19 offset0:7 offset1:8
ds_load_2addr_b32 v[15:16], v19 offset0:9 offset1:10
ds_load_2addr_b32 v[17:18], v19 offset0:11 offset1:12
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v4, v3 offset0:1 offset1:2
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v8, v7 offset0:3 offset1:4
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v10, v9 offset0:5 offset1:6
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v12, v11 offset0:7 offset1:8
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v14, v13 offset0:13 offset1:14
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v16, v15 offset0:11 offset1:12
s_waitcnt lgkmcnt(6)
ds_store_2addr_b32 v19, v18, v17 offset0:9 offset1:10
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_u32_u24_e32 v3, 60, v6
v_cvt_f32_i32_e32 v2, v2
v_cvt_f32_i32_e32 v1, v1
v_cvt_f32_i32_e32 v0, v0
v_mov_b32_e32 v4, 0
v_mad_u32_u24 v3, v5, 0x1e0, v3
s_add_i32 s1, s8, -1
s_add_i32 s14, s9, -1
s_add_i32 s15, s16, -1
s_mov_b64 s[12:13], 0
s_mov_b32 s17, 0
.LBB0_19:
s_add_u32 s18, s4, s12
s_addc_u32 s19, s5, s13
s_add_u32 s20, s6, s12
global_load_b32 v5, v4, s[18:19]
s_addc_u32 s21, s7, s13
s_add_u32 s18, s10, s12
s_addc_u32 s19, s11, s13
s_clause 0x1
global_load_b32 v6, v4, s[20:21]
global_load_b32 v7, v4, s[18:19]
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(1)
v_dual_add_f32 v5, v5, v2 :: v_dual_add_f32 v6, v6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v5, v5
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, s8, v5
s_waitcnt vmcnt(0)
v_dual_add_f32 v7, v7, v0 :: v_dual_cndmask_b32 v8, 0, v5
v_cvt_i32_f32_e32 v7, v7
v_cmp_ne_u32_e32 vcc_lo, s9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, s16, v7
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cndmask_b32_e64 v5, 0, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0, v5
v_cndmask_b32_e64 v7, v5, s15, vcc_lo
v_add_nc_u32_e32 v9, s17, v7
v_cmp_gt_i32_e32 vcc_lo, 0, v6
s_add_i32 s17, s17, s16
s_cmp_lg_u32 s12, 60
v_cndmask_b32_e64 v5, v6, s14, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v9, s9, v[5:6]
v_cndmask_b32_e64 v5, v8, s1, vcc_lo
ds_load_b32 v9, v3
v_add_nc_u32_e32 v3, 4, v3
v_mad_u64_u32 v[7:8], null, v6, s8, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[7:8]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[5:6], v9, off
s_cbranch_scc1 .LBB0_19
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.amdhsa_group_segment_fixed_size 3840
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, .Lfunc_end0-_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3840
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define TPB2D 8
__global__ void ldc_D3Q15_LBGK_ts(float * fOut, const float * fIn,
const int * snl,
const int * lnl, const float u_bc,
const float omega,const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
int X=threadIdx.x+blockIdx.x*blockDim.x;
int Y=threadIdx.y+blockIdx.y*blockDim.y;
int Z=threadIdx.z+blockIdx.z*blockDim.z;
if((X<Nx)&&(Y<Ny)&&(Z<Nz)){
int tid=X+Y*Nx+Z*Nx*Ny;
int dof;
//load fIn data into shared memory
__shared__ float fIns[TPB2D][TPB2D][15];
for(int spd=0;spd<15;spd++){
for(int y=0;y<TPB2D;y++){
for(int x=0;x<TPB2D;x++){
dof=(blockIdx.x*blockDim.x+x)+
(blockIdx.y*blockDim.y+y)*Nx+
(blockIdx.z*blockDim.z)*Nx*Ny;
fIns[y][x][spd]=fIn[spd*(Nx*Ny*Nz)+dof];
}
}
}
//compute density and velocity
float rho=0.; float ux=0.; float uy=0.; float uz=0.; float f_tmp;
for(int spd=0;spd<15;spd++){
f_tmp=fIns[threadIdx.y][threadIdx.x][spd];
rho+=f_tmp;
ux+=f_tmp*ex[spd];
uy+=f_tmp*ey[spd];
uz+=f_tmp*ez[spd];
}
ux/=rho; uy/=rho; uz/=rho;
//check for boundary condition and update
if(lnl[tid]==1){
for(int spd=1;spd<15;spd++){
f_tmp=3.0*(ex[spd]*(-ux)+ey[spd]*(u_bc-uy)+ez[spd]*(-uz));
fIns[threadIdx.y][threadIdx.x][spd]+=w[spd]*rho*f_tmp;
}
ux=0.; uy=u_bc;uz=0.;
}
if(snl[tid]==1){
ux=0.;uy=0.;uz=0.;
//-- bounce-back here as well..
// 1--2
f_tmp=fIns[threadIdx.y][threadIdx.x][2];
fIns[threadIdx.y][threadIdx.x][2]=fIns[threadIdx.y][threadIdx.x][1];
fIns[threadIdx.y][threadIdx.x][1]=f_tmp;
//3 -- 4
f_tmp=fIns[threadIdx.y][threadIdx.x][4];
fIns[threadIdx.y][threadIdx.x][4]=fIns[threadIdx.y][threadIdx.x][3];
fIns[threadIdx.y][threadIdx.x][3]=f_tmp;
//5 -- 6
f_tmp=fIns[threadIdx.y][threadIdx.x][6];
fIns[threadIdx.y][threadIdx.x][6]=fIns[threadIdx.y][threadIdx.x][5];
fIns[threadIdx.y][threadIdx.x][5]=f_tmp;
//7 -- 14
f_tmp=fIns[threadIdx.y][threadIdx.x][14];
fIns[threadIdx.y][threadIdx.x][14]=fIns[threadIdx.y][threadIdx.x][7];
fIns[threadIdx.y][threadIdx.x][7]=f_tmp;
//8--13
f_tmp=fIns[threadIdx.y][threadIdx.x][13];
fIns[threadIdx.y][threadIdx.x][13]=fIns[threadIdx.y][threadIdx.x][8];
fIns[threadIdx.y][threadIdx.x][8]=f_tmp;
//9--12
f_tmp=fIns[threadIdx.y][threadIdx.x][12];
fIns[threadIdx.y][threadIdx.x][12]=fIns[threadIdx.y][threadIdx.x][9];
fIns[threadIdx.y][threadIdx.x][9]=f_tmp;
//10--11
f_tmp=fIns[threadIdx.y][threadIdx.x][11];
fIns[threadIdx.y][threadIdx.x][11]=fIns[threadIdx.y][threadIdx.x][10];
fIns[threadIdx.y][threadIdx.x][10]=f_tmp;
//do not do relaxation on solid nodes since the result
//is annulled with the bounce-back.
}else{
//not a solid node, relaxation
float cu, fEq;
for(int spd=0;spd<15;spd++){
cu = 3.0*(ex[spd]*ux+ey[spd]*uy+ez[spd]*uz);
fEq=rho*w[spd]*(1.+cu+0.5*(cu*cu)-
(1.5)*(ux*ux+uy*uy+uz*uz));
fIns[threadIdx.y][threadIdx.x][spd]-=
omega*(fIns[threadIdx.y][threadIdx.x][spd]-fEq);
}
}
//now, everybody streams....
int X_t,Y_t,Z_t;
for(int spd=0;spd<15;spd++){
X_t=X+ex[spd];
Y_t=Y+ey[spd];
Z_t=Z+ez[spd];
if(X_t==Nx)
X_t=0;
if(Y_t==Ny)
Y_t=0;
if(Z_t==Nz)
Z_t=0;
if(X_t<0)
X_t=(Nx-1);
if(Y_t<0)
Y_t=(Ny-1);
if(Z_t<0)
Z_t=(Nz-1);
dof=X_t+Y_t*Nx+Z_t*Nx*Ny;
fOut[spd*Nx*Ny*Nz+dof]=fIns[threadIdx.y][threadIdx.x][spd];
}
}//if (X<Nx...
}
void ldc_D3Q15_LBGK_ts_cuda(float * fOut, const float * fIn, const int * snl,
const int * lnl, const float u_bc,
const float omega, const float * ex,
const float * ey, const float * ez,
const float * w, const int Nx,
const int Ny, const int Nz){
dim3 BLOCKS(TPB2D,TPB2D,1);
dim3 GRIDS((Nx+TPB2D-1)/TPB2D,(Ny+TPB2D-1)/TPB2D,Nz);
ldc_D3Q15_LBGK_ts<<<GRIDS,BLOCKS>>>(fOut,fIn,snl,lnl,u_bc,
omega,ex,ey,ez,w,Nx,Ny,Nz);
} | .text
.file "ldc_3D_LBGK_ts.hip"
.globl _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii # -- Begin function _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 4, 0x90
.type _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii,@function
_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii: # @_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, .Lfunc_end0-_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_endproc
# -- End function
.globl _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii # -- Begin function _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 4, 0x90
.type _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii,@function
_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii: # @_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 56(%rsp) # 8-byte Spill
movq %r8, 48(%rsp) # 8-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rcx, 40(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 360(%rsp), %r14d
movl 352(%rsp), %r15d
leal 7(%r15), %eax
leal 14(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%r14), %eax
leal 14(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
movl 368(%rsp), %ebx
sarl $3, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl %ebx, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 344(%rsp), %rax
movq 336(%rsp), %rcx
movq %rbp, 168(%rsp)
movq %r13, 160(%rsp)
movq %r12, 152(%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, 144(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rdx, 136(%rsp)
movq 56(%rsp), %rdx # 8-byte Reload
movq %rdx, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rax, 112(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebx, 20(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rax
movq %rax, 224(%rsp)
leaq 128(%rsp), %rax
movq %rax, 232(%rsp)
leaq 120(%rsp), %rax
movq %rax, 240(%rsp)
leaq 112(%rsp), %rax
movq %rax, 248(%rsp)
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, .Lfunc_end1-_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii,@object # @_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.section .rodata,"a",@progbits
.globl _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 3, 0x0
_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.quad _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.size _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df1b6_00000000-6_ldc_3D_LBGK_ts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 272(%rsp), %rax
movq %rax, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
leaq 296(%rsp), %rax
movq %rax, 232(%rsp)
leaq 304(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
.globl _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.globl _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.type _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, @function
_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, %r12
movq %rcx, %r13
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movq %r8, %r14
movq %r9, %r15
movl 144(%rsp), %ebx
movl 152(%rsp), %ebp
movl $8, 40(%rsp)
movl $8, 44(%rsp)
leal 14(%rbx), %eax
movl %ebx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 52(%rsp)
leal 14(%rbp), %eax
movl %ebp, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl 160(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq %rbp
.cfi_def_cfa_offset 152
pushq %rbx
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %r14, %r8
movss 76(%rsp), %xmm1
movss 72(%rsp), %xmm0
movq %r13, %rcx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z63__device_stub__Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iiiPfPKfPKiS3_ffS1_S1_S1_S1_iii
addq $48, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, .-_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ldc_3D_LBGK_ts.hip"
.globl _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii # -- Begin function _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 4, 0x90
.type _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii,@function
_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii: # @_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, .Lfunc_end0-_Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_endproc
# -- End function
.globl _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii # -- Begin function _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 4, 0x90
.type _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii,@function
_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii: # @_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 56(%rsp) # 8-byte Spill
movq %r8, 48(%rsp) # 8-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rcx, 40(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 360(%rsp), %r14d
movl 352(%rsp), %r15d
leal 7(%r15), %eax
leal 14(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%r14), %eax
leal 14(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
movl 368(%rsp), %ebx
sarl $3, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl %ebx, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 344(%rsp), %rax
movq 336(%rsp), %rcx
movq %rbp, 168(%rsp)
movq %r13, 160(%rsp)
movq %r12, 152(%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, 144(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rdx, 136(%rsp)
movq 56(%rsp), %rdx # 8-byte Reload
movq %rdx, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rax, 112(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebx, 20(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rax
movq %rax, 224(%rsp)
leaq 128(%rsp), %rax
movq %rax, 232(%rsp)
leaq 120(%rsp), %rax
movq %rax, 240(%rsp)
leaq 112(%rsp), %rax
movq %rax, 248(%rsp)
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii, .Lfunc_end1-_Z22ldc_D3Q15_LBGK_ts_cudaPfPKfPKiS3_ffS1_S1_S1_S1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii,@object # @_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.section .rodata,"a",@progbits
.globl _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.p2align 3, 0x0
_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii:
.quad _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.size _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17ldc_D3Q15_LBGK_tsPfPKfPKiS3_ffS1_S1_S1_S1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} | code for sm_80
Function : _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e280000002700 */
/*0020*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ ISETP.GT.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x001fc80003f04270 */
/*0060*/ ISETP.GT.OR P0, PT, R4, 0x2, P0 ; /* 0x000000020400780c */
/* 0x002fe20000704670 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fd800078e0203 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R4.reuse, 0x6, R5 ; /* 0x0000000604027824 */
/* 0x040fe200078e0205 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD R3, R4, c[0x0][0x188], RZ ; /* 0x0000620004037a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R10, R2, c[0x0][0x1b0], RZ ; /* 0x00006c00020a7a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005027a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fc400078e02ff */
/*0130*/ IMAD R4, R4, 0x6, RZ ; /* 0x0000000604047824 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.WIDE R10, R10, R11, c[0x0][0x1a8] ; /* 0x00006a000a0a7625 */
/* 0x000fc800078e020b */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R12, R0, R8, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x000fca00078e0208 */
/*0170*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea2000c1e1900 */
/*0190*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R0.reuse ; /* 0x000000ffff097224 */
/* 0x100fe200078e0000 */
/*01b0*/ BSSY B0, 0x470 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*01c0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*01e0*/ ISETP.GE.AND P1, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f26270 */
/*01f0*/ @P1 BRA 0x460 ; /* 0x0000026000001947 */
/* 0x000fea0003800000 */
/*0200*/ SHF.R.S32.HI R7, RZ, 0x1f, R9 ; /* 0x0000001fff077819 */
/* 0x000fe40000011409 */
/*0210*/ IADD3 R6, P1, R2, R9, RZ ; /* 0x0000000902067210 */
/* 0x000fc80007f3e0ff */
/*0220*/ LEA.HI.X.SX32 R7, R2, R7, 0x1, P1 ; /* 0x0000000702077211 */
/* 0x000fe400008f0eff */
/*0230*/ LEA R14, P1, R6, c[0x0][0x1a0], 0x3 ; /* 0x00006800060e7a11 */
/* 0x000fc800078218ff */
/*0240*/ LEA.HI.X R15, R6, c[0x0][0x1a4], R7, 0x3, P1 ; /* 0x00006900060f7a11 */
/* 0x000fca00008f1c07 */
/*0250*/ IMAD.WIDE R16, R4.reuse, 0x8, R14 ; /* 0x0000000804107825 */
/* 0x040fe400078e020e */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1b00 */
/*0270*/ IMAD.WIDE R18, R4, 0x8, R16 ; /* 0x0000000804127825 */
/* 0x000fe400078e0210 */
/*0280*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1b00 */
/*0290*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*02a0*/ IMAD.WIDE R6, R5, 0x8, R10 ; /* 0x0000000805067825 */
/* 0x000fc800078e020a */
/*02b0*/ IMAD.WIDE R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fca00078e0208 */
/*02c0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MOV R25, c[0x0][0x188] ; /* 0x0000620000197a02 */
/* 0x000fe40000000f00 */
/*02e0*/ SHF.R.S32.HI R22, RZ, 0x1f, R20 ; /* 0x0000001fff167819 */
/* 0x004fe40000011414 */
/*02f0*/ IADD3 R20, P1, R3, R20, RZ ; /* 0x0000001403147210 */
/* 0x000fc80007f3e0ff */
/*0300*/ LEA.HI.X.SX32 R21, R3, R22, 0x1, P1 ; /* 0x0000001603157211 */
/* 0x000fe400008f0eff */
/*0310*/ LEA R22, P1, R20, c[0x0][0x180], 0x3 ; /* 0x0000600014167a11 */
/* 0x000fc800078218ff */
/*0320*/ LEA.HI.X R23, R20, c[0x0][0x184], R21, 0x3, P1 ; /* 0x0000610014177a11 */
/* 0x000fca00008f1c15 */
/*0330*/ IMAD.WIDE R26, R25.reuse, 0x8, R22 ; /* 0x00000008191a7825 */
/* 0x040fe400078e0216 */
/*0340*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000ee2000c1e1b00 */
/*0360*/ IMAD.WIDE R24, R25, 0x8, R26 ; /* 0x0000000819187825 */
/* 0x000fcc00078e021a */
/*0370*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f22000c1e1b00 */
/*0380*/ DMUL R20, R16, R20 ; /* 0x0000001410147228 */
/* 0x028e8c0000000000 */
/*0390*/ DFMA R20, R14, R22, R20 ; /* 0x000000160e14722b */
/* 0x004f0c0000000014 */
/*03a0*/ DFMA R28, R18, R24, R20 ; /* 0x00000018121c722b */
/* 0x0100640000000014 */
/*03b0*/ IMAD.MOV.U32 R20, RZ, RZ, R6 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0006 */
/*03c0*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fca0000000f00 */
/*03d0*/ STG.E.64 [R20.64], R28 ; /* 0x0000001c14007986 */
/* 0x0021e8000c101b04 */
/*03e0*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f5e0ff */
/*0410*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007f7e0ff */
/*0420*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0430*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40001ffe4ff */
/*0440*/ ISETP.GE.AND P1, PT, R5, R22, PT ; /* 0x000000160500720c */
/* 0x004fda0003f26270 */
/*0450*/ @!P1 BRA 0x2c0 ; /* 0xfffffe6000009947 */
/* 0x001fea000383ffff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ @!P0 BRA 0x150 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} | .file "tmpxft_000a1fd4_00000000-6_computeCovDxdPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
.type _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i, @function
_Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movq %r8, 40(%rsp)
movl %r9d, 48(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 272(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i, .-_Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, @function
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, .-_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 8
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i,@function
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
s_cmp_gt_i32 s14, 2
s_cselect_b32 s2, -1, 0
s_cmp_gt_i32 s15, 5
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s8, s0, 0x58
s_addc_u32 s9, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s13, s20, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_7
s_clause 0x4
s_load_b32 s12, s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s21, s[0:1], 0x50
s_load_b128 s[0:3], s[0:1], 0x40
s_load_b32 s26, s[8:9], 0x0
s_mul_i32 s19, s14, 6
s_mul_i32 s18, s15, s10
s_mul_i32 s22, s10, 6
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s14, s12
s_ashr_i32 s13, s12, 31
s_mul_i32 s8, s11, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_mul_i32 s20, s26, s20
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s8, s16, s8
s_addc_u32 s9, s17, s9
s_lshl_b64 s[16:17], s[12:13], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s11, s8, s16
s_addc_u32 s12, s9, s17
s_add_u32 s13, s11, s16
s_addc_u32 s14, s12, s17
s_add_i32 s15, s19, s15
s_ashr_i32 s19, s18, 31
s_mul_i32 s24, s15, s21
s_lshl_b64 s[16:17], s[18:19], 3
s_ashr_i32 s25, s24, 31
s_add_u32 s15, s0, s16
s_addc_u32 s1, s1, s17
s_ashr_i32 s23, s22, 31
s_mov_b32 s21, 0
s_lshl_b64 s[18:19], s[22:23], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s16, s15, s18
s_addc_u32 s17, s1, s19
s_add_u32 s18, s16, s18
s_addc_u32 s19, s17, s19
s_lshl_b64 s[22:23], s[24:25], 3
s_add_u32 s2, s2, s22
s_addc_u32 s3, s3, s23
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
v_add_nc_u32_e32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_mov_b32 s23, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s15, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s19, v6, vcc_lo
s_clause 0x2
global_load_b64 v[5:6], v[7:8], off
global_load_b64 v[7:8], v[9:10], off
global_load_b64 v[9:10], v[11:12], off
v_ashrrev_i32_e32 v12, 31, v3
v_mov_b32_e32 v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[11:12]
v_lshlrev_b64 v[15:16], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v14, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v15
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v16, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_6:
global_load_b32 v15, v[11:12], off
v_add_nc_u32_e32 v3, 1, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v17, vcc_lo, s11, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s12, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s13, v15
s_clause 0x1
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[19:20], off
v_add_co_ci_u32_e32 v16, vcc_lo, s14, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
global_load_b64 v[15:16], v[15:16], off
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s23, vcc_lo, s23
s_waitcnt vmcnt(2)
v_mul_f64 v[17:18], v[7:8], v[17:18]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[5:6], v[19:20], v[17:18]
s_waitcnt vmcnt(0)
v_fma_f64 v[15:16], v[9:10], v[15:16], v[17:18]
global_store_b64 v[13:14], v[15:16], off
v_add_co_u32 v13, s0, v13, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, 0, v14, s0
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execnz .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, .Lfunc_end0-_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCovDxdPi(int *valid_points, int *starting_voxel_id, int *voxel_id, int valid_points_num, double *inverse_covariance, int voxel_num, double gauss_d1, double gauss_d2, double *point_gradients, double *cov_dxd_pi, int valid_voxel_num)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
int row = blockIdx.y;
int col = blockIdx.z;
if (row < 3 && col < 6) {
double *icov0 = inverse_covariance + row * 3 * voxel_num;
double *icov1 = icov0 + voxel_num;
double *icov2 = icov1 + voxel_num;
double *cov_dxd_pi_tmp = cov_dxd_pi + (row * 6 + col) * valid_voxel_num;
double *pg_tmp0 = point_gradients + col * valid_points_num;
double *pg_tmp1 = pg_tmp0 + 6 * valid_points_num;
double *pg_tmp2 = pg_tmp1 + 6 * valid_points_num;
for (int i = id; i < valid_points_num; i += stride) {
double pg0 = pg_tmp0[i];
double pg1 = pg_tmp1[i];
double pg2 = pg_tmp2[i];
for ( int j = starting_voxel_id[i]; j < starting_voxel_id[i + 1]; j++) {
int vid = voxel_id[j];
cov_dxd_pi_tmp[j] = icov0[vid] * pg0 + icov1[vid] * pg1 + icov2[vid] * pg2;
}
}
}
} | .text
.file "computeCovDxdPi.hip"
.globl _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i # -- Begin function _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 4, 0x90
.type _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i,@function
_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i: # @_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movl %r9d, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i, .Lfunc_end0-_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i,@object # @_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .rodata,"a",@progbits
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 3, 0x0
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
.quad _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e280000002700 */
/*0020*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ ISETP.GT.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x001fc80003f04270 */
/*0060*/ ISETP.GT.OR P0, PT, R4, 0x2, P0 ; /* 0x000000020400780c */
/* 0x002fe20000704670 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fd800078e0203 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R4.reuse, 0x6, R5 ; /* 0x0000000604027824 */
/* 0x040fe200078e0205 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD R3, R4, c[0x0][0x188], RZ ; /* 0x0000620004037a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R10, R2, c[0x0][0x1b0], RZ ; /* 0x00006c00020a7a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005027a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fc400078e02ff */
/*0130*/ IMAD R4, R4, 0x6, RZ ; /* 0x0000000604047824 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.WIDE R10, R10, R11, c[0x0][0x1a8] ; /* 0x00006a000a0a7625 */
/* 0x000fc800078e020b */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R12, R0, R8, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x000fca00078e0208 */
/*0170*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea2000c1e1900 */
/*0190*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R0.reuse ; /* 0x000000ffff097224 */
/* 0x100fe200078e0000 */
/*01b0*/ BSSY B0, 0x470 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*01c0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*01e0*/ ISETP.GE.AND P1, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f26270 */
/*01f0*/ @P1 BRA 0x460 ; /* 0x0000026000001947 */
/* 0x000fea0003800000 */
/*0200*/ SHF.R.S32.HI R7, RZ, 0x1f, R9 ; /* 0x0000001fff077819 */
/* 0x000fe40000011409 */
/*0210*/ IADD3 R6, P1, R2, R9, RZ ; /* 0x0000000902067210 */
/* 0x000fc80007f3e0ff */
/*0220*/ LEA.HI.X.SX32 R7, R2, R7, 0x1, P1 ; /* 0x0000000702077211 */
/* 0x000fe400008f0eff */
/*0230*/ LEA R14, P1, R6, c[0x0][0x1a0], 0x3 ; /* 0x00006800060e7a11 */
/* 0x000fc800078218ff */
/*0240*/ LEA.HI.X R15, R6, c[0x0][0x1a4], R7, 0x3, P1 ; /* 0x00006900060f7a11 */
/* 0x000fca00008f1c07 */
/*0250*/ IMAD.WIDE R16, R4.reuse, 0x8, R14 ; /* 0x0000000804107825 */
/* 0x040fe400078e020e */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1b00 */
/*0270*/ IMAD.WIDE R18, R4, 0x8, R16 ; /* 0x0000000804127825 */
/* 0x000fe400078e0210 */
/*0280*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1b00 */
/*0290*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*02a0*/ IMAD.WIDE R6, R5, 0x8, R10 ; /* 0x0000000805067825 */
/* 0x000fc800078e020a */
/*02b0*/ IMAD.WIDE R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fca00078e0208 */
/*02c0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MOV R25, c[0x0][0x188] ; /* 0x0000620000197a02 */
/* 0x000fe40000000f00 */
/*02e0*/ SHF.R.S32.HI R22, RZ, 0x1f, R20 ; /* 0x0000001fff167819 */
/* 0x004fe40000011414 */
/*02f0*/ IADD3 R20, P1, R3, R20, RZ ; /* 0x0000001403147210 */
/* 0x000fc80007f3e0ff */
/*0300*/ LEA.HI.X.SX32 R21, R3, R22, 0x1, P1 ; /* 0x0000001603157211 */
/* 0x000fe400008f0eff */
/*0310*/ LEA R22, P1, R20, c[0x0][0x180], 0x3 ; /* 0x0000600014167a11 */
/* 0x000fc800078218ff */
/*0320*/ LEA.HI.X R23, R20, c[0x0][0x184], R21, 0x3, P1 ; /* 0x0000610014177a11 */
/* 0x000fca00008f1c15 */
/*0330*/ IMAD.WIDE R26, R25.reuse, 0x8, R22 ; /* 0x00000008191a7825 */
/* 0x040fe400078e0216 */
/*0340*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000ee2000c1e1b00 */
/*0360*/ IMAD.WIDE R24, R25, 0x8, R26 ; /* 0x0000000819187825 */
/* 0x000fcc00078e021a */
/*0370*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f22000c1e1b00 */
/*0380*/ DMUL R20, R16, R20 ; /* 0x0000001410147228 */
/* 0x028e8c0000000000 */
/*0390*/ DFMA R20, R14, R22, R20 ; /* 0x000000160e14722b */
/* 0x004f0c0000000014 */
/*03a0*/ DFMA R28, R18, R24, R20 ; /* 0x00000018121c722b */
/* 0x0100640000000014 */
/*03b0*/ IMAD.MOV.U32 R20, RZ, RZ, R6 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0006 */
/*03c0*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fca0000000f00 */
/*03d0*/ STG.E.64 [R20.64], R28 ; /* 0x0000001c14007986 */
/* 0x0021e8000c101b04 */
/*03e0*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f5e0ff */
/*0410*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007f7e0ff */
/*0420*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0430*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40001ffe4ff */
/*0440*/ ISETP.GE.AND P1, PT, R5, R22, PT ; /* 0x000000160500720c */
/* 0x004fda0003f26270 */
/*0450*/ @!P1 BRA 0x2c0 ; /* 0xfffffe6000009947 */
/* 0x001fea000383ffff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ @!P0 BRA 0x150 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 8
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i,@function
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
s_cmp_gt_i32 s14, 2
s_cselect_b32 s2, -1, 0
s_cmp_gt_i32 s15, 5
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s8, s0, 0x58
s_addc_u32 s9, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s13, s20, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_7
s_clause 0x4
s_load_b32 s12, s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s21, s[0:1], 0x50
s_load_b128 s[0:3], s[0:1], 0x40
s_load_b32 s26, s[8:9], 0x0
s_mul_i32 s19, s14, 6
s_mul_i32 s18, s15, s10
s_mul_i32 s22, s10, 6
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s14, s12
s_ashr_i32 s13, s12, 31
s_mul_i32 s8, s11, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_mul_i32 s20, s26, s20
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s8, s16, s8
s_addc_u32 s9, s17, s9
s_lshl_b64 s[16:17], s[12:13], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s11, s8, s16
s_addc_u32 s12, s9, s17
s_add_u32 s13, s11, s16
s_addc_u32 s14, s12, s17
s_add_i32 s15, s19, s15
s_ashr_i32 s19, s18, 31
s_mul_i32 s24, s15, s21
s_lshl_b64 s[16:17], s[18:19], 3
s_ashr_i32 s25, s24, 31
s_add_u32 s15, s0, s16
s_addc_u32 s1, s1, s17
s_ashr_i32 s23, s22, 31
s_mov_b32 s21, 0
s_lshl_b64 s[18:19], s[22:23], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s16, s15, s18
s_addc_u32 s17, s1, s19
s_add_u32 s18, s16, s18
s_addc_u32 s19, s17, s19
s_lshl_b64 s[22:23], s[24:25], 3
s_add_u32 s2, s2, s22
s_addc_u32 s3, s3, s23
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
v_add_nc_u32_e32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_mov_b32 s23, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s15, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s19, v6, vcc_lo
s_clause 0x2
global_load_b64 v[5:6], v[7:8], off
global_load_b64 v[7:8], v[9:10], off
global_load_b64 v[9:10], v[11:12], off
v_ashrrev_i32_e32 v12, 31, v3
v_mov_b32_e32 v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[11:12]
v_lshlrev_b64 v[15:16], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v14, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v15
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v16, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_6:
global_load_b32 v15, v[11:12], off
v_add_nc_u32_e32 v3, 1, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v17, vcc_lo, s11, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s12, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s13, v15
s_clause 0x1
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[19:20], off
v_add_co_ci_u32_e32 v16, vcc_lo, s14, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
global_load_b64 v[15:16], v[15:16], off
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s23, vcc_lo, s23
s_waitcnt vmcnt(2)
v_mul_f64 v[17:18], v[7:8], v[17:18]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[5:6], v[19:20], v[17:18]
s_waitcnt vmcnt(0)
v_fma_f64 v[15:16], v[9:10], v[15:16], v[17:18]
global_store_b64 v[13:14], v[15:16], off
v_add_co_u32 v13, s0, v13, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, 0, v14, s0
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execnz .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, .Lfunc_end0-_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
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.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1fd4_00000000-6_computeCovDxdPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
.type _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i, @function
_Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movq %r8, 40(%rsp)
movl %r9d, 48(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 272(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i, .-_Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, @function
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z52__device_stub__Z15computeCovDxdPiPiS_S_iPdiddS0_S0_iPiS_S_iPdiddS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, .-_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeCovDxdPi.hip"
.globl _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i # -- Begin function _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 4, 0x90
.type _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i,@function
_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i: # @_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movl %r9d, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i, .Lfunc_end0-_Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i,@object # @_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.section .rodata,"a",@progbits
.globl _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.p2align 3, 0x0
_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i:
.quad _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.size _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__computeCovDxdPiPiS_S_iPdiddS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15computeCovDxdPiPiS_S_iPdiddS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | code for sm_80
Function : _Z20convolution3D_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 1.513957977294921875e-05 ; /* 0x000000feff047435 */
/* 0x000fc600000001ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e660000002500 */
/*0050*/ ISETP.LT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f01270 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*0080*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GT.OR P0, PT, R3, 0xfe, P0 ; /* 0x000000fe0300780c */
/* 0x000fe20000704670 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0xfe, P0 ; /* 0x000000fe0000780c */
/* 0x000fc80000704670 */
/*00c0*/ ISETP.GT.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fc80000704670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LEA R3, R3, R0, 0x8 ; /* 0x0000000003037211 */
/* 0x000fe200078e40ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*0130*/ LEA R3, R0, R3, 0x10 ; /* 0x0000000300037211 */
/* 0x000fe400078e80ff */
/*0140*/ MOV R0, 0x4 ; /* 0x0000000400007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R5, R3, -0x10101, RZ ; /* 0xfffefeff03057810 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0200 */
/*0170*/ LDG.E R8, [R4.64+0x80000] ; /* 0x0800000404087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IMAD.WIDE R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc600078e0200 */
/*01a0*/ LDG.E R10, [R4.64+0x40004] ; /* 0x04000404040a7981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R11, [R4.64+0x40804] ; /* 0x04080404040b7981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R15, [R4.64+0x80008] ; /* 0x08000804040f7981 */
/* 0x000f28000c1e1900 */
/*01f0*/ LDG.E R17, [R4.64+0x408] ; /* 0x0004080404117981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R19, [R4.64+0x80408] ; /* 0x0804080404137981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R21, [R4.64+0x808] ; /* 0x0008080404157981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R23, [R4.64+0x80808] ; /* 0x0808080404177981 */
/* 0x000f62000c1e1900 */
/*0230*/ FMUL R9, R8, 4 ; /* 0x4080000008097820 */
/* 0x004fc80000400000 */
/*0240*/ FFMA R9, R2, 2, R9 ; /* 0x4000000002097823 */
/* 0x008fc80000000009 */
/*0250*/ FFMA R9, R2, 5, R9 ; /* 0x40a0000002097823 */
/* 0x000fc80000000009 */
/*0260*/ FFMA R9, R8, 7, R9 ; /* 0x40e0000008097823 */
/* 0x000fc80000000009 */
/*0270*/ FFMA R9, R2, -8, R9 ; /* 0xc100000002097823 */
/* 0x000fe40000000009 */
/*0280*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0200 */
/*0290*/ FFMA R9, R8, 10, R9 ; /* 0x4120000008097823 */
/* 0x000fc80000000009 */
/*02a0*/ FFMA R9, R10, -3, R9 ; /* 0xc04000000a097823 */
/* 0x010fc80000000009 */
/*02b0*/ FFMA R6, R6, 6, R9 ; /* 0x40c0000006067823 */
/* 0x020fc80000000009 */
/*02c0*/ FFMA R6, R11, -9, R6 ; /* 0xc11000000b067823 */
/* 0x000fc80000000006 */
/*02d0*/ FFMA R6, R13, 2, R6 ; /* 0x400000000d067823 */
/* 0x000fc80000000006 */
/*02e0*/ FFMA R6, R15, 4, R6 ; /* 0x408000000f067823 */
/* 0x000fc80000000006 */
/*02f0*/ FFMA R6, R17, 5, R6 ; /* 0x40a0000011067823 */
/* 0x000fc80000000006 */
/*0300*/ FFMA R6, R19, 7, R6 ; /* 0x40e0000013067823 */
/* 0x000fc80000000006 */
/*0310*/ FFMA R6, R21, -8, R6 ; /* 0xc100000015067823 */
/* 0x000fc80000000006 */
/*0320*/ FFMA R23, R23, 10, R6 ; /* 0x4120000017177823 */
/* 0x000fca0000000006 */
/*0330*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .file "tmpxft_00025153_00000000-6_3DConvolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z6absValf
.type _Z6absValf, @function
_Z6absValf:
.LFB2071:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L13
.L10:
ret
.L13:
xorps .LC3(%rip), %xmm0
ret
.cfi_endproc
.LFE2071:
.size _Z6absValf, .-_Z6absValf
.globl _Z11percentDiffdd
.type _Z11percentDiffdd, @function
_Z11percentDiffdd:
.LFB2072:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L35
.L15:
cvtss2sd %xmm2, %xmm2
movsd .LC4(%rip), %xmm3
comisd %xmm2, %xmm3
jbe .L17
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L36
.L19:
pxor %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
pxor %xmm2, %xmm2
movsd .LC4(%rip), %xmm4
comisd %xmm3, %xmm4
ja .L14
.L17:
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
pxor %xmm1, %xmm1
comiss %xmm2, %xmm1
ja .L37
.L22:
addsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
ja .L38
.L24:
movaps %xmm2, %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L39
.L26:
movaps %xmm0, %xmm2
mulss .LC6(%rip), %xmm2
.L14:
movaps %xmm2, %xmm0
ret
.L35:
xorps .LC3(%rip), %xmm2
jmp .L15
.L36:
xorps .LC3(%rip), %xmm2
jmp .L19
.L37:
xorps .LC3(%rip), %xmm2
jmp .L22
.L38:
xorps .LC3(%rip), %xmm1
jmp .L24
.L39:
xorps .LC3(%rip), %xmm0
jmp .L26
.cfi_endproc
.LFE2072:
.size _Z11percentDiffdd, .-_Z11percentDiffdd
.globl _Z6conv3DPfS_
.type _Z6conv3DPfS_, @function
_Z6conv3DPfS_:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r14
leaq 524288(%rdi), %r12
leaq 263168(%rsi), %r15
addq $67108864, %r14
movss .LC7(%rip), %xmm5
movss .LC8(%rip), %xmm4
movss .LC9(%rip), %xmm3
movss .LC10(%rip), %xmm2
movss .LC11(%rip), %xmm1
movss .LC12(%rip), %xmm8
movss .LC13(%rip), %xmm7
movss .LC14(%rip), %xmm6
.L41:
leaq -524288(%r12), %rdx
leaq -262144(%r12), %rbp
leaq -261120(%r12), %rbx
leaq -260096(%r12), %r11
leaq -523264(%r12), %r10
leaq 1024(%r12), %r9
leaq -522240(%r12), %r8
leaq 2048(%r12), %rdi
movq %r15, %rsi
movq %r12, %rcx
leaq -264192(%r12), %r13
.L45:
movl $0, %eax
.L42:
movss (%rdx,%rax), %xmm9
movss (%rcx,%rax), %xmm10
movaps %xmm9, %xmm0
addss %xmm9, %xmm0
movaps %xmm10, %xmm11
mulss %xmm5, %xmm11
addss %xmm11, %xmm0
movaps %xmm9, %xmm11
mulss %xmm4, %xmm11
addss %xmm11, %xmm0
movaps %xmm10, %xmm11
mulss %xmm3, %xmm11
addss %xmm11, %xmm0
mulss %xmm2, %xmm9
addss %xmm9, %xmm0
mulss %xmm1, %xmm10
addss %xmm10, %xmm0
movaps %xmm8, %xmm9
mulss 4(%rbp,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm7, %xmm9
mulss 4(%rbx,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm6, %xmm9
mulss 4(%r11,%rax), %xmm9
addss %xmm9, %xmm0
movss 8(%rdx,%rax), %xmm9
addss %xmm9, %xmm9
addss %xmm9, %xmm0
movaps %xmm5, %xmm9
mulss 8(%rcx,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm4, %xmm9
mulss 8(%r10,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm3, %xmm9
mulss 8(%r9,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm2, %xmm9
mulss 8(%r8,%rax), %xmm9
addss %xmm9, %xmm0
movaps %xmm1, %xmm9
mulss 8(%rdi,%rax), %xmm9
addss %xmm9, %xmm0
movss %xmm0, 4(%rsi,%rax)
addq $4, %rax
cmpq $1016, %rax
jne .L42
addq $1024, %rdx
addq $1024, %rcx
addq $1024, %rbp
addq $1024, %rbx
addq $1024, %r11
addq $1024, %r10
addq $1024, %r9
addq $1024, %r8
addq $1024, %rdi
addq $1024, %rsi
cmpq %r13, %rdx
jne .L45
addq $262144, %r12
addq $262144, %r15
cmpq %r14, %r12
jne .L41
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z6conv3DPfS_, .-_Z6conv3DPfS_
.globl _Z4initPf
.type _Z4initPf, @function
_Z4initPf:
.LFB2074:
.cfi_startproc
endbr64
movq %rdi, %r10
movl $0, %r9d
.L49:
movslq %r9d, %r8
imulq $715827883, %r8, %r8
sarq $33, %r8
movl %r9d, %eax
sarl $31, %eax
subl %eax, %r8d
leal (%r8,%r8,2), %eax
sall $2, %eax
movl %r9d, %r8d
subl %eax, %r8d
movq %r10, %rcx
movl $0, %edi
.L53:
movslq %edi, %rax
imulq $-1840700269, %rax, %rax
shrq $32, %rax
addl %edi, %eax
sarl $2, %eax
movl %edi, %edx
sarl $31, %edx
subl %edx, %eax
leal 0(,%rax,8), %edx
subl %eax, %edx
movl %edi, %eax
subl %edx, %eax
leal (%r8,%rax,2), %esi
movl $0, %edx
.L50:
movslq %edx, %rax
imulq $1321528399, %rax, %rax
sarq $34, %rax
movl %edx, %r11d
sarl $31, %r11d
subl %r11d, %eax
leal (%rax,%rax,2), %r11d
leal (%rax,%r11,4), %r11d
movl %edx, %eax
subl %r11d, %eax
leal (%rax,%rax,2), %eax
addl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rdx,4)
addq $1, %rdx
cmpq $256, %rdx
jne .L50
addl $1, %edi
addq $1024, %rcx
cmpl $256, %edi
jne .L53
addl $1, %r9d
addq $262144, %r10
cmpl $256, %r9d
jne .L49
ret
.cfi_endproc
.LFE2074:
.size _Z4initPf, .-_Z4initPf
.section .rodata.str1.8
.align 8
.LC17:
.string "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.text
.globl _Z14compareResultsPfS_
.type _Z14compareResultsPfS_, @function
_Z14compareResultsPfS_:
.LFB2075:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
leaq 263168(%rsi), %r15
leaq 263168(%rdi), %rax
movq %rax, 8(%rsp)
movl $256, 4(%rsp)
movl $0, %ebp
jmp .L56
.L66:
addq $1024, %r12
addq $1024, %r13
cmpq %r14, %r12
je .L60
.L62:
movl $1, %ebx
.L59:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
call _Z11percentDiffdd
comiss .LC15(%rip), %xmm0
seta %al
movzbl %al, %eax
addl %eax, %ebp
addq $1, %rbx
cmpq $255, %rbx
jne .L59
jmp .L66
.L60:
addq $262144, %r15
addq $262144, 8(%rsp)
addl $256, 4(%rsp)
movl 4(%rsp), %eax
cmpl $65280, %eax
je .L61
.L56:
movq 8(%rsp), %r13
movq %r15, %r12
leaq 260096(%r15), %r14
jmp .L62
.L61:
movl %ebp, %edx
movsd .LC16(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z14compareResultsPfS_, .-_Z14compareResultsPfS_
.section .rodata.str1.8
.align 8
.LC18:
.string "setting device %d with name %s\n"
.text
.globl _Z13GPU_argv_initv
.type _Z13GPU_argv_initv, @function
_Z13GPU_argv_initv:
.LFB2076:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z13GPU_argv_initv, .-_Z13GPU_argv_initv
.globl _Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i
.type _Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i, @function
_Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i:
.LFB2103:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20convolution3D_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i, .-_Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i
.globl _Z20convolution3D_kernelPfS_i
.type _Z20convolution3D_kernelPfS_i, @function
_Z20convolution3D_kernelPfS_i:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z20convolution3D_kernelPfS_i, .-_Z20convolution3D_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC19:
.string "GPU Runtime: %0.6lfs\n"
.text
.globl _Z17convolution3DCudaPfS_S_
.type _Z17convolution3DCudaPfS_S_, @function
_Z17convolution3DCudaPfS_S_:
.LFB2077:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $32, 48(%rsp)
movl $1, 52(%rsp)
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $1, %ebx
jmp .L81
.L80:
addl $1, %ebx
cmpl $255, %ebx
je .L85
.L81:
movl $32, 32(%rsp)
movl $8, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L80
movl %ebx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z20convolution3D_kernelPfS_iPfS_i
jmp .L80
.L85:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z17convolution3DCudaPfS_S_, .-_Z17convolution3DCudaPfS_S_
.section .rodata.str1.1
.LC20:
.string "CPU Runtime: %0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2078:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z4initPf
call _Z13GPU_argv_initv
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17convolution3DCudaPfS_S_
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6conv3DPfS_
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z14compareResultsPfS_
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z20convolution3D_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z20convolution3D_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long 1202590843
.long 1065646817
.align 8
.LC5:
.long -536870912
.long 1044740494
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1082130432
.align 4
.LC8:
.long 1084227584
.align 4
.LC9:
.long 1088421888
.align 4
.LC10:
.long -1056964608
.align 4
.LC11:
.long 1092616192
.align 4
.LC12:
.long -1069547520
.align 4
.LC13:
.long 1086324736
.align 4
.LC14:
.long -1055916032
.align 4
.LC15:
.long 1056964608
.section .rodata.cst8
.align 8
.LC16:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20convolution3D_kernelPfS_i
.globl _Z20convolution3D_kernelPfS_i
.p2align 8
.type _Z20convolution3D_kernelPfS_i,@function
_Z20convolution3D_kernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_max3_i32 v2, v0, s3, v1
v_min3_i32 v3, s3, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 0xff, v2
v_cmp_lt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v6, 8, v1
s_lshl_b32 s4, s3, 16
v_add_nc_u32_e32 v2, -1, v0
s_add_i32 s5, s4, 0xffff0000
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v5, 0xffffff00, v6
s_add_i32 s6, s4, 0x10000
v_add_nc_u32_e32 v14, 1, v0
v_add_nc_u32_e32 v7, s4, v0
v_add_nc_u32_e32 v8, 0x100, v6
v_add_nc_u32_e32 v10, s5, v5
v_add_nc_u32_e32 v12, s6, v5
v_add_nc_u32_e32 v13, s5, v14
v_add_nc_u32_e32 v15, s6, v14
v_add_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v1, v10, v2
v_add_nc_u32_e32 v3, v12, v2
v_add_nc_u32_e32 v9, v13, v6
v_add_nc_u32_e32 v11, v15, v6
v_add_nc_u32_e32 v13, v13, v8
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v21, v[0:1], off
global_load_b32 v22, v[3:4], off
v_add_nc_u32_e32 v2, v7, v6
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, v7, v8
v_add_nc_u32_e32 v0, v15, v8
v_add_nc_u32_e32 v15, v12, v14
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[17:18], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v4, v10, v14
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v17, vcc_lo, s0, v17
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[7:8]
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v19, vcc_lo, s0, v2
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_lshlrev_b64 v[10:11], 2, v[11:12]
v_lshlrev_b64 v[12:13], 2, v[13:14]
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v3, vcc_lo
v_lshlrev_b64 v[14:15], 2, v[15:16]
global_load_b32 v16, v[17:18], off
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v17, v[19:20], off
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v18, v[6:7], off
v_add_co_u32 v6, vcc_lo, s0, v14
global_load_b32 v14, v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v15, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_clause 0x1
global_load_b32 v8, v[6:7], off
global_load_b32 v9, v[4:5], off
v_add_co_u32 v6, vcc_lo, s0, v10
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v13, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(9)
v_mul_f32_e32 v1, 4.0, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 2.0, v21
v_fmac_f32_e32 v1, 0x40a00000, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 0x40e00000, v22
v_fmac_f32_e32 v1, 0xc1000000, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 0x41200000, v22
s_waitcnt vmcnt(8)
v_fmamk_f32 v1, v16, 0xc0400000, v1
s_waitcnt vmcnt(7)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v17, 0x40c00000, v1
s_waitcnt vmcnt(6)
v_fmamk_f32 v5, v18, 0xc1100000, v1
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 2.0, v14
s_waitcnt vmcnt(4)
v_fmac_f32_e32 v5, 4.0, v8
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0x40a00000, v9
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v5, 0x40e00000, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0xc1000000, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, 0x41200000, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20convolution3D_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20convolution3D_kernelPfS_i, .Lfunc_end0-_Z20convolution3D_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20convolution3D_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20convolution3D_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* 3DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.5
#define GPU_DEVICE 0
/* Problem size */
#define NI 256
#define NJ 256
#define NK 256
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv3D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j, k;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK -1; ++k) // 2
{
//printf("i:%d\nj:%d\nk:%d\n", i, j, k);
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
}
}
void init(DATA_TYPE* A)
{
int i, j, k;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
for (k = 0; k < NK; ++k)
{
A[i*(NK * NJ) + j*NK + k] = i % 12 + 2 * (j % 7) + 3 * (k % 13);
}
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, k, fail;
fail = 0;
// Compare result from cpu and gpu...
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
for (k = 1; k < NK - 1; ++k) // 2
{
if (percentDiff(B[i*(NK * NJ) + j*NK + k], B_outputFromGpu[i*(NK * NJ) + j*NK + k]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void convolution3D_kernel(DATA_TYPE *A, DATA_TYPE *B, int i)
{
int k = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +2; c21 = +5; c31 = -8;
c12 = -3; c22 = +6; c32 = -9;
c13 = +4; c23 = +7; c33 = +10;
if ((i < (NI-1)) && (j < (NJ-1)) && (k < (NK-1)) && (i > 0) && (j > 0) && (k > 0))
{
B[i*(NK * NJ) + j*NK + k] = c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c21 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c23 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c31 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k - 1)] + c33 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k - 1)]
+ c12 * A[(i + 0)*(NK * NJ) + (j - 1)*NK + (k + 0)] + c22 * A[(i + 0)*(NK * NJ) + (j + 0)*NK + (k + 0)]
+ c32 * A[(i + 0)*(NK * NJ) + (j + 1)*NK + (k + 0)] + c11 * A[(i - 1)*(NK * NJ) + (j - 1)*NK + (k + 1)]
+ c13 * A[(i + 1)*(NK * NJ) + (j - 1)*NK + (k + 1)] + c21 * A[(i - 1)*(NK * NJ) + (j + 0)*NK + (k + 1)]
+ c23 * A[(i + 1)*(NK * NJ) + (j + 0)*NK + (k + 1)] + c31 * A[(i - 1)*(NK * NJ) + (j + 1)*NK + (k + 1)]
+ c33 * A[(i + 1)*(NK * NJ) + (j + 1)*NK + (k + 1)];
}
}
void convolution3DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)(ceil( ((float)NK) / ((float)block.x) )), (size_t)(ceil( ((float)NJ) / ((float)block.y) )));
t_start = rtclock();
int i;
for (i = 1; i < NI - 1; ++i) // 0
{
convolution3D_kernel<<< grid, block >>>(A_gpu, B_gpu, i);
}
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ * NK, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*NK*sizeof(DATA_TYPE));
init(A);
GPU_argv_init();
convolution3DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv3D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .text
.file "3DConvolution.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6absValf
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z6absValf
.p2align 4, 0x90
.type _Z6absValf,@function
_Z6absValf: # @_Z6absValf
.cfi_startproc
# %bb.0:
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end1:
.size _Z6absValf, .Lfunc_end1-_Z6absValf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11percentDiffdd
.LCPI2_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI2_2:
.quad 0x3e45798ee0000000 # double 9.9999999392252903E-9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_3:
.long 0x42c80000 # float 100
.text
.globl _Z11percentDiffdd
.p2align 4, 0x90
.type _Z11percentDiffdd,@function
_Z11percentDiffdd: # @_Z11percentDiffdd
.cfi_startproc
# %bb.0:
cvtsd2ss %xmm0, %xmm2
movaps .LCPI2_0(%rip), %xmm3 # xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm3
maxss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
jbe .LBB2_2
# %bb.1:
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movaps .LCPI2_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm4
maxss %xmm2, %xmm4
cvtss2sd %xmm4, %xmm4
xorps %xmm2, %xmm2
ucomisd %xmm4, %xmm3
ja .LBB2_3
.LBB2_2:
movaps %xmm0, %xmm2
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm1, %xmm3
xorps %xmm2, %xmm3
maxss %xmm1, %xmm3
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm1
xorps %xmm2, %xmm1
maxss %xmm0, %xmm1
divss %xmm1, %xmm3
xorps %xmm3, %xmm2
maxss %xmm3, %xmm2
mulss .LCPI2_3(%rip), %xmm2
.LBB2_3:
movaps %xmm2, %xmm0
retq
.Lfunc_end2:
.size _Z11percentDiffdd, .Lfunc_end2-_Z11percentDiffdd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6conv3DPfS_
.LCPI3_0:
.long 0x40800000 # float 4
.LCPI3_1:
.long 0x40a00000 # float 5
.LCPI3_2:
.long 0x40e00000 # float 7
.LCPI3_3:
.long 0x41000000 # float 8
.LCPI3_4:
.long 0x41200000 # float 10
.LCPI3_5:
.long 0xc0400000 # float -3
.LCPI3_6:
.long 0x40c00000 # float 6
.LCPI3_7:
.long 0xc1100000 # float -9
.text
.globl _Z6conv3DPfS_
.p2align 4, 0x90
.type _Z6conv3DPfS_,@function
_Z6conv3DPfS_: # @_Z6conv3DPfS_
.cfi_startproc
# %bb.0:
addq $263172, %rsi # imm = 0x40404
movl $1, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI3_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI3_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI3_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI3_5(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI3_6(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss .LCPI3_7(%rip), %xmm7 # xmm7 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # %.preheader86
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_3 Depth 3
movq %rsi, %rcx
movq %rdi, %rdx
movl $1, %r8d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_3 Depth 3
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r9,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
movss 8(%rdx,%r9,4), %xmm8 # xmm8 = mem[0],zero,zero,zero
movaps %xmm9, %xmm10
addss %xmm9, %xmm10
movss 524288(%rdx,%r9,4), %xmm11 # xmm11 = mem[0],zero,zero,zero
movaps %xmm11, %xmm12
mulss %xmm0, %xmm12
addss %xmm10, %xmm12
movaps %xmm9, %xmm10
mulss %xmm1, %xmm10
addss %xmm12, %xmm10
movaps %xmm11, %xmm12
mulss %xmm2, %xmm12
addss %xmm10, %xmm12
mulss %xmm3, %xmm9
subss %xmm9, %xmm12
mulss %xmm4, %xmm11
addss %xmm12, %xmm11
movss 262148(%rdx,%r9,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm5, %xmm9
addss %xmm11, %xmm9
movss 263172(%rdx,%r9,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm6, %xmm10
addss %xmm9, %xmm10
movss 264196(%rdx,%r9,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm7, %xmm9
addss %xmm10, %xmm9
addss %xmm8, %xmm8
addss %xmm9, %xmm8
movss 524296(%rdx,%r9,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm0, %xmm9
addss %xmm8, %xmm9
movss 1032(%rdx,%r9,4), %xmm8 # xmm8 = mem[0],zero,zero,zero
mulss %xmm1, %xmm8
addss %xmm9, %xmm8
movss 525320(%rdx,%r9,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm2, %xmm9
addss %xmm8, %xmm9
movss 2056(%rdx,%r9,4), %xmm8 # xmm8 = mem[0],zero,zero,zero
mulss %xmm3, %xmm8
subss %xmm8, %xmm9
movss 526344(%rdx,%r9,4), %xmm8 # xmm8 = mem[0],zero,zero,zero
mulss %xmm4, %xmm8
addss %xmm9, %xmm8
movss %xmm8, (%rcx,%r9,4)
incq %r9
cmpq $254, %r9
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=2
incq %r8
addq $1024, %rdx # imm = 0x400
addq $1024, %rcx # imm = 0x400
cmpq $255, %r8
jne .LBB3_2
# %bb.5: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $262144, %rdi # imm = 0x40000
addq $262144, %rsi # imm = 0x40000
cmpq $255, %rax
jne .LBB3_1
# %bb.6:
retq
.Lfunc_end3:
.size _Z6conv3DPfS_, .Lfunc_end3-_Z6conv3DPfS_
.cfi_endproc
# -- End function
.globl _Z4initPf # -- Begin function _Z4initPf
.p2align 4, 0x90
.type _Z4initPf,@function
_Z4initPf: # @_Z4initPf
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
.p2align 4, 0x90
.LBB4_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movl %eax, %edx
imulq %rcx, %rdx
shrq $35, %rdx
shll $2, %edx
leal (%rdx,%rdx,2), %esi
movl %eax, %edx
subl %esi, %edx
movq %rdi, %rsi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movl %r8d, %r9d
imulq $613566757, %r9, %r10 # imm = 0x24924925
shrq $32, %r10
movl %r8d, %r9d
subl %r10d, %r9d
shrl %r9d
addl %r10d, %r9d
shrl $2, %r9d
movl %r9d, %r10d
shll $4, %r10d
addl %r9d, %r9d
subl %r10d, %r9d
addl %edx, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %r10d, %r11d
imulq $1321528399, %r11, %r11 # imm = 0x4EC4EC4F
shrq $34, %r11
imull $39, %r11d, %r11d
movl %r9d, %ebx
subl %r11d, %ebx
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%rsi,%r10,4)
incq %r10
addl $3, %r9d
cmpq $256, %r10 # imm = 0x100
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %r8
addq $1024, %rsi # imm = 0x400
addl $2, %edx
cmpq $256, %r8 # imm = 0x100
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $262144, %rdi # imm = 0x40000
cmpq $256, %rax # imm = 0x100
jne .LBB4_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z4initPf, .Lfunc_end4-_Z4initPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compareResultsPfS_
.LCPI5_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI5_5:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI5_3:
.long 0x42c80000 # float 100
.LCPI5_4:
.long 0x3f000000 # float 0.5
.text
.globl _Z14compareResultsPfS_
.p2align 4, 0x90
.type _Z14compareResultsPfS_,@function
_Z14compareResultsPfS_: # @_Z14compareResultsPfS_
.cfi_startproc
# %bb.0:
addq $263172, %rsi # imm = 0x40404
addq $263172, %rdi # imm = 0x40404
xorl %eax, %eax
movl $1, %ecx
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
movss .LCPI5_4(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI5_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI5_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_1 Depth=1
incq %rcx
addq $262144, %rsi # imm = 0x40000
addq $262144, %rdi # imm = 0x40000
cmpq $255, %rcx
je .LBB5_9
.LBB5_1: # %.preheader18
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
# Child Loop BB5_3 Depth 3
movq %rdi, %rdx
movq %rsi, %r8
movl $1, %r9d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_2 Depth=2
incq %r9
addq $1024, %r8 # imm = 0x400
addq $1024, %rdx # imm = 0x400
cmpq $255, %r9
je .LBB5_8
.LBB5_2: # %.preheader
# Parent Loop BB5_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_3 Depth 3
xorl %r10d, %r10d
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=3
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB5_6: # %_Z11percentDiffdd.exit
# in Loop: Header=BB5_3 Depth=3
xorl %r11d, %r11d
ucomiss %xmm2, %xmm7
seta %r11b
addl %r11d, %eax
incq %r10
cmpq $254, %r10
je .LBB5_7
.LBB5_3: # Parent Loop BB5_1 Depth=1
# Parent Loop BB5_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r10,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%r8,%r10,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=3
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB5_5
jmp .LBB5_6
.LBB5_9:
movsd .LCPI5_5(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movl %eax, %esi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z14compareResultsPfS_, .Lfunc_end5-_Z14compareResultsPfS_
.cfi_endproc
# -- End function
.globl _Z13GPU_argv_initv # -- Begin function _Z13GPU_argv_initv
.p2align 4, 0x90
.type _Z13GPU_argv_initv,@function
_Z13GPU_argv_initv: # @_Z13GPU_argv_initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13GPU_argv_initv, .Lfunc_end6-_Z13GPU_argv_initv
.cfi_endproc
# -- End function
.globl _Z35__device_stub__convolution3D_kernelPfS_i # -- Begin function _Z35__device_stub__convolution3D_kernelPfS_i
.p2align 4, 0x90
.type _Z35__device_stub__convolution3D_kernelPfS_i,@function
_Z35__device_stub__convolution3D_kernelPfS_i: # @_Z35__device_stub__convolution3D_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20convolution3D_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size _Z35__device_stub__convolution3D_kernelPfS_i, .Lfunc_end7-_Z35__device_stub__convolution3D_kernelPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17convolution3DCudaPfS_S_
.LCPI8_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z17convolution3DCudaPfS_S_
.p2align 4, 0x90
.type _Z17convolution3DCudaPfS_S_,@function
_Z17convolution3DCudaPfS_S_: # @_Z17convolution3DCudaPfS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 96(%rsp) # 8-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $1, %r13d
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_2: # %_Z7rtclockv.exit
movq 32(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 40(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movabsq $137438953480, %r14 # imm = 0x2000000008
movabsq $34359738400, %r15 # imm = 0x800000020
leaq 112(%rsp), %rbp
leaq 104(%rsp), %rbx
leaq 32(%rsp), %r12
jmp .LBB8_3
.p2align 4, 0x90
.LBB8_5: # in Loop: Header=BB8_3 Depth=1
incl %r13d
cmpl $255, %r13d
je .LBB8_6
.LBB8_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_5
# %bb.4: # in Loop: Header=BB8_3 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r13d, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 28(%rsp), %rax
movq %rax, 48(%rsp)
leaq 64(%rsp), %rdi
leaq 120(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z20convolution3D_kernelPfS_i, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB8_5
.LBB8_6:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_8
# %bb.7:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_8: # %_Z7rtclockv.exit14
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sdq 88(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
cvtsi2sdq 32(%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd %xmm1, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq 96(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z17convolution3DCudaPfS_S_, .Lfunc_end8-_Z17convolution3DCudaPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI9_2:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI9_6:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI9_1:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI9_3:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI9_4:
.long 0x42c80000 # float 100
.LCPI9_5:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
movq %rbx, %rdx
.p2align 4, 0x90
.LBB9_1: # %.preheader14.i
# =>This Loop Header: Depth=1
# Child Loop BB9_2 Depth 2
# Child Loop BB9_3 Depth 3
movl %eax, %esi
imulq %rcx, %rsi
shrq $35, %rsi
shll $2, %esi
leal (%rsi,%rsi,2), %edi
movl %eax, %esi
subl %edi, %esi
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB9_2: # %.preheader.i
# Parent Loop BB9_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB9_3 Depth 3
movl %r8d, %r9d
imulq $613566757, %r9, %r10 # imm = 0x24924925
shrq $32, %r10
movl %r8d, %r9d
subl %r10d, %r9d
shrl %r9d
addl %r10d, %r9d
shrl $2, %r9d
movl %r9d, %r10d
shll $4, %r10d
addl %r9d, %r9d
subl %r10d, %r9d
addl %esi, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB9_3: # Parent Loop BB9_1 Depth=1
# Parent Loop BB9_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %r10d, %r11d
imulq $1321528399, %r11, %r11 # imm = 0x4EC4EC4F
shrq $34, %r11
imull $39, %r11d, %r11d
movl %r9d, %ebp
subl %r11d, %ebp
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, (%rdi,%r10,4)
incq %r10
addl $3, %r9d
cmpq $256, %r10 # imm = 0x100
jne .LBB9_3
# %bb.4: # in Loop: Header=BB9_2 Depth=2
incq %r8
addq $1024, %rdi # imm = 0x400
addl $2, %esi
cmpq $256, %r8 # imm = 0x100
jne .LBB9_2
# %bb.5: # in Loop: Header=BB9_1 Depth=1
incq %rax
addq $262144, %rdx # imm = 0x40000
cmpq $256, %rax # imm = 0x100
jne .LBB9_1
# %bb.6: # %_Z4initPf.exit
leaq 16(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %r12, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z17convolution3DCudaPfS_S_
leaq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_8
# %bb.7:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_8: # %_Z7rtclockv.exit
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI9_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r14, %rsi
callq _Z6conv3DPfS_
leaq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_10
# %bb.9:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_10: # %_Z7rtclockv.exit14
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LCPI9_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movq %r15, %rax
addq $263172, %rax # imm = 0x40404
movq %r14, %rcx
addq $263172, %rcx # imm = 0x40404
xorl %esi, %esi
movl $1, %edx
movaps .LCPI9_1(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI9_2(%rip), %xmm1 # xmm1 = mem[0],zero
movss .LCPI9_5(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI9_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI9_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB9_11
.p2align 4, 0x90
.LBB9_18: # in Loop: Header=BB9_11 Depth=1
incq %rdx
addq $262144, %rax # imm = 0x40000
addq $262144, %rcx # imm = 0x40000
cmpq $255, %rdx
je .LBB9_19
.LBB9_11: # %.preheader18.i
# =>This Loop Header: Depth=1
# Child Loop BB9_12 Depth 2
# Child Loop BB9_13 Depth 3
movq %rcx, %rdi
movq %rax, %r8
movl $1, %r9d
jmp .LBB9_12
.p2align 4, 0x90
.LBB9_17: # in Loop: Header=BB9_12 Depth=2
incq %r9
addq $1024, %r8 # imm = 0x400
addq $1024, %rdi # imm = 0x400
cmpq $255, %r9
je .LBB9_18
.LBB9_12: # %.preheader.i15
# Parent Loop BB9_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB9_13 Depth 3
xorl %r10d, %r10d
jmp .LBB9_13
.p2align 4, 0x90
.LBB9_15: # in Loop: Header=BB9_13 Depth=3
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB9_16: # %_Z11percentDiffdd.exit.i
# in Loop: Header=BB9_13 Depth=3
xorl %r11d, %r11d
ucomiss %xmm2, %xmm7
seta %r11b
addl %r11d, %esi
incq %r10
cmpq $254, %r10
je .LBB9_17
.LBB9_13: # Parent Loop BB9_11 Depth=1
# Parent Loop BB9_12 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r10,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%r8,%r10,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB9_15
# %bb.14: # in Loop: Header=BB9_13 Depth=3
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB9_15
jmp .LBB9_16
.LBB9_19: # %_Z14compareResultsPfS_.exit
movsd .LCPI9_6(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20convolution3D_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.size .L.str.1, 74
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "setting device %d with name %s\n"
.size .L.str.2, 32
.type _Z20convolution3D_kernelPfS_i,@object # @_Z20convolution3D_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z20convolution3D_kernelPfS_i
.p2align 3, 0x0
_Z20convolution3D_kernelPfS_i:
.quad _Z35__device_stub__convolution3D_kernelPfS_i
.size _Z20convolution3D_kernelPfS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU Runtime: %0.6lfs\n"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20convolution3D_kernelPfS_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__convolution3D_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20convolution3D_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20convolution3D_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 1.513957977294921875e-05 ; /* 0x000000feff047435 */
/* 0x000fc600000001ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e660000002500 */
/*0050*/ ISETP.LT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f01270 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*0080*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GT.OR P0, PT, R3, 0xfe, P0 ; /* 0x000000fe0300780c */
/* 0x000fe20000704670 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0xfe, P0 ; /* 0x000000fe0000780c */
/* 0x000fc80000704670 */
/*00c0*/ ISETP.GT.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fc80000704670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LEA R3, R3, R0, 0x8 ; /* 0x0000000003037211 */
/* 0x000fe200078e40ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*0130*/ LEA R3, R0, R3, 0x10 ; /* 0x0000000300037211 */
/* 0x000fe400078e80ff */
/*0140*/ MOV R0, 0x4 ; /* 0x0000000400007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R5, R3, -0x10101, RZ ; /* 0xfffefeff03057810 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0200 */
/*0170*/ LDG.E R8, [R4.64+0x80000] ; /* 0x0800000404087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IMAD.WIDE R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc600078e0200 */
/*01a0*/ LDG.E R10, [R4.64+0x40004] ; /* 0x04000404040a7981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R11, [R4.64+0x40804] ; /* 0x04080404040b7981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R15, [R4.64+0x80008] ; /* 0x08000804040f7981 */
/* 0x000f28000c1e1900 */
/*01f0*/ LDG.E R17, [R4.64+0x408] ; /* 0x0004080404117981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R19, [R4.64+0x80408] ; /* 0x0804080404137981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R21, [R4.64+0x808] ; /* 0x0008080404157981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R23, [R4.64+0x80808] ; /* 0x0808080404177981 */
/* 0x000f62000c1e1900 */
/*0230*/ FMUL R9, R8, 4 ; /* 0x4080000008097820 */
/* 0x004fc80000400000 */
/*0240*/ FFMA R9, R2, 2, R9 ; /* 0x4000000002097823 */
/* 0x008fc80000000009 */
/*0250*/ FFMA R9, R2, 5, R9 ; /* 0x40a0000002097823 */
/* 0x000fc80000000009 */
/*0260*/ FFMA R9, R8, 7, R9 ; /* 0x40e0000008097823 */
/* 0x000fc80000000009 */
/*0270*/ FFMA R9, R2, -8, R9 ; /* 0xc100000002097823 */
/* 0x000fe40000000009 */
/*0280*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0200 */
/*0290*/ FFMA R9, R8, 10, R9 ; /* 0x4120000008097823 */
/* 0x000fc80000000009 */
/*02a0*/ FFMA R9, R10, -3, R9 ; /* 0xc04000000a097823 */
/* 0x010fc80000000009 */
/*02b0*/ FFMA R6, R6, 6, R9 ; /* 0x40c0000006067823 */
/* 0x020fc80000000009 */
/*02c0*/ FFMA R6, R11, -9, R6 ; /* 0xc11000000b067823 */
/* 0x000fc80000000006 */
/*02d0*/ FFMA R6, R13, 2, R6 ; /* 0x400000000d067823 */
/* 0x000fc80000000006 */
/*02e0*/ FFMA R6, R15, 4, R6 ; /* 0x408000000f067823 */
/* 0x000fc80000000006 */
/*02f0*/ FFMA R6, R17, 5, R6 ; /* 0x40a0000011067823 */
/* 0x000fc80000000006 */
/*0300*/ FFMA R6, R19, 7, R6 ; /* 0x40e0000013067823 */
/* 0x000fc80000000006 */
/*0310*/ FFMA R6, R21, -8, R6 ; /* 0xc100000015067823 */
/* 0x000fc80000000006 */
/*0320*/ FFMA R23, R23, 10, R6 ; /* 0x4120000017177823 */
/* 0x000fca0000000006 */
/*0330*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20convolution3D_kernelPfS_i
.globl _Z20convolution3D_kernelPfS_i
.p2align 8
.type _Z20convolution3D_kernelPfS_i,@function
_Z20convolution3D_kernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_max3_i32 v2, v0, s3, v1
v_min3_i32 v3, s3, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 0xff, v2
v_cmp_lt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v6, 8, v1
s_lshl_b32 s4, s3, 16
v_add_nc_u32_e32 v2, -1, v0
s_add_i32 s5, s4, 0xffff0000
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v5, 0xffffff00, v6
s_add_i32 s6, s4, 0x10000
v_add_nc_u32_e32 v14, 1, v0
v_add_nc_u32_e32 v7, s4, v0
v_add_nc_u32_e32 v8, 0x100, v6
v_add_nc_u32_e32 v10, s5, v5
v_add_nc_u32_e32 v12, s6, v5
v_add_nc_u32_e32 v13, s5, v14
v_add_nc_u32_e32 v15, s6, v14
v_add_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v1, v10, v2
v_add_nc_u32_e32 v3, v12, v2
v_add_nc_u32_e32 v9, v13, v6
v_add_nc_u32_e32 v11, v15, v6
v_add_nc_u32_e32 v13, v13, v8
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v21, v[0:1], off
global_load_b32 v22, v[3:4], off
v_add_nc_u32_e32 v2, v7, v6
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, v7, v8
v_add_nc_u32_e32 v0, v15, v8
v_add_nc_u32_e32 v15, v12, v14
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[17:18], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v4, v10, v14
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v17, vcc_lo, s0, v17
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[7:8]
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v19, vcc_lo, s0, v2
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_lshlrev_b64 v[10:11], 2, v[11:12]
v_lshlrev_b64 v[12:13], 2, v[13:14]
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v3, vcc_lo
v_lshlrev_b64 v[14:15], 2, v[15:16]
global_load_b32 v16, v[17:18], off
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v17, v[19:20], off
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v18, v[6:7], off
v_add_co_u32 v6, vcc_lo, s0, v14
global_load_b32 v14, v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v15, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_clause 0x1
global_load_b32 v8, v[6:7], off
global_load_b32 v9, v[4:5], off
v_add_co_u32 v6, vcc_lo, s0, v10
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v13, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(9)
v_mul_f32_e32 v1, 4.0, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 2.0, v21
v_fmac_f32_e32 v1, 0x40a00000, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 0x40e00000, v22
v_fmac_f32_e32 v1, 0xc1000000, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, 0x41200000, v22
s_waitcnt vmcnt(8)
v_fmamk_f32 v1, v16, 0xc0400000, v1
s_waitcnt vmcnt(7)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v17, 0x40c00000, v1
s_waitcnt vmcnt(6)
v_fmamk_f32 v5, v18, 0xc1100000, v1
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 2.0, v14
s_waitcnt vmcnt(4)
v_fmac_f32_e32 v5, 4.0, v8
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0x40a00000, v9
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v5, 0x40e00000, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0xc1000000, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, 0x41200000, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20convolution3D_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20convolution3D_kernelPfS_i, .Lfunc_end0-_Z20convolution3D_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20convolution3D_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20convolution3D_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} | code for sm_80
Function : _Z12errorsKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fe400078e0203 */
/*0090*/ @P0 BRA 0x790 ; /* 0x000006f000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*00e0*/ @!P0 BRA 0x5d0 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0100*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0110*/ IADD3 R7, -R0, c[0x0][0x17c], RZ ; /* 0x00005f0000077a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0205 */
/*0140*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0170*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*0180*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0022a20000001400 */
/*0190*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 BRA 0x210 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*01c0*/ BSSY B0, 0x200 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*01d0*/ MOV R15, 0x1f0 ; /* 0x000001f0000f7802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0xe10 ; /* 0x00000c2000007944 */
/* 0x021fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ FMUL.FTZ R8, R14, R11 ; /* 0x0000000b0e087220 */
/* 0x006fe40000410000 */
/*0220*/ FMUL.FTZ R10, R11, 0.5 ; /* 0x3f0000000b0a7820 */
/* 0x000fe40000410000 */
/*0230*/ FFMA R11, -R8, R8, R14 ; /* 0x00000008080b7223 */
/* 0x000fc8000000010e */
/*0240*/ FFMA R8, R11, R10, R8 ; /* 0x0000000a0b087223 */
/* 0x000fc80000000008 */
/*0250*/ FADD R17, R8, R9 ; /* 0x0000000908117221 */
/* 0x020fca0000000000 */
/*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0280*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*0290*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0002a20000001400 */
/*02a0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 BRA 0x320 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*02d0*/ BSSY B0, 0x310 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*02e0*/ MOV R15, 0x300 ; /* 0x00000300000f7802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0xe10 ; /* 0x00000b1000007944 */
/* 0x001fea0003c00000 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x360 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0320*/ FMUL.FTZ R8, R14, R9 ; /* 0x000000090e087220 */
/* 0x006fe40000410000 */
/*0330*/ FMUL.FTZ R10, R9, 0.5 ; /* 0x3f000000090a7820 */
/* 0x000fe40000410000 */
/*0340*/ FFMA R9, -R8, R8, R14 ; /* 0x0000000808097223 */
/* 0x000fc8000000010e */
/*0350*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fc80000000008 */
/*0360*/ FADD R17, R17, R8 ; /* 0x0000000811117221 */
/* 0x000fca0000000000 */
/*0370*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0380*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea4000c1e1900 */
/*0390*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*03a0*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0002a20000001400 */
/*03b0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*03d0*/ @!P1 BRA 0x430 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*03e0*/ BSSY B0, 0x420 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*03f0*/ MOV R15, 0x410 ; /* 0x00000410000f7802 */
/* 0x000fe40000000f00 */
/*0400*/ CALL.REL.NOINC 0xe10 ; /* 0x00000a0000007944 */
/* 0x001fea0003c00000 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x470 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0430*/ FMUL.FTZ R8, R14, R9 ; /* 0x000000090e087220 */
/* 0x006fe40000410000 */
/*0440*/ FMUL.FTZ R10, R9, 0.5 ; /* 0x3f000000090a7820 */
/* 0x000fe40000410000 */
/*0450*/ FFMA R9, -R8, R8, R14 ; /* 0x0000000808097223 */
/* 0x000fc8000000010e */
/*0460*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fc80000000008 */
/*0470*/ FADD R17, R17, R8 ; /* 0x0000000811117221 */
/* 0x000fca0000000000 */
/*0480*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0490*/ LDG.E R4, [R4.64+0xc] ; /* 0x00000c0404047981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FMUL R14, R4, R4 ; /* 0x00000004040e7220 */
/* 0x004fc80000400000 */
/*04b0*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0002a20000001400 */
/*04c0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*04e0*/ @!P1 BRA 0x550 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*04f0*/ BSSY B0, 0x530 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*0500*/ MOV R15, 0x520 ; /* 0x00000520000f7802 */
/* 0x000fe40000000f00 */
/*0510*/ CALL.REL.NOINC 0xe10 ; /* 0x000008f000007944 */
/* 0x001fea0003c00000 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ MOV R9, R8 ; /* 0x0000000800097202 */
/* 0x000fe20000000f00 */
/*0540*/ BRA 0x590 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0550*/ FMUL.FTZ R9, R14, R11 ; /* 0x0000000b0e097220 */
/* 0x006fe40000410000 */
/*0560*/ FMUL.FTZ R5, R11, 0.5 ; /* 0x3f0000000b057820 */
/* 0x000fe40000410000 */
/*0570*/ FFMA R4, -R9, R9, R14 ; /* 0x0000000909047223 */
/* 0x000fc8000000010e */
/*0580*/ FFMA R9, R4, R5, R9 ; /* 0x0000000504097223 */
/* 0x000fc80000000009 */
/*0590*/ FADD R9, R17, R9 ; /* 0x0000000911097221 */
/* 0x000fe20000000000 */
/*05a0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*05c0*/ @P0 BRA 0x120 ; /* 0xfffffb5000000947 */
/* 0x000fea000383ffff */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000564000c1e1900 */
/*0600*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x002fd400000001ff */
/*0610*/ IMAD.WIDE R8, R6, R9, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x000fcc00078e0209 */
/*0620*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x008fc80000400000 */
/*0640*/ MUFU.RSQ R7, R14 ; /* 0x0000000e00077308 */
/* 0x0002e20000001400 */
/*0650*/ IADD3 R5, R14, -0xd000000, RZ ; /* 0xf30000000e057810 */
/* 0x000fc80007ffe0ff */
/*0660*/ ISETP.GT.U32.AND P0, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f04070 */
/*0670*/ @!P0 BRA 0x6e0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0680*/ BSSY B0, 0x6c0 ; /* 0x0000003000007945 */
/* 0x00afe20003800000 */
/*0690*/ MOV R15, 0x6b0 ; /* 0x000006b0000f7802 */
/* 0x000fe40000000f00 */
/*06a0*/ CALL.REL.NOINC 0xe10 ; /* 0x0000076000007944 */
/* 0x025fea0003c00000 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*06d0*/ BRA 0x720 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*06e0*/ FMUL.FTZ R5, R14, R7 ; /* 0x000000070e057220 */
/* 0x00afe40000410000 */
/*06f0*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*0700*/ FFMA R8, -R5, R5, R14 ; /* 0x0000000505087223 */
/* 0x000fc8000000010e */
/*0710*/ FFMA R5, R8, R7, R5 ; /* 0x0000000708057223 */
/* 0x000fc60000000005 */
/*0720*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0730*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x020fc60000000000 */
/*0740*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0750*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0003f6000c101904 */
/*0760*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0770*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0780*/ BRA 0x600 ; /* 0xfffffe7000007947 */
/* 0x000fea000383ffff */
/*0790*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*07a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x001fe200000001ff */
/*07b0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fc80000000f00 */
/*07c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*07d0*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fd60000000f00 */
/*07e0*/ @!P0 BRA 0xbc0 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*07f0*/ IADD3 R6, R7, -0x1, RZ ; /* 0xffffffff07067810 */
/* 0x000fe20007ffe0ff */
/*0800*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0b7435 */
/* 0x000fc600000001ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0820*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fd600078ec0ff */
/*0830*/ @!P0 BRA 0xb40 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0840*/ IADD3 R8, -R6, R7, RZ ; /* 0x0000000706087210 */
/* 0x000fe40007ffe1ff */
/*0850*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fe40000000f00 */
/*0860*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0870*/ @!P0 BRA 0xad0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*08a0*/ @!P1 BRA 0x9f0 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*08b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08c0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*08d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*08f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0900*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0910*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0920*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0930*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0940*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0950*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0960*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0970*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0980*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0990*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09a0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09b0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09c0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09d0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*09e0*/ @P1 BRA 0x8c0 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*09f0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0a00*/ @!P1 BRA 0xab0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R11, R11, R4.reuse, RZ ; /* 0x000000040b0b7224 */
/* 0x080fe200078e02ff */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a50*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a60*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a70*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a80*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a90*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0aa0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe400078e02ff */
/*0ab0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0ac0*/ @!P0 BRA 0xb40 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0ae0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc600078e02ff */
/*0af0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0b00*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b10*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b20*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b30*/ @P0 BRA 0xad0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0b40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0b50*/ @!P0 BRA 0xbc0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fd800078e02ff */
/*0b80*/ @P0 ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600080c */
/* 0x000fe20003f25270 */
/*0b90*/ @P0 IMAD R9, R11, R4, RZ ; /* 0x000000040b090224 */
/* 0x000fc600078e02ff */
/*0ba0*/ @P0 SEL R6, R4, 0x1, P1 ; /* 0x0000000104060807 */
/* 0x000fca0000800000 */
/*0bb0*/ @P0 IMAD R11, R6, R9, RZ ; /* 0x00000009060b0224 */
/* 0x000fe400078e02ff */
/*0bc0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0bd0*/ IMAD R8, R0, c[0x0][0x178], R7 ; /* 0x00005e0000087a24 */
/* 0x000fd200078e0207 */
/*0be0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e020d */
/*0bf0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000ea20000201400 */
/*0c10*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0c20*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f06270 */
/*0c30*/ FMUL R6, R11, R8 ; /* 0x000000080b067220 */
/* 0x004fcc0000400000 */
/*0c40*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0c50*/ I2F R10, R6 ; /* 0x00000006000a7306 */
/* 0x001e240000201400 */
/*0c60*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x001fe20000000000 */
/*0c70*/ @!P0 BRA 0x7c0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0c80*/ IMAD.WIDE R6, R4, R13, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fcc00078e020d */
/*0c90*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0ca0*/ BSSY B0, 0xda0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0cb0*/ FADD R5, -R5, R6 ; /* 0x0000000605057221 */
/* 0x004fc80000000100 */
/*0cc0*/ FMUL R14, R5, R5 ; /* 0x00000005050e7220 */
/* 0x000fc80000400000 */
/*0cd0*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0000620000001400 */
/*0ce0*/ IADD3 R5, R14, -0xd000000, RZ ; /* 0xf30000000e057810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.GT.U32.AND P0, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f04070 */
/*0d00*/ @!P0 BRA 0xd50 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0d10*/ MOV R15, 0xd30 ; /* 0x00000d30000f7802 */
/* 0x003fe40000000f00 */
/*0d20*/ CALL.REL.NOINC 0xe10 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0d30*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0d40*/ BRA 0xd90 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0d50*/ FMUL.FTZ R5, R14, R9 ; /* 0x000000090e057220 */
/* 0x003fe40000410000 */
/*0d60*/ FMUL.FTZ R7, R9, 0.5 ; /* 0x3f00000009077820 */
/* 0x000fe40000410000 */
/*0d70*/ FFMA R6, -R5, R5, R14 ; /* 0x0000000505067223 */
/* 0x000fc8000000010e */
/*0d80*/ FFMA R5, R6, R7, R5 ; /* 0x0000000706057223 */
/* 0x000fe40000000005 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0db0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f06270 */
/*0dd0*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x004fca0000000000 */
/*0de0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*0df0*/ @!P0 BRA 0x7a0 ; /* 0xfffff9a000008947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000782c0ff */
/*0e20*/ @!P1 MOV R8, R14 ; /* 0x0000000e00089202 */
/* 0x000fe20000000f00 */
/*0e30*/ @!P1 BRA 0xf40 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0e40*/ FSETP.GEU.FTZ.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fda0003f3e000 */
/*0e50*/ @!P1 MOV R8, 0x7fffffff ; /* 0x7fffffff00089802 */
/* 0x000fe20000000f00 */
/*0e60*/ @!P1 BRA 0xf40 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0e70*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3c200 */
/*0e80*/ @P1 FADD.FTZ R8, R14, 1 ; /* 0x3f8000000e081421 */
/* 0x000fe20000010000 */
/*0e90*/ @P1 BRA 0xf40 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0ea0*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3d200 */
/*0eb0*/ @P1 FFMA R10, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0a1823 */
/* 0x000fc800000000ff */
/*0ec0*/ @P1 MUFU.RSQ R11, R10 ; /* 0x0000000a000b1308 */
/* 0x000e240000001400 */
/*0ed0*/ @P1 FMUL.FTZ R13, R10, R11 ; /* 0x0000000b0a0d1220 */
/* 0x001fe40000410000 */
/*0ee0*/ @P1 FMUL.FTZ R11, R11, 0.5 ; /* 0x3f0000000b0b1820 */
/* 0x000fe40000410000 */
/*0ef0*/ @P1 FADD.FTZ R8, -R13, -RZ ; /* 0x800000ff0d081221 */
/* 0x000fc80000010100 */
/*0f00*/ @P1 FFMA R12, R13, R8, R10 ; /* 0x000000080d0c1223 */
/* 0x000fe2000000000a */
/*0f10*/ @!P1 MOV R8, R14 ; /* 0x0000000e00089202 */
/* 0x000fc60000000f00 */
/*0f20*/ @P1 FFMA R11, R12, R11, R13 ; /* 0x0000000b0c0b1223 */
/* 0x000fc8000000000d */
/*0f30*/ @P1 FMUL.FTZ R8, R11, 2.3283064365386962891e-10 ; /* 0x2f8000000b081820 */
/* 0x000fe40000410000 */
/*0f40*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0f50*/ MOV R10, R15 ; /* 0x0000000f000a7202 */
/* 0x000fca0000000f00 */
/*0f60*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0900a007950 */
/* 0x000fea0003c3ffff */
/*0f70*/ BRA 0xf70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} | .file "tmpxft_0006019a_00000000-6_errorsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12errorsKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
.globl _Z12errorsKernelPfS_S_ii
.type _Z12errorsKernelPfS_S_ii, @function
_Z12errorsKernelPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12errorsKernelPfS_S_ii, .-_Z12errorsKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12errorsKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12errorsKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12errorsKernelPfS_S_ii
.globl _Z12errorsKernelPfS_S_ii
.p2align 8
.type _Z12errorsKernelPfS_S_ii,@function
_Z12errorsKernelPfS_S_ii:
s_load_b32 s8, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v2, s[2:3]
s_clause 0x1
s_load_b32 s9, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s9, 0
v_mul_lo_u32 v5, v0, s9
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e64 s0, 1, v0
s_mov_b32 s3, 0
s_mov_b32 s2, s3
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_add_i32 s2, s2, 1
global_load_b32 v0, v1, s[10:11]
s_cmp_eq_u32 s2, s8
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v0
v_mul_f32_e32 v6, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_sqrt_f32_e32 v6, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v0
v_fma_f32 v10, -v8, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s1, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s1, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v6, v0, vcc_lo
v_add_f32_e32 v4, v4, v0
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_mov_b32_e32 v6, v1
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v6, 0
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v0, s1, v5
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, s9
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v0, v[7:8], off
v_cvt_f32_i32_e32 v7, s10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v7
v_cvt_i32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_add_f32_e32 v6, v6, v0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_mov_b32 s10, 1
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_5
s_mov_b32 s11, 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s11, s11, 1
s_mul_i32 s10, s10, s2
s_cmp_ge_u32 s11, s1
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12errorsKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12errorsKernelPfS_S_ii, .Lfunc_end0-_Z12errorsKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12errorsKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z12errorsKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
/*
const int sizePoint = 5;
const int sizeIndividum = 5;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
*/
const int sizePoint = 500;
const int sizeIndividum = 1000;
const int mathValueMutation = 5;
const float dispersionMutation = 5.0f;
const int powCount = 3;
const float randMaxCount = 20.0f;
const int maxPokoleney = 30;
__global__ void errorsKernel(float *points, float *individs, float *errors, int powCount, int sizePoint)
{
int id = threadIdx.x;
float ans = 0;
int x = 1;
for (int i = 0; i < sizePoint; i++)
{
for (int j = 0; j < powCount; j++)
{
for (int k = 0; k < j; k++)
{
x *= i;
}
x *= individs[id*powCount + j];
ans += x;
x = 1;
}
ans = points[i] - ans;
errors[id] += sqrt(ans * ans);
ans = 0;
}
} | .text
.file "errorsKernel.hip"
.globl _Z27__device_stub__errorsKernelPfS_S_ii # -- Begin function _Z27__device_stub__errorsKernelPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__errorsKernelPfS_S_ii,@function
_Z27__device_stub__errorsKernelPfS_S_ii: # @_Z27__device_stub__errorsKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12errorsKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__errorsKernelPfS_S_ii, .Lfunc_end0-_Z27__device_stub__errorsKernelPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12errorsKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12errorsKernelPfS_S_ii,@object # @_Z12errorsKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12errorsKernelPfS_S_ii
.p2align 3, 0x0
_Z12errorsKernelPfS_S_ii:
.quad _Z27__device_stub__errorsKernelPfS_S_ii
.size _Z12errorsKernelPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12errorsKernelPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__errorsKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12errorsKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12errorsKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fe400078e0203 */
/*0090*/ @P0 BRA 0x790 ; /* 0x000006f000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*00e0*/ @!P0 BRA 0x5d0 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0100*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0110*/ IADD3 R7, -R0, c[0x0][0x17c], RZ ; /* 0x00005f0000077a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0205 */
/*0140*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0170*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*0180*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0022a20000001400 */
/*0190*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 BRA 0x210 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*01c0*/ BSSY B0, 0x200 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*01d0*/ MOV R15, 0x1f0 ; /* 0x000001f0000f7802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0xe10 ; /* 0x00000c2000007944 */
/* 0x021fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ FMUL.FTZ R8, R14, R11 ; /* 0x0000000b0e087220 */
/* 0x006fe40000410000 */
/*0220*/ FMUL.FTZ R10, R11, 0.5 ; /* 0x3f0000000b0a7820 */
/* 0x000fe40000410000 */
/*0230*/ FFMA R11, -R8, R8, R14 ; /* 0x00000008080b7223 */
/* 0x000fc8000000010e */
/*0240*/ FFMA R8, R11, R10, R8 ; /* 0x0000000a0b087223 */
/* 0x000fc80000000008 */
/*0250*/ FADD R17, R8, R9 ; /* 0x0000000908117221 */
/* 0x020fca0000000000 */
/*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0280*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*0290*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0002a20000001400 */
/*02a0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 BRA 0x320 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*02d0*/ BSSY B0, 0x310 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*02e0*/ MOV R15, 0x300 ; /* 0x00000300000f7802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0xe10 ; /* 0x00000b1000007944 */
/* 0x001fea0003c00000 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x360 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0320*/ FMUL.FTZ R8, R14, R9 ; /* 0x000000090e087220 */
/* 0x006fe40000410000 */
/*0330*/ FMUL.FTZ R10, R9, 0.5 ; /* 0x3f000000090a7820 */
/* 0x000fe40000410000 */
/*0340*/ FFMA R9, -R8, R8, R14 ; /* 0x0000000808097223 */
/* 0x000fc8000000010e */
/*0350*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fc80000000008 */
/*0360*/ FADD R17, R17, R8 ; /* 0x0000000811117221 */
/* 0x000fca0000000000 */
/*0370*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0380*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea4000c1e1900 */
/*0390*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x004fc80000400000 */
/*03a0*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0002a20000001400 */
/*03b0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*03d0*/ @!P1 BRA 0x430 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*03e0*/ BSSY B0, 0x420 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*03f0*/ MOV R15, 0x410 ; /* 0x00000410000f7802 */
/* 0x000fe40000000f00 */
/*0400*/ CALL.REL.NOINC 0xe10 ; /* 0x00000a0000007944 */
/* 0x001fea0003c00000 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x470 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0430*/ FMUL.FTZ R8, R14, R9 ; /* 0x000000090e087220 */
/* 0x006fe40000410000 */
/*0440*/ FMUL.FTZ R10, R9, 0.5 ; /* 0x3f000000090a7820 */
/* 0x000fe40000410000 */
/*0450*/ FFMA R9, -R8, R8, R14 ; /* 0x0000000808097223 */
/* 0x000fc8000000010e */
/*0460*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fc80000000008 */
/*0470*/ FADD R17, R17, R8 ; /* 0x0000000811117221 */
/* 0x000fca0000000000 */
/*0480*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0490*/ LDG.E R4, [R4.64+0xc] ; /* 0x00000c0404047981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FMUL R14, R4, R4 ; /* 0x00000004040e7220 */
/* 0x004fc80000400000 */
/*04b0*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0002a20000001400 */
/*04c0*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*04e0*/ @!P1 BRA 0x550 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*04f0*/ BSSY B0, 0x530 ; /* 0x0000003000007945 */
/* 0x006fe20003800000 */
/*0500*/ MOV R15, 0x520 ; /* 0x00000520000f7802 */
/* 0x000fe40000000f00 */
/*0510*/ CALL.REL.NOINC 0xe10 ; /* 0x000008f000007944 */
/* 0x001fea0003c00000 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ MOV R9, R8 ; /* 0x0000000800097202 */
/* 0x000fe20000000f00 */
/*0540*/ BRA 0x590 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0550*/ FMUL.FTZ R9, R14, R11 ; /* 0x0000000b0e097220 */
/* 0x006fe40000410000 */
/*0560*/ FMUL.FTZ R5, R11, 0.5 ; /* 0x3f0000000b057820 */
/* 0x000fe40000410000 */
/*0570*/ FFMA R4, -R9, R9, R14 ; /* 0x0000000909047223 */
/* 0x000fc8000000010e */
/*0580*/ FFMA R9, R4, R5, R9 ; /* 0x0000000504097223 */
/* 0x000fc80000000009 */
/*0590*/ FADD R9, R17, R9 ; /* 0x0000000911097221 */
/* 0x000fe20000000000 */
/*05a0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*05c0*/ @P0 BRA 0x120 ; /* 0xfffffb5000000947 */
/* 0x000fea000383ffff */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000564000c1e1900 */
/*0600*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x002fd400000001ff */
/*0610*/ IMAD.WIDE R8, R6, R9, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x000fcc00078e0209 */
/*0620*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x008fc80000400000 */
/*0640*/ MUFU.RSQ R7, R14 ; /* 0x0000000e00077308 */
/* 0x0002e20000001400 */
/*0650*/ IADD3 R5, R14, -0xd000000, RZ ; /* 0xf30000000e057810 */
/* 0x000fc80007ffe0ff */
/*0660*/ ISETP.GT.U32.AND P0, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f04070 */
/*0670*/ @!P0 BRA 0x6e0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0680*/ BSSY B0, 0x6c0 ; /* 0x0000003000007945 */
/* 0x00afe20003800000 */
/*0690*/ MOV R15, 0x6b0 ; /* 0x000006b0000f7802 */
/* 0x000fe40000000f00 */
/*06a0*/ CALL.REL.NOINC 0xe10 ; /* 0x0000076000007944 */
/* 0x025fea0003c00000 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*06d0*/ BRA 0x720 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*06e0*/ FMUL.FTZ R5, R14, R7 ; /* 0x000000070e057220 */
/* 0x00afe40000410000 */
/*06f0*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*0700*/ FFMA R8, -R5, R5, R14 ; /* 0x0000000505087223 */
/* 0x000fc8000000010e */
/*0710*/ FFMA R5, R8, R7, R5 ; /* 0x0000000708057223 */
/* 0x000fc60000000005 */
/*0720*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0730*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x020fc60000000000 */
/*0740*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0750*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0003f6000c101904 */
/*0760*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0770*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0780*/ BRA 0x600 ; /* 0xfffffe7000007947 */
/* 0x000fea000383ffff */
/*0790*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*07a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x001fe200000001ff */
/*07b0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fc80000000f00 */
/*07c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*07d0*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fd60000000f00 */
/*07e0*/ @!P0 BRA 0xbc0 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*07f0*/ IADD3 R6, R7, -0x1, RZ ; /* 0xffffffff07067810 */
/* 0x000fe20007ffe0ff */
/*0800*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0b7435 */
/* 0x000fc600000001ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0820*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fd600078ec0ff */
/*0830*/ @!P0 BRA 0xb40 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0840*/ IADD3 R8, -R6, R7, RZ ; /* 0x0000000706087210 */
/* 0x000fe40007ffe1ff */
/*0850*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fe40000000f00 */
/*0860*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0870*/ @!P0 BRA 0xad0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*08a0*/ @!P1 BRA 0x9f0 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*08b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08c0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*08d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*08f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0900*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0910*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0920*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0930*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0940*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0950*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0960*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0970*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0980*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0990*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09a0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09b0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09c0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*09d0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe200078e02ff */
/*09e0*/ @P1 BRA 0x8c0 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*09f0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0a00*/ @!P1 BRA 0xab0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R11, R11, R4.reuse, RZ ; /* 0x000000040b0b7224 */
/* 0x080fe200078e02ff */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a50*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a60*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a70*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a80*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0a90*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0aa0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fe400078e02ff */
/*0ab0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0ac0*/ @!P0 BRA 0xb40 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0ae0*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc600078e02ff */
/*0af0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0b00*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b10*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b20*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0b30*/ @P0 BRA 0xad0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0b40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0b50*/ @!P0 BRA 0xbc0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fd800078e02ff */
/*0b80*/ @P0 ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600080c */
/* 0x000fe20003f25270 */
/*0b90*/ @P0 IMAD R9, R11, R4, RZ ; /* 0x000000040b090224 */
/* 0x000fc600078e02ff */
/*0ba0*/ @P0 SEL R6, R4, 0x1, P1 ; /* 0x0000000104060807 */
/* 0x000fca0000800000 */
/*0bb0*/ @P0 IMAD R11, R6, R9, RZ ; /* 0x00000009060b0224 */
/* 0x000fe400078e02ff */
/*0bc0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0bd0*/ IMAD R8, R0, c[0x0][0x178], R7 ; /* 0x00005e0000087a24 */
/* 0x000fd200078e0207 */
/*0be0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e020d */
/*0bf0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000ea20000201400 */
/*0c10*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0c20*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f06270 */
/*0c30*/ FMUL R6, R11, R8 ; /* 0x000000080b067220 */
/* 0x004fcc0000400000 */
/*0c40*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0c50*/ I2F R10, R6 ; /* 0x00000006000a7306 */
/* 0x001e240000201400 */
/*0c60*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x001fe20000000000 */
/*0c70*/ @!P0 BRA 0x7c0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0c80*/ IMAD.WIDE R6, R4, R13, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fcc00078e020d */
/*0c90*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0ca0*/ BSSY B0, 0xda0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0cb0*/ FADD R5, -R5, R6 ; /* 0x0000000605057221 */
/* 0x004fc80000000100 */
/*0cc0*/ FMUL R14, R5, R5 ; /* 0x00000005050e7220 */
/* 0x000fc80000400000 */
/*0cd0*/ MUFU.RSQ R9, R14 ; /* 0x0000000e00097308 */
/* 0x0000620000001400 */
/*0ce0*/ IADD3 R5, R14, -0xd000000, RZ ; /* 0xf30000000e057810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.GT.U32.AND P0, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f04070 */
/*0d00*/ @!P0 BRA 0xd50 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0d10*/ MOV R15, 0xd30 ; /* 0x00000d30000f7802 */
/* 0x003fe40000000f00 */
/*0d20*/ CALL.REL.NOINC 0xe10 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0d30*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0d40*/ BRA 0xd90 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0d50*/ FMUL.FTZ R5, R14, R9 ; /* 0x000000090e057220 */
/* 0x003fe40000410000 */
/*0d60*/ FMUL.FTZ R7, R9, 0.5 ; /* 0x3f00000009077820 */
/* 0x000fe40000410000 */
/*0d70*/ FFMA R6, -R5, R5, R14 ; /* 0x0000000505067223 */
/* 0x000fc8000000010e */
/*0d80*/ FFMA R5, R6, R7, R5 ; /* 0x0000000706057223 */
/* 0x000fe40000000005 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0db0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f06270 */
/*0dd0*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x004fca0000000000 */
/*0de0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*0df0*/ @!P0 BRA 0x7a0 ; /* 0xfffff9a000008947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000782c0ff */
/*0e20*/ @!P1 MOV R8, R14 ; /* 0x0000000e00089202 */
/* 0x000fe20000000f00 */
/*0e30*/ @!P1 BRA 0xf40 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0e40*/ FSETP.GEU.FTZ.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fda0003f3e000 */
/*0e50*/ @!P1 MOV R8, 0x7fffffff ; /* 0x7fffffff00089802 */
/* 0x000fe20000000f00 */
/*0e60*/ @!P1 BRA 0xf40 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0e70*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3c200 */
/*0e80*/ @P1 FADD.FTZ R8, R14, 1 ; /* 0x3f8000000e081421 */
/* 0x000fe20000010000 */
/*0e90*/ @P1 BRA 0xf40 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0ea0*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3d200 */
/*0eb0*/ @P1 FFMA R10, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0a1823 */
/* 0x000fc800000000ff */
/*0ec0*/ @P1 MUFU.RSQ R11, R10 ; /* 0x0000000a000b1308 */
/* 0x000e240000001400 */
/*0ed0*/ @P1 FMUL.FTZ R13, R10, R11 ; /* 0x0000000b0a0d1220 */
/* 0x001fe40000410000 */
/*0ee0*/ @P1 FMUL.FTZ R11, R11, 0.5 ; /* 0x3f0000000b0b1820 */
/* 0x000fe40000410000 */
/*0ef0*/ @P1 FADD.FTZ R8, -R13, -RZ ; /* 0x800000ff0d081221 */
/* 0x000fc80000010100 */
/*0f00*/ @P1 FFMA R12, R13, R8, R10 ; /* 0x000000080d0c1223 */
/* 0x000fe2000000000a */
/*0f10*/ @!P1 MOV R8, R14 ; /* 0x0000000e00089202 */
/* 0x000fc60000000f00 */
/*0f20*/ @P1 FFMA R11, R12, R11, R13 ; /* 0x0000000b0c0b1223 */
/* 0x000fc8000000000d */
/*0f30*/ @P1 FMUL.FTZ R8, R11, 2.3283064365386962891e-10 ; /* 0x2f8000000b081820 */
/* 0x000fe40000410000 */
/*0f40*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0f50*/ MOV R10, R15 ; /* 0x0000000f000a7202 */
/* 0x000fca0000000f00 */
/*0f60*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0900a007950 */
/* 0x000fea0003c3ffff */
/*0f70*/ BRA 0xf70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12errorsKernelPfS_S_ii
.globl _Z12errorsKernelPfS_S_ii
.p2align 8
.type _Z12errorsKernelPfS_S_ii,@function
_Z12errorsKernelPfS_S_ii:
s_load_b32 s8, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v2, s[2:3]
s_clause 0x1
s_load_b32 s9, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s9, 0
v_mul_lo_u32 v5, v0, s9
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e64 s0, 1, v0
s_mov_b32 s3, 0
s_mov_b32 s2, s3
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_add_i32 s2, s2, 1
global_load_b32 v0, v1, s[10:11]
s_cmp_eq_u32 s2, s8
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v0
v_mul_f32_e32 v6, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_sqrt_f32_e32 v6, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v0
v_fma_f32 v10, -v8, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s1, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s1, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v6, v0, vcc_lo
v_add_f32_e32 v4, v4, v0
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_mov_b32_e32 v6, v1
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v6, 0
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v0, s1, v5
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, s9
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v0, v[7:8], off
v_cvt_f32_i32_e32 v7, s10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v7
v_cvt_i32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_add_f32_e32 v6, v6, v0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_mov_b32 s10, 1
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_5
s_mov_b32 s11, 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s11, s11, 1
s_mul_i32 s10, s10, s2
s_cmp_ge_u32 s11, s1
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12errorsKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12errorsKernelPfS_S_ii, .Lfunc_end0-_Z12errorsKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12errorsKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z12errorsKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006019a_00000000-6_errorsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12errorsKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
.globl _Z12errorsKernelPfS_S_ii
.type _Z12errorsKernelPfS_S_ii, @function
_Z12errorsKernelPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12errorsKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12errorsKernelPfS_S_ii, .-_Z12errorsKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12errorsKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12errorsKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "errorsKernel.hip"
.globl _Z27__device_stub__errorsKernelPfS_S_ii # -- Begin function _Z27__device_stub__errorsKernelPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__errorsKernelPfS_S_ii,@function
_Z27__device_stub__errorsKernelPfS_S_ii: # @_Z27__device_stub__errorsKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12errorsKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__errorsKernelPfS_S_ii, .Lfunc_end0-_Z27__device_stub__errorsKernelPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12errorsKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12errorsKernelPfS_S_ii,@object # @_Z12errorsKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12errorsKernelPfS_S_ii
.p2align 3, 0x0
_Z12errorsKernelPfS_S_ii:
.quad _Z27__device_stub__errorsKernelPfS_S_ii
.size _Z12errorsKernelPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12errorsKernelPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__errorsKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12errorsKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void noarg() {}
extern "C" __global__ void simple_add(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
A[id] += 1.0;
}
extern "C" __global__ void four_mad(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float f = A[id];
f *= 41.0;
f += 37.0;
f *= 11.0;
f += 23.0;
f *= 2.0;
f += 13.0;
f *= 3.0;
f += 7.0;
A[id] = f;
}
#define PEAK_FLOP_MADD \
r0 = r1*r8+r0; \
r1 = r15*r9+r2; \
r2 = r14*r10+r4; \
r3 = r13*r11+r6; \
r4 = r12*r12+r8; \
r5 = r11*r13+r10; \
r6 = r10*r14+r12; \
r7 = r9*r15+r14; \
r8 = r7*r0+r1; \
r9 = r8*r1+r3; \
r10 = r6*r2+r5; \
r11 = r5*r3+r7; \
r12 = r4*r4+r9; \
r13 = r3*r5+r11; \
r14 = r2*r6+r13; \
r15 = r0*r7+r15; \
/**/
extern "C" __global__ void peak_flop(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
for(int i=0; i<50; i++) {
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
}
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
}
extern "C" __global__ void peak_flop_empty(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
} | .file "tmpxft_001a6487_00000000-6_micro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5noargvv
.type _Z23__device_stub__Z5noargvv, @function
_Z23__device_stub__Z5noargvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq noarg(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z5noargvv, .-_Z23__device_stub__Z5noargvv
.globl noarg
.type noarg, @function
noarg:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5noargvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size noarg, .-noarg
.globl _Z30__device_stub__Z10simple_addPfPf
.type _Z30__device_stub__Z10simple_addPfPf, @function
_Z30__device_stub__Z10simple_addPfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq simple_add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z10simple_addPfPf, .-_Z30__device_stub__Z10simple_addPfPf
.globl simple_add
.type simple_add, @function
simple_add:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10simple_addPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size simple_add, .-simple_add
.globl _Z27__device_stub__Z8four_madPfPf
.type _Z27__device_stub__Z8four_madPfPf, @function
_Z27__device_stub__Z8four_madPfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq four_mad(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z27__device_stub__Z8four_madPfPf, .-_Z27__device_stub__Z8four_madPfPf
.globl four_mad
.type four_mad, @function
four_mad:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8four_madPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size four_mad, .-four_mad
.globl _Z28__device_stub__Z9peak_flopPfPf
.type _Z28__device_stub__Z9peak_flopPfPf, @function
_Z28__device_stub__Z9peak_flopPfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq peak_flop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z28__device_stub__Z9peak_flopPfPf, .-_Z28__device_stub__Z9peak_flopPfPf
.globl peak_flop
.type peak_flop, @function
peak_flop:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9peak_flopPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size peak_flop, .-peak_flop
.globl _Z35__device_stub__Z15peak_flop_emptyPfPf
.type _Z35__device_stub__Z15peak_flop_emptyPfPf, @function
_Z35__device_stub__Z15peak_flop_emptyPfPf:
.LFB2059:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq peak_flop_empty(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z35__device_stub__Z15peak_flop_emptyPfPf, .-_Z35__device_stub__Z15peak_flop_emptyPfPf
.globl peak_flop_empty
.type peak_flop_empty, @function
peak_flop_empty:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15peak_flop_emptyPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size peak_flop_empty, .-peak_flop_empty
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "peak_flop_empty"
.LC1:
.string "peak_flop"
.LC2:
.string "four_mad"
.LC3:
.string "simple_add"
.LC4:
.string "noarg"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq peak_flop_empty(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq peak_flop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq four_mad(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq simple_add(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq noarg(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void noarg() {}
extern "C" __global__ void simple_add(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
A[id] += 1.0;
}
extern "C" __global__ void four_mad(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float f = A[id];
f *= 41.0;
f += 37.0;
f *= 11.0;
f += 23.0;
f *= 2.0;
f += 13.0;
f *= 3.0;
f += 7.0;
A[id] = f;
}
#define PEAK_FLOP_MADD \
r0 = r1*r8+r0; \
r1 = r15*r9+r2; \
r2 = r14*r10+r4; \
r3 = r13*r11+r6; \
r4 = r12*r12+r8; \
r5 = r11*r13+r10; \
r6 = r10*r14+r12; \
r7 = r9*r15+r14; \
r8 = r7*r0+r1; \
r9 = r8*r1+r3; \
r10 = r6*r2+r5; \
r11 = r5*r3+r7; \
r12 = r4*r4+r9; \
r13 = r3*r5+r11; \
r14 = r2*r6+r13; \
r15 = r0*r7+r15; \
/**/
extern "C" __global__ void peak_flop(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
for(int i=0; i<50; i++) {
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
}
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
}
extern "C" __global__ void peak_flop_empty(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
} | #include <hip/hip_runtime.h>
extern "C" __global__ void noarg() {}
extern "C" __global__ void simple_add(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
A[id] += 1.0;
}
extern "C" __global__ void four_mad(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float f = A[id];
f *= 41.0;
f += 37.0;
f *= 11.0;
f += 23.0;
f *= 2.0;
f += 13.0;
f *= 3.0;
f += 7.0;
A[id] = f;
}
#define PEAK_FLOP_MADD \
r0 = r1*r8+r0; \
r1 = r15*r9+r2; \
r2 = r14*r10+r4; \
r3 = r13*r11+r6; \
r4 = r12*r12+r8; \
r5 = r11*r13+r10; \
r6 = r10*r14+r12; \
r7 = r9*r15+r14; \
r8 = r7*r0+r1; \
r9 = r8*r1+r3; \
r10 = r6*r2+r5; \
r11 = r5*r3+r7; \
r12 = r4*r4+r9; \
r13 = r3*r5+r11; \
r14 = r2*r6+r13; \
r15 = r0*r7+r15; \
/**/
extern "C" __global__ void peak_flop(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
for(int i=0; i<50; i++) {
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
}
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
}
extern "C" __global__ void peak_flop_empty(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void noarg() {}
extern "C" __global__ void simple_add(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
A[id] += 1.0;
}
extern "C" __global__ void four_mad(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float f = A[id];
f *= 41.0;
f += 37.0;
f *= 11.0;
f += 23.0;
f *= 2.0;
f += 13.0;
f *= 3.0;
f += 7.0;
A[id] = f;
}
#define PEAK_FLOP_MADD \
r0 = r1*r8+r0; \
r1 = r15*r9+r2; \
r2 = r14*r10+r4; \
r3 = r13*r11+r6; \
r4 = r12*r12+r8; \
r5 = r11*r13+r10; \
r6 = r10*r14+r12; \
r7 = r9*r15+r14; \
r8 = r7*r0+r1; \
r9 = r8*r1+r3; \
r10 = r6*r2+r5; \
r11 = r5*r3+r7; \
r12 = r4*r4+r9; \
r13 = r3*r5+r11; \
r14 = r2*r6+r13; \
r15 = r0*r7+r15; \
/**/
extern "C" __global__ void peak_flop(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
for(int i=0; i<50; i++) {
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
}
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
}
extern "C" __global__ void peak_flop_empty(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected noarg
.globl noarg
.p2align 8
.type noarg,@function
noarg:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel noarg
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size noarg, .Lfunc_end0-noarg
.section .AMDGPU.csdata,"",@progbits
.text
.protected simple_add
.globl simple_add
.p2align 8
.type simple_add,@function
simple_add:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel simple_add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size simple_add, .Lfunc_end1-simple_add
.section .AMDGPU.csdata,"",@progbits
.text
.protected four_mad
.globl four_mad
.p2align 8
.type four_mad,@function
four_mad:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0x42240000
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fmaak_f32 v2, s0, v2, 0x42140000
s_mov_b32 s0, 0x41300000
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v2, s0, v2, 0x41b80000
s_mov_b32 s0, 0x40400000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v2, 2.0, v2, 0x41500000
v_fmaak_f32 v2, s0, v2, 0x40e00000
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel four_mad
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size four_mad, .Lfunc_end2-four_mad
.section .AMDGPU.csdata,"",@progbits
.text
.protected peak_flop
.globl peak_flop
.p2align 8
.type peak_flop,@function
peak_flop:
s_load_b32 s2, s[0:1], 0x14
s_mov_b32 s3, 0x3f1a36e2
s_mov_b32 s5, 0x3f43a92a
s_mov_b32 s4, 0x30553261
s_mov_b32 s7, 0x3f4d7dbf
s_mov_b32 s6, 0x487fcb92
s_mov_b32 s9, 0x3f50624d
s_mov_b32 s8, 0xd2f1a9fc
s_mov_b32 s11, 0x3f5205bc
s_mov_b32 s10, 0x1a36e2f
s_mov_b32 s13, 0x3f554c98
s_mov_b32 s12, 0x5f06f694
s_mov_b32 s14, 0x8db8bac7
s_mov_b32 s17, 0x3f589374
s_mov_b32 s16, 0xbc6a7efa
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0xeb1c432d
s_mov_b32 s15, 0x3f56f006
v_cvt_f64_i32_e32 v[2:3], v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[4:5], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f2a36e2
v_mul_f64 v[6:7], v[2:3], s[4:5]
v_mul_f64 v[20:21], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f3a36e2
s_mov_b32 s5, 0x3f53a92a
v_mul_f64 v[24:25], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f4a36e2
v_mul_f64 v[9:10], v[2:3], s[6:7]
v_mul_f64 v[11:12], v[2:3], s[8:9]
v_mul_f64 v[14:15], v[2:3], s[10:11]
v_mul_f64 v[16:17], v[2:3], s[12:13]
v_mul_f64 v[18:19], v[2:3], s[14:15]
v_mul_f64 v[22:23], v[2:3], s[4:5]
v_mul_f64 v[26:27], v[2:3], s[2:3]
v_mul_f64 v[28:29], v[2:3], s[16:17]
s_mov_b32 s2, 50
v_cvt_f32_f64_e32 v2, v[4:5]
v_cvt_f32_f64_e32 v8, v[6:7]
v_cvt_f32_f64_e32 v6, v[20:21]
v_cvt_f32_f64_e32 v5, v[24:25]
v_cvt_f32_f64_e32 v10, v[9:10]
v_cvt_f32_f64_e32 v13, v[11:12]
v_cvt_f32_f64_e32 v11, v[14:15]
v_cvt_f32_f64_e32 v12, v[16:17]
v_cvt_f32_f64_e32 v9, v[18:19]
v_cvt_f32_f64_e32 v7, v[22:23]
v_cvt_f32_f64_e32 v4, v[26:27]
v_cvt_f32_f64_e32 v0, v[28:29]
v_mov_b32_e32 v3, v2
.LBB3_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v3, v2, v4 :: v_dual_fmac_f32 v4, v7, v7
v_dual_fmac_f32 v5, v13, v9 :: v_dual_fmac_f32 v8, v11, v12
v_fma_f32 v2, v11, v12, v13
v_dual_fmac_f32 v7, v13, v9 :: v_dual_fmac_f32 v6, v10, v0
v_fmac_f32_e32 v9, v10, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_fma_f32 v10, v2, v8, v9
v_fma_f32 v11, v3, v9, v6
v_fmac_f32_e32 v0, v3, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v12, v2, v8, v10
v_fmac_f32_e32 v3, v6, v11
v_fma_f32 v8, v6, v11, v8
v_fma_f32 v2, v7, v5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v7, v5, v12
v_fma_f32 v13, v4, v4, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v6, v10, v12, v2
v_dual_fmac_f32 v5, v0, v8 :: v_dual_fmac_f32 v4, v2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v8
v_dual_fmac_f32 v7, v10, v12 :: v_dual_fmac_f32 v0, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v2, v6, v7, v9
v_fma_f32 v8, v3, v9, v5
v_fma_f32 v10, v6, v7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v7, v5, v8, v7
v_fma_f32 v6, v4, v13, v6
v_fmac_f32_e32 v3, v5, v8
v_fma_f32 v9, v4, v13, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v12, v11, v11, v7
v_fmac_f32_e32 v4, v0, v7
v_dual_fmac_f32 v8, v12, v12 :: v_dual_fmac_f32 v11, v6, v9
v_dual_fmac_f32 v12, v6, v9 :: v_dual_fmac_f32 v9, v0, v7
v_fmac_f32_e32 v13, v2, v10
v_fma_f32 v2, v2, v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v0, v3, v9
v_fma_f32 v6, v3, v9, v4
v_fma_f32 v5, v2, v13, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, v4, v6, v13
v_fma_f32 v7, v2, v13, v5
v_fma_f32 v2, v11, v12, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, v8, v8, v10
v_fma_f32 v9, v11, v12, v7
v_fmac_f32_e32 v12, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v8, v2, v9 :: v_dual_fmac_f32 v3, v4, v6
v_fma_f32 v4, v5, v7, v2
v_fmac_f32_e32 v6, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v10
v_dual_fmac_f32 v11, v0, v10 :: v_dual_fmac_f32 v0, v3, v9
v_fma_f32 v2, v4, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v3, v9, v11
v_fma_f32 v7, v4, v12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v10, v11, v5, v12
v_fma_f32 v4, v8, v13, v4
v_fma_f32 v9, v8, v13, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v12, v6, v6, v10
v_fmac_f32_e32 v13, v2, v7
v_fma_f32 v2, v2, v7, v4
v_fmac_f32_e32 v8, v0, v10
v_fmac_f32_e32 v6, v4, v9
v_fmac_f32_e32 v3, v11, v5
v_fmac_f32_e32 v5, v12, v12
v_fmac_f32_e32 v12, v4, v9
v_fmac_f32_e32 v9, v0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v4, v2, v13, v9
v_fma_f32 v7, v3, v9, v8
v_fmac_f32_e32 v0, v3, v9
v_fma_f32 v10, v2, v13, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v11, v8, v7, v13
v_fma_f32 v2, v6, v12, v2
v_fma_f32 v9, v6, v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v13, v5, v5, v11
v_fmac_f32_e32 v6, v0, v11
v_fmac_f32_e32 v3, v8, v7
v_fmac_f32_e32 v5, v2, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v11
v_fma_f32 v8, v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v0, v3, v9 :: v_dual_fmac_f32 v3, v6, v8
v_fmac_f32_e32 v12, v4, v10
v_fma_f32 v4, v4, v10, v2
v_fma_f32 v11, v6, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, v4, v12, v9
v_fma_f32 v10, v4, v12, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v7, v7, v11
v_fmac_f32_e32 v8, v12, v12
v_fma_f32 v4, v5, v13, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v9, v5, v13, v10
v_fmac_f32_e32 v13, v2, v10
v_fmac_f32_e32 v5, v0, v11
v_fma_f32 v2, v2, v10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v4, v9
v_fmac_f32_e32 v12, v4, v9
v_fmac_f32_e32 v9, v0, v11
v_fma_f32 v4, v2, v13, v9
v_fmac_f32_e32 v0, v3, v9
v_fma_f32 v6, v3, v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, v2, v13, v4
v_fmac_f32_e32 v3, v5, v6
v_fma_f32 v11, v5, v6, v13
v_fma_f32 v2, v7, v12, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v9, v7, v12, v10
v_fmac_f32_e32 v12, v4, v10
v_fma_f32 v13, v8, v8, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v4, v4, v10, v2
v_fmac_f32_e32 v8, v2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v11
v_dual_fmac_f32 v7, v0, v11 :: v_dual_fmac_f32 v0, v3, v9
v_fma_f32 v2, v4, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v3, v9, v7
v_fma_f32 v10, v4, v12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v11, v7, v5, v12
v_fma_f32 v4, v8, v13, v4
v_fma_f32 v9, v8, v13, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v12, v6, v6, v11
v_fmac_f32_e32 v13, v2, v10
v_fma_f32 v2, v2, v10, v4
v_fmac_f32_e32 v8, v0, v11
v_fmac_f32_e32 v6, v4, v9
v_fmac_f32_e32 v3, v7, v5
v_fmac_f32_e32 v5, v12, v12
v_fmac_f32_e32 v12, v4, v9
v_fmac_f32_e32 v9, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v4, v2, v13, v9
v_fma_f32 v7, v3, v9, v8
v_fmac_f32_e32 v0, v3, v9
v_fma_f32 v10, v2, v13, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v11, v8, v7, v13
v_fma_f32 v2, v6, v12, v2
v_fma_f32 v9, v6, v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v13, v5, v5, v11
v_fmac_f32_e32 v6, v0, v11
v_fmac_f32_e32 v3, v8, v7
v_fmac_f32_e32 v5, v2, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v11
v_fma_f32 v8, v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v0, v3, v9 :: v_dual_fmac_f32 v3, v6, v8
v_fmac_f32_e32 v12, v4, v10
v_fma_f32 v4, v4, v10, v2
v_fma_f32 v11, v6, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, v4, v12, v9
v_fma_f32 v10, v4, v12, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v7, v7, v11
v_fmac_f32_e32 v8, v12, v12
v_fma_f32 v4, v5, v13, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v9, v5, v13, v10
v_fmac_f32_e32 v13, v2, v10
v_fmac_f32_e32 v5, v0, v11
v_fma_f32 v2, v2, v10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v4, v9
v_fmac_f32_e32 v12, v4, v9
v_fmac_f32_e32 v9, v0, v11
v_fma_f32 v4, v2, v13, v9
v_fmac_f32_e32 v0, v3, v9
v_fma_f32 v10, v3, v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, v2, v13, v4
v_fmac_f32_e32 v3, v5, v10
v_fma_f32 v11, v5, v10, v13
v_fma_f32 v2, v7, v12, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v9, v7, v12, v6
v_fmac_f32_e32 v12, v4, v6
v_fma_f32 v13, v8, v8, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v4, v4, v6, v2
v_fmac_f32_e32 v8, v2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v13, v13
v_fmac_f32_e32 v13, v2, v9
v_fmac_f32_e32 v9, v0, v11
v_dual_fmac_f32 v7, v0, v11 :: v_dual_fmac_f32 v0, v3, v9
v_fma_f32 v2, v4, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v3, v9, v7
v_fma_f32 v5, v4, v12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v6, v7, v11, v12
v_fma_f32 v4, v8, v13, v4
v_fma_f32 v9, v8, v13, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v12, v10, v10, v6
v_dual_fmac_f32 v3, v7, v11 :: v_dual_fmac_f32 v8, v0, v6
v_fmac_f32_e32 v10, v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v12
v_fmac_f32_e32 v12, v4, v9
v_fmac_f32_e32 v9, v0, v6
v_fmac_f32_e32 v0, v3, v9
v_fmac_f32_e32 v13, v2, v5
v_fma_f32 v5, v2, v5, v4
v_fma_f32 v2, v3, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, v5, v13, v9
v_fma_f32 v7, v8, v2, v13
v_fmac_f32_e32 v3, v8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v6, v5, v13, v4
v_fma_f32 v5, v10, v12, v5
v_fma_f32 v13, v11, v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v9, v10, v12, v6
v_fmac_f32_e32 v12, v4, v6
v_fma_f32 v4, v4, v6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v2, v13, v13
v_dual_fmac_f32 v10, v0, v7 :: v_dual_fmac_f32 v11, v5, v9
v_fmac_f32_e32 v13, v5, v9
v_fmac_f32_e32 v9, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v5, v4, v12, v9
v_fma_f32 v6, v3, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v4, v12, v5
v_fma_f32 v8, v10, v6, v12
v_fma_f32 v4, v11, v13, v4
v_dual_fmac_f32 v0, v3, v9 :: v_dual_fmac_f32 v3, v10, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v9, v11, v13, v7
v_fmac_f32_e32 v13, v5, v7
v_fma_f32 v14, v2, v2, v8
v_fma_f32 v7, v5, v7, v4
v_fmac_f32_e32 v2, v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v14, v14
v_fmac_f32_e32 v14, v4, v9
v_fmac_f32_e32 v9, v0, v8
v_dual_fmac_f32 v11, v0, v8 :: v_dual_fmac_f32 v0, v3, v9
v_fma_f32 v4, v7, v13, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v3, v9, v11
v_fma_f32 v10, v7, v13, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v12, v11, v5, v13
v_fma_f32 v7, v2, v14, v7
v_fmac_f32_e32 v3, v11, v5
v_fma_f32 v15, v2, v14, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v8, v6, v6, v12
v_fmac_f32_e32 v2, v0, v12
v_fmac_f32_e32 v14, v4, v10
v_fma_f32 v16, v4, v10, v7
v_dual_fmac_f32 v6, v7, v15 :: v_dual_fmac_f32 v5, v8, v8
v_dual_fmac_f32 v8, v7, v15 :: v_dual_fmac_f32 v15, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v6, v8, v16
v_fma_f32 v4, v3, v15, v2
v_fma_f32 v11, v16, v14, v15
v_fmac_f32_e32 v0, v3, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v2, v4, v14
v_fma_f32 v12, v16, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v5, v5, v10
v_fma_f32 v9, v6, v8, v12
s_cbranch_scc0 .LBB3_1
v_add_f32_e32 v2, v2, v6
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v14
v_add_f32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v16
v_add_f32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v15
v_add_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v10
v_add_f32_e32 v2, v2, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v11
v_add_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v12
v_add_f32_e32 v4, v2, v9
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v3, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel peak_flop
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size peak_flop, .Lfunc_end3-peak_flop
.section .AMDGPU.csdata,"",@progbits
.text
.protected peak_flop_empty
.globl peak_flop_empty
.p2align 8
.type peak_flop_empty,@function
peak_flop_empty:
s_load_b32 s2, s[0:1], 0x14
s_mov_b32 s3, 0x3f1a36e2
s_mov_b32 s5, 0x3f33a92a
s_mov_b32 s4, 0x30553261
s_mov_b32 s7, 0x3f40624d
s_mov_b32 s6, 0xd2f1a9fc
s_mov_b32 s9, 0x3f46f006
s_mov_b32 s8, 0x8db8bac7
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0xeb1c432d
v_cvt_f64_i32_e32 v[2:3], v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[4:5], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f2a36e2
v_mul_f64 v[8:9], v[2:3], s[4:5]
v_mul_f64 v[6:7], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f3a36e2
v_mul_f64 v[12:13], v[2:3], s[6:7]
v_mul_f64 v[10:11], v[2:3], s[2:3]
s_mov_b32 s5, 0x3f43a92a
v_mul_f64 v[16:17], v[2:3], s[8:9]
v_mul_f64 v[14:15], v[2:3], s[4:5]
s_mov_b32 s3, 0x3f4a36e2
s_mov_b32 s7, 0x3f50624d
v_mul_f64 v[18:19], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f4d7dbf
s_mov_b32 s2, 0x487fcb92
s_mov_b32 s5, 0x3f53a92a
v_mul_f64 v[20:21], v[2:3], s[2:3]
s_mov_b32 s3, 0x3f5205bc
s_mov_b32 s2, 0x1a36e2f
s_mov_b32 s9, 0x3f56f006
v_cvt_f32_f64_e32 v22, v[4:5]
v_mul_f64 v[4:5], v[2:3], s[6:7]
v_cvt_f32_f64_e32 v23, v[8:9]
v_cvt_f32_f64_e32 v0, v[6:7]
v_mul_f64 v[6:7], v[2:3], s[2:3]
v_mul_f64 v[8:9], v[2:3], s[4:5]
v_cvt_f32_f64_e32 v24, v[10:11]
s_mov_b32 s3, 0x3f554c98
s_mov_b32 s2, 0x5f06f694
v_cvt_f32_f64_e32 v25, v[12:13]
v_mul_f64 v[10:11], v[2:3], s[2:3]
v_cvt_f32_f64_e32 v14, v[14:15]
v_mul_f64 v[12:13], v[2:3], s[8:9]
s_mov_b32 s3, 0x3f589374
s_mov_b32 s2, 0xbc6a7efa
v_cvt_f32_f64_e32 v15, v[16:17]
v_mul_f64 v[2:3], v[2:3], s[2:3]
v_cvt_f32_f64_e32 v16, v[18:19]
v_cvt_f32_f64_e32 v17, v[20:21]
v_cvt_f32_f64_e32 v4, v[4:5]
v_add_f32_e32 v0, v22, v0
v_cvt_f32_f64_e32 v5, v[6:7]
v_cvt_f32_f64_e32 v6, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, v0, v23
v_cvt_f32_f64_e32 v7, v[10:11]
v_cvt_f32_f64_e32 v8, v[12:13]
v_add_f32_e32 v0, v0, v24
v_cvt_f32_f64_e32 v3, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v25
v_add_f32_e32 v0, v0, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v15
v_add_f32_e32 v0, v0, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v17
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v7
v_add_f32_e32 v0, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_f32_e32 v2, v3, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel peak_flop_empty
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size peak_flop_empty, .Lfunc_end4-peak_flop_empty
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: noarg
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: noarg.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: simple_add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: simple_add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: four_mad
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: four_mad.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: peak_flop
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: peak_flop.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: peak_flop_empty
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: peak_flop_empty.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void noarg() {}
extern "C" __global__ void simple_add(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
A[id] += 1.0;
}
extern "C" __global__ void four_mad(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float f = A[id];
f *= 41.0;
f += 37.0;
f *= 11.0;
f += 23.0;
f *= 2.0;
f += 13.0;
f *= 3.0;
f += 7.0;
A[id] = f;
}
#define PEAK_FLOP_MADD \
r0 = r1*r8+r0; \
r1 = r15*r9+r2; \
r2 = r14*r10+r4; \
r3 = r13*r11+r6; \
r4 = r12*r12+r8; \
r5 = r11*r13+r10; \
r6 = r10*r14+r12; \
r7 = r9*r15+r14; \
r8 = r7*r0+r1; \
r9 = r8*r1+r3; \
r10 = r6*r2+r5; \
r11 = r5*r3+r7; \
r12 = r4*r4+r9; \
r13 = r3*r5+r11; \
r14 = r2*r6+r13; \
r15 = r0*r7+r15; \
/**/
extern "C" __global__ void peak_flop(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
for(int i=0; i<50; i++) {
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
PEAK_FLOP_MADD;
}
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
}
extern "C" __global__ void peak_flop_empty(float * A)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
float r0, r1, r2, r3, r4, r5, r6, r7;
float r8, r9, r10, r11, r12, r13, r14, r15;
r0 = 0.0001 * id;
r1 = 0.0001 * id;
r2 = 0.0002 * id;
r3 = 0.0003 * id;
r4 = 0.0004 * id;
r5 = 0.0005 * id;
r6 = 0.0006 * id;
r7 = 0.0007 * id;
r8 = 0.0008 * id;
r9 = 0.0009 * id;
r10 = 0.0010 * id;
r11 = 0.0011 * id;
r12 = 0.0012 * id;
r13 = 0.0013 * id;
r14 = 0.0014 * id;
r15 = 0.0015 * id;
r0 += r1 + r2 + r3 + r4 + r5 + r6 + r7 +
r8 + r9 + r10 + r11 + r12 + r13 + r14 + r15;
A[id] = r0;
} | .text
.file "micro.hip"
.globl __device_stub__noarg # -- Begin function __device_stub__noarg
.p2align 4, 0x90
.type __device_stub__noarg,@function
__device_stub__noarg: # @__device_stub__noarg
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $noarg, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__noarg, .Lfunc_end0-__device_stub__noarg
.cfi_endproc
# -- End function
.globl __device_stub__simple_add # -- Begin function __device_stub__simple_add
.p2align 4, 0x90
.type __device_stub__simple_add,@function
__device_stub__simple_add: # @__device_stub__simple_add
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $simple_add, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__simple_add, .Lfunc_end1-__device_stub__simple_add
.cfi_endproc
# -- End function
.globl __device_stub__four_mad # -- Begin function __device_stub__four_mad
.p2align 4, 0x90
.type __device_stub__four_mad,@function
__device_stub__four_mad: # @__device_stub__four_mad
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $four_mad, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size __device_stub__four_mad, .Lfunc_end2-__device_stub__four_mad
.cfi_endproc
# -- End function
.globl __device_stub__peak_flop # -- Begin function __device_stub__peak_flop
.p2align 4, 0x90
.type __device_stub__peak_flop,@function
__device_stub__peak_flop: # @__device_stub__peak_flop
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $peak_flop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size __device_stub__peak_flop, .Lfunc_end3-__device_stub__peak_flop
.cfi_endproc
# -- End function
.globl __device_stub__peak_flop_empty # -- Begin function __device_stub__peak_flop_empty
.p2align 4, 0x90
.type __device_stub__peak_flop_empty,@function
__device_stub__peak_flop_empty: # @__device_stub__peak_flop_empty
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $peak_flop_empty, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size __device_stub__peak_flop_empty, .Lfunc_end4-__device_stub__peak_flop_empty
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $noarg, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $simple_add, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $four_mad, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $peak_flop, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $peak_flop_empty, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type noarg,@object # @noarg
.section .rodata,"a",@progbits
.globl noarg
.p2align 3, 0x0
noarg:
.quad __device_stub__noarg
.size noarg, 8
.type simple_add,@object # @simple_add
.globl simple_add
.p2align 3, 0x0
simple_add:
.quad __device_stub__simple_add
.size simple_add, 8
.type four_mad,@object # @four_mad
.globl four_mad
.p2align 3, 0x0
four_mad:
.quad __device_stub__four_mad
.size four_mad, 8
.type peak_flop,@object # @peak_flop
.globl peak_flop
.p2align 3, 0x0
peak_flop:
.quad __device_stub__peak_flop
.size peak_flop, 8
.type peak_flop_empty,@object # @peak_flop_empty
.globl peak_flop_empty
.p2align 3, 0x0
peak_flop_empty:
.quad __device_stub__peak_flop_empty
.size peak_flop_empty, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "noarg"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "simple_add"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "four_mad"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "peak_flop"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "peak_flop_empty"
.size .L__unnamed_5, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__noarg
.addrsig_sym __device_stub__simple_add
.addrsig_sym __device_stub__four_mad
.addrsig_sym __device_stub__peak_flop
.addrsig_sym __device_stub__peak_flop_empty
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym noarg
.addrsig_sym simple_add
.addrsig_sym four_mad
.addrsig_sym peak_flop
.addrsig_sym peak_flop_empty
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6487_00000000-6_micro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5noargvv
.type _Z23__device_stub__Z5noargvv, @function
_Z23__device_stub__Z5noargvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq noarg(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z5noargvv, .-_Z23__device_stub__Z5noargvv
.globl noarg
.type noarg, @function
noarg:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5noargvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size noarg, .-noarg
.globl _Z30__device_stub__Z10simple_addPfPf
.type _Z30__device_stub__Z10simple_addPfPf, @function
_Z30__device_stub__Z10simple_addPfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq simple_add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z10simple_addPfPf, .-_Z30__device_stub__Z10simple_addPfPf
.globl simple_add
.type simple_add, @function
simple_add:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10simple_addPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size simple_add, .-simple_add
.globl _Z27__device_stub__Z8four_madPfPf
.type _Z27__device_stub__Z8four_madPfPf, @function
_Z27__device_stub__Z8four_madPfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq four_mad(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z27__device_stub__Z8four_madPfPf, .-_Z27__device_stub__Z8four_madPfPf
.globl four_mad
.type four_mad, @function
four_mad:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8four_madPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size four_mad, .-four_mad
.globl _Z28__device_stub__Z9peak_flopPfPf
.type _Z28__device_stub__Z9peak_flopPfPf, @function
_Z28__device_stub__Z9peak_flopPfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq peak_flop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z28__device_stub__Z9peak_flopPfPf, .-_Z28__device_stub__Z9peak_flopPfPf
.globl peak_flop
.type peak_flop, @function
peak_flop:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9peak_flopPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size peak_flop, .-peak_flop
.globl _Z35__device_stub__Z15peak_flop_emptyPfPf
.type _Z35__device_stub__Z15peak_flop_emptyPfPf, @function
_Z35__device_stub__Z15peak_flop_emptyPfPf:
.LFB2059:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq peak_flop_empty(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z35__device_stub__Z15peak_flop_emptyPfPf, .-_Z35__device_stub__Z15peak_flop_emptyPfPf
.globl peak_flop_empty
.type peak_flop_empty, @function
peak_flop_empty:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15peak_flop_emptyPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size peak_flop_empty, .-peak_flop_empty
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "peak_flop_empty"
.LC1:
.string "peak_flop"
.LC2:
.string "four_mad"
.LC3:
.string "simple_add"
.LC4:
.string "noarg"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq peak_flop_empty(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq peak_flop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq four_mad(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq simple_add(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq noarg(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "micro.hip"
.globl __device_stub__noarg # -- Begin function __device_stub__noarg
.p2align 4, 0x90
.type __device_stub__noarg,@function
__device_stub__noarg: # @__device_stub__noarg
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $noarg, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__noarg, .Lfunc_end0-__device_stub__noarg
.cfi_endproc
# -- End function
.globl __device_stub__simple_add # -- Begin function __device_stub__simple_add
.p2align 4, 0x90
.type __device_stub__simple_add,@function
__device_stub__simple_add: # @__device_stub__simple_add
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $simple_add, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__simple_add, .Lfunc_end1-__device_stub__simple_add
.cfi_endproc
# -- End function
.globl __device_stub__four_mad # -- Begin function __device_stub__four_mad
.p2align 4, 0x90
.type __device_stub__four_mad,@function
__device_stub__four_mad: # @__device_stub__four_mad
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $four_mad, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size __device_stub__four_mad, .Lfunc_end2-__device_stub__four_mad
.cfi_endproc
# -- End function
.globl __device_stub__peak_flop # -- Begin function __device_stub__peak_flop
.p2align 4, 0x90
.type __device_stub__peak_flop,@function
__device_stub__peak_flop: # @__device_stub__peak_flop
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $peak_flop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size __device_stub__peak_flop, .Lfunc_end3-__device_stub__peak_flop
.cfi_endproc
# -- End function
.globl __device_stub__peak_flop_empty # -- Begin function __device_stub__peak_flop_empty
.p2align 4, 0x90
.type __device_stub__peak_flop_empty,@function
__device_stub__peak_flop_empty: # @__device_stub__peak_flop_empty
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $peak_flop_empty, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size __device_stub__peak_flop_empty, .Lfunc_end4-__device_stub__peak_flop_empty
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $noarg, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $simple_add, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $four_mad, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $peak_flop, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $peak_flop_empty, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type noarg,@object # @noarg
.section .rodata,"a",@progbits
.globl noarg
.p2align 3, 0x0
noarg:
.quad __device_stub__noarg
.size noarg, 8
.type simple_add,@object # @simple_add
.globl simple_add
.p2align 3, 0x0
simple_add:
.quad __device_stub__simple_add
.size simple_add, 8
.type four_mad,@object # @four_mad
.globl four_mad
.p2align 3, 0x0
four_mad:
.quad __device_stub__four_mad
.size four_mad, 8
.type peak_flop,@object # @peak_flop
.globl peak_flop
.p2align 3, 0x0
peak_flop:
.quad __device_stub__peak_flop
.size peak_flop, 8
.type peak_flop_empty,@object # @peak_flop_empty
.globl peak_flop_empty
.p2align 3, 0x0
peak_flop_empty:
.quad __device_stub__peak_flop_empty
.size peak_flop_empty, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "noarg"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "simple_add"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "four_mad"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "peak_flop"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "peak_flop_empty"
.size .L__unnamed_5, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__noarg
.addrsig_sym __device_stub__simple_add
.addrsig_sym __device_stub__four_mad
.addrsig_sym __device_stub__peak_flop
.addrsig_sym __device_stub__peak_flop_empty
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym noarg
.addrsig_sym simple_add
.addrsig_sym four_mad
.addrsig_sym peak_flop
.addrsig_sym peak_flop_empty
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
cudaMalloc(&x_gpu, 256 * sizeof(int));
cudaMemcpy(x_gpu, x, 256 * sizeof(int), cudaMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} | code for sm_80
Function : _Z7add_onePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
cudaMalloc(&x_gpu, 256 * sizeof(int));
cudaMemcpy(x_gpu, x, 256 * sizeof(int), cudaMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} | .file "tmpxft_00098da7_00000000-6_cudaloop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7add_onePiPi
.type _Z26__device_stub__Z7add_onePiPi, @function
_Z26__device_stub__Z7add_onePiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7add_onePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z7add_onePiPi, .-_Z26__device_stub__Z7add_onePiPi
.globl _Z7add_onePi
.type _Z7add_onePi, @function
_Z7add_onePi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7add_onePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7add_onePi, .-_Z7add_onePi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $1080, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z26__device_stub__Z7add_onePiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7add_onePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_onePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
cudaMalloc(&x_gpu, 256 * sizeof(int));
cudaMemcpy(x_gpu, x, 256 * sizeof(int), cudaMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} | #include <hip/hip_runtime.h>
__global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
hipMalloc(&x_gpu, 256 * sizeof(int));
hipMemcpy(x_gpu, x, 256 * sizeof(int), hipMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
hipMalloc(&x_gpu, 256 * sizeof(int));
hipMemcpy(x_gpu, x, 256 * sizeof(int), hipMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_onePi
.globl _Z7add_onePi
.p2align 8
.type _Z7add_onePi,@function
_Z7add_onePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_onePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_onePi, .Lfunc_end0-_Z7add_onePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_onePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_onePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void add_one(int *x) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
x[index] = x[index] + 1;
}
int main() {
int x[256];
int* x_gpu;
hipMalloc(&x_gpu, 256 * sizeof(int));
hipMemcpy(x_gpu, x, 256 * sizeof(int), hipMemcpyHostToDevice);
add_one<<<1, 256>>>(x_gpu);
} | .text
.file "cudaloop.hip"
.globl _Z22__device_stub__add_onePi # -- Begin function _Z22__device_stub__add_onePi
.p2align 4, 0x90
.type _Z22__device_stub__add_onePi,@function
_Z22__device_stub__add_onePi: # @_Z22__device_stub__add_onePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7add_onePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__add_onePi, .Lfunc_end0-_Z22__device_stub__add_onePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1112, %rsp # imm = 0x458
.cfi_def_cfa_offset 1120
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7add_onePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $1112, %rsp # imm = 0x458
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_onePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_onePi,@object # @_Z7add_onePi
.section .rodata,"a",@progbits
.globl _Z7add_onePi
.p2align 3, 0x0
_Z7add_onePi:
.quad _Z22__device_stub__add_onePi
.size _Z7add_onePi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7add_onePi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_onePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_onePi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7add_onePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_onePi
.globl _Z7add_onePi
.p2align 8
.type _Z7add_onePi,@function
_Z7add_onePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_onePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_onePi, .Lfunc_end0-_Z7add_onePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_onePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_onePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098da7_00000000-6_cudaloop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7add_onePiPi
.type _Z26__device_stub__Z7add_onePiPi, @function
_Z26__device_stub__Z7add_onePiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7add_onePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z7add_onePiPi, .-_Z26__device_stub__Z7add_onePiPi
.globl _Z7add_onePi
.type _Z7add_onePi, @function
_Z7add_onePi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7add_onePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7add_onePi, .-_Z7add_onePi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $1080, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z26__device_stub__Z7add_onePiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7add_onePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_onePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaloop.hip"
.globl _Z22__device_stub__add_onePi # -- Begin function _Z22__device_stub__add_onePi
.p2align 4, 0x90
.type _Z22__device_stub__add_onePi,@function
_Z22__device_stub__add_onePi: # @_Z22__device_stub__add_onePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7add_onePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__add_onePi, .Lfunc_end0-_Z22__device_stub__add_onePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1112, %rsp # imm = 0x458
.cfi_def_cfa_offset 1120
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7add_onePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $1112, %rsp # imm = 0x458
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_onePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_onePi,@object # @_Z7add_onePi
.section .rodata,"a",@progbits
.globl _Z7add_onePi
.p2align 3, 0x0
_Z7add_onePi:
.quad _Z22__device_stub__add_onePi
.size _Z7add_onePi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7add_onePi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_onePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_onePi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
cudaDriverGetVersion(&driver_ver);
cudaRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
cudaGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++)
{
cudaGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
cudaDriverGetVersion(&driver_ver);
cudaRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
cudaGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++)
{
cudaGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} | .file "tmpxft_000b36d2_00000000-6_devinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Integrated"
.LC1:
.string "Discrete"
.LC2:
.string "Tesla Compute Cluster (TCC)"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Windows Display Driver Model (WDDM)"
.section .rodata.str1.1
.LC4:
.string "Enabled"
.LC5:
.string "Disabled"
.LC6:
.string "Yes"
.LC7:
.string "No"
.LC8:
.string "CUDA Driver Version: %d.%d\n"
.LC9:
.string "CUDA Runtime Version: %d.%d\n"
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC12:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1
.LC13:
.string "--- Device %d ---\n"
.LC14:
.string "Device: %s\n"
.LC15:
.string "Type: %s\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Compute Capability Version: %d.%d\n"
.section .rodata.str1.1
.LC17:
.string "Driver Mode: %s\n"
.LC18:
.string "Clock Rate: %d Mhz\n"
.LC19:
.string "Memory Clock Rate: %d Mhz\n"
.LC20:
.string "Global Memory Size: %llu MB\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Constant Memory Size: %llu KB\n"
.section .rodata.str1.1
.LC22:
.string "L2 Cache Size: %d KB\n"
.LC23:
.string "Memory Bandwidth: %d-bit\n"
.LC24:
.string "ECC Support: %s\n"
.LC25:
.string "Unified Addressing: %s\n"
.LC26:
.string "L1 Cache for Globals: %s\n"
.LC27:
.string "L1 Cache for Locals: %s\n"
.LC28:
.string "SM #: %d\n"
.section .rodata.str1.8
.align 8
.LC29:
.string "Max Grid Size: X - %d, Y - %d, Z - %d\n"
.align 8
.LC30:
.string "Max Block Size: X - %d, Y - %d, Z - %d\n"
.section .rodata.str1.1
.LC31:
.string "Wrap Size: %d\n"
.section .rodata.str1.8
.align 8
.LC32:
.string "Max # of Threads per Block: %d\n"
.section .rodata.str1.1
.LC33:
.string "Max # of Threads per SM: %d\n"
.LC34:
.string "Registers per Block: %d\n"
.LC35:
.string "Registers per SM: %d\n"
.section .rodata.str1.8
.align 8
.LC36:
.string "Shared Memory per Block: %llu KB\n"
.align 8
.LC37:
.string "Shared Memory per SM: %llu KB\n"
.align 8
.LC38:
.string "Single-to-Double Performance Ratio (in FLOPS): %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 8(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 4(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %esi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %esi, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jne .L4
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebp
leaq .LC13(%rip), %r14
leaq .LC10(%rip), %rbx
leaq .LC7(%rip), %r13
leaq .LC6(%rip), %r12
.L12:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 612(%rsp)
leaq .LC3(%rip), %rdx
leaq .LC2(%rip), %rax
cmovne %rax, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 624(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %eax
leal 1023(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $10, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 596(%rsp)
leaq .LC5(%rip), %rdx
leaq .LC4(%rip), %rax
cmovne %rax, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 620(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 648(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 652(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 664(%rsp), %edx
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 656(%rsp), %rdx
shrq $10, %rdx
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 684(%rsp), %edx
leaq .LC38(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jg .L12
.L5:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
cudaDriverGetVersion(&driver_ver);
cudaRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
cudaGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++)
{
cudaGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
hipDriverGetVersion(&driver_ver);
hipRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
hipGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++)
{
hipGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
hipDriverGetVersion(&driver_ver);
hipRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
hipGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++)
{
hipGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
int main(void)
{
int driver_ver, runtime_ver;
hipDriverGetVersion(&driver_ver);
hipRuntimeGetVersion(&runtime_ver);
printf("CUDA Driver Version: %d.%d\n", driver_ver / 1000, (driver_ver % 100) / 10);
printf("CUDA Runtime Version: %d.%d\n", runtime_ver / 1000, (runtime_ver % 100) / 10);
printf("\n");
int dev_count;
hipGetDeviceCount(&dev_count);
if (dev_count == 0)
{
printf("There are no available device(s) that support CUDA\n");
printf("\n");
exit(EXIT_SUCCESS);
}
else
{
printf("Detected %d CUDA Capable device(s)\n", dev_count);
printf("\n");
}
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++)
{
hipGetDeviceProperties(&dev_prop, i);
printf("--- Device %d ---\n", i);
printf("Device: %s\n", dev_prop.name);
printf("Type: %s\n", dev_prop.integrated ? "Integrated" : "Discrete");
printf("Compute Capability Version: %d.%d\n", dev_prop.major, dev_prop.minor);
printf("Driver Mode: %s\n", dev_prop.tccDriver ? "Tesla Compute Cluster (TCC)" : "Windows Display Driver Model (WDDM)");
printf("\n");
printf("Clock Rate: %d Mhz\n", dev_prop.clockRate / 1000);
printf("Memory Clock Rate: %d Mhz\n", dev_prop.memoryClockRate / 1000);
printf("\n");
printf("Global Memory Size: %llu MB\n", dev_prop.totalGlobalMem / (1024 * 1024));
printf("Constant Memory Size: %llu KB\n", dev_prop.totalConstMem / 1024);
printf("L2 Cache Size: %d KB\n", dev_prop.l2CacheSize / 1024);
printf("\n");
printf("Memory Bandwidth: %d-bit\n", dev_prop.memoryBusWidth);
printf("ECC Support: %s\n", dev_prop.ECCEnabled ? "Enabled" : "Disabled");
printf("Unified Addressing: %s\n", dev_prop.unifiedAddressing ? "Yes" : "No");
printf("\n");
printf("L1 Cache for Globals: %s\n", dev_prop.globalL1CacheSupported ? "Yes" : "No");
printf("L1 Cache for Locals: %s\n", dev_prop.localL1CacheSupported ? "Yes" : "No");
printf("\n");
printf("SM #: %d\n", dev_prop.multiProcessorCount);
printf("Max Grid Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxGridSize[0], dev_prop.maxGridSize[1], dev_prop.maxGridSize[2]);
printf("Max Block Size: X - %d, Y - %d, Z - %d\n", dev_prop.maxThreadsDim[0], dev_prop.maxThreadsDim[1], dev_prop.maxThreadsDim[2]);
printf("Wrap Size: %d\n", dev_prop.warpSize);
printf("\n");
printf("Max # of Threads per Block: %d\n", dev_prop.maxThreadsPerBlock);
printf("Max # of Threads per SM: %d\n", dev_prop.maxThreadsPerMultiProcessor);
printf("Registers per Block: %d\n", dev_prop.regsPerBlock);
printf("Registers per SM: %d\n", dev_prop.regsPerMultiprocessor);
printf("Shared Memory per Block: %llu KB\n", dev_prop.sharedMemPerBlock / 1024);
printf("Shared Memory per SM: %llu KB\n", dev_prop.sharedMemPerMultiprocessor / 1024);
printf("\n");
printf("Single-to-Double Performance Ratio (in FLOPS): %d\n", dev_prop.singleToDoublePrecisionPerfRatio);
printf("\n");
}
exit(EXIT_SUCCESS);
} | .text
.file "devinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 20(%rsp), %rdi
callq hipDriverGetVersion
leaq 16(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movslq 16(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
testl %esi, %esi
jne .LBB0_1
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movl $10, %edi
callq putchar@PLT
xorl %edi, %edi
callq exit
.LBB0_1:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, 12(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
leaq 24(%rsp), %rbx
movl $.L.str.9, %r14d
movl $.L.str.13, %r15d
movl $.L.str.22, %r12d
movl $.L.str.25, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
cmpl $0, 420(%rsp)
movl $.L.str.8, %esi
cmoveq %r14, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 384(%rsp), %esi
movl 388(%rsp), %edx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
cmpl $0, 620(%rsp)
movl $.L.str.12, %esi
cmoveq %r15, %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movslq 372(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.14, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movslq 632(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.15, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 312(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 640(%rsp), %eax
leal 1023(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $10, %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 636(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
cmpl $0, 604(%rsp)
movl $.L.str.21, %esi
cmoveq %r12, %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 628(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, 656(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
cmpl $0, 660(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 412(%rsp), %esi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl 368(%rsp), %ecx
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 348(%rsp), %esi
movl 352(%rsp), %edx
movl 356(%rsp), %ecx
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 344(%rsp), %esi
movl $.L.str.32, %edi
xorl %eax, %eax
callq printf
movl 648(%rsp), %esi
movl $.L.str.33, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.34, %edi
xorl %eax, %eax
callq printf
movl 672(%rsp), %esi
movl $.L.str.35, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.36, %edi
xorl %eax, %eax
callq printf
movq 664(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.37, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 692(%rsp), %esi
movl $.L.str.38, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_3
.LBB0_4: # %._crit_edge
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Driver Version: %d.%d\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Runtime Version: %d.%d\n"
.size .L.str.1, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "--- Device %d ---\n"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Device: %s\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Type: %s\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Integrated"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Discrete"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Compute Capability Version: %d.%d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Driver Mode: %s\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Tesla Compute Cluster (TCC)"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Windows Display Driver Model (WDDM)"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Clock Rate: %d Mhz\n"
.size .L.str.14, 20
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Memory Clock Rate: %d Mhz\n"
.size .L.str.15, 27
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Global Memory Size: %llu MB\n"
.size .L.str.16, 29
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Constant Memory Size: %llu KB\n"
.size .L.str.17, 31
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "L2 Cache Size: %d KB\n"
.size .L.str.18, 22
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Memory Bandwidth: %d-bit\n"
.size .L.str.19, 26
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "ECC Support: %s\n"
.size .L.str.20, 17
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Enabled"
.size .L.str.21, 8
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Disabled"
.size .L.str.22, 9
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Unified Addressing: %s\n"
.size .L.str.23, 24
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Yes"
.size .L.str.24, 4
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "No"
.size .L.str.25, 3
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "L1 Cache for Globals: %s\n"
.size .L.str.26, 26
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "L1 Cache for Locals: %s\n"
.size .L.str.27, 25
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "SM #: %d\n"
.size .L.str.28, 10
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Max Grid Size: X - %d, Y - %d, Z - %d\n"
.size .L.str.29, 39
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Max Block Size: X - %d, Y - %d, Z - %d\n"
.size .L.str.30, 40
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Wrap Size: %d\n"
.size .L.str.31, 15
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Max # of Threads per Block: %d\n"
.size .L.str.32, 32
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "Max # of Threads per SM: %d\n"
.size .L.str.33, 29
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz "Registers per Block: %d\n"
.size .L.str.34, 25
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz "Registers per SM: %d\n"
.size .L.str.35, 22
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz "Shared Memory per Block: %llu KB\n"
.size .L.str.36, 34
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz "Shared Memory per SM: %llu KB\n"
.size .L.str.37, 31
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz "Single-to-Double Performance Ratio (in FLOPS): %d\n"
.size .L.str.38, 51
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b36d2_00000000-6_devinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Integrated"
.LC1:
.string "Discrete"
.LC2:
.string "Tesla Compute Cluster (TCC)"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Windows Display Driver Model (WDDM)"
.section .rodata.str1.1
.LC4:
.string "Enabled"
.LC5:
.string "Disabled"
.LC6:
.string "Yes"
.LC7:
.string "No"
.LC8:
.string "CUDA Driver Version: %d.%d\n"
.LC9:
.string "CUDA Runtime Version: %d.%d\n"
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC12:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1
.LC13:
.string "--- Device %d ---\n"
.LC14:
.string "Device: %s\n"
.LC15:
.string "Type: %s\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Compute Capability Version: %d.%d\n"
.section .rodata.str1.1
.LC17:
.string "Driver Mode: %s\n"
.LC18:
.string "Clock Rate: %d Mhz\n"
.LC19:
.string "Memory Clock Rate: %d Mhz\n"
.LC20:
.string "Global Memory Size: %llu MB\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Constant Memory Size: %llu KB\n"
.section .rodata.str1.1
.LC22:
.string "L2 Cache Size: %d KB\n"
.LC23:
.string "Memory Bandwidth: %d-bit\n"
.LC24:
.string "ECC Support: %s\n"
.LC25:
.string "Unified Addressing: %s\n"
.LC26:
.string "L1 Cache for Globals: %s\n"
.LC27:
.string "L1 Cache for Locals: %s\n"
.LC28:
.string "SM #: %d\n"
.section .rodata.str1.8
.align 8
.LC29:
.string "Max Grid Size: X - %d, Y - %d, Z - %d\n"
.align 8
.LC30:
.string "Max Block Size: X - %d, Y - %d, Z - %d\n"
.section .rodata.str1.1
.LC31:
.string "Wrap Size: %d\n"
.section .rodata.str1.8
.align 8
.LC32:
.string "Max # of Threads per Block: %d\n"
.section .rodata.str1.1
.LC33:
.string "Max # of Threads per SM: %d\n"
.LC34:
.string "Registers per Block: %d\n"
.LC35:
.string "Registers per SM: %d\n"
.section .rodata.str1.8
.align 8
.LC36:
.string "Shared Memory per Block: %llu KB\n"
.align 8
.LC37:
.string "Shared Memory per SM: %llu KB\n"
.align 8
.LC38:
.string "Single-to-Double Performance Ratio (in FLOPS): %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 8(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 4(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %esi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %esi, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jne .L4
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebp
leaq .LC13(%rip), %r14
leaq .LC10(%rip), %rbx
leaq .LC7(%rip), %r13
leaq .LC6(%rip), %r12
.L12:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 612(%rsp)
leaq .LC3(%rip), %rdx
leaq .LC2(%rip), %rax
cmovne %rax, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 624(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %eax
leal 1023(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $10, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 596(%rsp)
leaq .LC5(%rip), %rdx
leaq .LC4(%rip), %rax
cmovne %rax, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 620(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 648(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 652(%rsp)
movq %r12, %rdx
cmove %r13, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 664(%rsp), %edx
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 656(%rsp), %rdx
shrq $10, %rdx
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 684(%rsp), %edx
leaq .LC38(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jg .L12
.L5:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "devinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 20(%rsp), %rdi
callq hipDriverGetVersion
leaq 16(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movslq 16(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
testl %esi, %esi
jne .LBB0_1
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movl $10, %edi
callq putchar@PLT
xorl %edi, %edi
callq exit
.LBB0_1:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, 12(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
leaq 24(%rsp), %rbx
movl $.L.str.9, %r14d
movl $.L.str.13, %r15d
movl $.L.str.22, %r12d
movl $.L.str.25, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
cmpl $0, 420(%rsp)
movl $.L.str.8, %esi
cmoveq %r14, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 384(%rsp), %esi
movl 388(%rsp), %edx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
cmpl $0, 620(%rsp)
movl $.L.str.12, %esi
cmoveq %r15, %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movslq 372(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.14, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movslq 632(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.15, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 312(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 640(%rsp), %eax
leal 1023(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $10, %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 636(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
cmpl $0, 604(%rsp)
movl $.L.str.21, %esi
cmoveq %r12, %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 628(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, 656(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
cmpl $0, 660(%rsp)
movl $.L.str.24, %esi
cmoveq %r13, %rsi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 412(%rsp), %esi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl 368(%rsp), %ecx
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 348(%rsp), %esi
movl 352(%rsp), %edx
movl 356(%rsp), %ecx
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 344(%rsp), %esi
movl $.L.str.32, %edi
xorl %eax, %eax
callq printf
movl 648(%rsp), %esi
movl $.L.str.33, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.34, %edi
xorl %eax, %eax
callq printf
movl 672(%rsp), %esi
movl $.L.str.35, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.36, %edi
xorl %eax, %eax
callq printf
movq 664(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.37, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl 692(%rsp), %esi
movl $.L.str.38, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_3
.LBB0_4: # %._crit_edge
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Driver Version: %d.%d\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Runtime Version: %d.%d\n"
.size .L.str.1, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "--- Device %d ---\n"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Device: %s\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Type: %s\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Integrated"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Discrete"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Compute Capability Version: %d.%d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Driver Mode: %s\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Tesla Compute Cluster (TCC)"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Windows Display Driver Model (WDDM)"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Clock Rate: %d Mhz\n"
.size .L.str.14, 20
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Memory Clock Rate: %d Mhz\n"
.size .L.str.15, 27
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Global Memory Size: %llu MB\n"
.size .L.str.16, 29
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Constant Memory Size: %llu KB\n"
.size .L.str.17, 31
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "L2 Cache Size: %d KB\n"
.size .L.str.18, 22
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Memory Bandwidth: %d-bit\n"
.size .L.str.19, 26
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "ECC Support: %s\n"
.size .L.str.20, 17
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Enabled"
.size .L.str.21, 8
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Disabled"
.size .L.str.22, 9
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Unified Addressing: %s\n"
.size .L.str.23, 24
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Yes"
.size .L.str.24, 4
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "No"
.size .L.str.25, 3
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "L1 Cache for Globals: %s\n"
.size .L.str.26, 26
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "L1 Cache for Locals: %s\n"
.size .L.str.27, 25
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "SM #: %d\n"
.size .L.str.28, 10
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Max Grid Size: X - %d, Y - %d, Z - %d\n"
.size .L.str.29, 39
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Max Block Size: X - %d, Y - %d, Z - %d\n"
.size .L.str.30, 40
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Wrap Size: %d\n"
.size .L.str.31, 15
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Max # of Threads per Block: %d\n"
.size .L.str.32, 32
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "Max # of Threads per SM: %d\n"
.size .L.str.33, 29
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz "Registers per Block: %d\n"
.size .L.str.34, 25
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz "Registers per SM: %d\n"
.size .L.str.35, 22
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz "Shared Memory per Block: %llu KB\n"
.size .L.str.36, 34
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz "Shared Memory per SM: %llu KB\n"
.size .L.str.37, 31
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz "Single-to-Double Performance Ratio (in FLOPS): %d\n"
.size .L.str.38, 51
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} | code for sm_80
Function : _Z8getmaxcuPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fe20003f25270 */
/*0060*/ IMAD R7, R3, c[0x0][0x0], R2 ; /* 0x0000000003077a24 */
/* 0x002fc800078e0202 */
/*0070*/ IMAD.WIDE R4, R7, R0, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fd000078e0200 */
/*0080*/ @!P1 STS.128 [RZ], RZ ; /* 0x000000ffff009388 */
/* 0x000fe80000000c00 */
/*0090*/ @!P1 STS.128 [0x10], RZ ; /* 0x000010ffff009388 */
/* 0x000fe80000000c00 */
/*00a0*/ @!P1 STS.128 [0x20], RZ ; /* 0x000020ffff009388 */
/* 0x000fe80000000c00 */
/*00b0*/ @!P1 STS.128 [0x30], RZ ; /* 0x000030ffff009388 */
/* 0x000fe80000000c00 */
/*00c0*/ @!P1 STS.128 [0x40], RZ ; /* 0x000040ffff009388 */
/* 0x000fe80000000c00 */
/*00d0*/ @!P1 STS.128 [0x50], RZ ; /* 0x000050ffff009388 */
/* 0x000fe80000000c00 */
/*00e0*/ @!P1 STS.128 [0x60], RZ ; /* 0x000060ffff009388 */
/* 0x000fe80000000c00 */
/*00f0*/ @!P1 STS.128 [0x70], RZ ; /* 0x000070ffff009388 */
/* 0x000fe80000000c00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ SHF.R.U32.HI R2, RZ, 0x3, R2 ; /* 0x00000003ff027819 */
/* 0x000fc80000011602 */
/*0130*/ LOP3.LUT R2, R2, 0x1ffffffc, RZ, 0xc0, !PT ; /* 0x1ffffffc02027812 */
/* 0x000fca00078ec0ff */
/*0140*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000ea40000000800 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fc80003f04070 */
/*0160*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x168], !P0 ; /* 0x00005a0007007a0c */
/* 0x000fda0004706670 */
/*0170*/ @!P0 STS [R2], R5 ; /* 0x0000000502008388 */
/* 0x0001e80000000800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01a0*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x001e220000000c00 */
/*01b0*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0000 */
/*01c0*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e680000000c00 */
/*01d0*/ LDS.128 R16, [0x20] ; /* 0x00002000ff107984 */
/* 0x000ea80000000c00 */
/*01e0*/ LDS.128 R4, [0x30] ; /* 0x00003000ff047984 */
/* 0x000ee20000000c00 */
/*01f0*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x001fc80007800200 */
/*0200*/ IMNMX R14, R13, R14, !PT ; /* 0x0000000e0d0e7217 */
/* 0x000fc80007800200 */
/*0210*/ IMNMX R15, R14, R15, !PT ; /* 0x0000000f0e0f7217 */
/* 0x000fc80007800200 */
/*0220*/ IMNMX R8, R15, R8, !PT ; /* 0x000000080f087217 */
/* 0x002fe40007800200 */
/*0230*/ LDS.128 R12, [0x40] ; /* 0x00004000ff0c7984 */
/* 0x000e240000000c00 */
/*0240*/ IMNMX R9, R8, R9, !PT ; /* 0x0000000908097217 */
/* 0x000fc80007800200 */
/*0250*/ IMNMX R10, R9, R10, !PT ; /* 0x0000000a090a7217 */
/* 0x000fc80007800200 */
/*0260*/ IMNMX R11, R10, R11, !PT ; /* 0x0000000b0a0b7217 */
/* 0x000fc80007800200 */
/*0270*/ IMNMX R16, R11, R16, !PT ; /* 0x000000100b107217 */
/* 0x004fe40007800200 */
/*0280*/ LDS.128 R8, [0x50] ; /* 0x00005000ff087984 */
/* 0x000e640000000c00 */
/*0290*/ IMNMX R17, R16, R17, !PT ; /* 0x0000001110117217 */
/* 0x000fc80007800200 */
/*02a0*/ IMNMX R18, R17, R18, !PT ; /* 0x0000001211127217 */
/* 0x000fc80007800200 */
/*02b0*/ IMNMX R19, R18, R19, !PT ; /* 0x0000001312137217 */
/* 0x000fc80007800200 */
/*02c0*/ IMNMX R4, R19, R4, !PT ; /* 0x0000000413047217 */
/* 0x008fe40007800200 */
/*02d0*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000ea40000000c00 */
/*02e0*/ IMNMX R5, R4, R5, !PT ; /* 0x0000000504057217 */
/* 0x000fc80007800200 */
/*02f0*/ IMNMX R6, R5, R6, !PT ; /* 0x0000000605067217 */
/* 0x000fc80007800200 */
/*0300*/ IMNMX R7, R6, R7, !PT ; /* 0x0000000706077217 */
/* 0x000fc80007800200 */
/*0310*/ IMNMX R12, R7, R12, !PT ; /* 0x0000000c070c7217 */
/* 0x001fe40007800200 */
/*0320*/ LDS.128 R4, [0x70] ; /* 0x00007000ff047984 */
/* 0x000e240000000c00 */
/*0330*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x000fc80007800200 */
/*0340*/ IMNMX R14, R13, R14, !PT ; /* 0x0000000e0d0e7217 */
/* 0x000fc80007800200 */
/*0350*/ IMNMX R15, R14, R15, !PT ; /* 0x0000000f0e0f7217 */
/* 0x000fc80007800200 */
/*0360*/ IMNMX R8, R15, R8, !PT ; /* 0x000000080f087217 */
/* 0x002fc80007800200 */
/*0370*/ IMNMX R9, R8, R9, !PT ; /* 0x0000000908097217 */
/* 0x000fc80007800200 */
/*0380*/ IMNMX R10, R9, R10, !PT ; /* 0x0000000a090a7217 */
/* 0x000fc80007800200 */
/*0390*/ IMNMX R11, R10, R11, !PT ; /* 0x0000000b0a0b7217 */
/* 0x000fc80007800200 */
/*03a0*/ IMNMX R16, R11, R16, !PT ; /* 0x000000100b107217 */
/* 0x004fc80007800200 */
/*03b0*/ IMNMX R17, R16, R17, !PT ; /* 0x0000001110117217 */
/* 0x000fc80007800200 */
/*03c0*/ IMNMX R18, R17, R18, !PT ; /* 0x0000001211127217 */
/* 0x000fc80007800200 */
/*03d0*/ IMNMX R19, R18, R19, !PT ; /* 0x0000001312137217 */
/* 0x000fc80007800200 */
/*03e0*/ IMNMX R4, R19, R4, !PT ; /* 0x0000000413047217 */
/* 0x001fc80007800200 */
/*03f0*/ IMNMX R5, R4, R5, !PT ; /* 0x0000000504057217 */
/* 0x000fc80007800200 */
/*0400*/ IMNMX R6, R5, R6, !PT ; /* 0x0000000605067217 */
/* 0x000fc80007800200 */
/*0410*/ IMNMX R7, R6, R7, !PT ; /* 0x0000000706077217 */
/* 0x000fca0007800200 */
/*0420*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} | .file "tmpxft_001b5a4a_00000000-6_getmaxcu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8getmaxcuPjiiPjii
.type _Z29__device_stub__Z8getmaxcuPjiiPjii, @function
_Z29__device_stub__Z8getmaxcuPjiiPjii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8getmaxcuPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8getmaxcuPjiiPjii, .-_Z29__device_stub__Z8getmaxcuPjiiPjii
.globl _Z8getmaxcuPjii
.type _Z8getmaxcuPjii, @function
_Z8getmaxcuPjii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8getmaxcuPjiiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8getmaxcuPjii, .-_Z8getmaxcuPjii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8getmaxcuPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8getmaxcuPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8getmaxcuPjii
.globl _Z8getmaxcuPjii
.p2align 8
.type _Z8getmaxcuPjii,@function
_Z8getmaxcuPjii:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s2, s15
s_mov_b32 s4, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
.LBB0_2:
v_mov_b32_e32 v2, s4
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s4, 0x80
ds_store_b32 v2, v1
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
v_lshrrev_b32_e32 v0, 3, v0
v_and_b32_e32 v0, 0x7c, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_i32_e64 s1, s1, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_u32_e64 s0, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_5
ds_store_b32 v0, v1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 4
ds_load_b32 v0, v0
.LBB0_7:
v_mov_b32_e32 v1, s0
s_add_i32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s0, 0x80
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v0, v0, v1
s_cbranch_scc0 .LBB0_7
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8getmaxcuPjii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8getmaxcuPjii, .Lfunc_end0-_Z8getmaxcuPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8getmaxcuPjii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8getmaxcuPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//function declaration
unsigned int getmax(unsigned int *, unsigned int);
//unsigned int getmaxSeq(unsigned int *, unsigned int);
__global__ void getmaxcu(unsigned int* num, int size, int threadCount)
{
__shared__ int localBiggest[32];
if (threadIdx.x==0) {
for (int i = 0; i < 32; i++) {
localBiggest[i] = 0;
}
}
__syncthreads();
int current = blockIdx.x *blockDim.x + threadIdx.x; //get current thread ID
int localBiggestCurrent = (current - blockIdx.x *blockDim.x)/32; //get currentID's warp number
//if current number is bigger than the biggest number so far in the warp, replace it
if ((num[current] > localBiggest[localBiggestCurrent]) && (current < size)) {
localBiggest[localBiggestCurrent] = num[current];
}
__syncthreads();
//using only one thread, loop through all the biggest numbers in each warp
//and return the biggest number out of them all
if (threadIdx.x==0) {
int biggest = localBiggest[0];
for (int i = 1; i < 32; i++) {
if (biggest < localBiggest[i]) {
biggest = localBiggest[i];
}
}
//once found the biggest number in this block, put back into global array
//num with corresponding block number
num[blockIdx.x] = biggest;
}
} | .text
.file "getmaxcu.hip"
.globl _Z23__device_stub__getmaxcuPjii # -- Begin function _Z23__device_stub__getmaxcuPjii
.p2align 4, 0x90
.type _Z23__device_stub__getmaxcuPjii,@function
_Z23__device_stub__getmaxcuPjii: # @_Z23__device_stub__getmaxcuPjii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8getmaxcuPjii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__getmaxcuPjii, .Lfunc_end0-_Z23__device_stub__getmaxcuPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8getmaxcuPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8getmaxcuPjii,@object # @_Z8getmaxcuPjii
.section .rodata,"a",@progbits
.globl _Z8getmaxcuPjii
.p2align 3, 0x0
_Z8getmaxcuPjii:
.quad _Z23__device_stub__getmaxcuPjii
.size _Z8getmaxcuPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8getmaxcuPjii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__getmaxcuPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8getmaxcuPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8getmaxcuPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fe20003f25270 */
/*0060*/ IMAD R7, R3, c[0x0][0x0], R2 ; /* 0x0000000003077a24 */
/* 0x002fc800078e0202 */
/*0070*/ IMAD.WIDE R4, R7, R0, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fd000078e0200 */
/*0080*/ @!P1 STS.128 [RZ], RZ ; /* 0x000000ffff009388 */
/* 0x000fe80000000c00 */
/*0090*/ @!P1 STS.128 [0x10], RZ ; /* 0x000010ffff009388 */
/* 0x000fe80000000c00 */
/*00a0*/ @!P1 STS.128 [0x20], RZ ; /* 0x000020ffff009388 */
/* 0x000fe80000000c00 */
/*00b0*/ @!P1 STS.128 [0x30], RZ ; /* 0x000030ffff009388 */
/* 0x000fe80000000c00 */
/*00c0*/ @!P1 STS.128 [0x40], RZ ; /* 0x000040ffff009388 */
/* 0x000fe80000000c00 */
/*00d0*/ @!P1 STS.128 [0x50], RZ ; /* 0x000050ffff009388 */
/* 0x000fe80000000c00 */
/*00e0*/ @!P1 STS.128 [0x60], RZ ; /* 0x000060ffff009388 */
/* 0x000fe80000000c00 */
/*00f0*/ @!P1 STS.128 [0x70], RZ ; /* 0x000070ffff009388 */
/* 0x000fe80000000c00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ SHF.R.U32.HI R2, RZ, 0x3, R2 ; /* 0x00000003ff027819 */
/* 0x000fc80000011602 */
/*0130*/ LOP3.LUT R2, R2, 0x1ffffffc, RZ, 0xc0, !PT ; /* 0x1ffffffc02027812 */
/* 0x000fca00078ec0ff */
/*0140*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000ea40000000800 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fc80003f04070 */
/*0160*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x168], !P0 ; /* 0x00005a0007007a0c */
/* 0x000fda0004706670 */
/*0170*/ @!P0 STS [R2], R5 ; /* 0x0000000502008388 */
/* 0x0001e80000000800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01a0*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x001e220000000c00 */
/*01b0*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0000 */
/*01c0*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e680000000c00 */
/*01d0*/ LDS.128 R16, [0x20] ; /* 0x00002000ff107984 */
/* 0x000ea80000000c00 */
/*01e0*/ LDS.128 R4, [0x30] ; /* 0x00003000ff047984 */
/* 0x000ee20000000c00 */
/*01f0*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x001fc80007800200 */
/*0200*/ IMNMX R14, R13, R14, !PT ; /* 0x0000000e0d0e7217 */
/* 0x000fc80007800200 */
/*0210*/ IMNMX R15, R14, R15, !PT ; /* 0x0000000f0e0f7217 */
/* 0x000fc80007800200 */
/*0220*/ IMNMX R8, R15, R8, !PT ; /* 0x000000080f087217 */
/* 0x002fe40007800200 */
/*0230*/ LDS.128 R12, [0x40] ; /* 0x00004000ff0c7984 */
/* 0x000e240000000c00 */
/*0240*/ IMNMX R9, R8, R9, !PT ; /* 0x0000000908097217 */
/* 0x000fc80007800200 */
/*0250*/ IMNMX R10, R9, R10, !PT ; /* 0x0000000a090a7217 */
/* 0x000fc80007800200 */
/*0260*/ IMNMX R11, R10, R11, !PT ; /* 0x0000000b0a0b7217 */
/* 0x000fc80007800200 */
/*0270*/ IMNMX R16, R11, R16, !PT ; /* 0x000000100b107217 */
/* 0x004fe40007800200 */
/*0280*/ LDS.128 R8, [0x50] ; /* 0x00005000ff087984 */
/* 0x000e640000000c00 */
/*0290*/ IMNMX R17, R16, R17, !PT ; /* 0x0000001110117217 */
/* 0x000fc80007800200 */
/*02a0*/ IMNMX R18, R17, R18, !PT ; /* 0x0000001211127217 */
/* 0x000fc80007800200 */
/*02b0*/ IMNMX R19, R18, R19, !PT ; /* 0x0000001312137217 */
/* 0x000fc80007800200 */
/*02c0*/ IMNMX R4, R19, R4, !PT ; /* 0x0000000413047217 */
/* 0x008fe40007800200 */
/*02d0*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000ea40000000c00 */
/*02e0*/ IMNMX R5, R4, R5, !PT ; /* 0x0000000504057217 */
/* 0x000fc80007800200 */
/*02f0*/ IMNMX R6, R5, R6, !PT ; /* 0x0000000605067217 */
/* 0x000fc80007800200 */
/*0300*/ IMNMX R7, R6, R7, !PT ; /* 0x0000000706077217 */
/* 0x000fc80007800200 */
/*0310*/ IMNMX R12, R7, R12, !PT ; /* 0x0000000c070c7217 */
/* 0x001fe40007800200 */
/*0320*/ LDS.128 R4, [0x70] ; /* 0x00007000ff047984 */
/* 0x000e240000000c00 */
/*0330*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x000fc80007800200 */
/*0340*/ IMNMX R14, R13, R14, !PT ; /* 0x0000000e0d0e7217 */
/* 0x000fc80007800200 */
/*0350*/ IMNMX R15, R14, R15, !PT ; /* 0x0000000f0e0f7217 */
/* 0x000fc80007800200 */
/*0360*/ IMNMX R8, R15, R8, !PT ; /* 0x000000080f087217 */
/* 0x002fc80007800200 */
/*0370*/ IMNMX R9, R8, R9, !PT ; /* 0x0000000908097217 */
/* 0x000fc80007800200 */
/*0380*/ IMNMX R10, R9, R10, !PT ; /* 0x0000000a090a7217 */
/* 0x000fc80007800200 */
/*0390*/ IMNMX R11, R10, R11, !PT ; /* 0x0000000b0a0b7217 */
/* 0x000fc80007800200 */
/*03a0*/ IMNMX R16, R11, R16, !PT ; /* 0x000000100b107217 */
/* 0x004fc80007800200 */
/*03b0*/ IMNMX R17, R16, R17, !PT ; /* 0x0000001110117217 */
/* 0x000fc80007800200 */
/*03c0*/ IMNMX R18, R17, R18, !PT ; /* 0x0000001211127217 */
/* 0x000fc80007800200 */
/*03d0*/ IMNMX R19, R18, R19, !PT ; /* 0x0000001312137217 */
/* 0x000fc80007800200 */
/*03e0*/ IMNMX R4, R19, R4, !PT ; /* 0x0000000413047217 */
/* 0x001fc80007800200 */
/*03f0*/ IMNMX R5, R4, R5, !PT ; /* 0x0000000504057217 */
/* 0x000fc80007800200 */
/*0400*/ IMNMX R6, R5, R6, !PT ; /* 0x0000000605067217 */
/* 0x000fc80007800200 */
/*0410*/ IMNMX R7, R6, R7, !PT ; /* 0x0000000706077217 */
/* 0x000fca0007800200 */
/*0420*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8getmaxcuPjii
.globl _Z8getmaxcuPjii
.p2align 8
.type _Z8getmaxcuPjii,@function
_Z8getmaxcuPjii:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s2, s15
s_mov_b32 s4, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
.LBB0_2:
v_mov_b32_e32 v2, s4
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s4, 0x80
ds_store_b32 v2, v1
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
v_lshrrev_b32_e32 v0, 3, v0
v_and_b32_e32 v0, 0x7c, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_i32_e64 s1, s1, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_u32_e64 s0, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_5
ds_store_b32 v0, v1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 4
ds_load_b32 v0, v0
.LBB0_7:
v_mov_b32_e32 v1, s0
s_add_i32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s0, 0x80
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v0, v0, v1
s_cbranch_scc0 .LBB0_7
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8getmaxcuPjii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8getmaxcuPjii, .Lfunc_end0-_Z8getmaxcuPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8getmaxcuPjii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8getmaxcuPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5a4a_00000000-6_getmaxcu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8getmaxcuPjiiPjii
.type _Z29__device_stub__Z8getmaxcuPjiiPjii, @function
_Z29__device_stub__Z8getmaxcuPjiiPjii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8getmaxcuPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8getmaxcuPjiiPjii, .-_Z29__device_stub__Z8getmaxcuPjiiPjii
.globl _Z8getmaxcuPjii
.type _Z8getmaxcuPjii, @function
_Z8getmaxcuPjii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8getmaxcuPjiiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8getmaxcuPjii, .-_Z8getmaxcuPjii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8getmaxcuPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8getmaxcuPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getmaxcu.hip"
.globl _Z23__device_stub__getmaxcuPjii # -- Begin function _Z23__device_stub__getmaxcuPjii
.p2align 4, 0x90
.type _Z23__device_stub__getmaxcuPjii,@function
_Z23__device_stub__getmaxcuPjii: # @_Z23__device_stub__getmaxcuPjii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8getmaxcuPjii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__getmaxcuPjii, .Lfunc_end0-_Z23__device_stub__getmaxcuPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8getmaxcuPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8getmaxcuPjii,@object # @_Z8getmaxcuPjii
.section .rodata,"a",@progbits
.globl _Z8getmaxcuPjii
.p2align 3, 0x0
_Z8getmaxcuPjii:
.quad _Z23__device_stub__getmaxcuPjii
.size _Z8getmaxcuPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8getmaxcuPjii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__getmaxcuPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8getmaxcuPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//cuda include
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
/*
#define BLOCKNUM 100
#define THREADNUM 150
*/
__global__ void GSrand(curandState *state, unsigned int seed){
int index = blockIdx.x * blockDim.x * threadIdx.x;
curand_init(seed, index, 0, &state[index]);
}
__device__ float Grand(curandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
curandState local_state = state[index];
float rand_num = curand_uniform(&local_state);
state[index] = local_state;
return rand_num;
}
__global__ void testRand(float *rand_data, curandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
rand_data[index] = Grand(state);
}
int main(int argc, char *argv[]){
int BLOCKNUM = atoi(argv[1]);
int THREADNUM = atoi(argv[2]);
//data initialization
int data_length = BLOCKNUM * THREADNUM;
curandState *dev_state;
cudaMalloc((void**) &dev_state, sizeof(curandState) * data_length);
//random initialization
GSrand<<<BLOCKNUM, THREADNUM>>>(dev_state, (unsigned int)time(NULL));
//malloc host & device data
float *host_rand_data = (float*)malloc(sizeof(float) * data_length);
float *dev_rand_data;
cudaMalloc((void**) &dev_rand_data, sizeof(float) * data_length);
//get rand data
testRand<<<BLOCKNUM, THREADNUM>>>(dev_rand_data, dev_state);
//cpy data from dev to host
cudaMemcpy((void*) host_rand_data, (const void*) dev_rand_data, sizeof(float) * data_length, cudaMemcpyDeviceToHost);
//output result
printf("RAND RESULT:~~\n");
int i;
for(i=0; i<data_length; ++i){
printf("%d: %f\n", i, host_rand_data[i]);
}
return 0;
} | .file "tmpxft_000b4584_00000000-6_rand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5GrandP17curandStateXORWOW
.type _Z5GrandP17curandStateXORWOW, @function
_Z5GrandP17curandStateXORWOW:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z5GrandP17curandStateXORWOW, .-_Z5GrandP17curandStateXORWOW
.globl _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
.type _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj, @function
_Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6GSrandP17curandStateXORWOWj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj, .-_Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
.globl _Z6GSrandP17curandStateXORWOWj
.type _Z6GSrandP17curandStateXORWOWj, @function
_Z6GSrandP17curandStateXORWOWj:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z6GSrandP17curandStateXORWOWj, .-_Z6GSrandP17curandStateXORWOWj
.globl _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8testRandPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z8testRandPfP17curandStateXORWOW
.type _Z8testRandPfP17curandStateXORWOW, @function
_Z8testRandPfP17curandStateXORWOW:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z8testRandPfP17curandStateXORWOW, .-_Z8testRandPfP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "RAND RESULT:~~\n"
.LC1:
.string "%d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r15d
imull %ebx, %r15d
movslq %r15d, %rbp
leaq 0(%rbp,%rbp,2), %rsi
salq $4, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 0(,%rbp,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L24
movl $0, %ebx
leaq .LC1(%rip), %r13
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L25
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %edi
call time@PLT
movl %eax, %esi
movq (%rsp), %rdi
call _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
jmp .L22
.L30:
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z8testRandPfP17curandStateXORWOW"
.align 8
.LC3:
.string "_Z6GSrandP17curandStateXORWOWj"
.section .rodata.str1.1
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8testRandPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6GSrandP17curandStateXORWOWj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//cuda include
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
/*
#define BLOCKNUM 100
#define THREADNUM 150
*/
__global__ void GSrand(curandState *state, unsigned int seed){
int index = blockIdx.x * blockDim.x * threadIdx.x;
curand_init(seed, index, 0, &state[index]);
}
__device__ float Grand(curandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
curandState local_state = state[index];
float rand_num = curand_uniform(&local_state);
state[index] = local_state;
return rand_num;
}
__global__ void testRand(float *rand_data, curandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
rand_data[index] = Grand(state);
}
int main(int argc, char *argv[]){
int BLOCKNUM = atoi(argv[1]);
int THREADNUM = atoi(argv[2]);
//data initialization
int data_length = BLOCKNUM * THREADNUM;
curandState *dev_state;
cudaMalloc((void**) &dev_state, sizeof(curandState) * data_length);
//random initialization
GSrand<<<BLOCKNUM, THREADNUM>>>(dev_state, (unsigned int)time(NULL));
//malloc host & device data
float *host_rand_data = (float*)malloc(sizeof(float) * data_length);
float *dev_rand_data;
cudaMalloc((void**) &dev_rand_data, sizeof(float) * data_length);
//get rand data
testRand<<<BLOCKNUM, THREADNUM>>>(dev_rand_data, dev_state);
//cpy data from dev to host
cudaMemcpy((void*) host_rand_data, (const void*) dev_rand_data, sizeof(float) * data_length, cudaMemcpyDeviceToHost);
//output result
printf("RAND RESULT:~~\n");
int i;
for(i=0; i<data_length; ++i){
printf("%d: %f\n", i, host_rand_data[i]);
}
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//cuda include
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
/*
#define BLOCKNUM 100
#define THREADNUM 150
*/
__global__ void GSrand(hiprandState *state, unsigned int seed){
int index = blockIdx.x * blockDim.x * threadIdx.x;
hiprand_init(seed, index, 0, &state[index]);
}
__device__ float Grand(hiprandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState local_state = state[index];
float rand_num = hiprand_uniform(&local_state);
state[index] = local_state;
return rand_num;
}
__global__ void testRand(float *rand_data, hiprandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
rand_data[index] = Grand(state);
}
int main(int argc, char *argv[]){
int BLOCKNUM = atoi(argv[1]);
int THREADNUM = atoi(argv[2]);
//data initialization
int data_length = BLOCKNUM * THREADNUM;
hiprandState *dev_state;
hipMalloc((void**) &dev_state, sizeof(hiprandState) * data_length);
//random initialization
GSrand<<<BLOCKNUM, THREADNUM>>>(dev_state, (unsigned int)time(NULL));
//malloc host & device data
float *host_rand_data = (float*)malloc(sizeof(float) * data_length);
float *dev_rand_data;
hipMalloc((void**) &dev_rand_data, sizeof(float) * data_length);
//get rand data
testRand<<<BLOCKNUM, THREADNUM>>>(dev_rand_data, dev_state);
//cpy data from dev to host
hipMemcpy((void*) host_rand_data, (const void*) dev_rand_data, sizeof(float) * data_length, hipMemcpyDeviceToHost);
//output result
printf("RAND RESULT:~~\n");
int i;
for(i=0; i<data_length; ++i){
printf("%d: %f\n", i, host_rand_data[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//cuda include
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
/*
#define BLOCKNUM 100
#define THREADNUM 150
*/
__global__ void GSrand(hiprandState *state, unsigned int seed){
int index = blockIdx.x * blockDim.x * threadIdx.x;
hiprand_init(seed, index, 0, &state[index]);
}
__device__ float Grand(hiprandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState local_state = state[index];
float rand_num = hiprand_uniform(&local_state);
state[index] = local_state;
return rand_num;
}
__global__ void testRand(float *rand_data, hiprandState *state){
int index = blockIdx.x * blockDim.x + threadIdx.x;
rand_data[index] = Grand(state);
}
int main(int argc, char *argv[]){
int BLOCKNUM = atoi(argv[1]);
int THREADNUM = atoi(argv[2]);
//data initialization
int data_length = BLOCKNUM * THREADNUM;
hiprandState *dev_state;
hipMalloc((void**) &dev_state, sizeof(hiprandState) * data_length);
//random initialization
GSrand<<<BLOCKNUM, THREADNUM>>>(dev_state, (unsigned int)time(NULL));
//malloc host & device data
float *host_rand_data = (float*)malloc(sizeof(float) * data_length);
float *dev_rand_data;
hipMalloc((void**) &dev_rand_data, sizeof(float) * data_length);
//get rand data
testRand<<<BLOCKNUM, THREADNUM>>>(dev_rand_data, dev_state);
//cpy data from dev to host
hipMemcpy((void*) host_rand_data, (const void*) dev_rand_data, sizeof(float) * data_length, hipMemcpyDeviceToHost);
//output result
printf("RAND RESULT:~~\n");
int i;
for(i=0; i<data_length; ++i){
printf("%d: %f\n", i, host_rand_data[i]);
}
return 0;
} | .text
.file "rand.hip"
.globl _Z21__device_stub__GSrandP12hiprandStatej # -- Begin function _Z21__device_stub__GSrandP12hiprandStatej
.p2align 4, 0x90
.type _Z21__device_stub__GSrandP12hiprandStatej,@function
_Z21__device_stub__GSrandP12hiprandStatej: # @_Z21__device_stub__GSrandP12hiprandStatej
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6GSrandP12hiprandStatej, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__GSrandP12hiprandStatej, .Lfunc_end0-_Z21__device_stub__GSrandP12hiprandStatej
.cfi_endproc
# -- End function
.globl _Z23__device_stub__testRandPfP12hiprandState # -- Begin function _Z23__device_stub__testRandPfP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__testRandPfP12hiprandState,@function
_Z23__device_stub__testRandPfP12hiprandState: # @_Z23__device_stub__testRandPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8testRandPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__testRandPfP12hiprandState, .Lfunc_end1-_Z23__device_stub__testRandPfP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbx
movq %rbx, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 88(%rsp), %rdi
callq hipMalloc
movl %r14d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r12d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 88(%rsp), %r14
xorl %edi, %edi
callq time
movq %r14, 56(%rsp)
movl %eax, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6GSrandP12hiprandStatej, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8testRandPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 80(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %ebp, %ebp
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r15
jne .LBB2_6
.LBB2_7: # %._crit_edge
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6GSrandP12hiprandStatej, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8testRandPfP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6GSrandP12hiprandStatej,@object # @_Z6GSrandP12hiprandStatej
.section .rodata,"a",@progbits
.globl _Z6GSrandP12hiprandStatej
.p2align 3, 0x0
_Z6GSrandP12hiprandStatej:
.quad _Z21__device_stub__GSrandP12hiprandStatej
.size _Z6GSrandP12hiprandStatej, 8
.type _Z8testRandPfP12hiprandState,@object # @_Z8testRandPfP12hiprandState
.globl _Z8testRandPfP12hiprandState
.p2align 3, 0x0
_Z8testRandPfP12hiprandState:
.quad _Z23__device_stub__testRandPfP12hiprandState
.size _Z8testRandPfP12hiprandState, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d: %f\n"
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6GSrandP12hiprandStatej"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8testRandPfP12hiprandState"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "RAND RESULT:~~"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__GSrandP12hiprandStatej
.addrsig_sym _Z23__device_stub__testRandPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6GSrandP12hiprandStatej
.addrsig_sym _Z8testRandPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b4584_00000000-6_rand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5GrandP17curandStateXORWOW
.type _Z5GrandP17curandStateXORWOW, @function
_Z5GrandP17curandStateXORWOW:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z5GrandP17curandStateXORWOW, .-_Z5GrandP17curandStateXORWOW
.globl _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
.type _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj, @function
_Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6GSrandP17curandStateXORWOWj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj, .-_Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
.globl _Z6GSrandP17curandStateXORWOWj
.type _Z6GSrandP17curandStateXORWOWj, @function
_Z6GSrandP17curandStateXORWOWj:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z6GSrandP17curandStateXORWOWj, .-_Z6GSrandP17curandStateXORWOWj
.globl _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8testRandPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z8testRandPfP17curandStateXORWOW
.type _Z8testRandPfP17curandStateXORWOW, @function
_Z8testRandPfP17curandStateXORWOW:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z8testRandPfP17curandStateXORWOW, .-_Z8testRandPfP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "RAND RESULT:~~\n"
.LC1:
.string "%d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r15d
imull %ebx, %r15d
movslq %r15d, %rbp
leaq 0(%rbp,%rbp,2), %rsi
salq $4, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 0(,%rbp,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L24
movl $0, %ebx
leaq .LC1(%rip), %r13
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L25
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %edi
call time@PLT
movl %eax, %esi
movq (%rsp), %rdi
call _Z44__device_stub__Z6GSrandP17curandStateXORWOWjP17curandStateXORWOWj
jmp .L22
.L30:
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z8testRandPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z8testRandPfP17curandStateXORWOW"
.align 8
.LC3:
.string "_Z6GSrandP17curandStateXORWOWj"
.section .rodata.str1.1
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8testRandPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6GSrandP17curandStateXORWOWj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rand.hip"
.globl _Z21__device_stub__GSrandP12hiprandStatej # -- Begin function _Z21__device_stub__GSrandP12hiprandStatej
.p2align 4, 0x90
.type _Z21__device_stub__GSrandP12hiprandStatej,@function
_Z21__device_stub__GSrandP12hiprandStatej: # @_Z21__device_stub__GSrandP12hiprandStatej
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6GSrandP12hiprandStatej, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__GSrandP12hiprandStatej, .Lfunc_end0-_Z21__device_stub__GSrandP12hiprandStatej
.cfi_endproc
# -- End function
.globl _Z23__device_stub__testRandPfP12hiprandState # -- Begin function _Z23__device_stub__testRandPfP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__testRandPfP12hiprandState,@function
_Z23__device_stub__testRandPfP12hiprandState: # @_Z23__device_stub__testRandPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8testRandPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__testRandPfP12hiprandState, .Lfunc_end1-_Z23__device_stub__testRandPfP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbx
movq %rbx, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 88(%rsp), %rdi
callq hipMalloc
movl %r14d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r12d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 88(%rsp), %r14
xorl %edi, %edi
callq time
movq %r14, 56(%rsp)
movl %eax, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6GSrandP12hiprandStatej, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8testRandPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 80(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %ebp, %ebp
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r15
jne .LBB2_6
.LBB2_7: # %._crit_edge
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6GSrandP12hiprandStatej, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8testRandPfP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6GSrandP12hiprandStatej,@object # @_Z6GSrandP12hiprandStatej
.section .rodata,"a",@progbits
.globl _Z6GSrandP12hiprandStatej
.p2align 3, 0x0
_Z6GSrandP12hiprandStatej:
.quad _Z21__device_stub__GSrandP12hiprandStatej
.size _Z6GSrandP12hiprandStatej, 8
.type _Z8testRandPfP12hiprandState,@object # @_Z8testRandPfP12hiprandState
.globl _Z8testRandPfP12hiprandState
.p2align 3, 0x0
_Z8testRandPfP12hiprandState:
.quad _Z23__device_stub__testRandPfP12hiprandState
.size _Z8testRandPfP12hiprandState, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d: %f\n"
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6GSrandP12hiprandStatej"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8testRandPfP12hiprandState"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "RAND RESULT:~~"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__GSrandP12hiprandStatej
.addrsig_sym _Z23__device_stub__testRandPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6GSrandP12hiprandStatej
.addrsig_sym _Z8testRandPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} | code for sm_80
Function : expkernel_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R7, 0x437c0000 ; /* 0x437c000000077802 */
/* 0x000fd20000000f00 */
/*00c0*/ FFMA.SAT R0, R2, R5, 0.5 ; /* 0x3f00000002007423 */
/* 0x004fc80000002005 */
/*00d0*/ FFMA.RM R0, R0, R7, 12582913 ; /* 0x4b40000100007423 */
/* 0x000fc80000004007 */
/*00e0*/ FADD R5, R0.reuse, -12583039 ; /* 0xcb40007f00057421 */
/* 0x040fe20000000000 */
/*00f0*/ SHF.L.U32 R0, R0, 0x17, RZ ; /* 0x0000001700007819 */
/* 0x000fc600000006ff */
/*0100*/ FFMA R5, R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */
/* 0x000fc80000000805 */
/*0110*/ FFMA R6, R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002067823 */
/* 0x000fe40000000005 */
/*0120*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0209 */
/*0130*/ MUFU.EX2 R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000000800 */
/*0140*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x001fca0000400000 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} | .file "tmpxft_0007a948_00000000-6_exp_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
.type _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf, @function
_Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq expkernel_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf, .-_Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
.globl expkernel_32
.type expkernel_32, @function
expkernel_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size expkernel_32, .-expkernel_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "expkernel_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq expkernel_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected expkernel_32
.globl expkernel_32
.p2align 8
.type expkernel_32,@function
expkernel_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
v_fma_f32 v4, v2, 0x3fb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel expkernel_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size expkernel_32, .Lfunc_end0-expkernel_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: expkernel_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: expkernel_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void expkernel_32(const int lengthA, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = exp(a[i]);
}
}
} | .text
.file "exp_32.hip"
.globl __device_stub__expkernel_32 # -- Begin function __device_stub__expkernel_32
.p2align 4, 0x90
.type __device_stub__expkernel_32,@function
__device_stub__expkernel_32: # @__device_stub__expkernel_32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $expkernel_32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__expkernel_32, .Lfunc_end0-__device_stub__expkernel_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $expkernel_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type expkernel_32,@object # @expkernel_32
.section .rodata,"a",@progbits
.globl expkernel_32
.p2align 3, 0x0
expkernel_32:
.quad __device_stub__expkernel_32
.size expkernel_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "expkernel_32"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__expkernel_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym expkernel_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : expkernel_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R7, 0x437c0000 ; /* 0x437c000000077802 */
/* 0x000fd20000000f00 */
/*00c0*/ FFMA.SAT R0, R2, R5, 0.5 ; /* 0x3f00000002007423 */
/* 0x004fc80000002005 */
/*00d0*/ FFMA.RM R0, R0, R7, 12582913 ; /* 0x4b40000100007423 */
/* 0x000fc80000004007 */
/*00e0*/ FADD R5, R0.reuse, -12583039 ; /* 0xcb40007f00057421 */
/* 0x040fe20000000000 */
/*00f0*/ SHF.L.U32 R0, R0, 0x17, RZ ; /* 0x0000001700007819 */
/* 0x000fc600000006ff */
/*0100*/ FFMA R5, R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */
/* 0x000fc80000000805 */
/*0110*/ FFMA R6, R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002067823 */
/* 0x000fe40000000005 */
/*0120*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0209 */
/*0130*/ MUFU.EX2 R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000000800 */
/*0140*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x001fca0000400000 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected expkernel_32
.globl expkernel_32
.p2align 8
.type expkernel_32,@function
expkernel_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
v_fma_f32 v4, v2, 0x3fb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel expkernel_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size expkernel_32, .Lfunc_end0-expkernel_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: expkernel_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: expkernel_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a948_00000000-6_exp_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
.type _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf, @function
_Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq expkernel_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf, .-_Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
.globl expkernel_32
.type expkernel_32, @function
expkernel_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12expkernel_32iPKfPfiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size expkernel_32, .-expkernel_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "expkernel_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq expkernel_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exp_32.hip"
.globl __device_stub__expkernel_32 # -- Begin function __device_stub__expkernel_32
.p2align 4, 0x90
.type __device_stub__expkernel_32,@function
__device_stub__expkernel_32: # @__device_stub__expkernel_32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $expkernel_32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__expkernel_32, .Lfunc_end0-__device_stub__expkernel_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $expkernel_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type expkernel_32,@object # @expkernel_32
.section .rodata,"a",@progbits
.globl expkernel_32
.p2align 3, 0x0
expkernel_32:
.quad __device_stub__expkernel_32
.size expkernel_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "expkernel_32"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__expkernel_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym expkernel_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} | code for sm_80
Function : _Z12gpu_gaussianiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR5, -UR4, UR7, URZ ; /* 0x0000000704057290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe13f */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR5, PT ; /* 0x0000000502007c0c */
/* 0x000fe2000bf06270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.GE.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fda0008706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0110*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fca00078e0200 */
/*0120*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fca0007ffe0ff */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0140*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} | .file "tmpxft_001115fb_00000000-6_gpu_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15gpu_applyFilterPfiS_i
.type _Z15gpu_applyFilterPfiS_i, @function
_Z15gpu_applyFilterPfiS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15gpu_applyFilterPfiS_i, .-_Z15gpu_applyFilterPfiS_i
.globl _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.type _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, @function
_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, .-_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.globl _Z12gpu_gaussianiiPfS_
.type _Z12gpu_gaussianiiPfS_, @function
_Z12gpu_gaussianiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpu_gaussianiiPfS_, .-_Z12gpu_gaussianiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12gpu_gaussianiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_gaussianiiPfS_
.globl _Z12gpu_gaussianiiPfS_
.p2align 8
.type _Z12gpu_gaussianiiPfS_,@function
_Z12gpu_gaussianiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s4, -2
s_add_i32 s3, s5, -2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, s4, v1, s[4:5]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v0, v0, v2, 1
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_gaussianiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_gaussianiiPfS_, .Lfunc_end0-_Z12gpu_gaussianiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_gaussianiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_gaussianiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float gpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
////////////////
// TO-DO #5.2 ////////////////////////////////////////////////
// Implement the GPU version of cpu_applyFilter() //
// //
// Does it make sense to have a separate gpu_applyFilter()? //
//////////////////////////////////////////////////////////////
return 0.0f;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
if (index_x < (width - 2) && index_y < (height - 2))
{
int offset_t = index_y * width + index_x;
int offset = (index_y + 1) * width + (index_x + 1);
image_out[offset] = gpu_applyFilter(&image[offset_t],
width, gaussian, 3);
}
} | .text
.file "gpu_gaussian.hip"
.globl _Z27__device_stub__gpu_gaussianiiPfS_ # -- Begin function _Z27__device_stub__gpu_gaussianiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__gpu_gaussianiiPfS_,@function
_Z27__device_stub__gpu_gaussianiiPfS_: # @_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_gaussianiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__gpu_gaussianiiPfS_, .Lfunc_end0-_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_gaussianiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_gaussianiiPfS_,@object # @_Z12gpu_gaussianiiPfS_
.section .rodata,"a",@progbits
.globl _Z12gpu_gaussianiiPfS_
.p2align 3, 0x0
_Z12gpu_gaussianiiPfS_:
.quad _Z27__device_stub__gpu_gaussianiiPfS_
.size _Z12gpu_gaussianiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpu_gaussianiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_gaussianiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_gaussianiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12gpu_gaussianiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR5, -UR4, UR7, URZ ; /* 0x0000000704057290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe13f */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR5, PT ; /* 0x0000000502007c0c */
/* 0x000fe2000bf06270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.GE.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fda0008706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0110*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fca00078e0200 */
/*0120*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fca0007ffe0ff */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0140*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_gaussianiiPfS_
.globl _Z12gpu_gaussianiiPfS_
.p2align 8
.type _Z12gpu_gaussianiiPfS_,@function
_Z12gpu_gaussianiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s4, -2
s_add_i32 s3, s5, -2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, s4, v1, s[4:5]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v0, v0, v2, 1
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_gaussianiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_gaussianiiPfS_, .Lfunc_end0-_Z12gpu_gaussianiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_gaussianiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_gaussianiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001115fb_00000000-6_gpu_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15gpu_applyFilterPfiS_i
.type _Z15gpu_applyFilterPfiS_i, @function
_Z15gpu_applyFilterPfiS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15gpu_applyFilterPfiS_i, .-_Z15gpu_applyFilterPfiS_i
.globl _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.type _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, @function
_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, .-_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.globl _Z12gpu_gaussianiiPfS_
.type _Z12gpu_gaussianiiPfS_, @function
_Z12gpu_gaussianiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpu_gaussianiiPfS_, .-_Z12gpu_gaussianiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12gpu_gaussianiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_gaussian.hip"
.globl _Z27__device_stub__gpu_gaussianiiPfS_ # -- Begin function _Z27__device_stub__gpu_gaussianiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__gpu_gaussianiiPfS_,@function
_Z27__device_stub__gpu_gaussianiiPfS_: # @_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_gaussianiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__gpu_gaussianiiPfS_, .Lfunc_end0-_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_gaussianiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_gaussianiiPfS_,@object # @_Z12gpu_gaussianiiPfS_
.section .rodata,"a",@progbits
.globl _Z12gpu_gaussianiiPfS_
.p2align 3, 0x0
_Z12gpu_gaussianiiPfS_:
.quad _Z27__device_stub__gpu_gaussianiiPfS_
.size _Z12gpu_gaussianiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpu_gaussianiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_gaussianiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_gaussianiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(cudaMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(cudaMemcpy(c_a, a, n * sizeof(int), cudaMemcpyHostToDevice));
HANDLE_ERROR(cudaMemcpy(c_b, b, n * sizeof(int), cudaMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
cudaDeviceSynchronize();
HANDLE_ERROR(cudaMemcpy(sum, c_sum, n * sizeof(int), cudaMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(cudaFree(c_a));
HANDLE_ERROR(cudaFree(c_b));
HANDLE_ERROR(cudaFree(c_sum));
return 0;
} | code for sm_80
Function : _Z9sumArraysPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea40000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R7, R6, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x0c0fe400078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(cudaMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(cudaMemcpy(c_a, a, n * sizeof(int), cudaMemcpyHostToDevice));
HANDLE_ERROR(cudaMemcpy(c_b, b, n * sizeof(int), cudaMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
cudaDeviceSynchronize();
HANDLE_ERROR(cudaMemcpy(sum, c_sum, n * sizeof(int), cudaMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(cudaFree(c_a));
HANDLE_ERROR(cudaFree(c_b));
HANDLE_ERROR(cudaFree(c_sum));
return 0;
} | .file "tmpxft_0000a25b_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L13
ret
.L13:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
.type _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_, @function
_Z32__device_stub__Z9sumArraysPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_, .-_Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
.globl _Z9sumArraysPiS_S_
.type _Z9sumArraysPiS_S_, @function
_Z9sumArraysPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9sumArraysPiS_S_, .-_Z9sumArraysPiS_S_
.section .rodata.str1.1
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ammusani/Parallel_Computing/main/Assignment_4/p2.cu"
.section .rodata.str1.1
.LC3:
.string "sum[%d] = %d\n"
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L45
.L25:
movq _ZL1n(%rip), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
.L26:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L47
.L27:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L48
.L28:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L49
.L29:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $45, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L50
.L30:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $46, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L51
.L31:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $47, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
jmp .L32
.L45:
call _ZL20__nv_init_managed_rtv
jmp .L25
.L46:
call _ZL20__nv_init_managed_rtv
jmp .L26
.L47:
call _ZL20__nv_init_managed_rtv
jmp .L27
.L48:
call _ZL20__nv_init_managed_rtv
jmp .L28
.L49:
call _ZL20__nv_init_managed_rtv
jmp .L29
.L50:
call _ZL20__nv_init_managed_rtv
jmp .L30
.L51:
call _ZL20__nv_init_managed_rtv
jmp .L31
.L33:
movq _ZL1n(%rip), %rax
cmpl %ebx, (%rax)
jle .L52
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
.L32:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L33
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L33
.L52:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L53
.L35:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $58, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L54
.L36:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $59, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L55
.L37:
movq _ZL1n(%rip), %rax
movl (%rax), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L38:
call cudaDeviceSynchronize@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L57
.L39:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $65, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC3(%rip), %r15
jmp .L40
.L53:
call _ZL20__nv_init_managed_rtv
jmp .L35
.L54:
call _ZL20__nv_init_managed_rtv
jmp .L36
.L55:
call _ZL20__nv_init_managed_rtv
jmp .L37
.L56:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
jmp .L38
.L57:
call _ZL20__nv_init_managed_rtv
jmp .L39
.L59:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
.L41:
movq _ZL1n(%rip), %rax
cmpl %ebx, (%rax)
jle .L58
movl 0(%rbp,%rbx,4), %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
.L40:
movl %ebx, %r14d
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L41
jmp .L59
.L58:
leaq .LC4(%rip), %rdi
call puts@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $75, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $76, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $77, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9sumArraysPiS_S_"
.LC6:
.string "n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL1n, @object
.size _ZL1n, 8
_ZL1n:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(cudaMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(cudaMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(cudaMemcpy(c_a, a, n * sizeof(int), cudaMemcpyHostToDevice));
HANDLE_ERROR(cudaMemcpy(c_b, b, n * sizeof(int), cudaMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
cudaDeviceSynchronize();
HANDLE_ERROR(cudaMemcpy(sum, c_sum, n * sizeof(int), cudaMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(cudaFree(c_a));
HANDLE_ERROR(cudaFree(c_b));
HANDLE_ERROR(cudaFree(c_sum));
return 0;
} | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(hipMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(hipMemcpy(c_a, a, n * sizeof(int), hipMemcpyHostToDevice));
HANDLE_ERROR(hipMemcpy(c_b, b, n * sizeof(int), hipMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
hipDeviceSynchronize();
HANDLE_ERROR(hipMemcpy(sum, c_sum, n * sizeof(int), hipMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(hipFree(c_a));
HANDLE_ERROR(hipFree(c_b));
HANDLE_ERROR(hipFree(c_sum));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(hipMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(hipMemcpy(c_a, a, n * sizeof(int), hipMemcpyHostToDevice));
HANDLE_ERROR(hipMemcpy(c_b, b, n * sizeof(int), hipMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
hipDeviceSynchronize();
HANDLE_ERROR(hipMemcpy(sum, c_sum, n * sizeof(int), hipMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(hipFree(c_a));
HANDLE_ERROR(hipFree(c_b));
HANDLE_ERROR(hipFree(c_sum));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumArraysPiS_S_
.globl _Z9sumArraysPiS_S_
.p2align 8
.type _Z9sumArraysPiS_S_,@function
_Z9sumArraysPiS_S_:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, n@rel32@lo+4
s_addc_u32 s3, s3, n@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumArraysPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumArraysPiS_S_, .Lfunc_end0-_Z9sumArraysPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected n.managed
.type n.managed,@object
.data
.globl n.managed
.p2align 2, 0x0
n.managed:
.long 5
.size n.managed, 4
.protected n
.type n,@object
.section .bss,"aw",@nobits
.globl n
.p2align 3, 0x0
n:
.quad 0
.size n, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym n.managed
.addrsig_sym n
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumArraysPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9sumArraysPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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