system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
__managed__ int n = 5;
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
__global__ void sumArrays(int *a, int *b, int *sum) {
int tid = threadIdx.x;
if(tid < n) {
sum[tid] = b[tid] + a[tid];
}
}
int main() {
scanf("%d", &n);
srand(time(0));
int *a;
int *b;
int *sum;
int *c_a;
int *c_b;
int *c_sum;
a = (int *)malloc(n * sizeof(int));
b = (int *)malloc(n * sizeof(int));
sum = (int *)malloc(n * sizeof(int));
HANDLE_ERROR(hipMalloc((void **)&c_a, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_b, n * sizeof(int)));
HANDLE_ERROR(hipMalloc((void **)&c_sum, n * sizeof(int)));
for (int i = 0; i < n; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
// To see the elements uncomment line 54 and 56, if this is 53
// printf("%d %d\n", a[i], b[i]);
}
// puts(" ");
HANDLE_ERROR(hipMemcpy(c_a, a, n * sizeof(int), hipMemcpyHostToDevice));
HANDLE_ERROR(hipMemcpy(c_b, b, n * sizeof(int), hipMemcpyHostToDevice));
sumArrays<<<1, n>>>(c_a, c_b, c_sum);
hipDeviceSynchronize();
HANDLE_ERROR(hipMemcpy(sum, c_sum, n * sizeof(int), hipMemcpyDeviceToHost));
for (int i = 0; i < n; i++) {
printf("sum[%d] = %d\n", i, sum[i]);
}
puts(" ");
free(a);
free(b);
free(sum);
HANDLE_ERROR(hipFree(c_a));
HANDLE_ERROR(hipFree(c_b));
HANDLE_ERROR(hipFree(c_sum));
return 0;
} | .text
.file "p2.hip"
.globl _Z24__device_stub__sumArraysPiS_S_ # -- Begin function _Z24__device_stub__sumArraysPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPiS_S_,@function
_Z24__device_stub__sumArraysPiS_S_: # @_Z24__device_stub__sumArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__sumArraysPiS_S_, .Lfunc_end0-_Z24__device_stub__sumArraysPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq n(%rip), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq n(%rip), %rax
movslq (%rax), %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movq n(%rip), %rax
movslq (%rax), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit21
movq n(%rip), %rax
movslq (%rax), %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_26
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit23.preheader
movq n(%rip), %rax
movl (%rax), %eax
testl %eax, %eax
jle .LBB1_9
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit23.preheader57
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %_ZL11HandleError10hipError_tPKci.exit23
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
movq n(%rip), %rax
movslq (%rax), %rax
cmpq %rax, %r12
jl .LBB1_8
.LBB1_9: # %_ZL11HandleError10hipError_tPKci.exit23._crit_edge
movq 16(%rsp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit25
movq 8(%rsp), %rdi
movq n(%rip), %rax
movslq (%rax), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit27
movq n(%rip), %rax
movl (%rax), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sumArraysPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq n(%rip), %rax
movslq (%rax), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.16: # %_ZL11HandleError10hipError_tPKci.exit29.preheader
movq n(%rip), %rax
cmpl $0, (%rax)
jle .LBB1_19
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit29.preheader56
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_18: # %_ZL11HandleError10hipError_tPKci.exit29
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
movq n(%rip), %rax
movslq (%rax), %rax
cmpq %rax, %r12
jl .LBB1_18
.LBB1_19: # %_ZL11HandleError10hipError_tPKci.exit29._crit_edge
movl $.L.str.3, %edi
callq puts
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit31
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL11HandleError10hipError_tPKci.exit33
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_ZL11HandleError10hipError_tPKci.exit35
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $47, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $48, %ecx
jmp .LBB1_2
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB1_2
.LBB1_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $60, %ecx
jmp .LBB1_2
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $61, %ecx
jmp .LBB1_2
.LBB1_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $67, %ecx
jmp .LBB1_2
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_2
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB1_2
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $79, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $n, %esi
movl $n.managed, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r8d
movq %rbx, %rdi
movl $4, %r9d
callq __hipRegisterManagedVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type n.managed,@object # @n.managed
.data
.p2align 2, 0x0
n.managed:
.long 5 # 0x5
.size n.managed, 4
.type _Z9sumArraysPiS_S_,@object # @_Z9sumArraysPiS_S_
.section .rodata,"a",@progbits
.globl _Z9sumArraysPiS_S_
.p2align 3, 0x0
_Z9sumArraysPiS_S_:
.quad _Z24__device_stub__sumArraysPiS_S_
.size _Z9sumArraysPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ammusani/Parallel_Computing/main/Assignment_4/p2.hip"
.size .L.str.1, 110
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sum[%d] = %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumArraysPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "n"
.size .L__unnamed_2, 2
.type n,@object # @n
.local n
.comm n,8,8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumArraysPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym n.managed
.addrsig_sym _Z9sumArraysPiS_S_
.addrsig_sym n
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sumArraysPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea40000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R7, R6, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x0c0fe400078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumArraysPiS_S_
.globl _Z9sumArraysPiS_S_
.p2align 8
.type _Z9sumArraysPiS_S_,@function
_Z9sumArraysPiS_S_:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, n@rel32@lo+4
s_addc_u32 s3, s3, n@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumArraysPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumArraysPiS_S_, .Lfunc_end0-_Z9sumArraysPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected n.managed
.type n.managed,@object
.data
.globl n.managed
.p2align 2, 0x0
n.managed:
.long 5
.size n.managed, 4
.protected n
.type n,@object
.section .bss,"aw",@nobits
.globl n
.p2align 3, 0x0
n:
.quad 0
.size n, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym n.managed
.addrsig_sym n
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumArraysPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9sumArraysPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000a25b_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L13
ret
.L13:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
.type _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_, @function
_Z32__device_stub__Z9sumArraysPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_, .-_Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
.globl _Z9sumArraysPiS_S_
.type _Z9sumArraysPiS_S_, @function
_Z9sumArraysPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9sumArraysPiS_S_, .-_Z9sumArraysPiS_S_
.section .rodata.str1.1
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ammusani/Parallel_Computing/main/Assignment_4/p2.cu"
.section .rodata.str1.1
.LC3:
.string "sum[%d] = %d\n"
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L45
.L25:
movq _ZL1n(%rip), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
.L26:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L47
.L27:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L48
.L28:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L49
.L29:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $45, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L50
.L30:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $46, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L51
.L31:
movq _ZL1n(%rip), %rax
movslq (%rax), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $47, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
jmp .L32
.L45:
call _ZL20__nv_init_managed_rtv
jmp .L25
.L46:
call _ZL20__nv_init_managed_rtv
jmp .L26
.L47:
call _ZL20__nv_init_managed_rtv
jmp .L27
.L48:
call _ZL20__nv_init_managed_rtv
jmp .L28
.L49:
call _ZL20__nv_init_managed_rtv
jmp .L29
.L50:
call _ZL20__nv_init_managed_rtv
jmp .L30
.L51:
call _ZL20__nv_init_managed_rtv
jmp .L31
.L33:
movq _ZL1n(%rip), %rax
cmpl %ebx, (%rax)
jle .L52
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
.L32:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L33
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L33
.L52:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L53
.L35:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $58, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L54
.L36:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $59, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L55
.L37:
movq _ZL1n(%rip), %rax
movl (%rax), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L38:
call cudaDeviceSynchronize@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L57
.L39:
movq _ZL1n(%rip), %rax
movslq (%rax), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $65, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC3(%rip), %r15
jmp .L40
.L53:
call _ZL20__nv_init_managed_rtv
jmp .L35
.L54:
call _ZL20__nv_init_managed_rtv
jmp .L36
.L55:
call _ZL20__nv_init_managed_rtv
jmp .L37
.L56:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9sumArraysPiS_S_PiS_S_
jmp .L38
.L57:
call _ZL20__nv_init_managed_rtv
jmp .L39
.L59:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
.L41:
movq _ZL1n(%rip), %rax
cmpl %ebx, (%rax)
jle .L58
movl 0(%rbp,%rbx,4), %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
.L40:
movl %ebx, %r14d
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L41
jmp .L59
.L58:
leaq .LC4(%rip), %rdi
call puts@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $75, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $76, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $77, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9sumArraysPiS_S_"
.LC6:
.string "n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL1n, @object
.size _ZL1n, 8
_ZL1n:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2.hip"
.globl _Z24__device_stub__sumArraysPiS_S_ # -- Begin function _Z24__device_stub__sumArraysPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPiS_S_,@function
_Z24__device_stub__sumArraysPiS_S_: # @_Z24__device_stub__sumArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__sumArraysPiS_S_, .Lfunc_end0-_Z24__device_stub__sumArraysPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq n(%rip), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq n(%rip), %rax
movslq (%rax), %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movq n(%rip), %rax
movslq (%rax), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit21
movq n(%rip), %rax
movslq (%rax), %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_26
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit23.preheader
movq n(%rip), %rax
movl (%rax), %eax
testl %eax, %eax
jle .LBB1_9
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit23.preheader57
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %_ZL11HandleError10hipError_tPKci.exit23
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
movq n(%rip), %rax
movslq (%rax), %rax
cmpq %rax, %r12
jl .LBB1_8
.LBB1_9: # %_ZL11HandleError10hipError_tPKci.exit23._crit_edge
movq 16(%rsp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit25
movq 8(%rsp), %rdi
movq n(%rip), %rax
movslq (%rax), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit27
movq n(%rip), %rax
movl (%rax), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sumArraysPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq n(%rip), %rax
movslq (%rax), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.16: # %_ZL11HandleError10hipError_tPKci.exit29.preheader
movq n(%rip), %rax
cmpl $0, (%rax)
jle .LBB1_19
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit29.preheader56
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_18: # %_ZL11HandleError10hipError_tPKci.exit29
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
movq n(%rip), %rax
movslq (%rax), %rax
cmpq %rax, %r12
jl .LBB1_18
.LBB1_19: # %_ZL11HandleError10hipError_tPKci.exit29._crit_edge
movl $.L.str.3, %edi
callq puts
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit31
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL11HandleError10hipError_tPKci.exit33
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_ZL11HandleError10hipError_tPKci.exit35
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $47, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $48, %ecx
jmp .LBB1_2
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB1_2
.LBB1_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $60, %ecx
jmp .LBB1_2
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $61, %ecx
jmp .LBB1_2
.LBB1_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $67, %ecx
jmp .LBB1_2
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_2
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB1_2
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $79, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $n, %esi
movl $n.managed, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r8d
movq %rbx, %rdi
movl $4, %r9d
callq __hipRegisterManagedVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type n.managed,@object # @n.managed
.data
.p2align 2, 0x0
n.managed:
.long 5 # 0x5
.size n.managed, 4
.type _Z9sumArraysPiS_S_,@object # @_Z9sumArraysPiS_S_
.section .rodata,"a",@progbits
.globl _Z9sumArraysPiS_S_
.p2align 3, 0x0
_Z9sumArraysPiS_S_:
.quad _Z24__device_stub__sumArraysPiS_S_
.size _Z9sumArraysPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ammusani/Parallel_Computing/main/Assignment_4/p2.hip"
.size .L.str.1, 110
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sum[%d] = %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumArraysPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "n"
.size .L__unnamed_2, 2
.type n,@object # @n
.local n
.comm n,8,8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumArraysPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym n.managed
.addrsig_sym _Z9sumArraysPiS_S_
.addrsig_sym n
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} | code for sm_80
Function : _Z4prodiPffS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5sommeiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} | .file "tmpxft_000a8735_00000000-6_vec_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
.type _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, @function
_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sommeiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, .-_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
.globl _Z5sommeiPfS_S_
.type _Z5sommeiPfS_S_, @function
_Z5sommeiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sommeiPfS_S_, .-_Z5sommeiPfS_S_
.globl _Z27__device_stub__Z4prodiPffS_iPffS_
.type _Z27__device_stub__Z4prodiPffS_iPffS_, @function
_Z27__device_stub__Z4prodiPffS_iPffS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 24(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4prodiPffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z4prodiPffS_iPffS_, .-_Z27__device_stub__Z4prodiPffS_iPffS_
.globl _Z4prodiPffS_
.type _Z4prodiPffS_, @function
_Z4prodiPffS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4prodiPffS_iPffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4prodiPffS_, .-_Z4prodiPffS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4prodiPffS_"
.LC1:
.string "_Z5sommeiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4prodiPffS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sommeiPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sommeiPfS_S_
.globl _Z5sommeiPfS_S_
.p2align 8
.type _Z5sommeiPfS_S_,@function
_Z5sommeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sommeiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sommeiPfS_S_, .Lfunc_end0-_Z5sommeiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4prodiPffS_
.globl _Z4prodiPffS_
.p2align 8
.type _Z4prodiPffS_,@function
_Z4prodiPffS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s4, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4prodiPffS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4prodiPffS_, .Lfunc_end1-_Z4prodiPffS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sommeiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sommeiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4prodiPffS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4prodiPffS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]*b;
} | .text
.file "vec_sum.hip"
.globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_
.p2align 4, 0x90
.type _Z20__device_stub__sommeiPfS_S_,@function
_Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sommeiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sommeiPfS_S_, .Lfunc_end0-_Z20__device_stub__sommeiPfS_S_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__prodiPffS_ # -- Begin function _Z19__device_stub__prodiPffS_
.p2align 4, 0x90
.type _Z19__device_stub__prodiPffS_,@function
_Z19__device_stub__prodiPffS_: # @_Z19__device_stub__prodiPffS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movss %xmm0, 8(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4prodiPffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__prodiPffS_, .Lfunc_end1-_Z19__device_stub__prodiPffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sommeiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4prodiPffS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sommeiPfS_S_,@object # @_Z5sommeiPfS_S_
.section .rodata,"a",@progbits
.globl _Z5sommeiPfS_S_
.p2align 3, 0x0
_Z5sommeiPfS_S_:
.quad _Z20__device_stub__sommeiPfS_S_
.size _Z5sommeiPfS_S_, 8
.type _Z4prodiPffS_,@object # @_Z4prodiPffS_
.globl _Z4prodiPffS_
.p2align 3, 0x0
_Z4prodiPffS_:
.quad _Z19__device_stub__prodiPffS_
.size _Z4prodiPffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sommeiPfS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4prodiPffS_"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sommeiPfS_S_
.addrsig_sym _Z19__device_stub__prodiPffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sommeiPfS_S_
.addrsig_sym _Z4prodiPffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4prodiPffS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5sommeiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sommeiPfS_S_
.globl _Z5sommeiPfS_S_
.p2align 8
.type _Z5sommeiPfS_S_,@function
_Z5sommeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sommeiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sommeiPfS_S_, .Lfunc_end0-_Z5sommeiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4prodiPffS_
.globl _Z4prodiPffS_
.p2align 8
.type _Z4prodiPffS_,@function
_Z4prodiPffS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s4, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4prodiPffS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4prodiPffS_, .Lfunc_end1-_Z4prodiPffS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sommeiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sommeiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4prodiPffS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4prodiPffS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8735_00000000-6_vec_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
.type _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, @function
_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sommeiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, .-_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
.globl _Z5sommeiPfS_S_
.type _Z5sommeiPfS_S_, @function
_Z5sommeiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sommeiPfS_S_, .-_Z5sommeiPfS_S_
.globl _Z27__device_stub__Z4prodiPffS_iPffS_
.type _Z27__device_stub__Z4prodiPffS_iPffS_, @function
_Z27__device_stub__Z4prodiPffS_iPffS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 24(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4prodiPffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z4prodiPffS_iPffS_, .-_Z27__device_stub__Z4prodiPffS_iPffS_
.globl _Z4prodiPffS_
.type _Z4prodiPffS_, @function
_Z4prodiPffS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4prodiPffS_iPffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4prodiPffS_, .-_Z4prodiPffS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4prodiPffS_"
.LC1:
.string "_Z5sommeiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4prodiPffS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sommeiPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_sum.hip"
.globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_
.p2align 4, 0x90
.type _Z20__device_stub__sommeiPfS_S_,@function
_Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sommeiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sommeiPfS_S_, .Lfunc_end0-_Z20__device_stub__sommeiPfS_S_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__prodiPffS_ # -- Begin function _Z19__device_stub__prodiPffS_
.p2align 4, 0x90
.type _Z19__device_stub__prodiPffS_,@function
_Z19__device_stub__prodiPffS_: # @_Z19__device_stub__prodiPffS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movss %xmm0, 8(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4prodiPffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__prodiPffS_, .Lfunc_end1-_Z19__device_stub__prodiPffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sommeiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4prodiPffS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sommeiPfS_S_,@object # @_Z5sommeiPfS_S_
.section .rodata,"a",@progbits
.globl _Z5sommeiPfS_S_
.p2align 3, 0x0
_Z5sommeiPfS_S_:
.quad _Z20__device_stub__sommeiPfS_S_
.size _Z5sommeiPfS_S_, 8
.type _Z4prodiPffS_,@object # @_Z4prodiPffS_
.globl _Z4prodiPffS_
.p2align 3, 0x0
_Z4prodiPffS_:
.quad _Z19__device_stub__prodiPffS_
.size _Z4prodiPffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sommeiPfS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4prodiPffS_"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sommeiPfS_S_
.addrsig_sym _Z19__device_stub__prodiPffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sommeiPfS_S_
.addrsig_sym _Z4prodiPffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------------------------------
// Compute an histogram of how many 0's and 1's are set using the current mask
__global__ void Gpu_Histogram (unsigned int *in, unsigned int *bins, const unsigned int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bin = (in[tid] & mask) >> i;
atomicAdd(&bins[bin],1);
}
// Compute an exclusive scan on the input array and store the result on the output array
__global__ void Gpu_ExScan (unsigned int *in, unsigned int *out, const size_t n)
{
extern __shared__ unsigned int cache2[];
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int offset = 1;
// Load the input into shared memory
cache2[2*tid] = in[2*tid];
cache2[2*tid+1] = in[2*tid+1];
__syncthreads();
// Build sum in place up the tree
for (int d = n >> 1; d > 0; d >>= 1)
{
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
cache2[bi] += cache2[ai];
}
offset *= 2;
}
// Clear the last element
if (tid == 0)
{
cache2[n-1] = 0;
}
// Transverse down and build scan
for (int d = 1; d < n; d *= 2)
{
offset >>= 1;
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
// Avoiding read-write bugs
int aux = cache2[ai];
cache2[ai] = cache2[bi];
cache2[bi] += aux;
}
}
__syncthreads();
// Write results to output
out[2*tid] = cache2[2*tid];
out[2*tid+1] = cache2[2*tid+1];
offset = out[1];
//__syncthreads();
//if (tid == 0)
// printf("Binscan 0 = %u || Binscan 1 = %u\n",out[0],out[1]);
}
// Calculate the predicate of each element on the input
__global__ void Gpu_Predicate (unsigned int *in, unsigned int *out, unsigned int *nout, const int mask, const int i)
{
int tid = threadIdx.x;
// Predicate format = Check if the ith bit of the element is set
unsigned int bit = (in[tid] & mask) >> i;
out[tid] = bit;
nout[tid] = !bit;
}
// Map the correct position of each element on input based on the scan array of the predicate
__global__ void Gpu_Mapping (unsigned int *in, unsigned int *out, unsigned int *bscan, unsigned int *scan, unsigned int *nscan, const int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bit = (in[tid] & mask) >> i;
// If bit is 1, than pred[tid] is active
if (bit)
{
int offset = bscan[1];
out[scan[tid] + offset] = in[tid];
}
// Bit 0 is active in npred[tid]
else
{
out[nscan[tid]] = in[tid];
}
}
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- CPU Functions ----------------------------------------------------------
void Print (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
printf("%4u\n",v[i]);
printf("\n");
}
void GetInput (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
scanf("%u",&v[i]);
}
void Swap (unsigned int* &a, unsigned int* &b)
{
unsigned int *temp = a;
a = b;
b = temp;
}
void RadixSort (unsigned int *in, unsigned int *out, const unsigned int N)
{
// Define kernel dimension
dim3 gridSize(1,1);
dim3 blockSize(N,1);
const int numBits = 1;
const int numBins = 2;
// Shared memory sizes
size_t sizeBins = sizeof(unsigned int)*numBins;
size_t sizeN = sizeof(unsigned int)*N;
// Allocate GPU memory
unsigned int *binHistogram, *binScan, *pred, *npred, *scan, *nscan;
cudaMalloc(&binHistogram,sizeof(unsigned int)*numBins);
cudaMalloc(&binScan,sizeof(unsigned int)*numBins);
cudaMalloc(&pred,sizeof(unsigned int)*N);
cudaMalloc(&npred,sizeof(unsigned int)*N);
cudaMalloc(&scan,sizeof(unsigned int)*N);
cudaMalloc(&nscan,sizeof(unsigned int)*N);
for (int i = 0; i < 8 * sizeof(unsigned int); i += numBits)
{
unsigned int mask = numBits << i;
// Reset the bins
cudaMemset(binHistogram,0,sizeof(unsigned int)*numBins);
cudaMemset(binScan,0,sizeof(unsigned int)*numBins);
// Call kernel to compute histogram
Gpu_Histogram<<<gridSize,blockSize>>>(in,binHistogram,mask,i);
// Call kernel to compute the exclusive scan on the histogram
Gpu_ExScan<<<1,numBins,2*sizeBins>>>(binHistogram,binScan,numBins);
// Call kernel that calculate the predicate
Gpu_Predicate<<<gridSize,blockSize>>>(in,pred,npred,mask,i);
// Call kernel to compute the exclusive scan on the predicates
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(pred,scan,N);
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(npred,nscan,N);
// Call kernel to do the final mapping using the scan array
Gpu_Mapping<<<gridSize,blockSize>>>(in,out,binScan,scan,nscan,mask,i);
Swap(out,in);
}
cudaMemcpy(out,in,sizeof(unsigned int)*N,cudaMemcpyDeviceToDevice);
// Free memory
cudaFree(binHistogram);
cudaFree(binScan);
cudaFree(pred);
cudaFree(npred);
cudaFree(scan);
cudaFree(nscan);
}
void Usage (char pName[])
{
printf("============================================\n");
printf("Usage:> %s < 'input_filename'\n",pName);
printf("Example:> %s < input\n",pName);
printf("============================================\n");
}
// ---------------------------------------------------------------------------------------------------------------------------
// ------------------------------------------------ MAIN FUNCTION ------------------------------------------------------------
int main (int argc, char *argv[])
{
if (argc-1 != 0)
{
Usage(argv[0]);
exit(1);
}
// Read size of the input
unsigned int N;
scanf("%u",&N);
// Declare and allocate memory for the host
unsigned int *in, *out;
unsigned int *d_in, *d_out;
in = new unsigned int[N]();
out = new unsigned int[N]();
cudaMalloc(&d_in,sizeof(unsigned int)*N);
cudaMalloc(&d_out,sizeof(unsigned int)*N);
// Get or Generate the array to sort
GetInput(in,N);
Print(in,N);
// Copy the array to the GPU
cudaMemcpy(d_in,in,sizeof(unsigned int)*N,cudaMemcpyHostToDevice);
// Initialize output array
cudaMemset(d_out,0,sizeof(unsigned int)*N);
// Sort the array using RadixSort
RadixSort(d_in,d_out,N);
// Print the result
cudaMemcpy(out,d_out,sizeof(unsigned int)*N,cudaMemcpyDeviceToHost);
Print(out,N);
delete [] in;
delete [] out;
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11Gpu_MappingPjS_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R10, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e020a */
/*0050*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0060*/ LOP3.LUT R0, R11, c[0x0][0x188], RZ, 0xc0, !PT ; /* 0x000062000b007a12 */
/* 0x004fc800078ec0ff */
/*0070*/ SHF.R.U32.HI R0, RZ, c[0x0][0x18c], R0 ; /* 0x00006300ff007a19 */
/* 0x000fc80000011600 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fd60000011409 */
/*00a0*/ @P0 LEA R6, P1, R9.reuse, c[0x0][0x178], 0x2 ; /* 0x00005e0009060a11 */
/* 0x040fe200078210ff */
/*00b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff050624 */
/* 0x000fe400078e00ff */
/*00c0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff040624 */
/* 0x000fe200078e00ff */
/*00d0*/ @P0 LEA.HI.X R7, R9, c[0x0][0x17c], R0, 0x2, P1 ; /* 0x00005f0009070a11 */
/* 0x000fc800008f1400 */
/*00e0*/ @P0 LDG.E R5, [R4.64+0x4] ; /* 0x0000040404050981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @P0 LDG.E R6, [R6.64] ; /* 0x0000000406060981 */
/* 0x000ea2000c1e1900 */
/*0100*/ @!P0 LEA R8, P1, R9, c[0x0][0x180], 0x2 ; /* 0x0000600009088a11 */
/* 0x000fc800078210ff */
/*0110*/ @!P0 LEA.HI.X R9, R9, c[0x0][0x184], R0, 0x2, P1 ; /* 0x0000610009098a11 */
/* 0x000fe200008f1400 */
/*0120*/ @P0 IMAD.IADD R2, R6, 0x1, R5 ; /* 0x0000000106020824 */
/* 0x004fcc00078e0205 */
/*0130*/ @!P0 LDG.E R2, [R8.64] ; /* 0x0000000408028981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R2, R2, R10, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e000a */
/*0150*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13Gpu_PredicatePjS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0080*/ LOP3.LUT R0, R2, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e0002007a12 */
/* 0x004fc800078ec0ff */
/*0090*/ SHF.R.U32.HI R9, RZ, c[0x0][0x17c], R0 ; /* 0x00005f00ff097a19 */
/* 0x000fc80000011600 */
/*00a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe6000c101904 */
/*00c0*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x000fca0000000000 */
/*00d0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10Gpu_ExScanPjS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*00d0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fca00078e00ff */
/*00f0*/ SHF.R.U64 R10, R10, R3, c[0x0][0x174] ; /* 0x00005d000a0a7619 */
/* 0x000fe40000001203 */
/*0100*/ IADD3 R3, R0, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f26270 */
/*0120*/ @!P0 LEA R9, R12, 0xfffffffc, 0x2 ; /* 0xfffffffc0c098811 */
/* 0x000fe200078e10ff */
/*0130*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0041e80000008a00 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P1 BRA 0x250 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0170*/ MOV R8, 0x1 ; /* 0x0000000100087802 */
/* 0x000fc60000000f00 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc40003f26270 */
/*01a0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fd60000011605 */
/*01b0*/ @!P1 IMAD R4, R3, R8, RZ ; /* 0x0000000803049224 */
/* 0x000fc800078e02ff */
/*01c0*/ @!P1 IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404079824 */
/* 0x001fc800078e00ff */
/*01d0*/ @!P1 IMAD R11, R8.reuse, 0x4, R7 ; /* 0x00000004080b9824 */
/* 0x040fe200078e0207 */
/*01e0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fe200000006ff */
/*01f0*/ @!P1 LDS R7, [R4.X4+-0x4] ; /* 0xfffffc0004079984 */
/* 0x000fe80000004800 */
/*0200*/ @!P1 LDS R6, [R11+-0x4] ; /* 0xfffffc000b069984 */
/* 0x000e240000000800 */
/*0210*/ @!P1 IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106069824 */
/* 0x001fca00078e0207 */
/*0220*/ @!P1 STS [R11+-0x4], R6 ; /* 0xfffffc060b009388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0240*/ @P1 BRA 0x180 ; /* 0xffffff3000001947 */
/* 0x001fea000383ffff */
/*0250*/ @!P0 STS [R9], RZ ; /* 0x000000ff09008388 */
/* 0x0003e20000000800 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f06070 */
/*0280*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011400 */
/*0290*/ ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f06100 */
/*02a0*/ @!P0 BRA 0x3f0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x002fc800078e00ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f26270 */
/*02e0*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*02f0*/ SHF.R.S32.HI R8, RZ, 0x1, R8 ; /* 0x00000001ff087819 */
/* 0x000fc60000011408 */
/*0300*/ BSSY B0, 0x3e0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06070 */
/*0320*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fc60003f06100 */
/*0330*/ @P1 BRA 0x3d0 ; /* 0x0000009000001947 */
/* 0x001fea0003800000 */
/*0340*/ IMAD R4, R3, R8, RZ ; /* 0x0000000803047224 */
/* 0x000fca00078e02ff */
/*0350*/ SHF.L.U32 R7, R4, 0x2, RZ ; /* 0x0000000204077819 */
/* 0x001fe200000006ff */
/*0360*/ LDS R6, [R4.X4+-0x4] ; /* 0xfffffc0004067984 */
/* 0x000fe80000004800 */
/*0370*/ IMAD R11, R8, 0x4, R7 ; /* 0x00000004080b7824 */
/* 0x000fca00078e0207 */
/*0380*/ LDS R7, [R11+-0x4] ; /* 0xfffffc000b077984 */
/* 0x000e280000000800 */
/*0390*/ STS [R4.X4+-0x4], R7 ; /* 0xfffffc0704007388 */
/* 0x001fe80000004800 */
/*03a0*/ LDS R9, [R11+-0x4] ; /* 0xfffffc000b097984 */
/* 0x000e240000000800 */
/*03b0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x001fca00078e0209 */
/*03c0*/ STS [R11+-0x4], R6 ; /* 0xfffffc060b007388 */
/* 0x0001e40000000800 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P0 BRA 0x2c0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fe20000010000 */
/*0400*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0410*/ LEA.HI.X R5, R0, c[0x0][0x16c], R13, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f140d */
/*0420*/ LDS.64 R2, [R2.X8] ; /* 0x0000000002027984 */
/* 0x001e280000008a00 */
/*0430*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe8000c101904 */
/*0440*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x000fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13Gpu_HistogramPjS_ji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0070*/ LOP3.LUT R0, R2, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0002007a12 */
/* 0x004fc800078ec0ff */
/*0080*/ SHF.R.U32.HI R0, RZ, c[0x0][0x174], R0 ; /* 0x00005d00ff007a19 */
/* 0x000fca0000011600 */
/*0090*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------------------------------
// Compute an histogram of how many 0's and 1's are set using the current mask
__global__ void Gpu_Histogram (unsigned int *in, unsigned int *bins, const unsigned int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bin = (in[tid] & mask) >> i;
atomicAdd(&bins[bin],1);
}
// Compute an exclusive scan on the input array and store the result on the output array
__global__ void Gpu_ExScan (unsigned int *in, unsigned int *out, const size_t n)
{
extern __shared__ unsigned int cache2[];
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int offset = 1;
// Load the input into shared memory
cache2[2*tid] = in[2*tid];
cache2[2*tid+1] = in[2*tid+1];
__syncthreads();
// Build sum in place up the tree
for (int d = n >> 1; d > 0; d >>= 1)
{
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
cache2[bi] += cache2[ai];
}
offset *= 2;
}
// Clear the last element
if (tid == 0)
{
cache2[n-1] = 0;
}
// Transverse down and build scan
for (int d = 1; d < n; d *= 2)
{
offset >>= 1;
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
// Avoiding read-write bugs
int aux = cache2[ai];
cache2[ai] = cache2[bi];
cache2[bi] += aux;
}
}
__syncthreads();
// Write results to output
out[2*tid] = cache2[2*tid];
out[2*tid+1] = cache2[2*tid+1];
offset = out[1];
//__syncthreads();
//if (tid == 0)
// printf("Binscan 0 = %u || Binscan 1 = %u\n",out[0],out[1]);
}
// Calculate the predicate of each element on the input
__global__ void Gpu_Predicate (unsigned int *in, unsigned int *out, unsigned int *nout, const int mask, const int i)
{
int tid = threadIdx.x;
// Predicate format = Check if the ith bit of the element is set
unsigned int bit = (in[tid] & mask) >> i;
out[tid] = bit;
nout[tid] = !bit;
}
// Map the correct position of each element on input based on the scan array of the predicate
__global__ void Gpu_Mapping (unsigned int *in, unsigned int *out, unsigned int *bscan, unsigned int *scan, unsigned int *nscan, const int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bit = (in[tid] & mask) >> i;
// If bit is 1, than pred[tid] is active
if (bit)
{
int offset = bscan[1];
out[scan[tid] + offset] = in[tid];
}
// Bit 0 is active in npred[tid]
else
{
out[nscan[tid]] = in[tid];
}
}
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- CPU Functions ----------------------------------------------------------
void Print (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
printf("%4u\n",v[i]);
printf("\n");
}
void GetInput (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
scanf("%u",&v[i]);
}
void Swap (unsigned int* &a, unsigned int* &b)
{
unsigned int *temp = a;
a = b;
b = temp;
}
void RadixSort (unsigned int *in, unsigned int *out, const unsigned int N)
{
// Define kernel dimension
dim3 gridSize(1,1);
dim3 blockSize(N,1);
const int numBits = 1;
const int numBins = 2;
// Shared memory sizes
size_t sizeBins = sizeof(unsigned int)*numBins;
size_t sizeN = sizeof(unsigned int)*N;
// Allocate GPU memory
unsigned int *binHistogram, *binScan, *pred, *npred, *scan, *nscan;
cudaMalloc(&binHistogram,sizeof(unsigned int)*numBins);
cudaMalloc(&binScan,sizeof(unsigned int)*numBins);
cudaMalloc(&pred,sizeof(unsigned int)*N);
cudaMalloc(&npred,sizeof(unsigned int)*N);
cudaMalloc(&scan,sizeof(unsigned int)*N);
cudaMalloc(&nscan,sizeof(unsigned int)*N);
for (int i = 0; i < 8 * sizeof(unsigned int); i += numBits)
{
unsigned int mask = numBits << i;
// Reset the bins
cudaMemset(binHistogram,0,sizeof(unsigned int)*numBins);
cudaMemset(binScan,0,sizeof(unsigned int)*numBins);
// Call kernel to compute histogram
Gpu_Histogram<<<gridSize,blockSize>>>(in,binHistogram,mask,i);
// Call kernel to compute the exclusive scan on the histogram
Gpu_ExScan<<<1,numBins,2*sizeBins>>>(binHistogram,binScan,numBins);
// Call kernel that calculate the predicate
Gpu_Predicate<<<gridSize,blockSize>>>(in,pred,npred,mask,i);
// Call kernel to compute the exclusive scan on the predicates
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(pred,scan,N);
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(npred,nscan,N);
// Call kernel to do the final mapping using the scan array
Gpu_Mapping<<<gridSize,blockSize>>>(in,out,binScan,scan,nscan,mask,i);
Swap(out,in);
}
cudaMemcpy(out,in,sizeof(unsigned int)*N,cudaMemcpyDeviceToDevice);
// Free memory
cudaFree(binHistogram);
cudaFree(binScan);
cudaFree(pred);
cudaFree(npred);
cudaFree(scan);
cudaFree(nscan);
}
void Usage (char pName[])
{
printf("============================================\n");
printf("Usage:> %s < 'input_filename'\n",pName);
printf("Example:> %s < input\n",pName);
printf("============================================\n");
}
// ---------------------------------------------------------------------------------------------------------------------------
// ------------------------------------------------ MAIN FUNCTION ------------------------------------------------------------
int main (int argc, char *argv[])
{
if (argc-1 != 0)
{
Usage(argv[0]);
exit(1);
}
// Read size of the input
unsigned int N;
scanf("%u",&N);
// Declare and allocate memory for the host
unsigned int *in, *out;
unsigned int *d_in, *d_out;
in = new unsigned int[N]();
out = new unsigned int[N]();
cudaMalloc(&d_in,sizeof(unsigned int)*N);
cudaMalloc(&d_out,sizeof(unsigned int)*N);
// Get or Generate the array to sort
GetInput(in,N);
Print(in,N);
// Copy the array to the GPU
cudaMemcpy(d_in,in,sizeof(unsigned int)*N,cudaMemcpyHostToDevice);
// Initialize output array
cudaMemset(d_out,0,sizeof(unsigned int)*N);
// Sort the array using RadixSort
RadixSort(d_in,d_out,N);
// Print the result
cudaMemcpy(out,d_out,sizeof(unsigned int)*N,cudaMemcpyDeviceToHost);
Print(out,N);
delete [] in;
delete [] out;
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------------------------------
// Compute an histogram of how many 0's and 1's are set using the current mask
__global__ void Gpu_Histogram (unsigned int *in, unsigned int *bins, const unsigned int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bin = (in[tid] & mask) >> i;
atomicAdd(&bins[bin],1);
}
// Compute an exclusive scan on the input array and store the result on the output array
__global__ void Gpu_ExScan (unsigned int *in, unsigned int *out, const size_t n)
{
extern __shared__ unsigned int cache2[];
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int offset = 1;
// Load the input into shared memory
cache2[2*tid] = in[2*tid];
cache2[2*tid+1] = in[2*tid+1];
__syncthreads();
// Build sum in place up the tree
for (int d = n >> 1; d > 0; d >>= 1)
{
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
cache2[bi] += cache2[ai];
}
offset *= 2;
}
// Clear the last element
if (tid == 0)
{
cache2[n-1] = 0;
}
// Transverse down and build scan
for (int d = 1; d < n; d *= 2)
{
offset >>= 1;
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
// Avoiding read-write bugs
int aux = cache2[ai];
cache2[ai] = cache2[bi];
cache2[bi] += aux;
}
}
__syncthreads();
// Write results to output
out[2*tid] = cache2[2*tid];
out[2*tid+1] = cache2[2*tid+1];
offset = out[1];
//__syncthreads();
//if (tid == 0)
// printf("Binscan 0 = %u || Binscan 1 = %u\n",out[0],out[1]);
}
// Calculate the predicate of each element on the input
__global__ void Gpu_Predicate (unsigned int *in, unsigned int *out, unsigned int *nout, const int mask, const int i)
{
int tid = threadIdx.x;
// Predicate format = Check if the ith bit of the element is set
unsigned int bit = (in[tid] & mask) >> i;
out[tid] = bit;
nout[tid] = !bit;
}
// Map the correct position of each element on input based on the scan array of the predicate
__global__ void Gpu_Mapping (unsigned int *in, unsigned int *out, unsigned int *bscan, unsigned int *scan, unsigned int *nscan, const int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bit = (in[tid] & mask) >> i;
// If bit is 1, than pred[tid] is active
if (bit)
{
int offset = bscan[1];
out[scan[tid] + offset] = in[tid];
}
// Bit 0 is active in npred[tid]
else
{
out[nscan[tid]] = in[tid];
}
}
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- CPU Functions ----------------------------------------------------------
void Print (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
printf("%4u\n",v[i]);
printf("\n");
}
void GetInput (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
scanf("%u",&v[i]);
}
void Swap (unsigned int* &a, unsigned int* &b)
{
unsigned int *temp = a;
a = b;
b = temp;
}
void RadixSort (unsigned int *in, unsigned int *out, const unsigned int N)
{
// Define kernel dimension
dim3 gridSize(1,1);
dim3 blockSize(N,1);
const int numBits = 1;
const int numBins = 2;
// Shared memory sizes
size_t sizeBins = sizeof(unsigned int)*numBins;
size_t sizeN = sizeof(unsigned int)*N;
// Allocate GPU memory
unsigned int *binHistogram, *binScan, *pred, *npred, *scan, *nscan;
hipMalloc(&binHistogram,sizeof(unsigned int)*numBins);
hipMalloc(&binScan,sizeof(unsigned int)*numBins);
hipMalloc(&pred,sizeof(unsigned int)*N);
hipMalloc(&npred,sizeof(unsigned int)*N);
hipMalloc(&scan,sizeof(unsigned int)*N);
hipMalloc(&nscan,sizeof(unsigned int)*N);
for (int i = 0; i < 8 * sizeof(unsigned int); i += numBits)
{
unsigned int mask = numBits << i;
// Reset the bins
hipMemset(binHistogram,0,sizeof(unsigned int)*numBins);
hipMemset(binScan,0,sizeof(unsigned int)*numBins);
// Call kernel to compute histogram
Gpu_Histogram<<<gridSize,blockSize>>>(in,binHistogram,mask,i);
// Call kernel to compute the exclusive scan on the histogram
Gpu_ExScan<<<1,numBins,2*sizeBins>>>(binHistogram,binScan,numBins);
// Call kernel that calculate the predicate
Gpu_Predicate<<<gridSize,blockSize>>>(in,pred,npred,mask,i);
// Call kernel to compute the exclusive scan on the predicates
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(pred,scan,N);
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(npred,nscan,N);
// Call kernel to do the final mapping using the scan array
Gpu_Mapping<<<gridSize,blockSize>>>(in,out,binScan,scan,nscan,mask,i);
Swap(out,in);
}
hipMemcpy(out,in,sizeof(unsigned int)*N,hipMemcpyDeviceToDevice);
// Free memory
hipFree(binHistogram);
hipFree(binScan);
hipFree(pred);
hipFree(npred);
hipFree(scan);
hipFree(nscan);
}
void Usage (char pName[])
{
printf("============================================\n");
printf("Usage:> %s < 'input_filename'\n",pName);
printf("Example:> %s < input\n",pName);
printf("============================================\n");
}
// ---------------------------------------------------------------------------------------------------------------------------
// ------------------------------------------------ MAIN FUNCTION ------------------------------------------------------------
int main (int argc, char *argv[])
{
if (argc-1 != 0)
{
Usage(argv[0]);
exit(1);
}
// Read size of the input
unsigned int N;
scanf("%u",&N);
// Declare and allocate memory for the host
unsigned int *in, *out;
unsigned int *d_in, *d_out;
in = new unsigned int[N]();
out = new unsigned int[N]();
hipMalloc(&d_in,sizeof(unsigned int)*N);
hipMalloc(&d_out,sizeof(unsigned int)*N);
// Get or Generate the array to sort
GetInput(in,N);
Print(in,N);
// Copy the array to the GPU
hipMemcpy(d_in,in,sizeof(unsigned int)*N,hipMemcpyHostToDevice);
// Initialize output array
hipMemset(d_out,0,sizeof(unsigned int)*N);
// Sort the array using RadixSort
RadixSort(d_in,d_out,N);
// Print the result
hipMemcpy(out,d_out,sizeof(unsigned int)*N,hipMemcpyDeviceToHost);
Print(out,N);
delete [] in;
delete [] out;
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------------------------------
// Compute an histogram of how many 0's and 1's are set using the current mask
__global__ void Gpu_Histogram (unsigned int *in, unsigned int *bins, const unsigned int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bin = (in[tid] & mask) >> i;
atomicAdd(&bins[bin],1);
}
// Compute an exclusive scan on the input array and store the result on the output array
__global__ void Gpu_ExScan (unsigned int *in, unsigned int *out, const size_t n)
{
extern __shared__ unsigned int cache2[];
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int offset = 1;
// Load the input into shared memory
cache2[2*tid] = in[2*tid];
cache2[2*tid+1] = in[2*tid+1];
__syncthreads();
// Build sum in place up the tree
for (int d = n >> 1; d > 0; d >>= 1)
{
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
cache2[bi] += cache2[ai];
}
offset *= 2;
}
// Clear the last element
if (tid == 0)
{
cache2[n-1] = 0;
}
// Transverse down and build scan
for (int d = 1; d < n; d *= 2)
{
offset >>= 1;
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
// Avoiding read-write bugs
int aux = cache2[ai];
cache2[ai] = cache2[bi];
cache2[bi] += aux;
}
}
__syncthreads();
// Write results to output
out[2*tid] = cache2[2*tid];
out[2*tid+1] = cache2[2*tid+1];
offset = out[1];
//__syncthreads();
//if (tid == 0)
// printf("Binscan 0 = %u || Binscan 1 = %u\n",out[0],out[1]);
}
// Calculate the predicate of each element on the input
__global__ void Gpu_Predicate (unsigned int *in, unsigned int *out, unsigned int *nout, const int mask, const int i)
{
int tid = threadIdx.x;
// Predicate format = Check if the ith bit of the element is set
unsigned int bit = (in[tid] & mask) >> i;
out[tid] = bit;
nout[tid] = !bit;
}
// Map the correct position of each element on input based on the scan array of the predicate
__global__ void Gpu_Mapping (unsigned int *in, unsigned int *out, unsigned int *bscan, unsigned int *scan, unsigned int *nscan, const int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bit = (in[tid] & mask) >> i;
// If bit is 1, than pred[tid] is active
if (bit)
{
int offset = bscan[1];
out[scan[tid] + offset] = in[tid];
}
// Bit 0 is active in npred[tid]
else
{
out[nscan[tid]] = in[tid];
}
}
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- CPU Functions ----------------------------------------------------------
void Print (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
printf("%4u\n",v[i]);
printf("\n");
}
void GetInput (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
scanf("%u",&v[i]);
}
void Swap (unsigned int* &a, unsigned int* &b)
{
unsigned int *temp = a;
a = b;
b = temp;
}
void RadixSort (unsigned int *in, unsigned int *out, const unsigned int N)
{
// Define kernel dimension
dim3 gridSize(1,1);
dim3 blockSize(N,1);
const int numBits = 1;
const int numBins = 2;
// Shared memory sizes
size_t sizeBins = sizeof(unsigned int)*numBins;
size_t sizeN = sizeof(unsigned int)*N;
// Allocate GPU memory
unsigned int *binHistogram, *binScan, *pred, *npred, *scan, *nscan;
hipMalloc(&binHistogram,sizeof(unsigned int)*numBins);
hipMalloc(&binScan,sizeof(unsigned int)*numBins);
hipMalloc(&pred,sizeof(unsigned int)*N);
hipMalloc(&npred,sizeof(unsigned int)*N);
hipMalloc(&scan,sizeof(unsigned int)*N);
hipMalloc(&nscan,sizeof(unsigned int)*N);
for (int i = 0; i < 8 * sizeof(unsigned int); i += numBits)
{
unsigned int mask = numBits << i;
// Reset the bins
hipMemset(binHistogram,0,sizeof(unsigned int)*numBins);
hipMemset(binScan,0,sizeof(unsigned int)*numBins);
// Call kernel to compute histogram
Gpu_Histogram<<<gridSize,blockSize>>>(in,binHistogram,mask,i);
// Call kernel to compute the exclusive scan on the histogram
Gpu_ExScan<<<1,numBins,2*sizeBins>>>(binHistogram,binScan,numBins);
// Call kernel that calculate the predicate
Gpu_Predicate<<<gridSize,blockSize>>>(in,pred,npred,mask,i);
// Call kernel to compute the exclusive scan on the predicates
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(pred,scan,N);
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(npred,nscan,N);
// Call kernel to do the final mapping using the scan array
Gpu_Mapping<<<gridSize,blockSize>>>(in,out,binScan,scan,nscan,mask,i);
Swap(out,in);
}
hipMemcpy(out,in,sizeof(unsigned int)*N,hipMemcpyDeviceToDevice);
// Free memory
hipFree(binHistogram);
hipFree(binScan);
hipFree(pred);
hipFree(npred);
hipFree(scan);
hipFree(nscan);
}
void Usage (char pName[])
{
printf("============================================\n");
printf("Usage:> %s < 'input_filename'\n",pName);
printf("Example:> %s < input\n",pName);
printf("============================================\n");
}
// ---------------------------------------------------------------------------------------------------------------------------
// ------------------------------------------------ MAIN FUNCTION ------------------------------------------------------------
int main (int argc, char *argv[])
{
if (argc-1 != 0)
{
Usage(argv[0]);
exit(1);
}
// Read size of the input
unsigned int N;
scanf("%u",&N);
// Declare and allocate memory for the host
unsigned int *in, *out;
unsigned int *d_in, *d_out;
in = new unsigned int[N]();
out = new unsigned int[N]();
hipMalloc(&d_in,sizeof(unsigned int)*N);
hipMalloc(&d_out,sizeof(unsigned int)*N);
// Get or Generate the array to sort
GetInput(in,N);
Print(in,N);
// Copy the array to the GPU
hipMemcpy(d_in,in,sizeof(unsigned int)*N,hipMemcpyHostToDevice);
// Initialize output array
hipMemset(d_out,0,sizeof(unsigned int)*N);
// Sort the array using RadixSort
RadixSort(d_in,d_out,N);
// Print the result
hipMemcpy(out,d_out,sizeof(unsigned int)*N,hipMemcpyDeviceToHost);
Print(out,N);
delete [] in;
delete [] out;
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Gpu_HistogramPjS_ji
.globl _Z13Gpu_HistogramPjS_ji
.p2align 8
.type _Z13Gpu_HistogramPjS_ji,@function
_Z13Gpu_HistogramPjS_ji:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[4:5]
s_waitcnt vmcnt(0)
v_and_b32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, s1, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Gpu_HistogramPjS_ji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Gpu_HistogramPjS_ji, .Lfunc_end0-_Z13Gpu_HistogramPjS_ji
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10Gpu_ExScanPjS_m
.globl _Z10Gpu_ExScanPjS_m
.p2align 8
.type _Z10Gpu_ExScanPjS_m,@function
_Z10Gpu_ExScanPjS_m:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v0, s2, v1
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 1, v2
v_lshlrev_b32_e32 v3, 3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, 1, v0
v_add_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v1
s_clause 0x1
global_load_b32 v7, v3, s[4:5]
global_load_b32 v8, v6, s[4:5]
v_add_nc_u32_e32 v3, 0, v6
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v5, s3, s2, 1
s_waitcnt vmcnt(1)
ds_store_b32 v4, v7
s_waitcnt vmcnt(0)
ds_store_b32 v3, v8
v_cmp_gt_i32_e32 vcc_lo, 1, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_5
v_add_nc_u32_e32 v6, 2, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_gt_u32_e32 vcc_lo, 2, v5
v_lshrrev_b32_e32 v5, 1, v5
s_lshl_b32 s6, s6, 1
s_cbranch_vccnz .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e64 v2, v5
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v7, s6, v1
v_mul_lo_u32 v8, s6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 2, v7
v_lshlrev_b32_e32 v8, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v7, v7, 0, -4
v_add3_u32 v8, v8, 0, -4
ds_load_b32 v7, v7
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v9, v7
ds_store_b32 v8, v7
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_7
s_lshl_b32 s5, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, 0
s_add_i32 s5, s5, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s5
ds_store_b32 v6, v5
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_12
v_add_nc_u32_e32 v5, 2, v0
s_mov_b32 s4, 1
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_10
.p2align 6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s7, s[4:5], s[2:3]
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_12
.LBB1_10:
s_lshr_b32 s6, s6, 1
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v2
s_cbranch_execz .LBB1_9
v_mul_lo_u32 v6, s6, v5
v_mul_lo_u32 v8, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v8, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v6, v6, 0, -4
v_add3_u32 v8, v8, 0, -4
ds_load_b32 v7, v6
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(1)
ds_store_b32 v8, v7
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v7, v9
ds_store_b32 v6, v7
s_branch .LBB1_9
.LBB1_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
ds_load_b32 v3, v3
v_lshlrev_b32_e32 v0, 2, v0
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(1)
global_store_b32 v0, v2, s[0:1]
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10Gpu_ExScanPjS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10Gpu_ExScanPjS_m, .Lfunc_end1-_Z10Gpu_ExScanPjS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13Gpu_PredicatePjS_S_ii
.globl _Z13Gpu_PredicatePjS_S_ii
.p2align 8
.type _Z13Gpu_PredicatePjS_S_ii,@function
_Z13Gpu_PredicatePjS_S_ii:
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, s7, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_clause 0x1
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v2, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Gpu_PredicatePjS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13Gpu_PredicatePjS_S_ii, .Lfunc_end2-_Z13Gpu_PredicatePjS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11Gpu_MappingPjS_S_S_S_ii
.globl _Z11Gpu_MappingPjS_S_S_S_ii
.p2align 8
.type _Z11Gpu_MappingPjS_S_S_S_ii,@function
_Z11Gpu_MappingPjS_S_S_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x28
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[2:3]
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, s5, v1
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[6:7]
s_load_b32 s3, s[4:5], 0x4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, s3, v0
.LBB3_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB3_4
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Gpu_MappingPjS_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11Gpu_MappingPjS_S_S_S_ii, .Lfunc_end3-_Z11Gpu_MappingPjS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Gpu_HistogramPjS_ji
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z13Gpu_HistogramPjS_ji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10Gpu_ExScanPjS_m
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10Gpu_ExScanPjS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Gpu_PredicatePjS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z13Gpu_PredicatePjS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Gpu_MappingPjS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Gpu_MappingPjS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------------------------------
// Compute an histogram of how many 0's and 1's are set using the current mask
__global__ void Gpu_Histogram (unsigned int *in, unsigned int *bins, const unsigned int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bin = (in[tid] & mask) >> i;
atomicAdd(&bins[bin],1);
}
// Compute an exclusive scan on the input array and store the result on the output array
__global__ void Gpu_ExScan (unsigned int *in, unsigned int *out, const size_t n)
{
extern __shared__ unsigned int cache2[];
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int offset = 1;
// Load the input into shared memory
cache2[2*tid] = in[2*tid];
cache2[2*tid+1] = in[2*tid+1];
__syncthreads();
// Build sum in place up the tree
for (int d = n >> 1; d > 0; d >>= 1)
{
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
cache2[bi] += cache2[ai];
}
offset *= 2;
}
// Clear the last element
if (tid == 0)
{
cache2[n-1] = 0;
}
// Transverse down and build scan
for (int d = 1; d < n; d *= 2)
{
offset >>= 1;
__syncthreads();
if (tid < d)
{
int ai = offset*(2*tid+1)-1;
int bi = offset*(2*tid+2)-1;
// Avoiding read-write bugs
int aux = cache2[ai];
cache2[ai] = cache2[bi];
cache2[bi] += aux;
}
}
__syncthreads();
// Write results to output
out[2*tid] = cache2[2*tid];
out[2*tid+1] = cache2[2*tid+1];
offset = out[1];
//__syncthreads();
//if (tid == 0)
// printf("Binscan 0 = %u || Binscan 1 = %u\n",out[0],out[1]);
}
// Calculate the predicate of each element on the input
__global__ void Gpu_Predicate (unsigned int *in, unsigned int *out, unsigned int *nout, const int mask, const int i)
{
int tid = threadIdx.x;
// Predicate format = Check if the ith bit of the element is set
unsigned int bit = (in[tid] & mask) >> i;
out[tid] = bit;
nout[tid] = !bit;
}
// Map the correct position of each element on input based on the scan array of the predicate
__global__ void Gpu_Mapping (unsigned int *in, unsigned int *out, unsigned int *bscan, unsigned int *scan, unsigned int *nscan, const int mask, const int i)
{
int tid = threadIdx.x;
unsigned int bit = (in[tid] & mask) >> i;
// If bit is 1, than pred[tid] is active
if (bit)
{
int offset = bscan[1];
out[scan[tid] + offset] = in[tid];
}
// Bit 0 is active in npred[tid]
else
{
out[nscan[tid]] = in[tid];
}
}
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- CPU Functions ----------------------------------------------------------
void Print (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
printf("%4u\n",v[i]);
printf("\n");
}
void GetInput (unsigned int *v, unsigned int N)
{
for (int i = 0; i < N; i++)
scanf("%u",&v[i]);
}
void Swap (unsigned int* &a, unsigned int* &b)
{
unsigned int *temp = a;
a = b;
b = temp;
}
void RadixSort (unsigned int *in, unsigned int *out, const unsigned int N)
{
// Define kernel dimension
dim3 gridSize(1,1);
dim3 blockSize(N,1);
const int numBits = 1;
const int numBins = 2;
// Shared memory sizes
size_t sizeBins = sizeof(unsigned int)*numBins;
size_t sizeN = sizeof(unsigned int)*N;
// Allocate GPU memory
unsigned int *binHistogram, *binScan, *pred, *npred, *scan, *nscan;
hipMalloc(&binHistogram,sizeof(unsigned int)*numBins);
hipMalloc(&binScan,sizeof(unsigned int)*numBins);
hipMalloc(&pred,sizeof(unsigned int)*N);
hipMalloc(&npred,sizeof(unsigned int)*N);
hipMalloc(&scan,sizeof(unsigned int)*N);
hipMalloc(&nscan,sizeof(unsigned int)*N);
for (int i = 0; i < 8 * sizeof(unsigned int); i += numBits)
{
unsigned int mask = numBits << i;
// Reset the bins
hipMemset(binHistogram,0,sizeof(unsigned int)*numBins);
hipMemset(binScan,0,sizeof(unsigned int)*numBins);
// Call kernel to compute histogram
Gpu_Histogram<<<gridSize,blockSize>>>(in,binHistogram,mask,i);
// Call kernel to compute the exclusive scan on the histogram
Gpu_ExScan<<<1,numBins,2*sizeBins>>>(binHistogram,binScan,numBins);
// Call kernel that calculate the predicate
Gpu_Predicate<<<gridSize,blockSize>>>(in,pred,npred,mask,i);
// Call kernel to compute the exclusive scan on the predicates
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(pred,scan,N);
Gpu_ExScan<<<gridSize,blockSize,sizeN>>>(npred,nscan,N);
// Call kernel to do the final mapping using the scan array
Gpu_Mapping<<<gridSize,blockSize>>>(in,out,binScan,scan,nscan,mask,i);
Swap(out,in);
}
hipMemcpy(out,in,sizeof(unsigned int)*N,hipMemcpyDeviceToDevice);
// Free memory
hipFree(binHistogram);
hipFree(binScan);
hipFree(pred);
hipFree(npred);
hipFree(scan);
hipFree(nscan);
}
void Usage (char pName[])
{
printf("============================================\n");
printf("Usage:> %s < 'input_filename'\n",pName);
printf("Example:> %s < input\n",pName);
printf("============================================\n");
}
// ---------------------------------------------------------------------------------------------------------------------------
// ------------------------------------------------ MAIN FUNCTION ------------------------------------------------------------
int main (int argc, char *argv[])
{
if (argc-1 != 0)
{
Usage(argv[0]);
exit(1);
}
// Read size of the input
unsigned int N;
scanf("%u",&N);
// Declare and allocate memory for the host
unsigned int *in, *out;
unsigned int *d_in, *d_out;
in = new unsigned int[N]();
out = new unsigned int[N]();
hipMalloc(&d_in,sizeof(unsigned int)*N);
hipMalloc(&d_out,sizeof(unsigned int)*N);
// Get or Generate the array to sort
GetInput(in,N);
Print(in,N);
// Copy the array to the GPU
hipMemcpy(d_in,in,sizeof(unsigned int)*N,hipMemcpyHostToDevice);
// Initialize output array
hipMemset(d_out,0,sizeof(unsigned int)*N);
// Sort the array using RadixSort
RadixSort(d_in,d_out,N);
// Print the result
hipMemcpy(out,d_out,sizeof(unsigned int)*N,hipMemcpyDeviceToHost);
Print(out,N);
delete [] in;
delete [] out;
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "radix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Gpu_HistogramPjS_ji # -- Begin function _Z28__device_stub__Gpu_HistogramPjS_ji
.p2align 4, 0x90
.type _Z28__device_stub__Gpu_HistogramPjS_ji,@function
_Z28__device_stub__Gpu_HistogramPjS_ji: # @_Z28__device_stub__Gpu_HistogramPjS_ji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Gpu_HistogramPjS_ji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__Gpu_HistogramPjS_ji, .Lfunc_end0-_Z28__device_stub__Gpu_HistogramPjS_ji
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Gpu_ExScanPjS_m # -- Begin function _Z25__device_stub__Gpu_ExScanPjS_m
.p2align 4, 0x90
.type _Z25__device_stub__Gpu_ExScanPjS_m,@function
_Z25__device_stub__Gpu_ExScanPjS_m: # @_Z25__device_stub__Gpu_ExScanPjS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10Gpu_ExScanPjS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__Gpu_ExScanPjS_m, .Lfunc_end1-_Z25__device_stub__Gpu_ExScanPjS_m
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Gpu_PredicatePjS_S_ii # -- Begin function _Z28__device_stub__Gpu_PredicatePjS_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__Gpu_PredicatePjS_S_ii,@function
_Z28__device_stub__Gpu_PredicatePjS_S_ii: # @_Z28__device_stub__Gpu_PredicatePjS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Gpu_PredicatePjS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__Gpu_PredicatePjS_S_ii, .Lfunc_end2-_Z28__device_stub__Gpu_PredicatePjS_S_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii # -- Begin function _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii,@function
_Z26__device_stub__Gpu_MappingPjS_S_S_S_ii: # @_Z26__device_stub__Gpu_MappingPjS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Gpu_MappingPjS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii, .Lfunc_end3-_Z26__device_stub__Gpu_MappingPjS_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z5PrintPjj # -- Begin function _Z5PrintPjj
.p2align 4, 0x90
.type _Z5PrintPjj,@function
_Z5PrintPjj: # @_Z5PrintPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB4_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z5PrintPjj, .Lfunc_end4-_Z5PrintPjj
.cfi_endproc
# -- End function
.globl _Z8GetInputPjj # -- Begin function _Z8GetInputPjj
.p2align 4, 0x90
.type _Z8GetInputPjj,@function
_Z8GetInputPjj: # @_Z8GetInputPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB5_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl %esi, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbx
decq %r14
jne .LBB5_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB5_4: # %._crit_edge
retq
.Lfunc_end5:
.size _Z8GetInputPjj, .Lfunc_end5-_Z8GetInputPjj
.cfi_endproc
# -- End function
.globl _Z4SwapRPjS0_ # -- Begin function _Z4SwapRPjS0_
.p2align 4, 0x90
.type _Z4SwapRPjS0_,@function
_Z4SwapRPjS0_: # @_Z4SwapRPjS0_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq %rax, (%rsi)
retq
.Lfunc_end6:
.size _Z4SwapRPjS0_, .Lfunc_end6-_Z4SwapRPjS0_
.cfi_endproc
# -- End function
.globl _Z9RadixSortPjS_j # -- Begin function _Z9RadixSortPjS_j
.p2align 4, 0x90
.type _Z9RadixSortPjS_j,@function
_Z9RadixSortPjS_j: # @_Z9RadixSortPjS_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbp
movabsq $4294967297, %rbx # imm = 0x100000001
movl %edx, %eax
leaq -1(%rax,%rbx), %r12
movq %rax, 200(%rsp) # 8-byte Spill
leaq (,%rax,4), %r14
leaq 88(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 176(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 168(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 160(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 152(%rsp), %rdi
movq %r14, 208(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
xorl %r13d, %r13d
leaq 1(%rbx), %rax
movq %rax, 232(%rsp) # 8-byte Spill
movq %r12, 224(%rsp) # 8-byte Spill
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_13: # in Loop: Header=BB7_1 Depth=1
incl %r13d
movq %r14, %rbp
cmpl $32, %r13d
movq %r15, %rbx
movq 216(%rsp), %r15 # 8-byte Reload
movq 224(%rsp), %r12 # 8-byte Reload
je .LBB7_14
.LBB7_1: # =>This Inner Loop Header: Depth=1
movq %r15, %r14
movq %rbp, %r15
movl $1, %ebp
movl %r13d, %ecx
shll %cl, %ebp
movq 88(%rsp), %rdi
movl $8, %edx
xorl %esi, %esi
callq hipMemset
movq 80(%rsp), %rdi
movl $8, %edx
xorl %esi, %esi
callq hipMemset
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_3
# %bb.2: # in Loop: Header=BB7_1 Depth=1
movq 88(%rsp), %rax
movq %r15, 64(%rsp)
movq %rax, 56(%rsp)
movl %ebp, 32(%rsp)
movl %r13d, 72(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z13Gpu_HistogramPjS_ji, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_3: # in Loop: Header=BB7_1 Depth=1
movl $16, %r8d
movq %rbx, %rdi
movl $1, %esi
movq 232(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.4: # in Loop: Header=BB7_1 Depth=1
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq $2, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z10Gpu_ExScanPjS_m, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_5: # in Loop: Header=BB7_1 Depth=1
movq %r14, 240(%rsp) # 8-byte Spill
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_7
# %bb.6: # in Loop: Header=BB7_1 Depth=1
movq 176(%rsp), %rax
movq 168(%rsp), %rcx
movq %r15, 64(%rsp)
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movl %ebp, 72(%rsp)
movl %r13d, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 184(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z13Gpu_PredicatePjS_S_ii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_7: # in Loop: Header=BB7_1 Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq 208(%rsp), %r14 # 8-byte Reload
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_9
# %bb.8: # in Loop: Header=BB7_1 Depth=1
movq 176(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq 200(%rsp), %rax # 8-byte Reload
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z10Gpu_ExScanPjS_m, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_9: # in Loop: Header=BB7_1 Depth=1
movq %r15, 216(%rsp) # 8-byte Spill
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_11
# %bb.10: # in Loop: Header=BB7_1 Depth=1
movq 168(%rsp), %rax
movq 152(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq 200(%rsp), %rax # 8-byte Reload
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z10Gpu_ExScanPjS_m, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_11: # in Loop: Header=BB7_1 Depth=1
movq %rbx, %r15
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 240(%rsp), %r14 # 8-byte Reload
jne .LBB7_13
# %bb.12: # in Loop: Header=BB7_1 Depth=1
movq 80(%rsp), %rax
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 216(%rsp), %rsi # 8-byte Reload
movq %rsi, 64(%rsp)
movq %r14, 56(%rsp)
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ebp, 196(%rsp)
movl %r13d, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 196(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 72(%rsp), %rdx
leaq 184(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z11Gpu_MappingPjS_S_S_S_ii, %edi
leaq 96(%rsp), %r9
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_13
.LBB7_14:
movq %r15, %rdi
movq %r14, %rsi
movq 208(%rsp), %rdx # 8-byte Reload
movl $3, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z9RadixSortPjS_j, .Lfunc_end7-_Z9RadixSortPjS_j
.cfi_endproc
# -- End function
.globl _Z5UsagePc # -- Begin function _Z5UsagePc
.p2align 4, 0x90
.type _Z5UsagePc,@function
_Z5UsagePc: # @_Z5UsagePc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end8:
.size _Z5UsagePc, .Lfunc_end8-_Z5UsagePc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jne .LBB9_11
# %bb.1:
leaq 4(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %r15d
shlq $2, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %rax, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl 4(%rsp), %esi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %r12d
testq %r12, %r12
je .LBB9_4
# %bb.2: # %.lr.ph.preheader.i
movq %rbx, %r15
.p2align 4, 0x90
.LBB9_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB9_3
.LBB9_4: # %_Z8GetInputPjj.exit
movl 4(%rsp), %r15d
testq %r15, %r15
je .LBB9_7
# %bb.5: # %.lr.ph.preheader.i9
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_6: # %.lr.ph.i11
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB9_6
.LBB9_7: # %_Z5PrintPjj.exit
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl 4(%rsp), %edx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl 4(%rsp), %edx
callq _Z9RadixSortPjS_j
movq 8(%rsp), %rsi
movl 4(%rsp), %edx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %r15d
testq %r15, %r15
je .LBB9_10
# %bb.8: # %.lr.ph.preheader.i16
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_9: # %.lr.ph.i18
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB9_9
.LBB9_10: # %_Z5PrintPjj.exit23
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB9_11:
.cfi_def_cfa_offset 64
movq (%rsi), %rdi
callq _Z5UsagePc
movl $1, %edi
callq exit
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Gpu_HistogramPjS_ji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Gpu_ExScanPjS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Gpu_PredicatePjS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Gpu_MappingPjS_S_S_S_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Gpu_HistogramPjS_ji,@object # @_Z13Gpu_HistogramPjS_ji
.section .rodata,"a",@progbits
.globl _Z13Gpu_HistogramPjS_ji
.p2align 3, 0x0
_Z13Gpu_HistogramPjS_ji:
.quad _Z28__device_stub__Gpu_HistogramPjS_ji
.size _Z13Gpu_HistogramPjS_ji, 8
.type _Z10Gpu_ExScanPjS_m,@object # @_Z10Gpu_ExScanPjS_m
.globl _Z10Gpu_ExScanPjS_m
.p2align 3, 0x0
_Z10Gpu_ExScanPjS_m:
.quad _Z25__device_stub__Gpu_ExScanPjS_m
.size _Z10Gpu_ExScanPjS_m, 8
.type _Z13Gpu_PredicatePjS_S_ii,@object # @_Z13Gpu_PredicatePjS_S_ii
.globl _Z13Gpu_PredicatePjS_S_ii
.p2align 3, 0x0
_Z13Gpu_PredicatePjS_S_ii:
.quad _Z28__device_stub__Gpu_PredicatePjS_S_ii
.size _Z13Gpu_PredicatePjS_S_ii, 8
.type _Z11Gpu_MappingPjS_S_S_S_ii,@object # @_Z11Gpu_MappingPjS_S_S_S_ii
.globl _Z11Gpu_MappingPjS_S_S_S_ii
.p2align 3, 0x0
_Z11Gpu_MappingPjS_S_S_S_ii:
.quad _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii
.size _Z11Gpu_MappingPjS_S_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4u\n"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%u"
.size .L.str.2, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage:> %s < 'input_filename'\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Example:> %s < input\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13Gpu_HistogramPjS_ji"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10Gpu_ExScanPjS_m"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13Gpu_PredicatePjS_S_ii"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11Gpu_MappingPjS_S_S_S_ii"
.size .L__unnamed_4, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "============================================"
.size .Lstr.1, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Gpu_HistogramPjS_ji
.addrsig_sym _Z25__device_stub__Gpu_ExScanPjS_m
.addrsig_sym _Z28__device_stub__Gpu_PredicatePjS_S_ii
.addrsig_sym _Z26__device_stub__Gpu_MappingPjS_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Gpu_HistogramPjS_ji
.addrsig_sym _Z10Gpu_ExScanPjS_m
.addrsig_sym _Z13Gpu_PredicatePjS_S_ii
.addrsig_sym _Z11Gpu_MappingPjS_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11Gpu_MappingPjS_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R10, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e020a */
/*0050*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0060*/ LOP3.LUT R0, R11, c[0x0][0x188], RZ, 0xc0, !PT ; /* 0x000062000b007a12 */
/* 0x004fc800078ec0ff */
/*0070*/ SHF.R.U32.HI R0, RZ, c[0x0][0x18c], R0 ; /* 0x00006300ff007a19 */
/* 0x000fc80000011600 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fd60000011409 */
/*00a0*/ @P0 LEA R6, P1, R9.reuse, c[0x0][0x178], 0x2 ; /* 0x00005e0009060a11 */
/* 0x040fe200078210ff */
/*00b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff050624 */
/* 0x000fe400078e00ff */
/*00c0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff040624 */
/* 0x000fe200078e00ff */
/*00d0*/ @P0 LEA.HI.X R7, R9, c[0x0][0x17c], R0, 0x2, P1 ; /* 0x00005f0009070a11 */
/* 0x000fc800008f1400 */
/*00e0*/ @P0 LDG.E R5, [R4.64+0x4] ; /* 0x0000040404050981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @P0 LDG.E R6, [R6.64] ; /* 0x0000000406060981 */
/* 0x000ea2000c1e1900 */
/*0100*/ @!P0 LEA R8, P1, R9, c[0x0][0x180], 0x2 ; /* 0x0000600009088a11 */
/* 0x000fc800078210ff */
/*0110*/ @!P0 LEA.HI.X R9, R9, c[0x0][0x184], R0, 0x2, P1 ; /* 0x0000610009098a11 */
/* 0x000fe200008f1400 */
/*0120*/ @P0 IMAD.IADD R2, R6, 0x1, R5 ; /* 0x0000000106020824 */
/* 0x004fcc00078e0205 */
/*0130*/ @!P0 LDG.E R2, [R8.64] ; /* 0x0000000408028981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R2, R2, R10, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e000a */
/*0150*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13Gpu_PredicatePjS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0080*/ LOP3.LUT R0, R2, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e0002007a12 */
/* 0x004fc800078ec0ff */
/*0090*/ SHF.R.U32.HI R9, RZ, c[0x0][0x17c], R0 ; /* 0x00005f00ff097a19 */
/* 0x000fc80000011600 */
/*00a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe6000c101904 */
/*00c0*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x000fca0000000000 */
/*00d0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10Gpu_ExScanPjS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*00d0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fca00078e00ff */
/*00f0*/ SHF.R.U64 R10, R10, R3, c[0x0][0x174] ; /* 0x00005d000a0a7619 */
/* 0x000fe40000001203 */
/*0100*/ IADD3 R3, R0, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f26270 */
/*0120*/ @!P0 LEA R9, R12, 0xfffffffc, 0x2 ; /* 0xfffffffc0c098811 */
/* 0x000fe200078e10ff */
/*0130*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0041e80000008a00 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P1 BRA 0x250 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0170*/ MOV R8, 0x1 ; /* 0x0000000100087802 */
/* 0x000fc60000000f00 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc40003f26270 */
/*01a0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fd60000011605 */
/*01b0*/ @!P1 IMAD R4, R3, R8, RZ ; /* 0x0000000803049224 */
/* 0x000fc800078e02ff */
/*01c0*/ @!P1 IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404079824 */
/* 0x001fc800078e00ff */
/*01d0*/ @!P1 IMAD R11, R8.reuse, 0x4, R7 ; /* 0x00000004080b9824 */
/* 0x040fe200078e0207 */
/*01e0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fe200000006ff */
/*01f0*/ @!P1 LDS R7, [R4.X4+-0x4] ; /* 0xfffffc0004079984 */
/* 0x000fe80000004800 */
/*0200*/ @!P1 LDS R6, [R11+-0x4] ; /* 0xfffffc000b069984 */
/* 0x000e240000000800 */
/*0210*/ @!P1 IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106069824 */
/* 0x001fca00078e0207 */
/*0220*/ @!P1 STS [R11+-0x4], R6 ; /* 0xfffffc060b009388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0240*/ @P1 BRA 0x180 ; /* 0xffffff3000001947 */
/* 0x001fea000383ffff */
/*0250*/ @!P0 STS [R9], RZ ; /* 0x000000ff09008388 */
/* 0x0003e20000000800 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f06070 */
/*0280*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011400 */
/*0290*/ ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f06100 */
/*02a0*/ @!P0 BRA 0x3f0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x002fc800078e00ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f26270 */
/*02e0*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*02f0*/ SHF.R.S32.HI R8, RZ, 0x1, R8 ; /* 0x00000001ff087819 */
/* 0x000fc60000011408 */
/*0300*/ BSSY B0, 0x3e0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06070 */
/*0320*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fc60003f06100 */
/*0330*/ @P1 BRA 0x3d0 ; /* 0x0000009000001947 */
/* 0x001fea0003800000 */
/*0340*/ IMAD R4, R3, R8, RZ ; /* 0x0000000803047224 */
/* 0x000fca00078e02ff */
/*0350*/ SHF.L.U32 R7, R4, 0x2, RZ ; /* 0x0000000204077819 */
/* 0x001fe200000006ff */
/*0360*/ LDS R6, [R4.X4+-0x4] ; /* 0xfffffc0004067984 */
/* 0x000fe80000004800 */
/*0370*/ IMAD R11, R8, 0x4, R7 ; /* 0x00000004080b7824 */
/* 0x000fca00078e0207 */
/*0380*/ LDS R7, [R11+-0x4] ; /* 0xfffffc000b077984 */
/* 0x000e280000000800 */
/*0390*/ STS [R4.X4+-0x4], R7 ; /* 0xfffffc0704007388 */
/* 0x001fe80000004800 */
/*03a0*/ LDS R9, [R11+-0x4] ; /* 0xfffffc000b097984 */
/* 0x000e240000000800 */
/*03b0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x001fca00078e0209 */
/*03c0*/ STS [R11+-0x4], R6 ; /* 0xfffffc060b007388 */
/* 0x0001e40000000800 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P0 BRA 0x2c0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fe20000010000 */
/*0400*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0410*/ LEA.HI.X R5, R0, c[0x0][0x16c], R13, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f140d */
/*0420*/ LDS.64 R2, [R2.X8] ; /* 0x0000000002027984 */
/* 0x001e280000008a00 */
/*0430*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe8000c101904 */
/*0440*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x000fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13Gpu_HistogramPjS_ji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0070*/ LOP3.LUT R0, R2, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0002007a12 */
/* 0x004fc800078ec0ff */
/*0080*/ SHF.R.U32.HI R0, RZ, c[0x0][0x174], R0 ; /* 0x00005d00ff007a19 */
/* 0x000fca0000011600 */
/*0090*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Gpu_HistogramPjS_ji
.globl _Z13Gpu_HistogramPjS_ji
.p2align 8
.type _Z13Gpu_HistogramPjS_ji,@function
_Z13Gpu_HistogramPjS_ji:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[4:5]
s_waitcnt vmcnt(0)
v_and_b32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, s1, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Gpu_HistogramPjS_ji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Gpu_HistogramPjS_ji, .Lfunc_end0-_Z13Gpu_HistogramPjS_ji
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10Gpu_ExScanPjS_m
.globl _Z10Gpu_ExScanPjS_m
.p2align 8
.type _Z10Gpu_ExScanPjS_m,@function
_Z10Gpu_ExScanPjS_m:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v0, s2, v1
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 1, v2
v_lshlrev_b32_e32 v3, 3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, 1, v0
v_add_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v1
s_clause 0x1
global_load_b32 v7, v3, s[4:5]
global_load_b32 v8, v6, s[4:5]
v_add_nc_u32_e32 v3, 0, v6
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v5, s3, s2, 1
s_waitcnt vmcnt(1)
ds_store_b32 v4, v7
s_waitcnt vmcnt(0)
ds_store_b32 v3, v8
v_cmp_gt_i32_e32 vcc_lo, 1, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_5
v_add_nc_u32_e32 v6, 2, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_gt_u32_e32 vcc_lo, 2, v5
v_lshrrev_b32_e32 v5, 1, v5
s_lshl_b32 s6, s6, 1
s_cbranch_vccnz .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e64 v2, v5
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v7, s6, v1
v_mul_lo_u32 v8, s6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 2, v7
v_lshlrev_b32_e32 v8, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v7, v7, 0, -4
v_add3_u32 v8, v8, 0, -4
ds_load_b32 v7, v7
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v9, v7
ds_store_b32 v8, v7
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_7
s_lshl_b32 s5, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, 0
s_add_i32 s5, s5, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s5
ds_store_b32 v6, v5
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_12
v_add_nc_u32_e32 v5, 2, v0
s_mov_b32 s4, 1
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_10
.p2align 6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s7, s[4:5], s[2:3]
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_12
.LBB1_10:
s_lshr_b32 s6, s6, 1
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v2
s_cbranch_execz .LBB1_9
v_mul_lo_u32 v6, s6, v5
v_mul_lo_u32 v8, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v8, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v6, v6, 0, -4
v_add3_u32 v8, v8, 0, -4
ds_load_b32 v7, v6
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(1)
ds_store_b32 v8, v7
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v7, v9
ds_store_b32 v6, v7
s_branch .LBB1_9
.LBB1_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
ds_load_b32 v3, v3
v_lshlrev_b32_e32 v0, 2, v0
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(1)
global_store_b32 v0, v2, s[0:1]
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10Gpu_ExScanPjS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10Gpu_ExScanPjS_m, .Lfunc_end1-_Z10Gpu_ExScanPjS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13Gpu_PredicatePjS_S_ii
.globl _Z13Gpu_PredicatePjS_S_ii
.p2align 8
.type _Z13Gpu_PredicatePjS_S_ii,@function
_Z13Gpu_PredicatePjS_S_ii:
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, s7, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_clause 0x1
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v2, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Gpu_PredicatePjS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13Gpu_PredicatePjS_S_ii, .Lfunc_end2-_Z13Gpu_PredicatePjS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11Gpu_MappingPjS_S_S_S_ii
.globl _Z11Gpu_MappingPjS_S_S_S_ii
.p2align 8
.type _Z11Gpu_MappingPjS_S_S_S_ii,@function
_Z11Gpu_MappingPjS_S_S_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x28
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[2:3]
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, s5, v1
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[6:7]
s_load_b32 s3, s[4:5], 0x4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, s3, v0
.LBB3_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB3_4
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Gpu_MappingPjS_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11Gpu_MappingPjS_S_S_S_ii, .Lfunc_end3-_Z11Gpu_MappingPjS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Gpu_HistogramPjS_ji
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z13Gpu_HistogramPjS_ji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10Gpu_ExScanPjS_m
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10Gpu_ExScanPjS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Gpu_PredicatePjS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z13Gpu_PredicatePjS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Gpu_MappingPjS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Gpu_MappingPjS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}
}
__global__ void printer()
{
printf("%d\n", threadIdx.x);
}
int main(int argc, char **argv)
{
printer<<<1, 1024>>>();
// Waits for all CUDA threads to complete.
cudaDeviceSynchronize();
check_cuda_errors();
return 0;
} | code for sm_80
Function : _Z7printerv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}
}
__global__ void printer()
{
printf("%d\n", threadIdx.x);
}
int main(int argc, char **argv)
{
printer<<<1, 1024>>>();
// Waits for all CUDA threads to complete.
cudaDeviceSynchronize();
check_cuda_errors();
return 0;
} | .file "tmpxft_000c1f69_00000000-6_printing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Last CUDA error %s\n"
.text
.globl _Z17check_cuda_errorsv
.type _Z17check_cuda_errorsv, @function
_Z17check_cuda_errorsv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z17check_cuda_errorsv, .-_Z17check_cuda_errorsv
.globl _Z25__device_stub__Z7printervv
.type _Z25__device_stub__Z7printervv, @function
_Z25__device_stub__Z7printervv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7printerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z7printervv, .-_Z25__device_stub__Z7printervv
.globl _Z7printerv
.type _Z7printerv, @function
_Z7printerv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7printervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7printerv, .-_Z7printerv
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
call _Z17check_cuda_errorsv
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z25__device_stub__Z7printervv
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z7printerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7printerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}
}
__global__ void printer()
{
printf("%d\n", threadIdx.x);
}
int main(int argc, char **argv)
{
printer<<<1, 1024>>>();
// Waits for all CUDA threads to complete.
cudaDeviceSynchronize();
check_cuda_errors();
return 0;
} | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void check_cuda_errors()
{
hipError_t rc;
rc = hipGetLastError();
if (rc != hipSuccess)
{
printf("Last CUDA error %s\n", hipGetErrorString(rc));
}
}
__global__ void printer()
{
printf("%d\n", threadIdx.x);
}
int main(int argc, char **argv)
{
printer<<<1, 1024>>>();
// Waits for all CUDA threads to complete.
hipDeviceSynchronize();
check_cuda_errors();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void check_cuda_errors()
{
hipError_t rc;
rc = hipGetLastError();
if (rc != hipSuccess)
{
printf("Last CUDA error %s\n", hipGetErrorString(rc));
}
}
__global__ void printer()
{
printf("%d\n", threadIdx.x);
}
int main(int argc, char **argv)
{
printer<<<1, 1024>>>();
// Waits for all CUDA threads to complete.
hipDeviceSynchronize();
check_cuda_errors();
return 0;
} | .text
.file "printing.hip"
.globl _Z17check_cuda_errorsv # -- Begin function _Z17check_cuda_errorsv
.p2align 4, 0x90
.type _Z17check_cuda_errorsv,@function
_Z17check_cuda_errorsv: # @_Z17check_cuda_errorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB0_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17check_cuda_errorsv, .Lfunc_end0-_Z17check_cuda_errorsv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__printerv # -- Begin function _Z22__device_stub__printerv
.p2align 4, 0x90
.type _Z22__device_stub__printerv,@function
_Z22__device_stub__printerv: # @_Z22__device_stub__printerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7printerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__printerv, .Lfunc_end1-_Z22__device_stub__printerv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7printerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_4: # %_Z17check_cuda_errorsv.exit
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7printerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Last CUDA error %s\n"
.size .L.str, 20
.type _Z7printerv,@object # @_Z7printerv
.section .rodata,"a",@progbits
.globl _Z7printerv
.p2align 3, 0x0
_Z7printerv:
.quad _Z22__device_stub__printerv
.size _Z7printerv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7printerv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__printerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7printerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1f69_00000000-6_printing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Last CUDA error %s\n"
.text
.globl _Z17check_cuda_errorsv
.type _Z17check_cuda_errorsv, @function
_Z17check_cuda_errorsv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z17check_cuda_errorsv, .-_Z17check_cuda_errorsv
.globl _Z25__device_stub__Z7printervv
.type _Z25__device_stub__Z7printervv, @function
_Z25__device_stub__Z7printervv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7printerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z7printervv, .-_Z25__device_stub__Z7printervv
.globl _Z7printerv
.type _Z7printerv, @function
_Z7printerv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7printervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7printerv, .-_Z7printerv
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
call _Z17check_cuda_errorsv
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z25__device_stub__Z7printervv
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z7printerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7printerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "printing.hip"
.globl _Z17check_cuda_errorsv # -- Begin function _Z17check_cuda_errorsv
.p2align 4, 0x90
.type _Z17check_cuda_errorsv,@function
_Z17check_cuda_errorsv: # @_Z17check_cuda_errorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB0_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17check_cuda_errorsv, .Lfunc_end0-_Z17check_cuda_errorsv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__printerv # -- Begin function _Z22__device_stub__printerv
.p2align 4, 0x90
.type _Z22__device_stub__printerv,@function
_Z22__device_stub__printerv: # @_Z22__device_stub__printerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7printerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__printerv, .Lfunc_end1-_Z22__device_stub__printerv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7printerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_4: # %_Z17check_cuda_errorsv.exit
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7printerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Last CUDA error %s\n"
.size .L.str, 20
.type _Z7printerv,@object # @_Z7printerv
.section .rodata,"a",@progbits
.globl _Z7printerv
.p2align 3, 0x0
_Z7printerv:
.quad _Z22__device_stub__printerv
.size _Z7printerv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7printerv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__printerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7printerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
cudaMalloc((void**)&Md, size);
cudaMalloc((void**)&Nd, size);
cudaMalloc((void**)&Pd, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
cudaMalloc((void**)&Md, size);
cudaMalloc((void**)&Nd, size);
cudaMalloc((void**)&Pd, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} | .file "tmpxft_0007658d_00000000-6_matmul2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.2f "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12336
orq $0, (%rsp)
subq $64, %rsp
.cfi_def_cfa_offset 12400
movq %fs:40, %rax
movq %rax, 12344(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdx
leaq 4144(%rsp), %rcx
movq %rcx, %rsi
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movl $0, %eax
.L13:
movss %xmm1, (%rdx,%rax)
movss %xmm0, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L13
subq $-128, %rdx
subq $-128, %rcx
cmpq %rsi, %rdx
jne .L12
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4144(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 8240(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 8368(%rsp), %rbp
leaq 12464(%rsp), %r14
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %r13
.L16:
leaq -128(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r14, %rbp
jne .L16
movq 12344(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $12352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $32, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
cudaMalloc((void**)&Md, size);
cudaMalloc((void**)&Nd, size);
cudaMalloc((void**)&Pd, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
hipMalloc((void**)&Md, size);
hipMalloc((void**)&Nd, size);
hipMalloc((void**)&Pd, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
hipMalloc((void**)&Md, size);
hipMalloc((void**)&Nd, size);
hipMalloc((void**)&Pd, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k = 0;
for(k = 0; k < ncols; k++){
float Melement = Md[row * ncols + k];
float Nelement = Nd[k * ncols + col];
PValue += Melement * Nelement;
}
Pd[row * ncols +col] = PValue;
}
int main(int argc, char **argv){
int i,j;
int size = Width * Width * sizeof(float);
float M[Width][Width], N[Width][Width], P[Width][Width];
float *Md, *Nd, *Pd;
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
M[i][j] = 1;
N[i][j] = 2;
}
}
hipMalloc((void**)&Md, size);
hipMalloc((void**)&Nd, size);
hipMalloc((void**)&Pd, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//setup the execution configuration
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(Width/TILE_WIDTH, Width/TILE_WIDTH);
//launch the device computation thread!
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//read P from the device
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
for(i = 0; i < Width; i++){
for(j = 0; j < Width; j++){
printf("%.2f ", P[i][j]);
}
printf("\n");
}
} | .text
.file "matmul2.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 12432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8304(%rsp), %rax
leaq 4208(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rax,%rsi,4) # imm = 0x3F800000
movl $1073741824, (%rcx,%rsi,4) # imm = 0x40000000
incq %rsi
cmpq $32, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rdx
subq $-128, %rax
subq $-128, %rcx
cmpq $32, %rdx
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 8304(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4208(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $32, %r15
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
subq $-128, %rbx
cmpq $32, %r14
jne .LBB1_7
# %bb.10:
xorl %eax, %eax
addq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007658d_00000000-6_matmul2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.2f "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12336
orq $0, (%rsp)
subq $64, %rsp
.cfi_def_cfa_offset 12400
movq %fs:40, %rax
movq %rax, 12344(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdx
leaq 4144(%rsp), %rcx
movq %rcx, %rsi
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movl $0, %eax
.L13:
movss %xmm1, (%rdx,%rax)
movss %xmm0, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L13
subq $-128, %rdx
subq $-128, %rcx
cmpq %rsi, %rdx
jne .L12
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4144(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 8240(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 8368(%rsp), %rbp
leaq 12464(%rsp), %r14
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %r13
.L16:
leaq -128(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r14, %rbp
jne .L16
movq 12344(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $12352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $32, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmul2.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 12432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8304(%rsp), %rax
leaq 4208(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rax,%rsi,4) # imm = 0x3F800000
movl $1073741824, (%rcx,%rsi,4) # imm = 0x40000000
incq %rsi
cmpq $32, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rdx
subq $-128, %rax
subq $-128, %rcx
cmpq $32, %rdx
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 8304(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4208(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $32, %r15
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
subq $-128, %rbx
cmpq $32, %r14
jne .LBB1_7
# %bb.10:
xorl %eax, %eax
addq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
cudaMallocManaged(&a, bytes);
cudaMallocManaged(&b, bytes);
cudaMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = cudaGetDevice(&id);
// Set some hints about the data and do some prefetching
cudaMemAdvise(a, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemAdvise(b, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
cudaMemAdvise(a, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemAdvise(b, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemPrefetchAsync(a, bytes, id);
cudaMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
cudaDeviceSynchronize();
// Prefetch to the host (CPU)
cudaMemPrefetchAsync(a, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(b, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, cudaCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
cudaFree(a);
cudaFree(b);
cudaFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
cudaMallocManaged(&a, bytes);
cudaMallocManaged(&b, bytes);
cudaMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = cudaGetDevice(&id);
// Set some hints about the data and do some prefetching
cudaMemAdvise(a, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemAdvise(b, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
cudaMemAdvise(a, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemAdvise(b, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemPrefetchAsync(a, bytes, id);
cudaMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
cudaDeviceSynchronize();
// Prefetch to the host (CPU)
cudaMemPrefetchAsync(a, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(b, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, cudaCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
cudaFree(a);
cudaFree(b);
cudaFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} | .file "tmpxft_00005f0e_00000000-6_vectorAdd_um_prefetch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "COMPLETED SUCCESSFULLY!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, 4(%rsp)
movl $-1, %ecx
movl $3, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl $-1, %ecx
movl $3, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemAdvise@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $262144, %rbx
jne .L12
movl 4(%rsp), %ecx
movl $1, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl 4(%rsp), %ecx
movl $1, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemAdvise@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $65536, %eax
.L14:
subl $1, %eax
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $65536, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
cudaMallocManaged(&a, bytes);
cudaMallocManaged(&b, bytes);
cudaMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = cudaGetDevice(&id);
// Set some hints about the data and do some prefetching
cudaMemAdvise(a, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemAdvise(b, bytes, cudaMemAdviseSetPreferredLocation, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
cudaMemAdvise(a, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemAdvise(b, bytes, cudaMemAdviseSetReadMostly, id);
cudaMemPrefetchAsync(a, bytes, id);
cudaMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
cudaDeviceSynchronize();
// Prefetch to the host (CPU)
cudaMemPrefetchAsync(a, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(b, bytes, cudaCpuDeviceId);
cudaMemPrefetchAsync(c, bytes, cudaCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
cudaFree(a);
cudaFree(b);
cudaFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
hipMallocManaged(&a, bytes);
hipMallocManaged(&b, bytes);
hipMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = hipGetDevice(&id);
// Set some hints about the data and do some prefetching
hipMemAdvise(a, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemAdvise(b, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
hipMemAdvise(a, bytes, hipMemAdviseSetReadMostly, id);
hipMemAdvise(b, bytes, hipMemAdviseSetReadMostly, id);
hipMemPrefetchAsync(a, bytes, id);
hipMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
hipDeviceSynchronize();
// Prefetch to the host (CPU)
hipMemPrefetchAsync(a, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(b, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, hipCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
hipFree(a);
hipFree(b);
hipFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
hipMallocManaged(&a, bytes);
hipMallocManaged(&b, bytes);
hipMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = hipGetDevice(&id);
// Set some hints about the data and do some prefetching
hipMemAdvise(a, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemAdvise(b, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
hipMemAdvise(a, bytes, hipMemAdviseSetReadMostly, id);
hipMemAdvise(b, bytes, hipMemAdviseSetReadMostly, id);
hipMemPrefetchAsync(a, bytes, id);
hipMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
hipDeviceSynchronize();
// Prefetch to the host (CPU)
hipMemPrefetchAsync(a, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(b, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, hipCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
hipFree(a);
hipFree(b);
hipFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int N) {
// Calculate global thread thread ID
int tid = (blockDim.x * blockIdx.x) + threadIdx.x;
// Boundary check
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
int main() {
// Array size of 2^16 (65536 elements)
const int N = 1 << 16;
size_t bytes = N * sizeof(int);
// Declare unified memory pointers
int *a, *b, *c;
// Allocation memory for these pointers
hipMallocManaged(&a, bytes);
hipMallocManaged(&b, bytes);
hipMallocManaged(&c, bytes);
// Get the device ID for prefetching calls
int id = hipGetDevice(&id);
// Set some hints about the data and do some prefetching
hipMemAdvise(a, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemAdvise(b, bytes, hipMemAdviseSetPreferredLocation, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, id);
// Initialize vectors
for (int i = 0; i < N; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
}
// Pre-fetch 'a' and 'b' arrays to the specified device (GPU)
hipMemAdvise(a, bytes, hipMemAdviseSetReadMostly, id);
hipMemAdvise(b, bytes, hipMemAdviseSetReadMostly, id);
hipMemPrefetchAsync(a, bytes, id);
hipMemPrefetchAsync(b, bytes, id);
// Threads per CTA (1024 threads per CTA)
int BLOCK_SIZE = 1 << 10;
// CTAs per Grid
int GRID_SIZE = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
// Call CUDA kernel
vectorAdd<<<GRID_SIZE, BLOCK_SIZE>>>(a, b, c, N);
// Wait for all previous operations before using values
// We need this because we don't get the implicit synchronization of
// cudaMemcpy like in the original example
hipDeviceSynchronize();
// Prefetch to the host (CPU)
hipMemPrefetchAsync(a, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(b, bytes, hipCpuDeviceId);
hipMemPrefetchAsync(c, bytes, hipCpuDeviceId);
// Verify the result on the CPU
for (int i = 0; i < N; i++) {
assert(c[i] == a[i] + b[i]);
}
// Free unified memory (same as memory allocated with cudaMalloc)
hipFree(a);
hipFree(b);
hipFree(c);
cout << "COMPLETED SUCCESSFULLY!\n";
return 0;
} | .text
.file "vectorAdd_um_prefetch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 4(%rsp), %rdi
callq hipGetDevice
movl %eax, 4(%rsp)
movq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $3, %edx
movl $-1, %ecx
callq hipMemAdvise
movq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $3, %edx
movl $-1, %ecx
callq hipMemAdvise
movq 24(%rsp), %rdi
movl 4(%rsp), %edx
xorl %ebx, %ebx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl 4(%rsp), %ecx
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMemAdvise
movq 8(%rsp), %rdi
movl 4(%rsp), %ecx
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMemAdvise
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl 4(%rsp), %edx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 960(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $65536, 36(%rsp) # imm = 0x10000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "COMPLETED SUCCESSFULLY!\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005f0e_00000000-6_vectorAdd_um_prefetch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "COMPLETED SUCCESSFULLY!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, 4(%rsp)
movl $-1, %ecx
movl $3, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl $-1, %ecx
movl $3, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemAdvise@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $262144, %rbx
jne .L12
movl 4(%rsp), %ecx
movl $1, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl 4(%rsp), %ecx
movl $1, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemAdvise@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $-1, %edx
movl $262144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $65536, %eax
.L14:
subl $1, %eax
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $65536, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd_um_prefetch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 4(%rsp), %rdi
callq hipGetDevice
movl %eax, 4(%rsp)
movq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $3, %edx
movl $-1, %ecx
callq hipMemAdvise
movq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $3, %edx
movl $-1, %ecx
callq hipMemAdvise
movq 24(%rsp), %rdi
movl 4(%rsp), %edx
xorl %ebx, %ebx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl 4(%rsp), %ecx
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMemAdvise
movq 8(%rsp), %rdi
movl 4(%rsp), %ecx
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMemAdvise
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl 4(%rsp), %edx
movl $262144, %esi # imm = 0x40000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 960(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $65536, 36(%rsp) # imm = 0x10000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "COMPLETED SUCCESSFULLY!\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} | code for sm_80
Function : _Z4axpyfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ SHF.L.U32 R0, R0, 0x3, RZ ; /* 0x0000000300007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f28000c1e1900 */
/*00d0*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x000f62000c1e1900 */
/*00e0*/ FFMA R7, R0, c[0x0][0x160], R7 ; /* 0x0000580000077a23 */
/* 0x004fca0000000007 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0100*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100404077981 */
/* 0x001ea2000c1e1900 */
/*0120*/ FFMA R9, R0, c[0x0][0x160], R9 ; /* 0x0000580000097a23 */
/* 0x008fca0000000009 */
/*0130*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c101904 */
/*0140*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x001ee2000c1e1900 */
/*0160*/ FFMA R11, R0, c[0x0][0x160], R11 ; /* 0x00005800000b7a23 */
/* 0x010fca000000000b */
/*0170*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0001e8000c101904 */
/*0180*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x001f22000c1e1900 */
/*01a0*/ FFMA R13, R0, c[0x0][0x160], R13 ; /* 0x00005800000d7a23 */
/* 0x020fca000000000d */
/*01b0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R0, [R2.64+0x10] ; /* 0x0000100402007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x001f62000c1e1900 */
/*01e0*/ FFMA R7, R0, c[0x0][0x160], R7 ; /* 0x0000580000077a23 */
/* 0x004fca0000000007 */
/*01f0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x000fe8000c101904 */
/*0200*/ LDG.E R0, [R2.64+0x14] ; /* 0x0000140402007981 */
/* 0x000ee4000c1e1900 */
/*0210*/ FFMA R9, R0, c[0x0][0x160], R9 ; /* 0x0000580000097a23 */
/* 0x008fca0000000009 */
/*0220*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c101904 */
/*0230*/ LDG.E R0, [R2.64+0x18] ; /* 0x0000180402007981 */
/* 0x000f24000c1e1900 */
/*0240*/ FFMA R11, R0, c[0x0][0x160], R11 ; /* 0x00005800000b7a23 */
/* 0x010fca000000000b */
/*0250*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c101904 */
/*0260*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000f64000c1e1900 */
/*0270*/ FFMA R13, R0, c[0x0][0x160], R13 ; /* 0x00005800000d7a23 */
/* 0x020fca000000000d */
/*0280*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} | .file "tmpxft_0019c537_00000000-6_multiAxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4axpyfPfS_fPfS_
.type _Z26__device_stub__Z4axpyfPfS_fPfS_, @function
_Z26__device_stub__Z4axpyfPfS_fPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyfPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z4axpyfPfS_fPfS_, .-_Z26__device_stub__Z4axpyfPfS_fPfS_
.globl _Z4axpyfPfS_
.type _Z4axpyfPfS_, @function
_Z4axpyfPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4axpyfPfS_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4axpyfPfS_, .-_Z4axpyfPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "CPU took %e seconds to run %d entry axpy \n"
.align 8
.LC4:
.string "For small case, y at end is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f \n"
.LC6:
.string "Time to run GPU code: %e \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r15d
movslq %eax, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r13d, %r13d
jle .L12
leal -1(%r13), %ecx
movl $0, %eax
movss .LC0(%rip), %xmm1
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm1, (%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L13
.L12:
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
call clock@PLT
movq %rax, 8(%rsp)
movl $100, %esi
leal -1(%r13), %ecx
movss .LC1(%rip), %xmm1
jmp .L14
.L15:
movaps %xmm1, %xmm0
mulss 0(%rbp,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L15
.L18:
subl $1, %esi
je .L16
.L14:
movl $0, %eax
testl %r15d, %r15d
jg .L15
jmp .L18
.L16:
call clock@PLT
movq 8(%rsp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
cmpl $39, %r13d
jle .L30
.L19:
call clock@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 15(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $16, %ecx
movl %r15d, %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L20:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r13d, %r13d
jle .L21
movq %rbx, %r14
leal -1(%r13), %eax
leaq 4(%rbx,%rax,4), %r15
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L22
.L21:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L19
.L33:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movss .LC1(%rip), %xmm0
call _Z26__device_stub__Z4axpyfPfS_fPfS_
jmp .L20
.L31:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movss .LC1(%rip), %xmm0
call _Z26__device_stub__Z4axpyfPfS_fPfS_
jmp .L23
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z4axpyfPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyfPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1056964608
.align 4
.LC2:
.long 1287568416
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
cudaMalloc((void**)&x_device, N*sizeof(float));
cudaMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
cudaMemcpy(x_device, x_host, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(y_device, y_host, N*sizeof(float), cudaMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
cudaMemcpy(y_host, y_device, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(x_device);
cudaFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyfPfS_
.globl _Z4axpyfPfS_
.p2align 8
.type _Z4axpyfPfS_,@function
_Z4axpyfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 3, v0
s_mov_b64 s[0:1], 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
s_add_u32 s0, s0, 4
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 32
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v5, s2, v4
global_store_b32 v[6:7], v5, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyfPfS_, .Lfunc_end0-_Z4axpyfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4axpyfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[idx];
}
}
int main(int argc, char** argv){
int N = atoi(argv[1]);
float a = 0.5;
float *x_host = (float *)malloc(N*sizeof(float));
float *y_host = (float *)malloc(N*sizeof(float));
int i;
for(i=0; i<N; i++){
x_host[i] = (float)i;
y_host[i] = 1.0;
}
float *z = (float *)malloc(N*sizeof(float));
clock_t startTime = clock();
int rep;
int nReps = 100;
for(rep=0; rep<nReps; rep++){
for(i=0; i<N; i++) z[i] = a*x_host[i] + y_host[i];
}
clock_t endTime = clock();
float cpuTime = float(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("CPU took %e seconds to run %d entry axpy \n", cpuTime, N);
free(z);
z = NULL;
if(N<40){
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
int j;
printf("For small case, y at end is: \n");
for(j=0; j<N; j++) printf("%f \n", y_host[j]);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
}
//starting GPU time
startTime = clock();
float* x_device;
float* y_device;
hipMalloc((void**)&x_device, N*sizeof(float));
hipMalloc((void**)&y_device, N*sizeof(float));
// copy from host to device
hipMemcpy(x_device, x_host, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(y_device, y_host, N*sizeof(float), hipMemcpyHostToDevice);
int n_entries_per_thread = 8;
int n_threads_per_block = 16/n_entries_per_thread;
int n_blocks = N/(n_threads_per_block*n_entries_per_thread);
axpy <<<n_blocks, n_threads_per_block>>> (a, x_device, y_device);
hipMemcpy(y_host, y_device, N*sizeof(float), hipMemcpyDeviceToHost);
hipFree(x_device);
hipFree(y_device);
x_device = NULL;
y_device = NULL;
endTime = clock();
float timeGPU = (float)(endTime-startTime)/(float)(nReps*CLOCKS_PER_SEC);
printf("Time to run GPU code: %e \n", timeGPU);
free(x_host);
free(y_host);
x_host=NULL;
y_host=NULL;
return 0;
} | .text
.file "multiAxpy.hip"
.globl _Z19__device_stub__axpyfPfS_ # -- Begin function _Z19__device_stub__axpyfPfS_
.p2align 4, 0x90
.type _Z19__device_stub__axpyfPfS_,@function
_Z19__device_stub__axpyfPfS_: # @_Z19__device_stub__axpyfPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyfPfS_, .Lfunc_end0-_Z19__device_stub__axpyfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4cbebc20 # float 1.0E+8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movl $1065353216, (%r14,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
callq clock
movq %rax, %rbp
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r12d, %esi
movb $1, %al
callq printf
cmpl $39, %r12d
jg .LBB1_10
# %bb.4:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $4, %edi
orq %r13, %rdi
leaq 2(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB1_9
# %bb.7: # %.lr.ph101.preheader
movl %r12d, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
jne .LBB1_8
.LBB1_9: # %._crit_edge102
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movabsq $4294967296, %r13 # imm = 0x100000000
.LBB1_10:
callq clock
movq %rax, %rbp
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $4, %edi
orq %r13, %rdi
addq $2, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq $0, 16(%rsp)
movq $0, 8(%rsp)
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyfPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyfPfS_,@object # @_Z4axpyfPfS_
.section .rodata,"a",@progbits
.globl _Z4axpyfPfS_
.p2align 3, 0x0
_Z4axpyfPfS_:
.quad _Z19__device_stub__axpyfPfS_
.size _Z4axpyfPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU took %e seconds to run %d entry axpy \n"
.size .L.str, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f \n"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time to run GPU code: %e \n"
.size .L.str.3, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4axpyfPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "For small case, y at end is: "
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyfPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyfPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4axpyfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ SHF.L.U32 R0, R0, 0x3, RZ ; /* 0x0000000300007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f28000c1e1900 */
/*00d0*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x000f62000c1e1900 */
/*00e0*/ FFMA R7, R0, c[0x0][0x160], R7 ; /* 0x0000580000077a23 */
/* 0x004fca0000000007 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0100*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100404077981 */
/* 0x001ea2000c1e1900 */
/*0120*/ FFMA R9, R0, c[0x0][0x160], R9 ; /* 0x0000580000097a23 */
/* 0x008fca0000000009 */
/*0130*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c101904 */
/*0140*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x001ee2000c1e1900 */
/*0160*/ FFMA R11, R0, c[0x0][0x160], R11 ; /* 0x00005800000b7a23 */
/* 0x010fca000000000b */
/*0170*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0001e8000c101904 */
/*0180*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x001f22000c1e1900 */
/*01a0*/ FFMA R13, R0, c[0x0][0x160], R13 ; /* 0x00005800000d7a23 */
/* 0x020fca000000000d */
/*01b0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R0, [R2.64+0x10] ; /* 0x0000100402007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x001f62000c1e1900 */
/*01e0*/ FFMA R7, R0, c[0x0][0x160], R7 ; /* 0x0000580000077a23 */
/* 0x004fca0000000007 */
/*01f0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x000fe8000c101904 */
/*0200*/ LDG.E R0, [R2.64+0x14] ; /* 0x0000140402007981 */
/* 0x000ee4000c1e1900 */
/*0210*/ FFMA R9, R0, c[0x0][0x160], R9 ; /* 0x0000580000097a23 */
/* 0x008fca0000000009 */
/*0220*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c101904 */
/*0230*/ LDG.E R0, [R2.64+0x18] ; /* 0x0000180402007981 */
/* 0x000f24000c1e1900 */
/*0240*/ FFMA R11, R0, c[0x0][0x160], R11 ; /* 0x00005800000b7a23 */
/* 0x010fca000000000b */
/*0250*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c101904 */
/*0260*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000f64000c1e1900 */
/*0270*/ FFMA R13, R0, c[0x0][0x160], R13 ; /* 0x00005800000d7a23 */
/* 0x020fca000000000d */
/*0280*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyfPfS_
.globl _Z4axpyfPfS_
.p2align 8
.type _Z4axpyfPfS_,@function
_Z4axpyfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 3, v0
s_mov_b64 s[0:1], 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
s_add_u32 s0, s0, 4
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 32
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v5, s2, v4
global_store_b32 v[6:7], v5, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyfPfS_, .Lfunc_end0-_Z4axpyfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4axpyfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c537_00000000-6_multiAxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4axpyfPfS_fPfS_
.type _Z26__device_stub__Z4axpyfPfS_fPfS_, @function
_Z26__device_stub__Z4axpyfPfS_fPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyfPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z4axpyfPfS_fPfS_, .-_Z26__device_stub__Z4axpyfPfS_fPfS_
.globl _Z4axpyfPfS_
.type _Z4axpyfPfS_, @function
_Z4axpyfPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4axpyfPfS_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4axpyfPfS_, .-_Z4axpyfPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "CPU took %e seconds to run %d entry axpy \n"
.align 8
.LC4:
.string "For small case, y at end is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f \n"
.LC6:
.string "Time to run GPU code: %e \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r15d
movslq %eax, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r13d, %r13d
jle .L12
leal -1(%r13), %ecx
movl $0, %eax
movss .LC0(%rip), %xmm1
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm1, (%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L13
.L12:
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
call clock@PLT
movq %rax, 8(%rsp)
movl $100, %esi
leal -1(%r13), %ecx
movss .LC1(%rip), %xmm1
jmp .L14
.L15:
movaps %xmm1, %xmm0
mulss 0(%rbp,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L15
.L18:
subl $1, %esi
je .L16
.L14:
movl $0, %eax
testl %r15d, %r15d
jg .L15
jmp .L18
.L16:
call clock@PLT
movq 8(%rsp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
cmpl $39, %r13d
jle .L30
.L19:
call clock@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 15(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $16, %ecx
movl %r15d, %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L20:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r13d, %r13d
jle .L21
movq %rbx, %r14
leal -1(%r13), %eax
leaq 4(%rbx,%rax,4), %r15
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L22
.L21:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L19
.L33:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movss .LC1(%rip), %xmm0
call _Z26__device_stub__Z4axpyfPfS_fPfS_
jmp .L20
.L31:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movss .LC1(%rip), %xmm0
call _Z26__device_stub__Z4axpyfPfS_fPfS_
jmp .L23
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z4axpyfPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyfPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1056964608
.align 4
.LC2:
.long 1287568416
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiAxpy.hip"
.globl _Z19__device_stub__axpyfPfS_ # -- Begin function _Z19__device_stub__axpyfPfS_
.p2align 4, 0x90
.type _Z19__device_stub__axpyfPfS_,@function
_Z19__device_stub__axpyfPfS_: # @_Z19__device_stub__axpyfPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyfPfS_, .Lfunc_end0-_Z19__device_stub__axpyfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4cbebc20 # float 1.0E+8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movl $1065353216, (%r14,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
callq clock
movq %rax, %rbp
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r12d, %esi
movb $1, %al
callq printf
cmpl $39, %r12d
jg .LBB1_10
# %bb.4:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $4, %edi
orq %r13, %rdi
leaq 2(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB1_9
# %bb.7: # %.lr.ph101.preheader
movl %r12d, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
jne .LBB1_8
.LBB1_9: # %._crit_edge102
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movabsq $4294967296, %r13 # imm = 0x100000000
.LBB1_10:
callq clock
movq %rax, %rbp
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $4, %edi
orq %r13, %rdi
addq $2, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4axpyfPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq $0, 16(%rsp)
movq $0, 8(%rsp)
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyfPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyfPfS_,@object # @_Z4axpyfPfS_
.section .rodata,"a",@progbits
.globl _Z4axpyfPfS_
.p2align 3, 0x0
_Z4axpyfPfS_:
.quad _Z19__device_stub__axpyfPfS_
.size _Z4axpyfPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU took %e seconds to run %d entry axpy \n"
.size .L.str, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f \n"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time to run GPU code: %e \n"
.size .L.str.3, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4axpyfPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "For small case, y at end is: "
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyfPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyfPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
cudaMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
cudaMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaFree(gpu_block1);
cudaFree(gpu_block2);
cudaFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} | code for sm_80
Function : _Z3modPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0009 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00a0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00b0*/ IABS R3, R4 ; /* 0x0000000400037213 */
/* 0x001fe40000000000 */
/*00c0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e240000209400 */
/*00d0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x008fe40000000000 */
/*00f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f46270 */
/*0100*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R7, R7, R3, R12 ; /* 0x0000000307077224 */
/* 0x000fe400078e020c */
/*0190*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0009 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fc80007ffe0ff */
/*01f0*/ @!P2 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff0707a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8multiplyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8subtractPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
cudaMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
cudaMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaFree(gpu_block1);
cudaFree(gpu_block2);
cudaFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} | .file "tmpxft_0010dbdf_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z31__device_stub__Z8subtractPiS_S_PiS_S_
.type _Z31__device_stub__Z8subtractPiS_S_PiS_S_, @function
_Z31__device_stub__Z8subtractPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8subtractPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z8subtractPiS_S_PiS_S_, .-_Z31__device_stub__Z8subtractPiS_S_PiS_S_
.globl _Z8subtractPiS_S_
.type _Z8subtractPiS_S_, @function
_Z8subtractPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8subtractPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8subtractPiS_S_, .-_Z8subtractPiS_S_
.globl _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
.type _Z31__device_stub__Z8multiplyPiS_S_PiS_S_, @function
_Z31__device_stub__Z8multiplyPiS_S_PiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z8multiplyPiS_S_PiS_S_, .-_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
.globl _Z8multiplyPiS_S_
.type _Z8multiplyPiS_S_, @function
_Z8multiplyPiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8multiplyPiS_S_, .-_Z8multiplyPiS_S_
.globl _Z26__device_stub__Z3modPiS_S_PiS_S_
.type _Z26__device_stub__Z3modPiS_S_PiS_S_, @function
_Z26__device_stub__Z3modPiS_S_PiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3modPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z26__device_stub__Z3modPiS_S_PiS_S_, .-_Z26__device_stub__Z3modPiS_S_PiS_S_
.globl _Z3modPiS_S_
.type _Z3modPiS_S_, @function
_Z3modPiS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3modPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z3modPiS_S_, .-_Z3modPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "///////////////////////OUTPUT ADD///////////////\n"
.align 8
.LC1:
.string "///////////////////////OUTPUT SUBTRACT///////////////\n"
.align 8
.LC2:
.string "///////////////////////OUTPUT MULTIPLY///////////////\n"
.align 8
.LC3:
.string "///////////////////////OUTPUT MOD///////////////\n"
.align 8
.LC4:
.string "Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n"
.text
.globl _Z8main_subiiii
.type _Z8main_subiiii, @function
_Z8main_subiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -128(%rbp)
movl %esi, -132(%rbp)
movl %edx, -136(%rbp)
movl %ecx, -124(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movslq %edi, %r15
leaq 0(,%r15,4), %rax
movq %rax, -120(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L36:
cmpq %rdx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L38
orq $0, -8(%rsp,%rax)
.L38:
movq %rsp, %r13
movq -120(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L39:
cmpq %rdx, %rsp
je .L40
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L39
.L40:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L41
orq $0, -8(%rsp,%rax)
.L41:
movq %rsp, %r14
movq -120(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L42:
cmpq %rdx, %rsp
je .L43
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L42
.L43:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L44
orq $0, -8(%rsp,%rax)
.L44:
movq %rsp, %r12
cmpl $0, -128(%rbp)
jle .L45
movl $0, %ebx
.L46:
movl %ebx, 0(%r13,%rbx,4)
call rand@PLT
cltd
shrl $30, %edx
addl %edx, %eax
andl $3, %eax
subl %edx, %eax
movl %eax, (%r14,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
jne .L46
.L45:
leaq -104(%rbp), %rdi
movq -120(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl -124(%rbp), %eax
cmpl $3, %eax
je .L47
jg .L48
cmpl $1, %eax
je .L49
cmpl $2, %eax
jne .L51
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z31__device_stub__Z8subtractPiS_S_PiS_S_
jmp .L51
.L48:
cmpl $4, -124(%rbp)
jne .L51
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z26__device_stub__Z3modPiS_S_PiS_S_
jmp .L51
.L49:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L51:
movl $2, %ecx
movq -120(%rbp), %rbx
movq %rbx, %rdx
movq -104(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -96(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movl -128(%rbp), %eax
testl %eax, %eax
jle .L35
movl %eax, %r13d
subl $1, %r13d
shrl $2, %r13d
addl $1, %r13d
movl %r13d, %r13d
salq $2, %r13
movl $0, %ebx
leaq .LC4(%rip), %r14
.L58:
movl %ebx, %edx
movl 4(%r12,%rbx,4), %r9d
movl (%r12,%rbx,4), %ecx
movl 12(%r12,%rbx,4), %eax
pushq %rax
leal 3(%rbx), %eax
pushq %rax
movl 8(%r12,%rbx,4), %eax
pushq %rax
leal 2(%rbx), %eax
pushq %rax
leal 1(%rbx), %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $32, %rsp
cmpq %r13, %rbx
jne .L58
.L35:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L64
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L63:
.cfi_restore_state
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L51
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
jmp .L51
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8main_subiiii, .-_Z8main_subiiii
.section .rodata.str1.8
.align 8
.LC5:
.string "Warning: Total thread count is not evenly divisible by the block size\n"
.align 8
.LC6:
.string "The total number of threads will be rounded up to %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
cmpl $1, %edi
jg .L71
movl $256, %ebp
movl $4096, %r12d
movl $1048576, %ebx
.L66:
movl $1, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $2, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $3, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $4, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl %edi, %r12d
movq %rsi, %r13
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movl $256, %ebp
cmpl $2, %r12d
jg .L72
.L67:
movl %ebx, %eax
cltd
idivl %ebp
movl %eax, %r12d
testl %edx, %edx
je .L66
leal 1(%rax), %r12d
movl %ebp, %ebx
imull %r12d, %ebx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L66
.L72:
movq 16(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L67
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z3modPiS_S_"
.LC8:
.string "_Z8multiplyPiS_S_"
.LC9:
.string "_Z8subtractPiS_S_"
.LC10:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3modPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8subtractPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
cudaMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
cudaMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost );
cudaFree(gpu_block1);
cudaFree(gpu_block2);
cudaFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
hipMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
hipMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipFree(gpu_block1);
hipFree(gpu_block2);
hipFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
hipMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
hipMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipFree(gpu_block1);
hipFree(gpu_block2);
hipFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8subtractPiS_S_
.globl _Z8subtractPiS_S_
.p2align 8
.type _Z8subtractPiS_S_,@function
_Z8subtractPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8subtractPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8subtractPiS_S_, .Lfunc_end1-_Z8subtractPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8multiplyPiS_S_
.globl _Z8multiplyPiS_S_
.p2align 8
.type _Z8multiplyPiS_S_,@function
_Z8multiplyPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8multiplyPiS_S_, .Lfunc_end2-_Z8multiplyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3modPiS_S_
.globl _Z3modPiS_S_
.p2align 8
.type _Z3modPiS_S_,@function
_Z3modPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3modPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3modPiS_S_, .Lfunc_end3-_Z3modPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8subtractPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8subtractPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3modPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3modPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]+array2[i];
}
//SUBTRACT=2
__global__ void subtract(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]-array2[i];
}
//MULTIPLY=3
__global__ void multiply(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]*array2[i];
}
//MOD=4
__global__ void mod(int * array1,int * array2,int * array3)
{
const unsigned int i = (blockIdx.x * blockDim.x) + threadIdx.x;
array3[i]=array1[i]%array2[i];
}
//////////////////////////GPU FUNCTION//////////////////////////////////
void main_sub(int N, int BLOCK_SIZE, int NUM_BLOCKS, int whichOperation)
{
/* Declare statically four arrays of ARRAY_SIZE each */
int array1[ARRAY_SIZE];
int array2[ARRAY_SIZE];
int array3[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++)
{
array1[i] = i;
array2[i] = (rand()%4);
//Check that array1 and array 2 inputs are correct
//printf("ARRAY1 at %i\nARRAY2 at %i\n\n", array1[i], array2[i]);
}
/* Declare pointers for GPU based params */
int *gpu_block1;
int *gpu_block2;
int *gpu_block3;
hipMalloc((void **)&gpu_block1, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block2, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_block3, ARRAY_SIZE_IN_BYTES);
hipMemcpy( gpu_block1, array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block2, array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
hipMemcpy( gpu_block3, array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
/* Execute our kernel */
switch(whichOperation) {
//ADD
case 1 :
printf("///////////////////////OUTPUT ADD///////////////\n");
add<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//SUBTRACT
case 2 :
printf("///////////////////////OUTPUT SUBTRACT///////////////\n");
subtract<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MULTIPLY
case 3 :
printf("///////////////////////OUTPUT MULTIPLY///////////////\n");
multiply<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
//MOD
case 4 :
printf("///////////////////////OUTPUT MOD///////////////\n");
mod<<<NUM_BLOCKS, BLOCK_SIZE>>>(gpu_block1,gpu_block2,gpu_block3);
break;
}
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy( array1, gpu_block1, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array2, gpu_block2, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipMemcpy( array3, gpu_block3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost );
hipFree(gpu_block1);
hipFree(gpu_block2);
hipFree(gpu_block3);
/* Iterate through the arrays and print */
for(int i = 0; i < ARRAY_SIZE; i+=4)
{
printf("Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n", i, array3[i], i+1, array3[i+1],i+2, array3[i+2], i+3, array3[i+3]);
}
}
//////////////////////////MAIN///////////////////////////////////
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = (1 << 20);
int blockSize = 256;
if (argc >= 2) {
totalThreads = atoi(argv[1]);
}
if (argc >= 3) {
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
main_sub(totalThreads,blockSize,numBlocks, 1);
main_sub(totalThreads,blockSize,numBlocks, 2);
main_sub(totalThreads,blockSize,numBlocks, 3);
main_sub(totalThreads,blockSize,numBlocks, 4);
} | .text
.file "assignment.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__subtractPiS_S_ # -- Begin function _Z23__device_stub__subtractPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__subtractPiS_S_,@function
_Z23__device_stub__subtractPiS_S_: # @_Z23__device_stub__subtractPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8subtractPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__subtractPiS_S_, .Lfunc_end1-_Z23__device_stub__subtractPiS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiplyPiS_S_ # -- Begin function _Z23__device_stub__multiplyPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPiS_S_,@function
_Z23__device_stub__multiplyPiS_S_: # @_Z23__device_stub__multiplyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__multiplyPiS_S_, .Lfunc_end2-_Z23__device_stub__multiplyPiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__modPiS_S_ # -- Begin function _Z18__device_stub__modPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__modPiS_S_,@function
_Z18__device_stub__modPiS_S_: # @_Z18__device_stub__modPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3modPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__modPiS_S_, .Lfunc_end3-_Z18__device_stub__modPiS_S_
.cfi_endproc
# -- End function
.globl _Z8main_subiiii # -- Begin function _Z8main_subiiii
.p2align 4, 0x90
.type _Z8main_subiiii,@function
_Z8main_subiiii: # @_Z8main_subiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $ecx killed $ecx def $rcx
movq %rcx, -192(%rbp) # 8-byte Spill
movl %edx, -44(%rbp) # 4-byte Spill
movl %esi, -48(%rbp) # 4-byte Spill
movl %edi, %r13d
movq %rsp, %r15
leaq 15(,%r13,4), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movq %rsp, %r12
subq %rax, %r12
movq %r12, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
movl %edi, -180(%rbp) # 4-byte Spill
testl %edi, %edi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, (%r15,%rbx,4)
callq rand
# kill: def $eax killed $eax def $rax
leal 3(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-4, %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB4_2
.LBB4_3: # %._crit_edge
movl -180(%rbp), %r13d # 4-byte Reload
movslq %r13d, %rbx
shlq $2, %rbx
leaq -72(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq -72(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -192(%rbp), %rax # 8-byte Reload
decl %eax
cmpl $3, %eax
ja .LBB4_14
# %bb.4: # %._crit_edge
jmpq *.LJTI4_0(,%rax,8)
.LBB4_5:
movl $.Lstr.3, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.6:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3addPiS_S_, %edi
jmp .LBB4_13
.LBB4_9:
movl $.Lstr.1, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.10:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8multiplyPiS_S_, %edi
jmp .LBB4_13
.LBB4_11:
movl $.Lstr, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.12:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3modPiS_S_, %edi
jmp .LBB4_13
.LBB4_7:
movl $.Lstr.2, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.8:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8subtractPiS_S_, %edi
.LBB4_13:
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_14:
movq -72(%rbp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -56(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
testl %r13d, %r13d
jle .LBB4_17
# %bb.15: # %.lr.ph102.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph102
# =>This Inner Loop Header: Depth=1
leal 1(%r15), %ecx
movl (%r14,%r15,4), %edx
movl 4(%r14,%r15,4), %r8d
leal 2(%r15), %r9d
movl 8(%r14,%r15,4), %r10d
leal 3(%r15), %r11d
movl 12(%r14,%r15,4), %ebx
subq $8, %rsp
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
pushq %rbx
pushq %r11
pushq %r10
callq printf
addq $32, %rsp
addq $4, %r15
cmpl %r13d, %r15d
jl .LBB4_16
.LBB4_17: # %._crit_edge103
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size _Z8main_subiiii, .Lfunc_end4-_Z8main_subiiii
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI4_0:
.quad .LBB4_5
.quad .LBB4_7
.quad .LBB4_9
.quad .LBB4_11
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
movl $1048576, %ebx # imm = 0x100000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $256, %r14d # imm = 0x100
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB5_4:
movl %ebx, %eax
cltd
idivl %r14d
movl %eax, %ebp
testl %edx, %edx
je .LBB5_6
# %bb.5:
incl %ebp
movl %ebp, %ebx
imull %r14d, %ebx
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.6, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
.LBB5_6:
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $1, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $2, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $3, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $4, %ecx
callq _Z8main_subiiii
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8subtractPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3modPiS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type _Z8subtractPiS_S_,@object # @_Z8subtractPiS_S_
.globl _Z8subtractPiS_S_
.p2align 3, 0x0
_Z8subtractPiS_S_:
.quad _Z23__device_stub__subtractPiS_S_
.size _Z8subtractPiS_S_, 8
.type _Z8multiplyPiS_S_,@object # @_Z8multiplyPiS_S_
.globl _Z8multiplyPiS_S_
.p2align 3, 0x0
_Z8multiplyPiS_S_:
.quad _Z23__device_stub__multiplyPiS_S_
.size _Z8multiplyPiS_S_, 8
.type _Z3modPiS_S_,@object # @_Z3modPiS_S_
.globl _Z3modPiS_S_
.p2align 3, 0x0
_Z3modPiS_S_:
.quad _Z18__device_stub__modPiS_S_
.size _Z3modPiS_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n"
.size .L.str.4, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The total number of threads will be rounded up to %d\n"
.size .L.str.6, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8subtractPiS_S_"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8multiplyPiS_S_"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3modPiS_S_"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "///////////////////////OUTPUT MOD///////////////"
.size .Lstr, 49
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "///////////////////////OUTPUT MULTIPLY///////////////"
.size .Lstr.1, 54
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "///////////////////////OUTPUT SUBTRACT///////////////"
.size .Lstr.2, 54
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "///////////////////////OUTPUT ADD///////////////"
.size .Lstr.3, 49
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Warning: Total thread count is not evenly divisible by the block size"
.size .Lstr.4, 70
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym _Z23__device_stub__subtractPiS_S_
.addrsig_sym _Z23__device_stub__multiplyPiS_S_
.addrsig_sym _Z18__device_stub__modPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _Z8subtractPiS_S_
.addrsig_sym _Z8multiplyPiS_S_
.addrsig_sym _Z3modPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3modPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0009 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00a0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00b0*/ IABS R3, R4 ; /* 0x0000000400037213 */
/* 0x001fe40000000000 */
/*00c0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e240000209400 */
/*00d0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x008fe40000000000 */
/*00f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f46270 */
/*0100*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R7, R7, R3, R12 ; /* 0x0000000307077224 */
/* 0x000fe400078e020c */
/*0190*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0009 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fc80007ffe0ff */
/*01f0*/ @!P2 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff0707a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8multiplyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8subtractPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8subtractPiS_S_
.globl _Z8subtractPiS_S_
.p2align 8
.type _Z8subtractPiS_S_,@function
_Z8subtractPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8subtractPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8subtractPiS_S_, .Lfunc_end1-_Z8subtractPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8multiplyPiS_S_
.globl _Z8multiplyPiS_S_
.p2align 8
.type _Z8multiplyPiS_S_,@function
_Z8multiplyPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8multiplyPiS_S_, .Lfunc_end2-_Z8multiplyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3modPiS_S_
.globl _Z3modPiS_S_
.p2align 8
.type _Z3modPiS_S_,@function
_Z3modPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3modPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3modPiS_S_, .Lfunc_end3-_Z3modPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8subtractPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8subtractPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3modPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3modPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010dbdf_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z31__device_stub__Z8subtractPiS_S_PiS_S_
.type _Z31__device_stub__Z8subtractPiS_S_PiS_S_, @function
_Z31__device_stub__Z8subtractPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8subtractPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z8subtractPiS_S_PiS_S_, .-_Z31__device_stub__Z8subtractPiS_S_PiS_S_
.globl _Z8subtractPiS_S_
.type _Z8subtractPiS_S_, @function
_Z8subtractPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8subtractPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8subtractPiS_S_, .-_Z8subtractPiS_S_
.globl _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
.type _Z31__device_stub__Z8multiplyPiS_S_PiS_S_, @function
_Z31__device_stub__Z8multiplyPiS_S_PiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z8multiplyPiS_S_PiS_S_, .-_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
.globl _Z8multiplyPiS_S_
.type _Z8multiplyPiS_S_, @function
_Z8multiplyPiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8multiplyPiS_S_, .-_Z8multiplyPiS_S_
.globl _Z26__device_stub__Z3modPiS_S_PiS_S_
.type _Z26__device_stub__Z3modPiS_S_PiS_S_, @function
_Z26__device_stub__Z3modPiS_S_PiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3modPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z26__device_stub__Z3modPiS_S_PiS_S_, .-_Z26__device_stub__Z3modPiS_S_PiS_S_
.globl _Z3modPiS_S_
.type _Z3modPiS_S_, @function
_Z3modPiS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3modPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z3modPiS_S_, .-_Z3modPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "///////////////////////OUTPUT ADD///////////////\n"
.align 8
.LC1:
.string "///////////////////////OUTPUT SUBTRACT///////////////\n"
.align 8
.LC2:
.string "///////////////////////OUTPUT MULTIPLY///////////////\n"
.align 8
.LC3:
.string "///////////////////////OUTPUT MOD///////////////\n"
.align 8
.LC4:
.string "Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n"
.text
.globl _Z8main_subiiii
.type _Z8main_subiiii, @function
_Z8main_subiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -128(%rbp)
movl %esi, -132(%rbp)
movl %edx, -136(%rbp)
movl %ecx, -124(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movslq %edi, %r15
leaq 0(,%r15,4), %rax
movq %rax, -120(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L36:
cmpq %rdx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L38
orq $0, -8(%rsp,%rax)
.L38:
movq %rsp, %r13
movq -120(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L39:
cmpq %rdx, %rsp
je .L40
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L39
.L40:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L41
orq $0, -8(%rsp,%rax)
.L41:
movq %rsp, %r14
movq -120(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L42:
cmpq %rdx, %rsp
je .L43
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L42
.L43:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L44
orq $0, -8(%rsp,%rax)
.L44:
movq %rsp, %r12
cmpl $0, -128(%rbp)
jle .L45
movl $0, %ebx
.L46:
movl %ebx, 0(%r13,%rbx,4)
call rand@PLT
cltd
shrl $30, %edx
addl %edx, %eax
andl $3, %eax
subl %edx, %eax
movl %eax, (%r14,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
jne .L46
.L45:
leaq -104(%rbp), %rdi
movq -120(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl -124(%rbp), %eax
cmpl $3, %eax
je .L47
jg .L48
cmpl $1, %eax
je .L49
cmpl $2, %eax
jne .L51
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z31__device_stub__Z8subtractPiS_S_PiS_S_
jmp .L51
.L48:
cmpl $4, -124(%rbp)
jne .L51
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z26__device_stub__Z3modPiS_S_PiS_S_
jmp .L51
.L49:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L51:
movl $2, %ecx
movq -120(%rbp), %rbx
movq %rbx, %rdx
movq -104(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -96(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movl -128(%rbp), %eax
testl %eax, %eax
jle .L35
movl %eax, %r13d
subl $1, %r13d
shrl $2, %r13d
addl $1, %r13d
movl %r13d, %r13d
salq $2, %r13
movl $0, %ebx
leaq .LC4(%rip), %r14
.L58:
movl %ebx, %edx
movl 4(%r12,%rbx,4), %r9d
movl (%r12,%rbx,4), %ecx
movl 12(%r12,%rbx,4), %eax
pushq %rax
leal 3(%rbx), %eax
pushq %rax
movl 8(%r12,%rbx,4), %eax
pushq %rax
leal 2(%rbx), %eax
pushq %rax
leal 1(%rbx), %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $32, %rsp
cmpq %r13, %rbx
jne .L58
.L35:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L64
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L63:
.cfi_restore_state
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L51
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -136(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z31__device_stub__Z8multiplyPiS_S_PiS_S_
jmp .L51
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8main_subiiii, .-_Z8main_subiiii
.section .rodata.str1.8
.align 8
.LC5:
.string "Warning: Total thread count is not evenly divisible by the block size\n"
.align 8
.LC6:
.string "The total number of threads will be rounded up to %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
cmpl $1, %edi
jg .L71
movl $256, %ebp
movl $4096, %r12d
movl $1048576, %ebx
.L66:
movl $1, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $2, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $3, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $4, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z8main_subiiii
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl %edi, %r12d
movq %rsi, %r13
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movl $256, %ebp
cmpl $2, %r12d
jg .L72
.L67:
movl %ebx, %eax
cltd
idivl %ebp
movl %eax, %r12d
testl %edx, %edx
je .L66
leal 1(%rax), %r12d
movl %ebp, %ebx
imull %r12d, %ebx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L66
.L72:
movq 16(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L67
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z3modPiS_S_"
.LC8:
.string "_Z8multiplyPiS_S_"
.LC9:
.string "_Z8subtractPiS_S_"
.LC10:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3modPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8subtractPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "assignment.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__subtractPiS_S_ # -- Begin function _Z23__device_stub__subtractPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__subtractPiS_S_,@function
_Z23__device_stub__subtractPiS_S_: # @_Z23__device_stub__subtractPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8subtractPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__subtractPiS_S_, .Lfunc_end1-_Z23__device_stub__subtractPiS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiplyPiS_S_ # -- Begin function _Z23__device_stub__multiplyPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPiS_S_,@function
_Z23__device_stub__multiplyPiS_S_: # @_Z23__device_stub__multiplyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__multiplyPiS_S_, .Lfunc_end2-_Z23__device_stub__multiplyPiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__modPiS_S_ # -- Begin function _Z18__device_stub__modPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__modPiS_S_,@function
_Z18__device_stub__modPiS_S_: # @_Z18__device_stub__modPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3modPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__modPiS_S_, .Lfunc_end3-_Z18__device_stub__modPiS_S_
.cfi_endproc
# -- End function
.globl _Z8main_subiiii # -- Begin function _Z8main_subiiii
.p2align 4, 0x90
.type _Z8main_subiiii,@function
_Z8main_subiiii: # @_Z8main_subiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $ecx killed $ecx def $rcx
movq %rcx, -192(%rbp) # 8-byte Spill
movl %edx, -44(%rbp) # 4-byte Spill
movl %esi, -48(%rbp) # 4-byte Spill
movl %edi, %r13d
movq %rsp, %r15
leaq 15(,%r13,4), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movq %rsp, %r12
subq %rax, %r12
movq %r12, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
movl %edi, -180(%rbp) # 4-byte Spill
testl %edi, %edi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, (%r15,%rbx,4)
callq rand
# kill: def $eax killed $eax def $rax
leal 3(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-4, %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB4_2
.LBB4_3: # %._crit_edge
movl -180(%rbp), %r13d # 4-byte Reload
movslq %r13d, %rbx
shlq $2, %rbx
leaq -72(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq -72(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -192(%rbp), %rax # 8-byte Reload
decl %eax
cmpl $3, %eax
ja .LBB4_14
# %bb.4: # %._crit_edge
jmpq *.LJTI4_0(,%rax,8)
.LBB4_5:
movl $.Lstr.3, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.6:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3addPiS_S_, %edi
jmp .LBB4_13
.LBB4_9:
movl $.Lstr.1, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.10:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8multiplyPiS_S_, %edi
jmp .LBB4_13
.LBB4_11:
movl $.Lstr, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.12:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3modPiS_S_, %edi
jmp .LBB4_13
.LBB4_7:
movl $.Lstr.2, %edi
callq puts@PLT
movl -44(%rbp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -48(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.8:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movq %rdx, -128(%rbp)
leaq -144(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rax
movq %rax, -168(%rbp)
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8subtractPiS_S_, %edi
.LBB4_13:
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_14:
movq -72(%rbp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -56(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
testl %r13d, %r13d
jle .LBB4_17
# %bb.15: # %.lr.ph102.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph102
# =>This Inner Loop Header: Depth=1
leal 1(%r15), %ecx
movl (%r14,%r15,4), %edx
movl 4(%r14,%r15,4), %r8d
leal 2(%r15), %r9d
movl 8(%r14,%r15,4), %r10d
leal 3(%r15), %r11d
movl 12(%r14,%r15,4), %ebx
subq $8, %rsp
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
pushq %rbx
pushq %r11
pushq %r10
callq printf
addq $32, %rsp
addq $4, %r15
cmpl %r13d, %r15d
jl .LBB4_16
.LBB4_17: # %._crit_edge103
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size _Z8main_subiiii, .Lfunc_end4-_Z8main_subiiii
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI4_0:
.quad .LBB4_5
.quad .LBB4_7
.quad .LBB4_9
.quad .LBB4_11
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
movl $1048576, %ebx # imm = 0x100000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $256, %r14d # imm = 0x100
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB5_4:
movl %ebx, %eax
cltd
idivl %r14d
movl %eax, %ebp
testl %edx, %edx
je .LBB5_6
# %bb.5:
incl %ebp
movl %ebp, %ebx
imull %r14d, %ebx
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.6, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
.LBB5_6:
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $1, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $2, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $3, %ecx
callq _Z8main_subiiii
movl %ebx, %edi
movl %r14d, %esi
movl %ebp, %edx
movl $4, %ecx
callq _Z8main_subiiii
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8subtractPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3modPiS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type _Z8subtractPiS_S_,@object # @_Z8subtractPiS_S_
.globl _Z8subtractPiS_S_
.p2align 3, 0x0
_Z8subtractPiS_S_:
.quad _Z23__device_stub__subtractPiS_S_
.size _Z8subtractPiS_S_, 8
.type _Z8multiplyPiS_S_,@object # @_Z8multiplyPiS_S_
.globl _Z8multiplyPiS_S_
.p2align 3, 0x0
_Z8multiplyPiS_S_:
.quad _Z23__device_stub__multiplyPiS_S_
.size _Z8multiplyPiS_S_, 8
.type _Z3modPiS_S_,@object # @_Z3modPiS_S_
.globl _Z3modPiS_S_
.p2align 3, 0x0
_Z3modPiS_S_:
.quad _Z18__device_stub__modPiS_S_
.size _Z3modPiS_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Index %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\t\tIndex %i:\t %i\n"
.size .L.str.4, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The total number of threads will be rounded up to %d\n"
.size .L.str.6, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8subtractPiS_S_"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8multiplyPiS_S_"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3modPiS_S_"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "///////////////////////OUTPUT MOD///////////////"
.size .Lstr, 49
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "///////////////////////OUTPUT MULTIPLY///////////////"
.size .Lstr.1, 54
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "///////////////////////OUTPUT SUBTRACT///////////////"
.size .Lstr.2, 54
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "///////////////////////OUTPUT ADD///////////////"
.size .Lstr.3, 49
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Warning: Total thread count is not evenly divisible by the block size"
.size .Lstr.4, 70
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym _Z23__device_stub__subtractPiS_S_
.addrsig_sym _Z23__device_stub__multiplyPiS_S_
.addrsig_sym _Z18__device_stub__modPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _Z8subtractPiS_S_
.addrsig_sym _Z8multiplyPiS_S_
.addrsig_sym _Z3modPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
cudaMalloc((void**)&d_m, mSize);
cudaMalloc((void**)&d_n, nSize);
cudaMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
cudaMemcpy(d_m, m, mSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, n, nSize, cudaMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
cudaThreadSynchronize();
cudaMemcpy(p, d_p, pSize, cudaMemcpyDeviceToHost);
if (cudaGetLastError() != cudaSuccess) {
printf("Error %d\n", cudaGetLastError());
exit(-1);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
cudaFree(d_n);
cudaFree(d_m);
cudaFree(d_p);
} | code for sm_80
Function : _Z20TiledMatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, -0xe, PT ; /* 0xfffffff20600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0420*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0520*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0530*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0540*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe40000000004 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0580*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
cudaMalloc((void**)&d_m, mSize);
cudaMalloc((void**)&d_n, nSize);
cudaMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
cudaMemcpy(d_m, m, mSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, n, nSize, cudaMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
cudaThreadSynchronize();
cudaMemcpy(p, d_p, pSize, cudaMemcpyDeviceToHost);
if (cudaGetLastError() != cudaSuccess) {
printf("Error %d\n", cudaGetLastError());
exit(-1);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
cudaFree(d_n);
cudaFree(d_m);
cudaFree(d_p);
} | .file "tmpxft_00103500_00000000-6_tiledMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11generateMatPfmm
.type _Z11generateMatPfmm, @function
_Z11generateMatPfmm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %r14
movq %rdx, %r12
leaq 0(,%rdx,4), %r15
movq %rdi, %rbp
movl $0, %r13d
jmp .L5
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq %r12, %rbx
jne .L6
.L7:
addq $1, %r13
addq %r15, %rbp
cmpq %r13, %r14
je .L3
.L5:
movl $0, %ebx
testq %r12, %r12
jne .L6
jmp .L7
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11generateMatPfmm, .-_Z11generateMatPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z8printMatPfmm
.type _Z8printMatPfmm, @function
_Z8printMatPfmm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
testq %rsi, %rsi
je .L16
movq %rdx, %r12
leaq 0(,%rdx,4), %r15
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
jmp .L17
.L18:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L18
.L19:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
addq %r15, %rbp
cmpq %r14, 8(%rsp)
je .L16
.L17:
movl $0, %ebx
testq %r12, %r12
jne .L18
jmp .L19
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8printMatPfmm, .-_Z8printMatPfmm
.globl _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20TiledMatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.type _Z20TiledMatrixMulKernelPfS_S_iii, @function
_Z20TiledMatrixMulKernelPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20TiledMatrixMulKernelPfS_S_iii, .-_Z20TiledMatrixMulKernelPfS_S_iii
.section .rodata.str1.1
.LC3:
.string "Error %d\n"
.LC5:
.string "The elapsed time is %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L38
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 44(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r13d
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
movl %r14d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r14d, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movslq %r15d, %rcx
movslq %ebp, %rsi
movq %rcx, 32(%rsp)
movq %rcx, %rdx
movq 8(%rsp), %rdi
call _Z11generateMatPfmm
movslq %r14d, %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z11generateMatPfmm
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 96(%rsp)
movl $16, 100(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC2(%rip), %xmm0
call ceil@PLT
movsd %xmm0, 32(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rax
movl %eax, 108(%rsp)
cvttsd2siq 32(%rsp), %rax
movl %eax, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 108(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
jmp .L33
.L40:
movl %r14d, %r9d
movl %r15d, %r8d
movl 44(%rsp), %ecx
movq 80(%rsp), %rdx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L34
.L41:
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z20TiledMatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20TiledMatrixMulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1068498944
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
cudaMalloc((void**)&d_m, mSize);
cudaMalloc((void**)&d_n, nSize);
cudaMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
cudaMemcpy(d_m, m, mSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, n, nSize, cudaMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
cudaThreadSynchronize();
cudaMemcpy(p, d_p, pSize, cudaMemcpyDeviceToHost);
if (cudaGetLastError() != cudaSuccess) {
printf("Error %d\n", cudaGetLastError());
exit(-1);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
cudaFree(d_n);
cudaFree(d_m);
cudaFree(d_p);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
hipMalloc((void**)&d_m, mSize);
hipMalloc((void**)&d_n, nSize);
hipMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
hipMemcpy(d_m, m, mSize, hipMemcpyHostToDevice);
hipMemcpy(d_n, n, nSize, hipMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
hipDeviceSynchronize();
hipMemcpy(p, d_p, pSize, hipMemcpyDeviceToHost);
if (hipGetLastError() != hipSuccess) {
printf("Error %d\n", hipGetLastError());
exit(-1);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
hipFree(d_n);
hipFree(d_m);
hipFree(d_p);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
hipMalloc((void**)&d_m, mSize);
hipMalloc((void**)&d_n, nSize);
hipMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
hipMemcpy(d_m, m, mSize, hipMemcpyHostToDevice);
hipMemcpy(d_n, n, nSize, hipMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
hipDeviceSynchronize();
hipMemcpy(p, d_p, pSize, hipMemcpyDeviceToHost);
if (hipGetLastError() != hipSuccess) {
printf("Error %d\n", hipGetLastError());
exit(-1);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
hipFree(d_n);
hipFree(d_m);
hipFree(d_p);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20TiledMatrixMulKernelPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 8
.type _Z20TiledMatrixMulKernelPfS_S_iii,@function
_Z20TiledMatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s10, v0
s_cmp_lt_i32 s9, -14
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v6, 6, v5
s_add_i32 s3, s9, -1
v_cmp_le_i32_e64 s12, s10, v0
s_ashr_i32 s11, s3, 31
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v7, 0x400, v2
s_lshr_b32 s11, s11, 28
v_add_nc_u32_e32 v8, v6, v2
v_mad_u64_u32 v[2:3], null, v4, s9, v[1:2]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v4
v_add_nc_u32_e32 v9, v7, v6
v_mov_b32_e32 v3, 0
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s9, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v8, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v5
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s9, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v7
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v6
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20TiledMatrixMulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20TiledMatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z20TiledMatrixMulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20TiledMatrixMulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20TiledMatrixMulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the M and N tiles required to compute the P element
for (int ph = 0; ph < (k - 1)/TILE_WIDTH + 1; ++ph) {
// Collaborative loading of M and N tiles into shared memory
if (Row < j && ph * TILE_WIDTH + tx < k) {
ds_M[ty][tx] = M[Row*k + ph*TILE_WIDTH + tx];
} else {
ds_M[ty][tx] = 0.0;
}
if (Col < l && ph * TILE_WIDTH + ty < k) {
ds_N[ty][tx] = N[(ph*TILE_WIDTH + ty)*l + Col];
} else {
ds_N[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_WIDTH; ++i) {
Pvalue += ds_M[ty][i] * ds_N[i][tx];
}
__syncthreads();
}
if (Row < j && Col < l) {
P[Row * l + Col] = Pvalue;
}
}
void generateMat(float *m, size_t height, size_t width){
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
m[i*width+j] = rand() % 100;
}
}
}
void printMat(float *m, size_t height, size_t width) {
int i, j;
for (i = 0; i < height; i++){
for (j = 0; j < width; j++) {
printf("%f ", m[i*width+j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char**argv){
int j,k,l;
if (argc >= 3) {
j = strtol(argv[1], NULL, 10);
k = strtol(argv[2], NULL, 10);
l = strtol(argv[3], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float * m, *n, *p;
float * d_m, *d_p, *d_n;
long mSize = j * k * sizeof(float);
long nSize = k * l * sizeof(float);
long pSize = j * l * sizeof(float);
hipMalloc((void**)&d_m, mSize);
hipMalloc((void**)&d_n, nSize);
hipMalloc((void**)&d_p, pSize);
m = (float *)malloc(mSize);
n = (float *)malloc(nSize);
p = (float *)malloc(pSize);
generateMat(m, j, k);
generateMat(n, k, l);
hipMemcpy(d_m, m, mSize, hipMemcpyHostToDevice);
hipMemcpy(d_n, n, nSize, hipMemcpyHostToDevice);
dim3 threadDims(TILE_WIDTH, TILE_WIDTH, 1);
dim3 blockDims(ceil(j * 1.0/ TILE_WIDTH), ceil(l * 1.0/TILE_WIDTH), 1);
TiledMatrixMulKernel<<<blockDims, threadDims>>>(d_m, d_n, d_p, j, k, l);
hipDeviceSynchronize();
hipMemcpy(p, d_p, pSize, hipMemcpyDeviceToHost);
if (hipGetLastError() != hipSuccess) {
printf("Error %d\n", hipGetLastError());
exit(-1);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The elapsed time is %f s\n", elapsedTime / 1000.0);
free(n); free(m); free(p);
hipFree(d_n);
hipFree(d_m);
hipFree(d_p);
} | .text
.file "tiledMatMul.hip"
.globl _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii # -- Begin function _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii,@function
_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii: # @_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z11generateMatPfmm # -- Begin function _Z11generateMatPfmm
.p2align 4, 0x90
.type _Z11generateMatPfmm,@function
_Z11generateMatPfmm: # @_Z11generateMatPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rdx,4), %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addq %r12, %r15
cmpq %r14, %r13
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_7: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11generateMatPfmm, .Lfunc_end1-_Z11generateMatPfmm
.cfi_endproc
# -- End function
.globl _Z8printMatPfmm # -- Begin function _Z8printMatPfmm
.p2align 4, 0x90
.type _Z8printMatPfmm,@function
_Z8printMatPfmm: # @_Z8printMatPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rdx,4), %r12
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq %r12, %r15
cmpq %r14, %r13
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testq %rbx, %rbx
je .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbp
cmpq %rbp, %rbx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_7: # %._crit_edge16
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z8printMatPfmm, .Lfunc_end2-_Z8printMatPfmm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.LCPI3_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jl .LBB3_17
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, 72(%rsp) # 8-byte Spill
shlq $32, %r14
movq %r14, %rbp
imulq %r15, %rbp
sarq $30, %rbp
movq %r15, %r13
shlq $32, %r13
movq %r13, (%rsp) # 8-byte Spill
imulq %r12, %r13
sarq $30, %r13
movq %r14, %rbx
movq %r12, 64(%rsp) # 8-byte Spill
imulq %r12, %rbx
sarq $30, %rbx
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbp, 104(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %r13, 112(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, 120(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 128(%rsp) # 8-byte Spill
movq %r15, 96(%rsp) # 8-byte Spill
movslq %r15d, %r12
testq %r14, %r14
je .LBB3_7
# %bb.2: # %.preheader.lr.ph.i
movslq 72(%rsp), %r14 # 4-byte Folded Reload
leaq (,%r12,4), %r13
xorl %ebx, %ebx
movq 88(%rsp), %r15 # 8-byte Reload
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge.i
# in Loop: Header=BB3_3 Depth=1
incq %rbx
addq %r13, %r15
cmpq %r14, %rbx
je .LBB3_7
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB3_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB3_3 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB3_5
jmp .LBB3_6
.LBB3_7: # %_Z11generateMatPfmm.exit
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB3_13
# %bb.8: # %.preheader.lr.ph.i49
movq 64(%rsp), %rax # 8-byte Reload
movq %rax, %rbp
shlq $32, %rbp
movslq %eax, %r14
leaq (,%r14,4), %rax
movq %rax, (%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq 80(%rsp), %r15 # 8-byte Reload
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # %._crit_edge.i57
# in Loop: Header=BB3_9 Depth=1
incq %rbx
addq (%rsp), %r15 # 8-byte Folded Reload
cmpq %r12, %rbx
je .LBB3_13
.LBB3_9: # %.preheader.i51
# =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
testq %rbp, %rbp
je .LBB3_12
# %bb.10: # %.lr.ph.i53
# in Loop: Header=BB3_9 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB3_11
jmp .LBB3_12
.LBB3_13: # %_Z11generateMatPfmm.exit60
movq 32(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq 104(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %r12 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rbx
movq 64(%rsp), %r13 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl %r12d, 60(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movl %r13d, 52(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 52(%rsp), %rax
movq %rax, 248(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 128(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_18
# %bb.16:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI3_1(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.LBB3_17:
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 320
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20TiledMatrixMulKernelPfS_S_iii,@object # @_Z20TiledMatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z20TiledMatrixMulKernelPfS_S_iii:
.quad _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.size _Z20TiledMatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error %d\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The elapsed time is %f s\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20TiledMatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20TiledMatrixMulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20TiledMatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, -0xe, PT ; /* 0xfffffff20600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0420*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0520*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0530*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0540*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe40000000004 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0580*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20TiledMatrixMulKernelPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 8
.type _Z20TiledMatrixMulKernelPfS_S_iii,@function
_Z20TiledMatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s10, v0
s_cmp_lt_i32 s9, -14
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v6, 6, v5
s_add_i32 s3, s9, -1
v_cmp_le_i32_e64 s12, s10, v0
s_ashr_i32 s11, s3, 31
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v7, 0x400, v2
s_lshr_b32 s11, s11, 28
v_add_nc_u32_e32 v8, v6, v2
v_mad_u64_u32 v[2:3], null, v4, s9, v[1:2]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v4
v_add_nc_u32_e32 v9, v7, v6
v_mov_b32_e32 v3, 0
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s9, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v8, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v5
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s9, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v7
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v6
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20TiledMatrixMulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20TiledMatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z20TiledMatrixMulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20TiledMatrixMulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20TiledMatrixMulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103500_00000000-6_tiledMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11generateMatPfmm
.type _Z11generateMatPfmm, @function
_Z11generateMatPfmm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %r14
movq %rdx, %r12
leaq 0(,%rdx,4), %r15
movq %rdi, %rbp
movl $0, %r13d
jmp .L5
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq %r12, %rbx
jne .L6
.L7:
addq $1, %r13
addq %r15, %rbp
cmpq %r13, %r14
je .L3
.L5:
movl $0, %ebx
testq %r12, %r12
jne .L6
jmp .L7
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11generateMatPfmm, .-_Z11generateMatPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z8printMatPfmm
.type _Z8printMatPfmm, @function
_Z8printMatPfmm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
testq %rsi, %rsi
je .L16
movq %rdx, %r12
leaq 0(,%rdx,4), %r15
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
jmp .L17
.L18:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L18
.L19:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
addq %r15, %rbp
cmpq %r14, 8(%rsp)
je .L16
.L17:
movl $0, %ebx
testq %r12, %r12
jne .L18
jmp .L19
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8printMatPfmm, .-_Z8printMatPfmm
.globl _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20TiledMatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.type _Z20TiledMatrixMulKernelPfS_S_iii, @function
_Z20TiledMatrixMulKernelPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20TiledMatrixMulKernelPfS_S_iii, .-_Z20TiledMatrixMulKernelPfS_S_iii
.section .rodata.str1.1
.LC3:
.string "Error %d\n"
.LC5:
.string "The elapsed time is %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L38
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 44(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r13d
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
movl %r14d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r14d, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movslq %r15d, %rcx
movslq %ebp, %rsi
movq %rcx, 32(%rsp)
movq %rcx, %rdx
movq 8(%rsp), %rdi
call _Z11generateMatPfmm
movslq %r14d, %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z11generateMatPfmm
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 96(%rsp)
movl $16, 100(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC2(%rip), %xmm0
call ceil@PLT
movsd %xmm0, 32(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rax
movl %eax, 108(%rsp)
cvttsd2siq 32(%rsp), %rax
movl %eax, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 108(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
jmp .L33
.L40:
movl %r14d, %r9d
movl %r15d, %r8d
movl 44(%rsp), %ecx
movq 80(%rsp), %rdx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z47__device_stub__Z20TiledMatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L34
.L41:
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z20TiledMatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20TiledMatrixMulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1068498944
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tiledMatMul.hip"
.globl _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii # -- Begin function _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii,@function
_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii: # @_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z11generateMatPfmm # -- Begin function _Z11generateMatPfmm
.p2align 4, 0x90
.type _Z11generateMatPfmm,@function
_Z11generateMatPfmm: # @_Z11generateMatPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rdx,4), %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addq %r12, %r15
cmpq %r14, %r13
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_7: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11generateMatPfmm, .Lfunc_end1-_Z11generateMatPfmm
.cfi_endproc
# -- End function
.globl _Z8printMatPfmm # -- Begin function _Z8printMatPfmm
.p2align 4, 0x90
.type _Z8printMatPfmm,@function
_Z8printMatPfmm: # @_Z8printMatPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rdx,4), %r12
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq %r12, %r15
cmpq %r14, %r13
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testq %rbx, %rbx
je .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbp
cmpq %rbp, %rbx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_7: # %._crit_edge16
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z8printMatPfmm, .Lfunc_end2-_Z8printMatPfmm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.LCPI3_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jl .LBB3_17
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, 72(%rsp) # 8-byte Spill
shlq $32, %r14
movq %r14, %rbp
imulq %r15, %rbp
sarq $30, %rbp
movq %r15, %r13
shlq $32, %r13
movq %r13, (%rsp) # 8-byte Spill
imulq %r12, %r13
sarq $30, %r13
movq %r14, %rbx
movq %r12, 64(%rsp) # 8-byte Spill
imulq %r12, %rbx
sarq $30, %rbx
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbp, 104(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %r13, 112(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, 120(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 128(%rsp) # 8-byte Spill
movq %r15, 96(%rsp) # 8-byte Spill
movslq %r15d, %r12
testq %r14, %r14
je .LBB3_7
# %bb.2: # %.preheader.lr.ph.i
movslq 72(%rsp), %r14 # 4-byte Folded Reload
leaq (,%r12,4), %r13
xorl %ebx, %ebx
movq 88(%rsp), %r15 # 8-byte Reload
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge.i
# in Loop: Header=BB3_3 Depth=1
incq %rbx
addq %r13, %r15
cmpq %r14, %rbx
je .LBB3_7
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB3_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB3_3 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB3_5
jmp .LBB3_6
.LBB3_7: # %_Z11generateMatPfmm.exit
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB3_13
# %bb.8: # %.preheader.lr.ph.i49
movq 64(%rsp), %rax # 8-byte Reload
movq %rax, %rbp
shlq $32, %rbp
movslq %eax, %r14
leaq (,%r14,4), %rax
movq %rax, (%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq 80(%rsp), %r15 # 8-byte Reload
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # %._crit_edge.i57
# in Loop: Header=BB3_9 Depth=1
incq %rbx
addq (%rsp), %r15 # 8-byte Folded Reload
cmpq %r12, %rbx
je .LBB3_13
.LBB3_9: # %.preheader.i51
# =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
testq %rbp, %rbp
je .LBB3_12
# %bb.10: # %.lr.ph.i53
# in Loop: Header=BB3_9 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB3_11
jmp .LBB3_12
.LBB3_13: # %_Z11generateMatPfmm.exit60
movq 32(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq 104(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %r12 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rbx
movq 64(%rsp), %r13 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl %r12d, 60(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movl %r13d, 52(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 52(%rsp), %rax
movq %rax, 248(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 128(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_18
# %bb.16:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI3_1(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.LBB3_17:
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 320
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20TiledMatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20TiledMatrixMulKernelPfS_S_iii,@object # @_Z20TiledMatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z20TiledMatrixMulKernelPfS_S_iii:
.quad _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.size _Z20TiledMatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error %d\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The elapsed time is %f s\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20TiledMatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20TiledMatrixMulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 94;
const int ASCII_OFFSET = 33;
const size_t PWD_TRY_ARR_MEM_SIZE = (sizeof(char) * PWD_LENGTH) * KERNEL_SIZE;
const size_t PWD_HASH_ARR_MEM_SIZE = (sizeof(char) * HASH_LENGTH) * KERNEL_SIZE;
const size_t COMP_ARR_MEM_SIZE = (sizeof(int) * KERNEL_SIZE);
// Application variables
std::string pwdSalt = "";
std::string checkFor = "";
std::string testPwdStr = "";
std::string testHash = "";
bool passwordFound = false;
std::string resultPassword = "";
unsigned long maxPwdAttempts;
int kernelPasses = 0;
// Timing variables
double totalRunTime = 0;
/**
* Caculates the maximum number of attempts based on password length
*/
__host__
void calcMaxAttempts() {
for (int i = 1; i <= PWD_LENGTH; i++) {
maxPwdAttempts += pow(CHARACTER_SET, i);
}
maxPwdAttempts += KERNEL_SIZE - 1;
}
/**
* Take user input and parse into salt and hash
*/
__host__
void parseInputHash(std::string arg) {
pwdSalt = arg.substr(0,12);
checkFor = arg.substr(12,HASH_LENGTH);
std::cout << "User Entered the Following Password Hash Information...\n";
std::cout << "Salt: " << pwdSalt << "\n";
std::cout << "Hash: " << checkFor << "\n";
}
/**
* Create hash from brute force password string
*/
__host__
std::string createHash(std::string password) {
// Create password hash from password try and salt
testHash = crypt((char *) password.c_str(), (char *) pwdSalt.c_str());
return testHash.substr(12,HASH_LENGTH);
}
/**
* Helper function to copy the individual hash to the hash array
*/
__host__
void copyHashToArr(int arrIndx, std::string hash, char *charArr) {
// Calculate array offset
int offset = arrIndx * HASH_LENGTH;
// Loop through input hash to insert into hash array
for (int i = 0; i < HASH_LENGTH; i++) {
charArr[offset + i] = hash[i];
}
}
/**
* Helper function to pull a password out of password character array
*/
__host__
std::string getPwdTry(int arrIndx, char *pwdCharArr) {
// Calculate array offset
int offset = arrIndx * PWD_LENGTH;
// temp string for password
std::string tmpPwd = "";
for (int i = 0; i < PWD_LENGTH; i++) {
// Skip blank characters
if (pwdCharArr[offset + i] != ' ') {
tmpPwd += pwdCharArr[offset + i];
}
}
return tmpPwd;
}
/**
* Debug Helper Function to print character array entries
*/
__host__
void printArr(int length, char *charArr) {
// Loop through character array
for (int i = 0; i < (KERNEL_SIZE * length); i++) {
if ((i == 0) || (i % length) != 0) {
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
} else {
std::cout << ", ";
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
}
}
std::cout << std::endl;
}
/**
* Create brute force password attemps
*/
__global__
void kernel_createPwdTry(int numPass, char *tryArr) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Create unique guess number based on thread and number of times kernel has been run
int guess = (numPass * KERNEL_SIZE) + curThread;
// Set fourth letter of four letter password
tryArr[(curThread * PWD_LENGTH) + 3] = (guess % CHARACTER_SET) + ASCII_OFFSET;
// Reduce guess number
guess = guess / CHARACTER_SET;
// If necessary, set third letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 2] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 2] = 32; // Space
}
// If necessary, set second letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 1] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 1] = 32; // Space
}
// If necessary, set first letter of four and reduce guess number
if (guess > 0) {
tryArr[curThread * PWD_LENGTH] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[curThread * PWD_LENGTH] = 32; // Space
}
}
/**
* Kernel to check brute force password hash with the one application is looking for
*/
__global__
void kernel_checkHash(char *lookingFor, char *hashArr, int *compares) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Get array offset
int offset = (curThread * HASH_LENGTH);
// Flag to indicate match
int match = 1;
for (int i = 0; i < HASH_LENGTH; i++) {
//printf("hashArr idx %d = %c --- lookingFor idx %d = %c Match = %d\n",
// i, hashArr[offset + i], i, lookingFor[i], match);
if (hashArr[offset + i] != lookingFor[i]) {
//printf("NO MATCH FOR HASH - %d\n", curThread);
match = 0;
break;
}
}
compares[curThread] = match;
//if (match == 0) {
//printf("!!! MATCH !!!\n");
// compares[curThread] = 1;
//}
}
/**
* Main sub routine which runs cracking loop
*/
void main_sub0() {
// Time variables
clock_t start;
clock_t stop;
double elapsedTime;
// Declare host variables
char *h_pwdTryArr;
char *h_pwdHashArr;
char *h_checkingFor;
int *h_compareArr;
// Declare device variables
char *d_pwdTryArr;
char *d_pwdHashArr;
char *d_checkingFor;
int *d_compareArr;
// Allocate Host memory
h_pwdTryArr = (char *)malloc(PWD_TRY_ARR_MEM_SIZE);
h_pwdHashArr = (char *)malloc(PWD_HASH_ARR_MEM_SIZE);
h_checkingFor = (char *)malloc(HASH_LENGTH * sizeof(char));
h_compareArr = (int *)malloc(COMP_ARR_MEM_SIZE);
// Allocate GPU memory
cudaMalloc((void **) &d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE);
cudaMalloc((void **) &d_pwdHashArr, PWD_HASH_ARR_MEM_SIZE);
cudaMalloc((void **) &d_checkingFor, (HASH_LENGTH * sizeof(char)));
cudaMalloc((void **) &d_compareArr, COMP_ARR_MEM_SIZE);
strcpy(h_checkingFor, checkFor.c_str());
// Fill array
//for (int i = 0; i < (KERNEL_SIZE * PWD_LENGTH); i++) {
// h_pwdTryArr[i] = 'Z';
//}
// DEBUG PRINT ORIGINAL PASSWORDS
//std::cout << "PWDTRYARR BEFORE KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Copy host to device
cudaMemcpy(d_pwdTryArr, h_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
while ((!passwordFound) && ((kernelPasses * KERNEL_SIZE) < maxPwdAttempts)) {
printf("Running round %'d of %'d password attempts\n", (kernelPasses + 1), KERNEL_SIZE);
//std::cout << "Running round " << (kernelPasses + 1) << " of ";
//std::cout << KERNEL_SIZE << " password attempts\n";
// Start clock for kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Create Brute Force Passwords... ";
// Run create password kernel
kernel_createPwdTry<<<NUM_BLOCKS,NUM_THREADS>>>(kernelPasses, d_pwdTryArr);
// Stop clock for kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
cudaMemcpy(h_pwdTryArr, d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, cudaMemcpyDeviceToHost);
// DEBUG PRINT CREATED PASSWORDS
//std::cout << "PWDTRYARR AFTER KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Start clock for host hash creation timing
start = clock();
std::cout << "** Running Host Method to Create Hashes... ";
// Iterate through passowrd try array
for (int i = 0; i < (KERNEL_SIZE); i++) {
// Reset string
testPwdStr = "";
testPwdStr = getPwdTry(i, h_pwdTryArr);
/**
for (int j = 0; j < PWD_LENGTH; j++) {
char c = h_pwdTryArr[(i * PWD_LENGTH) + j];
if (c != ' ') {
testPwdStr += c;
}
}
**/
// Print Debug Logic
//std::cout << testPwdStr << " --- ";
//std::cout << createHash(testPwdStr) << std::endl;
copyHashToArr(i, createHash(testPwdStr), h_pwdHashArr);
// Create hash of password and store in hash array
// strcpy(h_pwdHashArr[i], createHash(testPwdStr).c_str());
}
// Stop clock for host hash creation timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// DEBUG PRINT CREATED HASHES
//std::cout << "PWDHASHARR\n";
//printArr(HASH_LENGTH, h_pwdHashArr);
// Copy host to device
cudaMemcpy(d_checkingFor, h_checkingFor, (HASH_LENGTH * sizeof(char)), cudaMemcpyHostToDevice);
cudaMemcpy(d_pwdHashArr, h_pwdHashArr, PWD_HASH_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_compareArr, h_compareArr, COMP_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
// DEBUG PRINT LOOKINGFOR HASH
//std::cout << "LOOKINGFOR\n";
//for (int i = 0; i < HASH_LENGTH; i++) {
// std::cout << h_checkingFor[i];
//}
//std::cout << std::endl;
// Start clock for hash comparison kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Check Password Hashes... ";
// Run check hash kernel
kernel_checkHash<<<NUM_BLOCKS, NUM_THREADS>>>(d_checkingFor, d_pwdHashArr, d_compareArr);
// Stop clock for hash comparison kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
cudaMemcpy(h_compareArr, d_compareArr, COMP_ARR_MEM_SIZE, cudaMemcpyDeviceToHost);
// DEBUG PRINT COMPAREARR
//std::cout << "COMPAREARR --- ";
//for (int i = 0; i < KERNEL_SIZE; i++) {
// std::cout << h_compareArr[i] << ", ";
//}
//std::cout << std::endl;
// Start clock for host checking for match timing
start = clock();
std::cout << "** Checking on Host for hash match... ";
// Check if there is a match
for (int i = 0; i < KERNEL_SIZE; i++) {
if (h_compareArr[i] == 1) {
passwordFound = true;
resultPassword = getPwdTry(i, h_pwdTryArr);
//std::cout << "MATCH FOUND: ";
//std::cout << getPwdTry(i, h_pwdTryArr) << "\n";
}
}
// Stop clock for host checking for match timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Incrememnt kernel pass
kernelPasses++;
}
free(h_pwdTryArr);
free(h_pwdHashArr);
free(h_checkingFor);
free(h_compareArr);
cudaFree(d_pwdTryArr);
cudaFree(d_pwdHashArr);
cudaFree(d_checkingFor);
cudaFree(d_compareArr);
}
/**
* Main application
*/
int main(int argc, char *argv[]) {
setlocale(LC_NUMERIC, "");
// Variable for command line argument
std::string argument = "";
// Make sure hash has been passed to program via command line
if (argc < 2) {
std::cout << "!!! ERROR !!! Please enter hash as argument !!!\n";
return EXIT_FAILURE;
} else {
argument = argv[1];
if (argument.length() != 77) {
std::cout << "!!! ERROR !!! Hash must be 77 characters long !!!\n";
return EXIT_FAILURE;
}
}
// Parse argument into salt and hash
parseInputHash(argument);
calcMaxAttempts();
std::cout << "Attempting to crack password...\n";
main_sub0();
if (passwordFound) {
std::cout << "Password found --- " << resultPassword << "\n";
} else {
std::cout << "Password not found\n";
}
// Display total number of attempts
printf("%'d attempts processed\n", kernelPasses * KERNEL_SIZE);
printf("%'.5f total processing time\n", totalRunTime);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z16kernel_checkHashPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x610 ; /* 0x000005e000007945 */
/* 0x000fe20003800000 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0202 */
/*0070*/ IMAD R5, R7, 0x40, R0 ; /* 0x0000004007057824 */
/* 0x000fe200078e0200 */
/*0080*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0090*/ IADD3 R4, P0, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x040fe40007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f0eff */
/*00b0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc600000f0eff */
/*00c0*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0100*/ @P0 BRA 0x600 ; /* 0x000004f000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea8000c1e1100 */
/*0120*/ LDG.E.U8 R9, [R4.64+0x1] ; /* 0x0000010404097981 */
/* 0x000ea4000c1e1100 */
/*0130*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0150*/ @P0 BRA 0x600 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea8000c1e1100 */
/*0170*/ LDG.E.U8 R9, [R4.64+0x2] ; /* 0x0000020404097981 */
/* 0x000ea4000c1e1100 */
/*0180*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01a0*/ @P0 BRA 0x600 ; /* 0x0000045000000947 */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E.U8 R6, [R2.64+0x3] ; /* 0x0000030402067981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ LDG.E.U8 R9, [R4.64+0x3] ; /* 0x0000030404097981 */
/* 0x000ea4000c1e1100 */
/*01d0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*01e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01f0*/ @P0 BRA 0x600 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0200*/ LDG.E.U8 R6, [R2.64+0x4] ; /* 0x0000040402067981 */
/* 0x000ea8000c1e1100 */
/*0210*/ LDG.E.U8 R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ea4000c1e1100 */
/*0220*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0240*/ @P0 BRA 0x600 ; /* 0x000003b000000947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E.U8 R6, [R2.64+0x5] ; /* 0x0000050402067981 */
/* 0x000ea8000c1e1100 */
/*0260*/ LDG.E.U8 R9, [R4.64+0x5] ; /* 0x0000050404097981 */
/* 0x000ea4000c1e1100 */
/*0270*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0290*/ @P0 BRA 0x600 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E.U8 R6, [R2.64+0x6] ; /* 0x0000060402067981 */
/* 0x000ea8000c1e1100 */
/*02b0*/ LDG.E.U8 R9, [R4.64+0x6] ; /* 0x0000060404097981 */
/* 0x000ea4000c1e1100 */
/*02c0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*02e0*/ @P0 BRA 0x600 ; /* 0x0000031000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E.U8 R6, [R2.64+0x7] ; /* 0x0000070402067981 */
/* 0x000ea8000c1e1100 */
/*0300*/ LDG.E.U8 R9, [R4.64+0x7] ; /* 0x0000070404097981 */
/* 0x000ea4000c1e1100 */
/*0310*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0320*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fd800000001ff */
/*0330*/ @P0 BRA 0x600 ; /* 0x000002c000000947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.U8 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ea8000c1e1100 */
/*0350*/ LDG.E.U8 R9, [R4.64+0x8] ; /* 0x0000080404097981 */
/* 0x000ea4000c1e1100 */
/*0360*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0380*/ @P0 BRA 0x600 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E.U8 R6, [R2.64+0x9] ; /* 0x0000090402067981 */
/* 0x000ea8000c1e1100 */
/*03a0*/ LDG.E.U8 R9, [R4.64+0x9] ; /* 0x0000090404097981 */
/* 0x000ea4000c1e1100 */
/*03b0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*03c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*03d0*/ @P0 BRA 0x600 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.U8 R6, [R2.64+0xa] ; /* 0x00000a0402067981 */
/* 0x000ea8000c1e1100 */
/*03f0*/ LDG.E.U8 R9, [R4.64+0xa] ; /* 0x00000a0404097981 */
/* 0x000ea4000c1e1100 */
/*0400*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0420*/ @P0 BRA 0x600 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R6, [R2.64+0xb] ; /* 0x00000b0402067981 */
/* 0x000ea8000c1e1100 */
/*0440*/ LDG.E.U8 R9, [R4.64+0xb] ; /* 0x00000b0404097981 */
/* 0x000ea4000c1e1100 */
/*0450*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0470*/ @P0 BRA 0x600 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ea8000c1e1100 */
/*0490*/ LDG.E.U8 R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x000ea4000c1e1100 */
/*04a0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*04c0*/ @P0 BRA 0x600 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E.U8 R6, [R2.64+0xd] ; /* 0x00000d0402067981 */
/* 0x000ea8000c1e1100 */
/*04e0*/ LDG.E.U8 R9, [R4.64+0xd] ; /* 0x00000d0404097981 */
/* 0x000ea4000c1e1100 */
/*04f0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe40003f05270 */
/*0500*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fd60000000f00 */
/*0510*/ @P0 BRA 0x600 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E.U8 R6, [R2.64+0xe] ; /* 0x00000e0402067981 */
/* 0x000ea8000c1e1100 */
/*0530*/ LDG.E.U8 R9, [R4.64+0xe] ; /* 0x00000e0404097981 */
/* 0x000ea4000c1e1100 */
/*0540*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0560*/ @P0 BRA 0x600 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E.U8 R2, [R2.64+0xf] ; /* 0x00000f0402027981 */
/* 0x000ea8000c1e1100 */
/*0580*/ LDG.E.U8 R5, [R4.64+0xf] ; /* 0x00000f0404057981 */
/* 0x000ea2000c1e1100 */
/*0590*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*05a0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*05b0*/ @P0 BRA 0x600 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x40, PT ; /* 0x000000400000780c */
/* 0x000fda0003f06070 */
/*05e0*/ @!P0 BRA 0x70 ; /* 0xfffffa8000008947 */
/* 0x000fea000383ffff */
/*05f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe400078e00ff */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0202 */
/*0630*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19kernel_createPwdTryiPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R10, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff0a7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x20 ; /* 0x00000020ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff037624 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD R3, R3, 0x4000, R0 ; /* 0x0000400003037824 */
/* 0x000fe400078e0200 */
/*00a0*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.HI R2, R3.reuse, -0x51b3bea3, R2 ; /* 0xae4c415d03027827 */
/* 0x040fe200078e0202 */
/*00c0*/ ISETP.GT.AND P0, PT, R3, 0x5d, PT ; /* 0x0000005d0300780c */
/* 0x000fc80003f04270 */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fc80000011602 */
/*00e0*/ LEA.HI.SX32 R7, R2, R5, 0x1a ; /* 0x0000000502077211 */
/* 0x000fca00078fd2ff */
/*00f0*/ @P0 MOV R5, R7 ; /* 0x0000000700050202 */
/* 0x000fe20000000f00 */
/*0100*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R6, R7.reuse, -0x5e, R3 ; /* 0xffffffa207067824 */
/* 0x040fe400078e0203 */
/*0120*/ @P0 IMAD.HI R2, R7, -0x51b3bea3, R4 ; /* 0xae4c415d07020827 */
/* 0x000fca00078e0204 */
/*0130*/ @P0 SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff050819 */
/* 0x000fc80000011602 */
/*0140*/ @P0 LEA.HI R2, R2, R5, RZ, 0x1a ; /* 0x0000000502020211 */
/* 0x000fe200078fd0ff */
/*0150*/ @P0 IMAD.WIDE.U32 R4, R3, 0x76abbf91, RZ ; /* 0x76abbf9103040825 */
/* 0x000fc800078e00ff */
/*0160*/ @P0 IMAD R8, R2, -0x5e, R7 ; /* 0xffffffa202080824 */
/* 0x000fe200078e0207 */
/*0170*/ @P0 SHF.R.U32.HI R7, RZ, 0xc, R5 ; /* 0x0000000cff070819 */
/* 0x000fc80000011605 */
/*0180*/ ISETP.GT.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f24270 */
/*0190*/ @P1 IMAD.WIDE.U32 R2, R7, -0x51b3bea3, RZ ; /* 0xae4c415d07021825 */
/* 0x000fca00078e00ff */
/*01a0*/ @P1 SHF.R.U32.HI R2, RZ, 0x6, R3 ; /* 0x00000006ff021819 */
/* 0x000fca0000011603 */
/*01b0*/ @P1 IMAD R9, R2, -0x5e, R7 ; /* 0xffffffa202091824 */
/* 0x000fe400078e0207 */
/*01c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0002 */
/*01d0*/ IADD3 R2, P3, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f7e0ff */
/*01e0*/ @P1 IADD3 R9, R9, 0x21, RZ ; /* 0x0000002109091810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f46270 */
/*0200*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P3 ; /* 0x00005b0000037a11 */
/* 0x000fd600018f0eff */
/*0210*/ @P2 IMAD.WIDE.U32 R4, R7, -0x51b3bea3, RZ ; /* 0xae4c415d07042825 */
/* 0x000fca00078e00ff */
/*0220*/ @P2 SHF.R.U32.HI R0, RZ, 0x6, R5 ; /* 0x00000006ff002819 */
/* 0x000fe40000011605 */
/*0230*/ IADD3 R5, R6, 0x21, RZ ; /* 0x0000002106057810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P0 PRMT R4, R10, 0x7610, R4 ; /* 0x000076100a048816 */
/* 0x000fe20000000004 */
/*0250*/ @P2 IMAD R0, R0, -0x5e, R7 ; /* 0xffffffa200002824 */
/* 0x000fe200078e0207 */
/*0260*/ @!P1 PRMT R6, R10, 0x7610, R6 ; /* 0x000076100a069816 */
/* 0x000fe20000000006 */
/*0270*/ STG.E.U8 [R2.64+0x3], R5 ; /* 0x0000030502007986 */
/* 0x000fe2000c101104 */
/*0280*/ @P0 IADD3 R7, R8, 0x21, RZ ; /* 0x0000002108070810 */
/* 0x000fe40007ffe0ff */
/*0290*/ @P2 IADD3 R11, R0, 0x21, RZ ; /* 0x00000021000b2810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ @!P0 STG.E.U8 [R2.64+0x2], R4 ; /* 0x0000020402008986 */
/* 0x000fe8000c101104 */
/*02b0*/ @!P1 STG.E.U8 [R2.64+0x1], R6 ; /* 0x0000010602009986 */
/* 0x000fe8000c101104 */
/*02c0*/ @P0 STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702000986 */
/* 0x000fe8000c101104 */
/*02d0*/ @P1 STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902001986 */
/* 0x000fe8000c101104 */
/*02e0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101104 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 94;
const int ASCII_OFFSET = 33;
const size_t PWD_TRY_ARR_MEM_SIZE = (sizeof(char) * PWD_LENGTH) * KERNEL_SIZE;
const size_t PWD_HASH_ARR_MEM_SIZE = (sizeof(char) * HASH_LENGTH) * KERNEL_SIZE;
const size_t COMP_ARR_MEM_SIZE = (sizeof(int) * KERNEL_SIZE);
// Application variables
std::string pwdSalt = "";
std::string checkFor = "";
std::string testPwdStr = "";
std::string testHash = "";
bool passwordFound = false;
std::string resultPassword = "";
unsigned long maxPwdAttempts;
int kernelPasses = 0;
// Timing variables
double totalRunTime = 0;
/**
* Caculates the maximum number of attempts based on password length
*/
__host__
void calcMaxAttempts() {
for (int i = 1; i <= PWD_LENGTH; i++) {
maxPwdAttempts += pow(CHARACTER_SET, i);
}
maxPwdAttempts += KERNEL_SIZE - 1;
}
/**
* Take user input and parse into salt and hash
*/
__host__
void parseInputHash(std::string arg) {
pwdSalt = arg.substr(0,12);
checkFor = arg.substr(12,HASH_LENGTH);
std::cout << "User Entered the Following Password Hash Information...\n";
std::cout << "Salt: " << pwdSalt << "\n";
std::cout << "Hash: " << checkFor << "\n";
}
/**
* Create hash from brute force password string
*/
__host__
std::string createHash(std::string password) {
// Create password hash from password try and salt
testHash = crypt((char *) password.c_str(), (char *) pwdSalt.c_str());
return testHash.substr(12,HASH_LENGTH);
}
/**
* Helper function to copy the individual hash to the hash array
*/
__host__
void copyHashToArr(int arrIndx, std::string hash, char *charArr) {
// Calculate array offset
int offset = arrIndx * HASH_LENGTH;
// Loop through input hash to insert into hash array
for (int i = 0; i < HASH_LENGTH; i++) {
charArr[offset + i] = hash[i];
}
}
/**
* Helper function to pull a password out of password character array
*/
__host__
std::string getPwdTry(int arrIndx, char *pwdCharArr) {
// Calculate array offset
int offset = arrIndx * PWD_LENGTH;
// temp string for password
std::string tmpPwd = "";
for (int i = 0; i < PWD_LENGTH; i++) {
// Skip blank characters
if (pwdCharArr[offset + i] != ' ') {
tmpPwd += pwdCharArr[offset + i];
}
}
return tmpPwd;
}
/**
* Debug Helper Function to print character array entries
*/
__host__
void printArr(int length, char *charArr) {
// Loop through character array
for (int i = 0; i < (KERNEL_SIZE * length); i++) {
if ((i == 0) || (i % length) != 0) {
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
} else {
std::cout << ", ";
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
}
}
std::cout << std::endl;
}
/**
* Create brute force password attemps
*/
__global__
void kernel_createPwdTry(int numPass, char *tryArr) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Create unique guess number based on thread and number of times kernel has been run
int guess = (numPass * KERNEL_SIZE) + curThread;
// Set fourth letter of four letter password
tryArr[(curThread * PWD_LENGTH) + 3] = (guess % CHARACTER_SET) + ASCII_OFFSET;
// Reduce guess number
guess = guess / CHARACTER_SET;
// If necessary, set third letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 2] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 2] = 32; // Space
}
// If necessary, set second letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 1] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 1] = 32; // Space
}
// If necessary, set first letter of four and reduce guess number
if (guess > 0) {
tryArr[curThread * PWD_LENGTH] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[curThread * PWD_LENGTH] = 32; // Space
}
}
/**
* Kernel to check brute force password hash with the one application is looking for
*/
__global__
void kernel_checkHash(char *lookingFor, char *hashArr, int *compares) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Get array offset
int offset = (curThread * HASH_LENGTH);
// Flag to indicate match
int match = 1;
for (int i = 0; i < HASH_LENGTH; i++) {
//printf("hashArr idx %d = %c --- lookingFor idx %d = %c Match = %d\n",
// i, hashArr[offset + i], i, lookingFor[i], match);
if (hashArr[offset + i] != lookingFor[i]) {
//printf("NO MATCH FOR HASH - %d\n", curThread);
match = 0;
break;
}
}
compares[curThread] = match;
//if (match == 0) {
//printf("!!! MATCH !!!\n");
// compares[curThread] = 1;
//}
}
/**
* Main sub routine which runs cracking loop
*/
void main_sub0() {
// Time variables
clock_t start;
clock_t stop;
double elapsedTime;
// Declare host variables
char *h_pwdTryArr;
char *h_pwdHashArr;
char *h_checkingFor;
int *h_compareArr;
// Declare device variables
char *d_pwdTryArr;
char *d_pwdHashArr;
char *d_checkingFor;
int *d_compareArr;
// Allocate Host memory
h_pwdTryArr = (char *)malloc(PWD_TRY_ARR_MEM_SIZE);
h_pwdHashArr = (char *)malloc(PWD_HASH_ARR_MEM_SIZE);
h_checkingFor = (char *)malloc(HASH_LENGTH * sizeof(char));
h_compareArr = (int *)malloc(COMP_ARR_MEM_SIZE);
// Allocate GPU memory
cudaMalloc((void **) &d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE);
cudaMalloc((void **) &d_pwdHashArr, PWD_HASH_ARR_MEM_SIZE);
cudaMalloc((void **) &d_checkingFor, (HASH_LENGTH * sizeof(char)));
cudaMalloc((void **) &d_compareArr, COMP_ARR_MEM_SIZE);
strcpy(h_checkingFor, checkFor.c_str());
// Fill array
//for (int i = 0; i < (KERNEL_SIZE * PWD_LENGTH); i++) {
// h_pwdTryArr[i] = 'Z';
//}
// DEBUG PRINT ORIGINAL PASSWORDS
//std::cout << "PWDTRYARR BEFORE KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Copy host to device
cudaMemcpy(d_pwdTryArr, h_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
while ((!passwordFound) && ((kernelPasses * KERNEL_SIZE) < maxPwdAttempts)) {
printf("Running round %'d of %'d password attempts\n", (kernelPasses + 1), KERNEL_SIZE);
//std::cout << "Running round " << (kernelPasses + 1) << " of ";
//std::cout << KERNEL_SIZE << " password attempts\n";
// Start clock for kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Create Brute Force Passwords... ";
// Run create password kernel
kernel_createPwdTry<<<NUM_BLOCKS,NUM_THREADS>>>(kernelPasses, d_pwdTryArr);
// Stop clock for kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
cudaMemcpy(h_pwdTryArr, d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, cudaMemcpyDeviceToHost);
// DEBUG PRINT CREATED PASSWORDS
//std::cout << "PWDTRYARR AFTER KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Start clock for host hash creation timing
start = clock();
std::cout << "** Running Host Method to Create Hashes... ";
// Iterate through passowrd try array
for (int i = 0; i < (KERNEL_SIZE); i++) {
// Reset string
testPwdStr = "";
testPwdStr = getPwdTry(i, h_pwdTryArr);
/**
for (int j = 0; j < PWD_LENGTH; j++) {
char c = h_pwdTryArr[(i * PWD_LENGTH) + j];
if (c != ' ') {
testPwdStr += c;
}
}
**/
// Print Debug Logic
//std::cout << testPwdStr << " --- ";
//std::cout << createHash(testPwdStr) << std::endl;
copyHashToArr(i, createHash(testPwdStr), h_pwdHashArr);
// Create hash of password and store in hash array
// strcpy(h_pwdHashArr[i], createHash(testPwdStr).c_str());
}
// Stop clock for host hash creation timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// DEBUG PRINT CREATED HASHES
//std::cout << "PWDHASHARR\n";
//printArr(HASH_LENGTH, h_pwdHashArr);
// Copy host to device
cudaMemcpy(d_checkingFor, h_checkingFor, (HASH_LENGTH * sizeof(char)), cudaMemcpyHostToDevice);
cudaMemcpy(d_pwdHashArr, h_pwdHashArr, PWD_HASH_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_compareArr, h_compareArr, COMP_ARR_MEM_SIZE, cudaMemcpyHostToDevice);
// DEBUG PRINT LOOKINGFOR HASH
//std::cout << "LOOKINGFOR\n";
//for (int i = 0; i < HASH_LENGTH; i++) {
// std::cout << h_checkingFor[i];
//}
//std::cout << std::endl;
// Start clock for hash comparison kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Check Password Hashes... ";
// Run check hash kernel
kernel_checkHash<<<NUM_BLOCKS, NUM_THREADS>>>(d_checkingFor, d_pwdHashArr, d_compareArr);
// Stop clock for hash comparison kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
cudaMemcpy(h_compareArr, d_compareArr, COMP_ARR_MEM_SIZE, cudaMemcpyDeviceToHost);
// DEBUG PRINT COMPAREARR
//std::cout << "COMPAREARR --- ";
//for (int i = 0; i < KERNEL_SIZE; i++) {
// std::cout << h_compareArr[i] << ", ";
//}
//std::cout << std::endl;
// Start clock for host checking for match timing
start = clock();
std::cout << "** Checking on Host for hash match... ";
// Check if there is a match
for (int i = 0; i < KERNEL_SIZE; i++) {
if (h_compareArr[i] == 1) {
passwordFound = true;
resultPassword = getPwdTry(i, h_pwdTryArr);
//std::cout << "MATCH FOUND: ";
//std::cout << getPwdTry(i, h_pwdTryArr) << "\n";
}
}
// Stop clock for host checking for match timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Incrememnt kernel pass
kernelPasses++;
}
free(h_pwdTryArr);
free(h_pwdHashArr);
free(h_checkingFor);
free(h_compareArr);
cudaFree(d_pwdTryArr);
cudaFree(d_pwdHashArr);
cudaFree(d_checkingFor);
cudaFree(d_compareArr);
}
/**
* Main application
*/
int main(int argc, char *argv[]) {
setlocale(LC_NUMERIC, "");
// Variable for command line argument
std::string argument = "";
// Make sure hash has been passed to program via command line
if (argc < 2) {
std::cout << "!!! ERROR !!! Please enter hash as argument !!!\n";
return EXIT_FAILURE;
} else {
argument = argv[1];
if (argument.length() != 77) {
std::cout << "!!! ERROR !!! Hash must be 77 characters long !!!\n";
return EXIT_FAILURE;
}
}
// Parse argument into salt and hash
parseInputHash(argument);
calcMaxAttempts();
std::cout << "Attempting to crack password...\n";
main_sub0();
if (passwordFound) {
std::cout << "Password found --- " << resultPassword << "\n";
} else {
std::cout << "Password not found\n";
}
// Display total number of attempts
printf("%'d attempts processed\n", kernelPasses * KERNEL_SIZE);
printf("%'.5f total processing time\n", totalRunTime);
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 94;
const int ASCII_OFFSET = 33;
const size_t PWD_TRY_ARR_MEM_SIZE = (sizeof(char) * PWD_LENGTH) * KERNEL_SIZE;
const size_t PWD_HASH_ARR_MEM_SIZE = (sizeof(char) * HASH_LENGTH) * KERNEL_SIZE;
const size_t COMP_ARR_MEM_SIZE = (sizeof(int) * KERNEL_SIZE);
// Application variables
std::string pwdSalt = "";
std::string checkFor = "";
std::string testPwdStr = "";
std::string testHash = "";
bool passwordFound = false;
std::string resultPassword = "";
unsigned long maxPwdAttempts;
int kernelPasses = 0;
// Timing variables
double totalRunTime = 0;
/**
* Caculates the maximum number of attempts based on password length
*/
__host__
void calcMaxAttempts() {
for (int i = 1; i <= PWD_LENGTH; i++) {
maxPwdAttempts += pow(CHARACTER_SET, i);
}
maxPwdAttempts += KERNEL_SIZE - 1;
}
/**
* Take user input and parse into salt and hash
*/
__host__
void parseInputHash(std::string arg) {
pwdSalt = arg.substr(0,12);
checkFor = arg.substr(12,HASH_LENGTH);
std::cout << "User Entered the Following Password Hash Information...\n";
std::cout << "Salt: " << pwdSalt << "\n";
std::cout << "Hash: " << checkFor << "\n";
}
/**
* Create hash from brute force password string
*/
__host__
std::string createHash(std::string password) {
// Create password hash from password try and salt
testHash = crypt((char *) password.c_str(), (char *) pwdSalt.c_str());
return testHash.substr(12,HASH_LENGTH);
}
/**
* Helper function to copy the individual hash to the hash array
*/
__host__
void copyHashToArr(int arrIndx, std::string hash, char *charArr) {
// Calculate array offset
int offset = arrIndx * HASH_LENGTH;
// Loop through input hash to insert into hash array
for (int i = 0; i < HASH_LENGTH; i++) {
charArr[offset + i] = hash[i];
}
}
/**
* Helper function to pull a password out of password character array
*/
__host__
std::string getPwdTry(int arrIndx, char *pwdCharArr) {
// Calculate array offset
int offset = arrIndx * PWD_LENGTH;
// temp string for password
std::string tmpPwd = "";
for (int i = 0; i < PWD_LENGTH; i++) {
// Skip blank characters
if (pwdCharArr[offset + i] != ' ') {
tmpPwd += pwdCharArr[offset + i];
}
}
return tmpPwd;
}
/**
* Debug Helper Function to print character array entries
*/
__host__
void printArr(int length, char *charArr) {
// Loop through character array
for (int i = 0; i < (KERNEL_SIZE * length); i++) {
if ((i == 0) || (i % length) != 0) {
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
} else {
std::cout << ", ";
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
}
}
std::cout << std::endl;
}
/**
* Create brute force password attemps
*/
__global__
void kernel_createPwdTry(int numPass, char *tryArr) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Create unique guess number based on thread and number of times kernel has been run
int guess = (numPass * KERNEL_SIZE) + curThread;
// Set fourth letter of four letter password
tryArr[(curThread * PWD_LENGTH) + 3] = (guess % CHARACTER_SET) + ASCII_OFFSET;
// Reduce guess number
guess = guess / CHARACTER_SET;
// If necessary, set third letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 2] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 2] = 32; // Space
}
// If necessary, set second letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 1] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 1] = 32; // Space
}
// If necessary, set first letter of four and reduce guess number
if (guess > 0) {
tryArr[curThread * PWD_LENGTH] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[curThread * PWD_LENGTH] = 32; // Space
}
}
/**
* Kernel to check brute force password hash with the one application is looking for
*/
__global__
void kernel_checkHash(char *lookingFor, char *hashArr, int *compares) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Get array offset
int offset = (curThread * HASH_LENGTH);
// Flag to indicate match
int match = 1;
for (int i = 0; i < HASH_LENGTH; i++) {
//printf("hashArr idx %d = %c --- lookingFor idx %d = %c Match = %d\n",
// i, hashArr[offset + i], i, lookingFor[i], match);
if (hashArr[offset + i] != lookingFor[i]) {
//printf("NO MATCH FOR HASH - %d\n", curThread);
match = 0;
break;
}
}
compares[curThread] = match;
//if (match == 0) {
//printf("!!! MATCH !!!\n");
// compares[curThread] = 1;
//}
}
/**
* Main sub routine which runs cracking loop
*/
void main_sub0() {
// Time variables
clock_t start;
clock_t stop;
double elapsedTime;
// Declare host variables
char *h_pwdTryArr;
char *h_pwdHashArr;
char *h_checkingFor;
int *h_compareArr;
// Declare device variables
char *d_pwdTryArr;
char *d_pwdHashArr;
char *d_checkingFor;
int *d_compareArr;
// Allocate Host memory
h_pwdTryArr = (char *)malloc(PWD_TRY_ARR_MEM_SIZE);
h_pwdHashArr = (char *)malloc(PWD_HASH_ARR_MEM_SIZE);
h_checkingFor = (char *)malloc(HASH_LENGTH * sizeof(char));
h_compareArr = (int *)malloc(COMP_ARR_MEM_SIZE);
// Allocate GPU memory
hipMalloc((void **) &d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE);
hipMalloc((void **) &d_pwdHashArr, PWD_HASH_ARR_MEM_SIZE);
hipMalloc((void **) &d_checkingFor, (HASH_LENGTH * sizeof(char)));
hipMalloc((void **) &d_compareArr, COMP_ARR_MEM_SIZE);
strcpy(h_checkingFor, checkFor.c_str());
// Fill array
//for (int i = 0; i < (KERNEL_SIZE * PWD_LENGTH); i++) {
// h_pwdTryArr[i] = 'Z';
//}
// DEBUG PRINT ORIGINAL PASSWORDS
//std::cout << "PWDTRYARR BEFORE KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Copy host to device
hipMemcpy(d_pwdTryArr, h_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, hipMemcpyHostToDevice);
while ((!passwordFound) && ((kernelPasses * KERNEL_SIZE) < maxPwdAttempts)) {
printf("Running round %'d of %'d password attempts\n", (kernelPasses + 1), KERNEL_SIZE);
//std::cout << "Running round " << (kernelPasses + 1) << " of ";
//std::cout << KERNEL_SIZE << " password attempts\n";
// Start clock for kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Create Brute Force Passwords... ";
// Run create password kernel
kernel_createPwdTry<<<NUM_BLOCKS,NUM_THREADS>>>(kernelPasses, d_pwdTryArr);
// Stop clock for kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
hipMemcpy(h_pwdTryArr, d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, hipMemcpyDeviceToHost);
// DEBUG PRINT CREATED PASSWORDS
//std::cout << "PWDTRYARR AFTER KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Start clock for host hash creation timing
start = clock();
std::cout << "** Running Host Method to Create Hashes... ";
// Iterate through passowrd try array
for (int i = 0; i < (KERNEL_SIZE); i++) {
// Reset string
testPwdStr = "";
testPwdStr = getPwdTry(i, h_pwdTryArr);
/**
for (int j = 0; j < PWD_LENGTH; j++) {
char c = h_pwdTryArr[(i * PWD_LENGTH) + j];
if (c != ' ') {
testPwdStr += c;
}
}
**/
// Print Debug Logic
//std::cout << testPwdStr << " --- ";
//std::cout << createHash(testPwdStr) << std::endl;
copyHashToArr(i, createHash(testPwdStr), h_pwdHashArr);
// Create hash of password and store in hash array
// strcpy(h_pwdHashArr[i], createHash(testPwdStr).c_str());
}
// Stop clock for host hash creation timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// DEBUG PRINT CREATED HASHES
//std::cout << "PWDHASHARR\n";
//printArr(HASH_LENGTH, h_pwdHashArr);
// Copy host to device
hipMemcpy(d_checkingFor, h_checkingFor, (HASH_LENGTH * sizeof(char)), hipMemcpyHostToDevice);
hipMemcpy(d_pwdHashArr, h_pwdHashArr, PWD_HASH_ARR_MEM_SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_compareArr, h_compareArr, COMP_ARR_MEM_SIZE, hipMemcpyHostToDevice);
// DEBUG PRINT LOOKINGFOR HASH
//std::cout << "LOOKINGFOR\n";
//for (int i = 0; i < HASH_LENGTH; i++) {
// std::cout << h_checkingFor[i];
//}
//std::cout << std::endl;
// Start clock for hash comparison kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Check Password Hashes... ";
// Run check hash kernel
kernel_checkHash<<<NUM_BLOCKS, NUM_THREADS>>>(d_checkingFor, d_pwdHashArr, d_compareArr);
// Stop clock for hash comparison kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
hipMemcpy(h_compareArr, d_compareArr, COMP_ARR_MEM_SIZE, hipMemcpyDeviceToHost);
// DEBUG PRINT COMPAREARR
//std::cout << "COMPAREARR --- ";
//for (int i = 0; i < KERNEL_SIZE; i++) {
// std::cout << h_compareArr[i] << ", ";
//}
//std::cout << std::endl;
// Start clock for host checking for match timing
start = clock();
std::cout << "** Checking on Host for hash match... ";
// Check if there is a match
for (int i = 0; i < KERNEL_SIZE; i++) {
if (h_compareArr[i] == 1) {
passwordFound = true;
resultPassword = getPwdTry(i, h_pwdTryArr);
//std::cout << "MATCH FOUND: ";
//std::cout << getPwdTry(i, h_pwdTryArr) << "\n";
}
}
// Stop clock for host checking for match timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Incrememnt kernel pass
kernelPasses++;
}
free(h_pwdTryArr);
free(h_pwdHashArr);
free(h_checkingFor);
free(h_compareArr);
hipFree(d_pwdTryArr);
hipFree(d_pwdHashArr);
hipFree(d_checkingFor);
hipFree(d_compareArr);
}
/**
* Main application
*/
int main(int argc, char *argv[]) {
setlocale(LC_NUMERIC, "");
// Variable for command line argument
std::string argument = "";
// Make sure hash has been passed to program via command line
if (argc < 2) {
std::cout << "!!! ERROR !!! Please enter hash as argument !!!\n";
return EXIT_FAILURE;
} else {
argument = argv[1];
if (argument.length() != 77) {
std::cout << "!!! ERROR !!! Hash must be 77 characters long !!!\n";
return EXIT_FAILURE;
}
}
// Parse argument into salt and hash
parseInputHash(argument);
calcMaxAttempts();
std::cout << "Attempting to crack password...\n";
main_sub0();
if (passwordFound) {
std::cout << "Password found --- " << resultPassword << "\n";
} else {
std::cout << "Password not found\n";
}
// Display total number of attempts
printf("%'d attempts processed\n", kernelPasses * KERNEL_SIZE);
printf("%'.5f total processing time\n", totalRunTime);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 94;
const int ASCII_OFFSET = 33;
const size_t PWD_TRY_ARR_MEM_SIZE = (sizeof(char) * PWD_LENGTH) * KERNEL_SIZE;
const size_t PWD_HASH_ARR_MEM_SIZE = (sizeof(char) * HASH_LENGTH) * KERNEL_SIZE;
const size_t COMP_ARR_MEM_SIZE = (sizeof(int) * KERNEL_SIZE);
// Application variables
std::string pwdSalt = "";
std::string checkFor = "";
std::string testPwdStr = "";
std::string testHash = "";
bool passwordFound = false;
std::string resultPassword = "";
unsigned long maxPwdAttempts;
int kernelPasses = 0;
// Timing variables
double totalRunTime = 0;
/**
* Caculates the maximum number of attempts based on password length
*/
__host__
void calcMaxAttempts() {
for (int i = 1; i <= PWD_LENGTH; i++) {
maxPwdAttempts += pow(CHARACTER_SET, i);
}
maxPwdAttempts += KERNEL_SIZE - 1;
}
/**
* Take user input and parse into salt and hash
*/
__host__
void parseInputHash(std::string arg) {
pwdSalt = arg.substr(0,12);
checkFor = arg.substr(12,HASH_LENGTH);
std::cout << "User Entered the Following Password Hash Information...\n";
std::cout << "Salt: " << pwdSalt << "\n";
std::cout << "Hash: " << checkFor << "\n";
}
/**
* Create hash from brute force password string
*/
__host__
std::string createHash(std::string password) {
// Create password hash from password try and salt
testHash = crypt((char *) password.c_str(), (char *) pwdSalt.c_str());
return testHash.substr(12,HASH_LENGTH);
}
/**
* Helper function to copy the individual hash to the hash array
*/
__host__
void copyHashToArr(int arrIndx, std::string hash, char *charArr) {
// Calculate array offset
int offset = arrIndx * HASH_LENGTH;
// Loop through input hash to insert into hash array
for (int i = 0; i < HASH_LENGTH; i++) {
charArr[offset + i] = hash[i];
}
}
/**
* Helper function to pull a password out of password character array
*/
__host__
std::string getPwdTry(int arrIndx, char *pwdCharArr) {
// Calculate array offset
int offset = arrIndx * PWD_LENGTH;
// temp string for password
std::string tmpPwd = "";
for (int i = 0; i < PWD_LENGTH; i++) {
// Skip blank characters
if (pwdCharArr[offset + i] != ' ') {
tmpPwd += pwdCharArr[offset + i];
}
}
return tmpPwd;
}
/**
* Debug Helper Function to print character array entries
*/
__host__
void printArr(int length, char *charArr) {
// Loop through character array
for (int i = 0; i < (KERNEL_SIZE * length); i++) {
if ((i == 0) || (i % length) != 0) {
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
} else {
std::cout << ", ";
if (charArr[i] != ' ') {
std::cout << charArr[i];
}
}
}
std::cout << std::endl;
}
/**
* Create brute force password attemps
*/
__global__
void kernel_createPwdTry(int numPass, char *tryArr) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Create unique guess number based on thread and number of times kernel has been run
int guess = (numPass * KERNEL_SIZE) + curThread;
// Set fourth letter of four letter password
tryArr[(curThread * PWD_LENGTH) + 3] = (guess % CHARACTER_SET) + ASCII_OFFSET;
// Reduce guess number
guess = guess / CHARACTER_SET;
// If necessary, set third letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 2] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 2] = 32; // Space
}
// If necessary, set second letter of four and reduce guess number
if (guess > 0) {
tryArr[(curThread * PWD_LENGTH) + 1] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[(curThread * PWD_LENGTH) + 1] = 32; // Space
}
// If necessary, set first letter of four and reduce guess number
if (guess > 0) {
tryArr[curThread * PWD_LENGTH] = (guess % CHARACTER_SET) + ASCII_OFFSET;
guess = guess / CHARACTER_SET;
} else {
tryArr[curThread * PWD_LENGTH] = 32; // Space
}
}
/**
* Kernel to check brute force password hash with the one application is looking for
*/
__global__
void kernel_checkHash(char *lookingFor, char *hashArr, int *compares) {
// Get current thread
int curThread = blockIdx.x * blockDim.x + threadIdx.x;
// Get array offset
int offset = (curThread * HASH_LENGTH);
// Flag to indicate match
int match = 1;
for (int i = 0; i < HASH_LENGTH; i++) {
//printf("hashArr idx %d = %c --- lookingFor idx %d = %c Match = %d\n",
// i, hashArr[offset + i], i, lookingFor[i], match);
if (hashArr[offset + i] != lookingFor[i]) {
//printf("NO MATCH FOR HASH - %d\n", curThread);
match = 0;
break;
}
}
compares[curThread] = match;
//if (match == 0) {
//printf("!!! MATCH !!!\n");
// compares[curThread] = 1;
//}
}
/**
* Main sub routine which runs cracking loop
*/
void main_sub0() {
// Time variables
clock_t start;
clock_t stop;
double elapsedTime;
// Declare host variables
char *h_pwdTryArr;
char *h_pwdHashArr;
char *h_checkingFor;
int *h_compareArr;
// Declare device variables
char *d_pwdTryArr;
char *d_pwdHashArr;
char *d_checkingFor;
int *d_compareArr;
// Allocate Host memory
h_pwdTryArr = (char *)malloc(PWD_TRY_ARR_MEM_SIZE);
h_pwdHashArr = (char *)malloc(PWD_HASH_ARR_MEM_SIZE);
h_checkingFor = (char *)malloc(HASH_LENGTH * sizeof(char));
h_compareArr = (int *)malloc(COMP_ARR_MEM_SIZE);
// Allocate GPU memory
hipMalloc((void **) &d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE);
hipMalloc((void **) &d_pwdHashArr, PWD_HASH_ARR_MEM_SIZE);
hipMalloc((void **) &d_checkingFor, (HASH_LENGTH * sizeof(char)));
hipMalloc((void **) &d_compareArr, COMP_ARR_MEM_SIZE);
strcpy(h_checkingFor, checkFor.c_str());
// Fill array
//for (int i = 0; i < (KERNEL_SIZE * PWD_LENGTH); i++) {
// h_pwdTryArr[i] = 'Z';
//}
// DEBUG PRINT ORIGINAL PASSWORDS
//std::cout << "PWDTRYARR BEFORE KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Copy host to device
hipMemcpy(d_pwdTryArr, h_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, hipMemcpyHostToDevice);
while ((!passwordFound) && ((kernelPasses * KERNEL_SIZE) < maxPwdAttempts)) {
printf("Running round %'d of %'d password attempts\n", (kernelPasses + 1), KERNEL_SIZE);
//std::cout << "Running round " << (kernelPasses + 1) << " of ";
//std::cout << KERNEL_SIZE << " password attempts\n";
// Start clock for kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Create Brute Force Passwords... ";
// Run create password kernel
kernel_createPwdTry<<<NUM_BLOCKS,NUM_THREADS>>>(kernelPasses, d_pwdTryArr);
// Stop clock for kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
hipMemcpy(h_pwdTryArr, d_pwdTryArr, PWD_TRY_ARR_MEM_SIZE, hipMemcpyDeviceToHost);
// DEBUG PRINT CREATED PASSWORDS
//std::cout << "PWDTRYARR AFTER KERNEL EXECUTION\n";
//printArr(PWD_LENGTH, h_pwdTryArr);
// Start clock for host hash creation timing
start = clock();
std::cout << "** Running Host Method to Create Hashes... ";
// Iterate through passowrd try array
for (int i = 0; i < (KERNEL_SIZE); i++) {
// Reset string
testPwdStr = "";
testPwdStr = getPwdTry(i, h_pwdTryArr);
/**
for (int j = 0; j < PWD_LENGTH; j++) {
char c = h_pwdTryArr[(i * PWD_LENGTH) + j];
if (c != ' ') {
testPwdStr += c;
}
}
**/
// Print Debug Logic
//std::cout << testPwdStr << " --- ";
//std::cout << createHash(testPwdStr) << std::endl;
copyHashToArr(i, createHash(testPwdStr), h_pwdHashArr);
// Create hash of password and store in hash array
// strcpy(h_pwdHashArr[i], createHash(testPwdStr).c_str());
}
// Stop clock for host hash creation timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// DEBUG PRINT CREATED HASHES
//std::cout << "PWDHASHARR\n";
//printArr(HASH_LENGTH, h_pwdHashArr);
// Copy host to device
hipMemcpy(d_checkingFor, h_checkingFor, (HASH_LENGTH * sizeof(char)), hipMemcpyHostToDevice);
hipMemcpy(d_pwdHashArr, h_pwdHashArr, PWD_HASH_ARR_MEM_SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_compareArr, h_compareArr, COMP_ARR_MEM_SIZE, hipMemcpyHostToDevice);
// DEBUG PRINT LOOKINGFOR HASH
//std::cout << "LOOKINGFOR\n";
//for (int i = 0; i < HASH_LENGTH; i++) {
// std::cout << h_checkingFor[i];
//}
//std::cout << std::endl;
// Start clock for hash comparison kernel timing
start = clock();
std::cout << "** Running GPU Kernel to Check Password Hashes... ";
// Run check hash kernel
kernel_checkHash<<<NUM_BLOCKS, NUM_THREADS>>>(d_checkingFor, d_pwdHashArr, d_compareArr);
// Stop clock for hash comparison kernel timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Copy device to host
hipMemcpy(h_compareArr, d_compareArr, COMP_ARR_MEM_SIZE, hipMemcpyDeviceToHost);
// DEBUG PRINT COMPAREARR
//std::cout << "COMPAREARR --- ";
//for (int i = 0; i < KERNEL_SIZE; i++) {
// std::cout << h_compareArr[i] << ", ";
//}
//std::cout << std::endl;
// Start clock for host checking for match timing
start = clock();
std::cout << "** Checking on Host for hash match... ";
// Check if there is a match
for (int i = 0; i < KERNEL_SIZE; i++) {
if (h_compareArr[i] == 1) {
passwordFound = true;
resultPassword = getPwdTry(i, h_pwdTryArr);
//std::cout << "MATCH FOUND: ";
//std::cout << getPwdTry(i, h_pwdTryArr) << "\n";
}
}
// Stop clock for host checking for match timing and output results
stop = clock();
elapsedTime = double(stop - start) / CLOCKS_PER_SEC;
totalRunTime += elapsedTime;
printf("Took %.5f seconds to run\n", elapsedTime);
// Incrememnt kernel pass
kernelPasses++;
}
free(h_pwdTryArr);
free(h_pwdHashArr);
free(h_checkingFor);
free(h_compareArr);
hipFree(d_pwdTryArr);
hipFree(d_pwdHashArr);
hipFree(d_checkingFor);
hipFree(d_compareArr);
}
/**
* Main application
*/
int main(int argc, char *argv[]) {
setlocale(LC_NUMERIC, "");
// Variable for command line argument
std::string argument = "";
// Make sure hash has been passed to program via command line
if (argc < 2) {
std::cout << "!!! ERROR !!! Please enter hash as argument !!!\n";
return EXIT_FAILURE;
} else {
argument = argv[1];
if (argument.length() != 77) {
std::cout << "!!! ERROR !!! Hash must be 77 characters long !!!\n";
return EXIT_FAILURE;
}
}
// Parse argument into salt and hash
parseInputHash(argument);
calcMaxAttempts();
std::cout << "Attempting to crack password...\n";
main_sub0();
if (passwordFound) {
std::cout << "Password found --- " << resultPassword << "\n";
} else {
std::cout << "Password not found\n";
}
// Display total number of attempts
printf("%'d attempts processed\n", kernelPasses * KERNEL_SIZE);
printf("%'.5f total processing time\n", totalRunTime);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19kernel_createPwdTryiPc
.globl _Z19kernel_createPwdTryiPc
.p2align 8
.type _Z19kernel_createPwdTryiPc,@function
_Z19kernel_createPwdTryiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v4, s3, 14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v0, v4, 0xae4c415d
v_add_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 31, v0
v_ashrrev_i32_e32 v0, 6, v0
v_add_nc_u32_e32 v1, v0, v1
v_lshlrev_b32_e32 v0, 2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v1, 0x5e
v_or_b32_e32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_sub_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u16 v6, v3, 33
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_store_b8 v[2:3], v6, off
v_cmpx_gt_i32_e32 0x5e, v4
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
v_or_b32_e32 v2, 2, v0
v_mov_b32_e32 v4, 32
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[2:3], v4, off
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_4
v_mul_hi_u32 v2, v1, 0xae4c415d
v_or_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_lshrrev_b32_e32 v4, 6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, 0x5e
v_sub_nc_u32_e32 v1, v1, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u16 v6, v1, 33
v_mov_b32_e32 v1, v4
global_store_b8 v[2:3], v6, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 1, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_6
v_or_b32_e32 v2, 1, v0
v_mov_b32_e32 v4, 32
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[2:3], v4, off
.LBB0_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_8
v_mul_hi_u32 v2, v1, 0xae4c415d
v_or_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_lshrrev_b32_e32 v4, 6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, 0x5e
v_sub_nc_u32_e32 v1, v1, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u16 v6, v1, 33
v_mov_b32_e32 v1, v4
global_store_b8 v[2:3], v6, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v2, 32
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
v_mul_hi_u32 v2, v1, 0xae4c415d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 6, v2
v_mul_lo_u32 v2, v2, 0x5e
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v2
v_add_nc_u16 v2, v1, 33
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernel_createPwdTryiPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19kernel_createPwdTryiPc, .Lfunc_end0-_Z19kernel_createPwdTryiPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16kernel_checkHashPcS_Pi
.globl _Z16kernel_checkHashPcS_Pi
.p2align 8
.type _Z16kernel_checkHashPcS_Pi,@function
_Z16kernel_checkHashPcS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], 0
v_lshlrev_b32_e32 v0, 6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v0
v_add_co_u32 v0, vcc_lo, s6, v0
s_mov_b32 s6, 0
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_4
.LBB1_2:
v_add_co_u32 v4, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_u32 s8, s4, s2
s_addc_u32 s9, s5, s3
global_load_u8 v6, v3, s[8:9]
global_load_u8 v4, v[4:5], off
s_or_b32 s7, s7, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v4, v6
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB1_1
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 64
v_mov_b32_e32 v4, 1
s_cselect_b32 s9, -1, 0
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_branch .LBB1_1
.LBB1_4:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_checkHashPcS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16kernel_checkHashPcS_Pi, .Lfunc_end1-_Z16kernel_checkHashPcS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernel_createPwdTryiPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19kernel_createPwdTryiPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
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.size: 8
.value_kind: hidden_global_offset_x
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.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernel_checkHashPcS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernel_checkHashPcS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kernel_checkHashPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x610 ; /* 0x000005e000007945 */
/* 0x000fe20003800000 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0202 */
/*0070*/ IMAD R5, R7, 0x40, R0 ; /* 0x0000004007057824 */
/* 0x000fe200078e0200 */
/*0080*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0090*/ IADD3 R4, P0, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x040fe40007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f0eff */
/*00b0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc600000f0eff */
/*00c0*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0100*/ @P0 BRA 0x600 ; /* 0x000004f000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea8000c1e1100 */
/*0120*/ LDG.E.U8 R9, [R4.64+0x1] ; /* 0x0000010404097981 */
/* 0x000ea4000c1e1100 */
/*0130*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0150*/ @P0 BRA 0x600 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea8000c1e1100 */
/*0170*/ LDG.E.U8 R9, [R4.64+0x2] ; /* 0x0000020404097981 */
/* 0x000ea4000c1e1100 */
/*0180*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01a0*/ @P0 BRA 0x600 ; /* 0x0000045000000947 */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E.U8 R6, [R2.64+0x3] ; /* 0x0000030402067981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ LDG.E.U8 R9, [R4.64+0x3] ; /* 0x0000030404097981 */
/* 0x000ea4000c1e1100 */
/*01d0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*01e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01f0*/ @P0 BRA 0x600 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0200*/ LDG.E.U8 R6, [R2.64+0x4] ; /* 0x0000040402067981 */
/* 0x000ea8000c1e1100 */
/*0210*/ LDG.E.U8 R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ea4000c1e1100 */
/*0220*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0240*/ @P0 BRA 0x600 ; /* 0x000003b000000947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E.U8 R6, [R2.64+0x5] ; /* 0x0000050402067981 */
/* 0x000ea8000c1e1100 */
/*0260*/ LDG.E.U8 R9, [R4.64+0x5] ; /* 0x0000050404097981 */
/* 0x000ea4000c1e1100 */
/*0270*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0290*/ @P0 BRA 0x600 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E.U8 R6, [R2.64+0x6] ; /* 0x0000060402067981 */
/* 0x000ea8000c1e1100 */
/*02b0*/ LDG.E.U8 R9, [R4.64+0x6] ; /* 0x0000060404097981 */
/* 0x000ea4000c1e1100 */
/*02c0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*02e0*/ @P0 BRA 0x600 ; /* 0x0000031000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E.U8 R6, [R2.64+0x7] ; /* 0x0000070402067981 */
/* 0x000ea8000c1e1100 */
/*0300*/ LDG.E.U8 R9, [R4.64+0x7] ; /* 0x0000070404097981 */
/* 0x000ea4000c1e1100 */
/*0310*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0320*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fd800000001ff */
/*0330*/ @P0 BRA 0x600 ; /* 0x000002c000000947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.U8 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ea8000c1e1100 */
/*0350*/ LDG.E.U8 R9, [R4.64+0x8] ; /* 0x0000080404097981 */
/* 0x000ea4000c1e1100 */
/*0360*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0380*/ @P0 BRA 0x600 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E.U8 R6, [R2.64+0x9] ; /* 0x0000090402067981 */
/* 0x000ea8000c1e1100 */
/*03a0*/ LDG.E.U8 R9, [R4.64+0x9] ; /* 0x0000090404097981 */
/* 0x000ea4000c1e1100 */
/*03b0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*03c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*03d0*/ @P0 BRA 0x600 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.U8 R6, [R2.64+0xa] ; /* 0x00000a0402067981 */
/* 0x000ea8000c1e1100 */
/*03f0*/ LDG.E.U8 R9, [R4.64+0xa] ; /* 0x00000a0404097981 */
/* 0x000ea4000c1e1100 */
/*0400*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0420*/ @P0 BRA 0x600 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R6, [R2.64+0xb] ; /* 0x00000b0402067981 */
/* 0x000ea8000c1e1100 */
/*0440*/ LDG.E.U8 R9, [R4.64+0xb] ; /* 0x00000b0404097981 */
/* 0x000ea4000c1e1100 */
/*0450*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0470*/ @P0 BRA 0x600 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ea8000c1e1100 */
/*0490*/ LDG.E.U8 R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x000ea4000c1e1100 */
/*04a0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*04c0*/ @P0 BRA 0x600 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E.U8 R6, [R2.64+0xd] ; /* 0x00000d0402067981 */
/* 0x000ea8000c1e1100 */
/*04e0*/ LDG.E.U8 R9, [R4.64+0xd] ; /* 0x00000d0404097981 */
/* 0x000ea4000c1e1100 */
/*04f0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe40003f05270 */
/*0500*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fd60000000f00 */
/*0510*/ @P0 BRA 0x600 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E.U8 R6, [R2.64+0xe] ; /* 0x00000e0402067981 */
/* 0x000ea8000c1e1100 */
/*0530*/ LDG.E.U8 R9, [R4.64+0xe] ; /* 0x00000e0404097981 */
/* 0x000ea4000c1e1100 */
/*0540*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*0560*/ @P0 BRA 0x600 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E.U8 R2, [R2.64+0xf] ; /* 0x00000f0402027981 */
/* 0x000ea8000c1e1100 */
/*0580*/ LDG.E.U8 R5, [R4.64+0xf] ; /* 0x00000f0404057981 */
/* 0x000ea2000c1e1100 */
/*0590*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*05a0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*05b0*/ @P0 BRA 0x600 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x40, PT ; /* 0x000000400000780c */
/* 0x000fda0003f06070 */
/*05e0*/ @!P0 BRA 0x70 ; /* 0xfffffa8000008947 */
/* 0x000fea000383ffff */
/*05f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe400078e00ff */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0202 */
/*0630*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19kernel_createPwdTryiPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R10, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff0a7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x20 ; /* 0x00000020ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff037624 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD R3, R3, 0x4000, R0 ; /* 0x0000400003037824 */
/* 0x000fe400078e0200 */
/*00a0*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.HI R2, R3.reuse, -0x51b3bea3, R2 ; /* 0xae4c415d03027827 */
/* 0x040fe200078e0202 */
/*00c0*/ ISETP.GT.AND P0, PT, R3, 0x5d, PT ; /* 0x0000005d0300780c */
/* 0x000fc80003f04270 */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fc80000011602 */
/*00e0*/ LEA.HI.SX32 R7, R2, R5, 0x1a ; /* 0x0000000502077211 */
/* 0x000fca00078fd2ff */
/*00f0*/ @P0 MOV R5, R7 ; /* 0x0000000700050202 */
/* 0x000fe20000000f00 */
/*0100*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R6, R7.reuse, -0x5e, R3 ; /* 0xffffffa207067824 */
/* 0x040fe400078e0203 */
/*0120*/ @P0 IMAD.HI R2, R7, -0x51b3bea3, R4 ; /* 0xae4c415d07020827 */
/* 0x000fca00078e0204 */
/*0130*/ @P0 SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff050819 */
/* 0x000fc80000011602 */
/*0140*/ @P0 LEA.HI R2, R2, R5, RZ, 0x1a ; /* 0x0000000502020211 */
/* 0x000fe200078fd0ff */
/*0150*/ @P0 IMAD.WIDE.U32 R4, R3, 0x76abbf91, RZ ; /* 0x76abbf9103040825 */
/* 0x000fc800078e00ff */
/*0160*/ @P0 IMAD R8, R2, -0x5e, R7 ; /* 0xffffffa202080824 */
/* 0x000fe200078e0207 */
/*0170*/ @P0 SHF.R.U32.HI R7, RZ, 0xc, R5 ; /* 0x0000000cff070819 */
/* 0x000fc80000011605 */
/*0180*/ ISETP.GT.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f24270 */
/*0190*/ @P1 IMAD.WIDE.U32 R2, R7, -0x51b3bea3, RZ ; /* 0xae4c415d07021825 */
/* 0x000fca00078e00ff */
/*01a0*/ @P1 SHF.R.U32.HI R2, RZ, 0x6, R3 ; /* 0x00000006ff021819 */
/* 0x000fca0000011603 */
/*01b0*/ @P1 IMAD R9, R2, -0x5e, R7 ; /* 0xffffffa202091824 */
/* 0x000fe400078e0207 */
/*01c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0002 */
/*01d0*/ IADD3 R2, P3, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f7e0ff */
/*01e0*/ @P1 IADD3 R9, R9, 0x21, RZ ; /* 0x0000002109091810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f46270 */
/*0200*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P3 ; /* 0x00005b0000037a11 */
/* 0x000fd600018f0eff */
/*0210*/ @P2 IMAD.WIDE.U32 R4, R7, -0x51b3bea3, RZ ; /* 0xae4c415d07042825 */
/* 0x000fca00078e00ff */
/*0220*/ @P2 SHF.R.U32.HI R0, RZ, 0x6, R5 ; /* 0x00000006ff002819 */
/* 0x000fe40000011605 */
/*0230*/ IADD3 R5, R6, 0x21, RZ ; /* 0x0000002106057810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P0 PRMT R4, R10, 0x7610, R4 ; /* 0x000076100a048816 */
/* 0x000fe20000000004 */
/*0250*/ @P2 IMAD R0, R0, -0x5e, R7 ; /* 0xffffffa200002824 */
/* 0x000fe200078e0207 */
/*0260*/ @!P1 PRMT R6, R10, 0x7610, R6 ; /* 0x000076100a069816 */
/* 0x000fe20000000006 */
/*0270*/ STG.E.U8 [R2.64+0x3], R5 ; /* 0x0000030502007986 */
/* 0x000fe2000c101104 */
/*0280*/ @P0 IADD3 R7, R8, 0x21, RZ ; /* 0x0000002108070810 */
/* 0x000fe40007ffe0ff */
/*0290*/ @P2 IADD3 R11, R0, 0x21, RZ ; /* 0x00000021000b2810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ @!P0 STG.E.U8 [R2.64+0x2], R4 ; /* 0x0000020402008986 */
/* 0x000fe8000c101104 */
/*02b0*/ @!P1 STG.E.U8 [R2.64+0x1], R6 ; /* 0x0000010602009986 */
/* 0x000fe8000c101104 */
/*02c0*/ @P0 STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702000986 */
/* 0x000fe8000c101104 */
/*02d0*/ @P1 STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902001986 */
/* 0x000fe8000c101104 */
/*02e0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101104 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19kernel_createPwdTryiPc
.globl _Z19kernel_createPwdTryiPc
.p2align 8
.type _Z19kernel_createPwdTryiPc,@function
_Z19kernel_createPwdTryiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v4, s3, 14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v0, v4, 0xae4c415d
v_add_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 31, v0
v_ashrrev_i32_e32 v0, 6, v0
v_add_nc_u32_e32 v1, v0, v1
v_lshlrev_b32_e32 v0, 2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v1, 0x5e
v_or_b32_e32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_sub_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u16 v6, v3, 33
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_store_b8 v[2:3], v6, off
v_cmpx_gt_i32_e32 0x5e, v4
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
v_or_b32_e32 v2, 2, v0
v_mov_b32_e32 v4, 32
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[2:3], v4, off
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_4
v_mul_hi_u32 v2, v1, 0xae4c415d
v_or_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_lshrrev_b32_e32 v4, 6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, 0x5e
v_sub_nc_u32_e32 v1, v1, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u16 v6, v1, 33
v_mov_b32_e32 v1, v4
global_store_b8 v[2:3], v6, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 1, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_6
v_or_b32_e32 v2, 1, v0
v_mov_b32_e32 v4, 32
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[2:3], v4, off
.LBB0_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_8
v_mul_hi_u32 v2, v1, 0xae4c415d
v_or_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_lshrrev_b32_e32 v4, 6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, 0x5e
v_sub_nc_u32_e32 v1, v1, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u16 v6, v1, 33
v_mov_b32_e32 v1, v4
global_store_b8 v[2:3], v6, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v2, 32
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
v_mul_hi_u32 v2, v1, 0xae4c415d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 6, v2
v_mul_lo_u32 v2, v2, 0x5e
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v2
v_add_nc_u16 v2, v1, 33
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernel_createPwdTryiPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19kernel_createPwdTryiPc, .Lfunc_end0-_Z19kernel_createPwdTryiPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16kernel_checkHashPcS_Pi
.globl _Z16kernel_checkHashPcS_Pi
.p2align 8
.type _Z16kernel_checkHashPcS_Pi,@function
_Z16kernel_checkHashPcS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], 0
v_lshlrev_b32_e32 v0, 6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v0
v_add_co_u32 v0, vcc_lo, s6, v0
s_mov_b32 s6, 0
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_4
.LBB1_2:
v_add_co_u32 v4, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_u32 s8, s4, s2
s_addc_u32 s9, s5, s3
global_load_u8 v6, v3, s[8:9]
global_load_u8 v4, v[4:5], off
s_or_b32 s7, s7, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v4, v6
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB1_1
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 64
v_mov_b32_e32 v4, 1
s_cselect_b32 s9, -1, 0
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_branch .LBB1_1
.LBB1_4:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_checkHashPcS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16kernel_checkHashPcS_Pi, .Lfunc_end1-_Z16kernel_checkHashPcS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernel_createPwdTryiPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19kernel_createPwdTryiPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernel_checkHashPcS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernel_checkHashPcS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
cudaEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
cudaMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
cudaMalloc((void**)&cuda_max, sizeof(unsigned long long));
cudaMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
cudaMemset(cuda_max, 0, sizeof(unsigned long long));
cudaMemset(mtx, 0, sizeof(int));
// set up timing variables
cudaEventCreate(&cuda_start);
cudaEventCreate(&cuda_stop);
cudaMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), cudaMemcpyHostToDevice);
// copy from host to device
cudaEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
cudaEventRecord(cuda_stop, 0);
cudaEventSynchronize(cuda_stop);
cudaEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
cudaMemcpy(seq_max, cuda_max, sizeof(unsigned long long), cudaMemcpyDeviceToHost);
// destroy timers
cudaEventDestroy(cuda_start);
cudaEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
cudaFree(cuda_array);
cudaFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} | code for sm_80
Function : _Z19find_maximum_kernelPyS_Piy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x220 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0090*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*00a0*/ @P0 BRA 0x210 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff087624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*0120*/ LEA R2, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004027a11 */
/* 0x000fc800078018ff */
/*0130*/ LEA.HI.X R3, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x0000590004037a11 */
/* 0x000fcc00000f1c05 */
/*0140*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IMAD R4, R8, c[0x0][0x0], RZ ; /* 0x0000000008047a24 */
/* 0x000fca00078e02ff */
/*0160*/ IADD3 R9, P1, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fc80007f3e0ff */
/*0170*/ IADD3 R4, P0, R0, R9, RZ ; /* 0x0000000900047210 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fc600008e0606 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f26070 */
/*01a0*/ IMAD.X R5, RZ, RZ, R6, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0606 */
/*01b0*/ ISETP.GE.U32.AND.EX P1, PT, R5, c[0x0][0x17c], PT, P1 ; /* 0x00005f0005007a0c */
/* 0x000fe40003f26110 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x004fc80003f04070 */
/*01d0*/ ISETP.GT.U32.AND.EX P0, PT, R13, R3, PT, P0 ; /* 0x000000030d00720c */
/* 0x000fc80003f04100 */
/*01e0*/ SEL R11, R11, R2, P0 ; /* 0x000000020b0b7207 */
/* 0x000fe40000000000 */
/*01f0*/ SEL R13, R13, R3, P0 ; /* 0x000000030d0d7207 */
/* 0x000fe20000000000 */
/*0200*/ @!P1 BRA 0x120 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0230*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x000fe20000000f00 */
/*0240*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000d */
/*0260*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0270*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0001e80000008a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0290*/ @!P0 BRA 0x3e0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.SHL.U32 R0, R7, 0x8, RZ ; /* 0x0000000807007824 */
/* 0x001fe400078e00ff */
/*02b0*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fc4000f8e00ff */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe20003f04070 */
/*02e0*/ BSSY B0, 0x380 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*02f0*/ ISETP.GT.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f04100 */
/*0300*/ @!P0 BRA 0x370 ; /* 0x0000006000008947 */
/* 0x001fea0003800000 */
/*0310*/ IMAD R4, R6, 0x8, R0 ; /* 0x0000000806047824 */
/* 0x000fe200078e0200 */
/*0320*/ LDS.64 R2, [R7.X8] ; /* 0x0000000007027984 */
/* 0x000fea0000008a00 */
/*0330*/ LDS.64 R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000a00 */
/*0340*/ ISETP.GE.U32.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x001fc80003f06070 */
/*0350*/ ISETP.GE.U32.AND.EX P0, PT, R3, R5, PT, P0 ; /* 0x000000050300720c */
/* 0x000fda0003f06100 */
/*0360*/ @!P0 STS.64 [R7.X8], R4 ; /* 0x0000000407008388 */
/* 0x0001e40000008a00 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ SHF.R.U64 R6, R6, 0x1, R9.reuse ; /* 0x0000000106067819 */
/* 0x100fe20000001209 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe40000011609 */
/*03b0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*03c0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f05300 */
/*03d0*/ @P0 BRA 0x2d0 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*03e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ BSSY B0, 0x4a0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0420*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0450*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0460*/ ATOMG.E.CAS.STRONG.GPU PT, R0, [R2], R4, R5 ; /* 0x00000004020073a9 */
/* 0x000ea400001ee105 */
/*0470*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0480*/ @P0 BRA 0x440 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*04b0*/ LDS.64 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e220000000a00 */
/*04c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*04d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000e24000c1e1b00 */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, R8, PT ; /* 0x000000080600720c */
/* 0x001fc80003f06070 */
/*04f0*/ ISETP.GE.U32.AND.EX P0, PT, R7, R9, PT, P0 ; /* 0x000000090700720c */
/* 0x000fda0003f06100 */
/*0500*/ @!P0 STG.E.64 [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x000fe8000c101b06 */
/*0510*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64], RZ ; /* 0x000000ff02ff79a8 */
/* 0x000fe2000c1ee1c6 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
cudaEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
cudaMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
cudaMalloc((void**)&cuda_max, sizeof(unsigned long long));
cudaMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
cudaMemset(cuda_max, 0, sizeof(unsigned long long));
cudaMemset(mtx, 0, sizeof(int));
// set up timing variables
cudaEventCreate(&cuda_start);
cudaEventCreate(&cuda_stop);
cudaMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), cudaMemcpyHostToDevice);
// copy from host to device
cudaEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
cudaEventRecord(cuda_stop, 0);
cudaEventSynchronize(cuda_stop);
cudaEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
cudaMemcpy(seq_max, cuda_max, sizeof(unsigned long long), cudaMemcpyDeviceToHost);
// destroy timers
cudaEventDestroy(cuda_start);
cudaEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
cudaFree(cuda_array);
cudaFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} | .file "tmpxft_000ce53b_00000000-6_max_elem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
.type _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy, @function
_Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19find_maximum_kernelPyS_Piy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy, .-_Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.type _Z19find_maximum_kernelPyS_Piy, @function
_Z19find_maximum_kernelPyS_Piy:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z19find_maximum_kernelPyS_Piy, .-_Z19find_maximum_kernelPyS_Piy
.globl _Z18kernel_max_wrapperPyS_Piy
.type _Z18kernel_max_wrapperPyS_Piy, @function
_Z18kernel_max_wrapperPyS_Piy:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbx
leaq 1048575(%rcx), %rax
shrq $20, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z18kernel_max_wrapperPyS_Piy, .-_Z18kernel_max_wrapperPyS_Piy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size of array: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "----------------------------------------------------------"
.section .rodata.str1.1
.LC4:
.string "Max: "
.LC5:
.string "[CUDA] Elapsed time: "
.LC6:
.string " clock cycles"
.LC7:
.string "Starting sequential version."
.LC10:
.string "[SEQUENTIAL] Elapsed time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $20971520, 24(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 24(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi10_M_extractIyEERSiRT_@PLT
movq 24(%rsp), %rax
leaq 0(,%rax,8), %rdi
call malloc@PLT
movq %rax, %rbp
movl $8, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 24(%rsp), %rsi
testq %rsi, %rsi
je .L16
movl $0, %ebx
movabsq $-9223372036854775808, %r13
jmp .L21
.L17:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L18
.L19:
subsd .LC2(%rip), %xmm0
cvttsd2siq %xmm0, %rax
movq %rax, 0(%rbp,%rbx,8)
xorq %r13, 0(%rbp,%rbx,8)
.L20:
addq $1, %rbx
movq 24(%rsp), %rsi
cmpq %rsi, %rbx
jnb .L16
.L21:
call rand@PLT
cltq
testq %rax, %rax
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L18:
divsd .LC1(%rip), %xmm0
comisd .LC2(%rip), %xmm0
jnb .L19
cvttsd2siq %xmm0, %rax
movq %rax, 0(%rbp,%rbx,8)
jmp .L20
.L16:
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $8, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $4, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movq 24(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z18kernel_max_wrapperPyS_Piy
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC3(%rip), %r13
movq %r13, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r12), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 8(%rsp)
movq $0, (%r12)
movq 24(%rsp), %rdx
testq %rdx, %rdx
je .L22
movq %rbp, %rax
leaq 0(%rbp,%rdx,8), %rcx
jmp .L24
.L23:
addq $8, %rax
cmpq %rcx, %rax
je .L22
.L24:
movq (%rax), %rdx
cmpq %rdx, (%r12)
jnb .L23
movq %rdx, (%r12)
jmp .L23
.L22:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC8(%rip), %xmm0
mulsd .LC9(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %r14
movq %r14, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r12), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z19find_maximum_kernelPyS_Piy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z19find_maximum_kernelPyS_Piy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1745955581
.long 1059857858
.align 8
.LC2:
.long 0
.long 1138753536
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC9:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
cudaEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
cudaMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
cudaMalloc((void**)&cuda_max, sizeof(unsigned long long));
cudaMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
cudaMemset(cuda_max, 0, sizeof(unsigned long long));
cudaMemset(mtx, 0, sizeof(int));
// set up timing variables
cudaEventCreate(&cuda_start);
cudaEventCreate(&cuda_stop);
cudaMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), cudaMemcpyHostToDevice);
// copy from host to device
cudaEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
cudaEventRecord(cuda_stop, 0);
cudaEventSynchronize(cuda_stop);
cudaEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
cudaMemcpy(seq_max, cuda_max, sizeof(unsigned long long), cudaMemcpyDeviceToHost);
// destroy timers
cudaEventDestroy(cuda_start);
cudaEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
cudaFree(cuda_array);
cudaFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
hipEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
hipMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
hipMalloc((void**)&cuda_max, sizeof(unsigned long long));
hipMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
hipMemset(cuda_max, 0, sizeof(unsigned long long));
hipMemset(mtx, 0, sizeof(int));
// set up timing variables
hipEventCreate(&cuda_start);
hipEventCreate(&cuda_stop);
hipMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), hipMemcpyHostToDevice);
// copy from host to device
hipEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
hipEventRecord(cuda_stop, 0);
hipEventSynchronize(cuda_stop);
hipEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
hipMemcpy(seq_max, cuda_max, sizeof(unsigned long long), hipMemcpyDeviceToHost);
// destroy timers
hipEventDestroy(cuda_start);
hipEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
hipFree(cuda_array);
hipFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
hipEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
hipMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
hipMalloc((void**)&cuda_max, sizeof(unsigned long long));
hipMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
hipMemset(cuda_max, 0, sizeof(unsigned long long));
hipMemset(mtx, 0, sizeof(int));
// set up timing variables
hipEventCreate(&cuda_start);
hipEventCreate(&cuda_stop);
hipMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), hipMemcpyHostToDevice);
// copy from host to device
hipEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
hipEventRecord(cuda_stop, 0);
hipEventSynchronize(cuda_stop);
hipEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
hipMemcpy(seq_max, cuda_max, sizeof(unsigned long long), hipMemcpyDeviceToHost);
// destroy timers
hipEventDestroy(cuda_start);
hipEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
hipFree(cuda_array);
hipFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_maximum_kernelPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 8
.type _Z19find_maximum_kernelPyS_Piy,@function
_Z19find_maximum_kernelPyS_Piy:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s11, exec_lo
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, s7
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s10
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 3
.p2align 6
.LBB0_2:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, s2, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s2, s9, v6, s2
v_cmp_le_u64_e64 s3, s[4:5], v[1:2]
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s12, s3, s12
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, v[3:4], v[7:8]
v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v3, v7, v3
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_lshlrev_b32_e32 v5, 3, v0
s_cmp_lt_u32 s10, 2
ds_store_b64 v5, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
s_lshr_b32 s2, s10, 1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_lshr_b64 s[2:3], s[2:3], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_10
.LBB0_7:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, v0, s2, 3
ds_load_b64 v[6:7], v5
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
ds_store_b64 v5, v[2:3]
s_branch .LBB0_6
.LBB0_10:
s_mov_b32 s4, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_12:
s_waitcnt lgkmcnt(0)
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_load_b64 v[3:4], v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[0:1]
s_cbranch_vccnz .LBB0_15
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_15:
global_atomic_swap_b32 v2, v2, s[2:3]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19find_maximum_kernelPyS_Piy
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19find_maximum_kernelPyS_Piy, .Lfunc_end0-_Z19find_maximum_kernelPyS_Piy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19find_maximum_kernelPyS_Piy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19find_maximum_kernelPyS_Piy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
int main()
{
// Declare arrays, mutex, and size
// default size is 20971520
unsigned long long int N = 20971520;
unsigned long long *seq_array, *cuda_array, *seq_max, *cuda_max;
int *mtx;
// Declare timers
float cuda_elapsed_time;
hipEvent_t cuda_start, cuda_stop;
double seq_start, seq_stop, seq_elapsed_time;
cout << "Enter size of array: ";
cin >> N;
// allocate memory for seq
seq_array = (unsigned long long*)malloc(N*sizeof(unsigned long long));
seq_max = (unsigned long long*)malloc(sizeof(unsigned long long));
srand(time(0));
// set array of seq to random double values
for(unsigned long long int i=0; i<N; i++){
seq_array[i] = ((unsigned long long)rand() /((unsigned long long) RAND_MAX / (10000000000000.0)));
}
// allocate memory for cuda
hipMalloc((void**)&cuda_array, N*sizeof(unsigned long long));
hipMalloc((void**)&cuda_max, sizeof(unsigned long long));
hipMalloc((void**)&mtx, sizeof(int));
// set values of max and mtx to all 0
hipMemset(cuda_max, 0, sizeof(unsigned long long));
hipMemset(mtx, 0, sizeof(int));
// set up timing variables
hipEventCreate(&cuda_start);
hipEventCreate(&cuda_stop);
hipMemcpy(cuda_array, seq_array, N*sizeof(unsigned long long), hipMemcpyHostToDevice);
// copy from host to device
hipEventRecord(cuda_start, 0);
// START CUDA
kernel_max_wrapper(cuda_array, cuda_max, mtx, N);
// copy from device to host
hipEventRecord(cuda_stop, 0);
hipEventSynchronize(cuda_stop);
hipEventElapsedTime(&cuda_elapsed_time, cuda_start, cuda_stop);
hipMemcpy(seq_max, cuda_max, sizeof(unsigned long long), hipMemcpyDeviceToHost);
// destroy timers
hipEventDestroy(cuda_start);
hipEventDestroy(cuda_stop);
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[CUDA] Elapsed time: " << cuda_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
cout << endl;
cout << "Starting sequential version." << endl;
seq_start = (double) clock();
*seq_max = 0;
for(unsigned long long int j = 0; j < N ; j++){
if(seq_array[j] > *seq_max){
*seq_max = seq_array[j];
}
}
seq_stop = (double) clock();
seq_elapsed_time = (double) (seq_stop - seq_start)/CLOCKS_PER_SEC;
seq_elapsed_time *= 1000.0;
cout << "----------------------------------------------------------" << endl;
cout << "Max: " << *seq_max << endl;
cout << "[SEQUENTIAL] Elapsed time: " << seq_elapsed_time << " clock cycles" << endl;
cout << "----------------------------------------------------------" << endl;
// free and cuda free
free(seq_array);
free(seq_max);
hipFree(cuda_array);
hipFree(cuda_max);
return 0;
}
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
// 1 dimensional
dim3 gridSize = (N + 512 * 2048 - 1) / (512 * 2048);
dim3 blockSize = 256;
find_maximum_kernel<<< gridSize, blockSize >>>(arr, max, mtx, N);
}
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N)
{
long long index = threadIdx.x + blockIdx.x*blockDim.x;
long long span = gridDim.x*blockDim.x;
__shared__ unsigned long long cache[256];
unsigned long long temp = 0;
for (unsigned long long int offset = 0; index + offset < N; offset += span) {
if (temp < arr[index+offset]) {
temp = arr[index+offset];
}
}
cache[threadIdx.x] = temp;
__syncthreads();
// cuda reduction
for (unsigned long long int offset = blockDim.x/2; offset != 0; offset /= 2) {
if (threadIdx.x < offset) {
if (cache[threadIdx.x] < cache[threadIdx.x + offset]) {
cache[threadIdx.x] = cache[threadIdx.x + offset];
}
}
__syncthreads();
}
// atomic setting of max!
if(threadIdx.x == 0){
// lock mtx
while(atomicCAS(mtx, 0, 1) != 0);
if (*max < cache[0]) {
*max = cache[0];
}
// unlock mtx
atomicExch(mtx, 0);
}
} | .text
.file "max_elem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3f2c25c268112afd # double 2.147483647E-4
.LCPI0_3:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_5:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $20971520, (%rsp) # imm = 0x1400000
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractIyEERSiRT_
movq (%rsp), %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq (%rsp), %rsi
testq %rsi, %rsi
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %xmm0
punpckldq .LCPI0_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI0_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI0_2(%rip), %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
subsd .LCPI0_3(%rip), %xmm1
sarq $63, %rcx
cvttsd2si %xmm1, %rdx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, (%rbx,%r15,8)
incq %r15
movq (%rsp), %rsi
cmpq %rsi, %r15
jb .LBB0_2
.LBB0_3: # %._crit_edge
shlq $3, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $8, %edx
xorl %esi, %esi
callq hipMemset
movq 48(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movq 48(%rsp), %rdx
movq (%rsp), %rcx
callq _Z18kernel_max_wrapperPyS_Piy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movl $8, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_6
# %bb.5:
movzbl 67(%r15), %eax
jmp .LBB0_7
.LBB0_6:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_49
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r15)
je .LBB0_10
# %bb.9:
movzbl 67(%r15), %ecx
jmp .LBB0_11
.LBB0_10:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_49
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%r12)
je .LBB0_14
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB0_15
.LBB0_14:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r15)
je .LBB0_18
# %bb.17:
movzbl 67(%r15), %eax
jmp .LBB0_19
.LBB0_18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r15)
je .LBB0_22
# %bb.21:
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_22:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r15)
je .LBB0_26
# %bb.25:
movzbl 67(%r15), %eax
jmp .LBB0_27
.LBB0_26:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r15
movq $0, (%r14)
movq (%rsp), %rax
testq %rax, %rax
je .LBB0_32
# %bb.28: # %.lr.ph72
movq (%r14), %rdx
xorl %ecx, %ecx
jmp .LBB0_29
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_29 Depth=1
incq %rcx
cmpq %rcx, %rax
je .LBB0_32
.LBB0_29: # =>This Inner Loop Header: Depth=1
movq (%rbx,%rcx,8), %rsi
cmpq %rdx, %rsi
jbe .LBB0_31
# %bb.30: # in Loop: Header=BB0_29 Depth=1
movq %rsi, (%r14)
movq %rsi, %rdx
jmp .LBB0_31
.LBB0_32: # %._crit_edge73
callq clock
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB0_49
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r13)
je .LBB0_35
# %bb.34:
movzbl 67(%r13), %eax
jmp .LBB0_36
.LBB0_35:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB0_49
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cvtsi2sd %r15, %xmm0
cvtsi2sd %r12, %xmm1
subsd %xmm0, %xmm1
divsd .LCPI0_4(%rip), %xmm1
mulsd .LCPI0_5(%rip), %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
cmpb $0, 56(%r13)
je .LBB0_39
# %bb.38:
movzbl 67(%r13), %ecx
jmp .LBB0_40
.LBB0_39:
movq %r13, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_49
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB0_43
# %bb.42:
movzbl 67(%r12), %eax
jmp .LBB0_44
.LBB0_43:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r15)
je .LBB0_47
# %bb.46:
movzbl 67(%r15), %eax
jmp .LBB0_48
.LBB0_47:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_49:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z18kernel_max_wrapperPyS_Piy # -- Begin function _Z18kernel_max_wrapperPyS_Piy
.p2align 4, 0x90
.type _Z18kernel_max_wrapperPyS_Piy,@function
_Z18kernel_max_wrapperPyS_Piy: # @_Z18kernel_max_wrapperPyS_Piy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leaq 1048575(%rcx), %rax
shrq $20, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_maximum_kernelPyS_Piy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18kernel_max_wrapperPyS_Piy, .Lfunc_end1-_Z18kernel_max_wrapperPyS_Piy
.cfi_endproc
# -- End function
.globl _Z34__device_stub__find_maximum_kernelPyS_Piy # -- Begin function _Z34__device_stub__find_maximum_kernelPyS_Piy
.p2align 4, 0x90
.type _Z34__device_stub__find_maximum_kernelPyS_Piy,@function
_Z34__device_stub__find_maximum_kernelPyS_Piy: # @_Z34__device_stub__find_maximum_kernelPyS_Piy
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_maximum_kernelPyS_Piy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__find_maximum_kernelPyS_Piy, .Lfunc_end2-_Z34__device_stub__find_maximum_kernelPyS_Piy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19find_maximum_kernelPyS_Piy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size of array: "
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "----------------------------------------------------------"
.size .L.str.1, 59
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[CUDA] Elapsed time: "
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " clock cycles"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Starting sequential version."
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[SEQUENTIAL] Elapsed time: "
.size .L.str.6, 28
.type _Z19find_maximum_kernelPyS_Piy,@object # @_Z19find_maximum_kernelPyS_Piy
.section .rodata,"a",@progbits
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 3, 0x0
_Z19find_maximum_kernelPyS_Piy:
.quad _Z34__device_stub__find_maximum_kernelPyS_Piy
.size _Z19find_maximum_kernelPyS_Piy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19find_maximum_kernelPyS_Piy"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__find_maximum_kernelPyS_Piy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z19find_maximum_kernelPyS_Piy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19find_maximum_kernelPyS_Piy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x220 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0090*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*00a0*/ @P0 BRA 0x210 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff087624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*0120*/ LEA R2, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004027a11 */
/* 0x000fc800078018ff */
/*0130*/ LEA.HI.X R3, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x0000590004037a11 */
/* 0x000fcc00000f1c05 */
/*0140*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IMAD R4, R8, c[0x0][0x0], RZ ; /* 0x0000000008047a24 */
/* 0x000fca00078e02ff */
/*0160*/ IADD3 R9, P1, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fc80007f3e0ff */
/*0170*/ IADD3 R4, P0, R0, R9, RZ ; /* 0x0000000900047210 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fc600008e0606 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f26070 */
/*01a0*/ IMAD.X R5, RZ, RZ, R6, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0606 */
/*01b0*/ ISETP.GE.U32.AND.EX P1, PT, R5, c[0x0][0x17c], PT, P1 ; /* 0x00005f0005007a0c */
/* 0x000fe40003f26110 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x004fc80003f04070 */
/*01d0*/ ISETP.GT.U32.AND.EX P0, PT, R13, R3, PT, P0 ; /* 0x000000030d00720c */
/* 0x000fc80003f04100 */
/*01e0*/ SEL R11, R11, R2, P0 ; /* 0x000000020b0b7207 */
/* 0x000fe40000000000 */
/*01f0*/ SEL R13, R13, R3, P0 ; /* 0x000000030d0d7207 */
/* 0x000fe20000000000 */
/*0200*/ @!P1 BRA 0x120 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0230*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x000fe20000000f00 */
/*0240*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000d */
/*0260*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0270*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0001e80000008a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0290*/ @!P0 BRA 0x3e0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.SHL.U32 R0, R7, 0x8, RZ ; /* 0x0000000807007824 */
/* 0x001fe400078e00ff */
/*02b0*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fc4000f8e00ff */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe20003f04070 */
/*02e0*/ BSSY B0, 0x380 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*02f0*/ ISETP.GT.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f04100 */
/*0300*/ @!P0 BRA 0x370 ; /* 0x0000006000008947 */
/* 0x001fea0003800000 */
/*0310*/ IMAD R4, R6, 0x8, R0 ; /* 0x0000000806047824 */
/* 0x000fe200078e0200 */
/*0320*/ LDS.64 R2, [R7.X8] ; /* 0x0000000007027984 */
/* 0x000fea0000008a00 */
/*0330*/ LDS.64 R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000a00 */
/*0340*/ ISETP.GE.U32.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x001fc80003f06070 */
/*0350*/ ISETP.GE.U32.AND.EX P0, PT, R3, R5, PT, P0 ; /* 0x000000050300720c */
/* 0x000fda0003f06100 */
/*0360*/ @!P0 STS.64 [R7.X8], R4 ; /* 0x0000000407008388 */
/* 0x0001e40000008a00 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ SHF.R.U64 R6, R6, 0x1, R9.reuse ; /* 0x0000000106067819 */
/* 0x100fe20000001209 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe40000011609 */
/*03b0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*03c0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f05300 */
/*03d0*/ @P0 BRA 0x2d0 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*03e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ BSSY B0, 0x4a0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0420*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0450*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0460*/ ATOMG.E.CAS.STRONG.GPU PT, R0, [R2], R4, R5 ; /* 0x00000004020073a9 */
/* 0x000ea400001ee105 */
/*0470*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0480*/ @P0 BRA 0x440 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*04b0*/ LDS.64 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e220000000a00 */
/*04c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*04d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000e24000c1e1b00 */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, R8, PT ; /* 0x000000080600720c */
/* 0x001fc80003f06070 */
/*04f0*/ ISETP.GE.U32.AND.EX P0, PT, R7, R9, PT, P0 ; /* 0x000000090700720c */
/* 0x000fda0003f06100 */
/*0500*/ @!P0 STG.E.64 [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x000fe8000c101b06 */
/*0510*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64], RZ ; /* 0x000000ff02ff79a8 */
/* 0x000fe2000c1ee1c6 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_maximum_kernelPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 8
.type _Z19find_maximum_kernelPyS_Piy,@function
_Z19find_maximum_kernelPyS_Piy:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s11, exec_lo
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, s7
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s10
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 3
.p2align 6
.LBB0_2:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, s2, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s2, s9, v6, s2
v_cmp_le_u64_e64 s3, s[4:5], v[1:2]
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s12, s3, s12
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, v[3:4], v[7:8]
v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v3, v7, v3
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_lshlrev_b32_e32 v5, 3, v0
s_cmp_lt_u32 s10, 2
ds_store_b64 v5, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
s_lshr_b32 s2, s10, 1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_lshr_b64 s[2:3], s[2:3], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_10
.LBB0_7:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, v0, s2, 3
ds_load_b64 v[6:7], v5
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
ds_store_b64 v5, v[2:3]
s_branch .LBB0_6
.LBB0_10:
s_mov_b32 s4, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_12:
s_waitcnt lgkmcnt(0)
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_load_b64 v[3:4], v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[0:1]
s_cbranch_vccnz .LBB0_15
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_15:
global_atomic_swap_b32 v2, v2, s[2:3]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19find_maximum_kernelPyS_Piy
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19find_maximum_kernelPyS_Piy, .Lfunc_end0-_Z19find_maximum_kernelPyS_Piy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19find_maximum_kernelPyS_Piy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19find_maximum_kernelPyS_Piy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce53b_00000000-6_max_elem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
.type _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy, @function
_Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19find_maximum_kernelPyS_Piy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy, .-_Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.type _Z19find_maximum_kernelPyS_Piy, @function
_Z19find_maximum_kernelPyS_Piy:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z19find_maximum_kernelPyS_Piy, .-_Z19find_maximum_kernelPyS_Piy
.globl _Z18kernel_max_wrapperPyS_Piy
.type _Z18kernel_max_wrapperPyS_Piy, @function
_Z18kernel_max_wrapperPyS_Piy:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbx
leaq 1048575(%rcx), %rax
shrq $20, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z44__device_stub__Z19find_maximum_kernelPyS_PiyPyS_Piy
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z18kernel_max_wrapperPyS_Piy, .-_Z18kernel_max_wrapperPyS_Piy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size of array: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "----------------------------------------------------------"
.section .rodata.str1.1
.LC4:
.string "Max: "
.LC5:
.string "[CUDA] Elapsed time: "
.LC6:
.string " clock cycles"
.LC7:
.string "Starting sequential version."
.LC10:
.string "[SEQUENTIAL] Elapsed time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $20971520, 24(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 24(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi10_M_extractIyEERSiRT_@PLT
movq 24(%rsp), %rax
leaq 0(,%rax,8), %rdi
call malloc@PLT
movq %rax, %rbp
movl $8, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 24(%rsp), %rsi
testq %rsi, %rsi
je .L16
movl $0, %ebx
movabsq $-9223372036854775808, %r13
jmp .L21
.L17:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L18
.L19:
subsd .LC2(%rip), %xmm0
cvttsd2siq %xmm0, %rax
movq %rax, 0(%rbp,%rbx,8)
xorq %r13, 0(%rbp,%rbx,8)
.L20:
addq $1, %rbx
movq 24(%rsp), %rsi
cmpq %rsi, %rbx
jnb .L16
.L21:
call rand@PLT
cltq
testq %rax, %rax
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L18:
divsd .LC1(%rip), %xmm0
comisd .LC2(%rip), %xmm0
jnb .L19
cvttsd2siq %xmm0, %rax
movq %rax, 0(%rbp,%rbx,8)
jmp .L20
.L16:
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $8, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $4, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movq 24(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z18kernel_max_wrapperPyS_Piy
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC3(%rip), %r13
movq %r13, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r12), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 8(%rsp)
movq $0, (%r12)
movq 24(%rsp), %rdx
testq %rdx, %rdx
je .L22
movq %rbp, %rax
leaq 0(%rbp,%rdx,8), %rcx
jmp .L24
.L23:
addq $8, %rax
cmpq %rcx, %rax
je .L22
.L24:
movq (%rax), %rdx
cmpq %rdx, (%r12)
jnb .L23
movq %rdx, (%r12)
jmp .L23
.L22:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC8(%rip), %xmm0
mulsd .LC9(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %r14
movq %r14, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r12), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z19find_maximum_kernelPyS_Piy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z19find_maximum_kernelPyS_Piy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1745955581
.long 1059857858
.align 8
.LC2:
.long 0
.long 1138753536
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC9:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_elem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3f2c25c268112afd # double 2.147483647E-4
.LCPI0_3:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_5:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $20971520, (%rsp) # imm = 0x1400000
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractIyEERSiRT_
movq (%rsp), %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq (%rsp), %rsi
testq %rsi, %rsi
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %xmm0
punpckldq .LCPI0_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI0_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI0_2(%rip), %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
subsd .LCPI0_3(%rip), %xmm1
sarq $63, %rcx
cvttsd2si %xmm1, %rdx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, (%rbx,%r15,8)
incq %r15
movq (%rsp), %rsi
cmpq %rsi, %r15
jb .LBB0_2
.LBB0_3: # %._crit_edge
shlq $3, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $8, %edx
xorl %esi, %esi
callq hipMemset
movq 48(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movq 48(%rsp), %rdx
movq (%rsp), %rcx
callq _Z18kernel_max_wrapperPyS_Piy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movl $8, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_6
# %bb.5:
movzbl 67(%r15), %eax
jmp .LBB0_7
.LBB0_6:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_49
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r15)
je .LBB0_10
# %bb.9:
movzbl 67(%r15), %ecx
jmp .LBB0_11
.LBB0_10:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_49
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%r12)
je .LBB0_14
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB0_15
.LBB0_14:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r15)
je .LBB0_18
# %bb.17:
movzbl 67(%r15), %eax
jmp .LBB0_19
.LBB0_18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r15)
je .LBB0_22
# %bb.21:
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_22:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r15)
je .LBB0_26
# %bb.25:
movzbl 67(%r15), %eax
jmp .LBB0_27
.LBB0_26:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r15
movq $0, (%r14)
movq (%rsp), %rax
testq %rax, %rax
je .LBB0_32
# %bb.28: # %.lr.ph72
movq (%r14), %rdx
xorl %ecx, %ecx
jmp .LBB0_29
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_29 Depth=1
incq %rcx
cmpq %rcx, %rax
je .LBB0_32
.LBB0_29: # =>This Inner Loop Header: Depth=1
movq (%rbx,%rcx,8), %rsi
cmpq %rdx, %rsi
jbe .LBB0_31
# %bb.30: # in Loop: Header=BB0_29 Depth=1
movq %rsi, (%r14)
movq %rsi, %rdx
jmp .LBB0_31
.LBB0_32: # %._crit_edge73
callq clock
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB0_49
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r13)
je .LBB0_35
# %bb.34:
movzbl 67(%r13), %eax
jmp .LBB0_36
.LBB0_35:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB0_49
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cvtsi2sd %r15, %xmm0
cvtsi2sd %r12, %xmm1
subsd %xmm0, %xmm1
divsd .LCPI0_4(%rip), %xmm1
mulsd .LCPI0_5(%rip), %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
cmpb $0, 56(%r13)
je .LBB0_39
# %bb.38:
movzbl 67(%r13), %ecx
jmp .LBB0_40
.LBB0_39:
movq %r13, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_49
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB0_43
# %bb.42:
movzbl 67(%r12), %eax
jmp .LBB0_44
.LBB0_43:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_49
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r15)
je .LBB0_47
# %bb.46:
movzbl 67(%r15), %eax
jmp .LBB0_48
.LBB0_47:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_49:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z18kernel_max_wrapperPyS_Piy # -- Begin function _Z18kernel_max_wrapperPyS_Piy
.p2align 4, 0x90
.type _Z18kernel_max_wrapperPyS_Piy,@function
_Z18kernel_max_wrapperPyS_Piy: # @_Z18kernel_max_wrapperPyS_Piy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leaq 1048575(%rcx), %rax
shrq $20, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_maximum_kernelPyS_Piy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18kernel_max_wrapperPyS_Piy, .Lfunc_end1-_Z18kernel_max_wrapperPyS_Piy
.cfi_endproc
# -- End function
.globl _Z34__device_stub__find_maximum_kernelPyS_Piy # -- Begin function _Z34__device_stub__find_maximum_kernelPyS_Piy
.p2align 4, 0x90
.type _Z34__device_stub__find_maximum_kernelPyS_Piy,@function
_Z34__device_stub__find_maximum_kernelPyS_Piy: # @_Z34__device_stub__find_maximum_kernelPyS_Piy
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_maximum_kernelPyS_Piy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__find_maximum_kernelPyS_Piy, .Lfunc_end2-_Z34__device_stub__find_maximum_kernelPyS_Piy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19find_maximum_kernelPyS_Piy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size of array: "
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "----------------------------------------------------------"
.size .L.str.1, 59
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[CUDA] Elapsed time: "
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " clock cycles"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Starting sequential version."
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[SEQUENTIAL] Elapsed time: "
.size .L.str.6, 28
.type _Z19find_maximum_kernelPyS_Piy,@object # @_Z19find_maximum_kernelPyS_Piy
.section .rodata,"a",@progbits
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 3, 0x0
_Z19find_maximum_kernelPyS_Piy:
.quad _Z34__device_stub__find_maximum_kernelPyS_Piy
.size _Z19find_maximum_kernelPyS_Piy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19find_maximum_kernelPyS_Piy"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__find_maximum_kernelPyS_Piy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z19find_maximum_kernelPyS_Piy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) += Chze(mm, nn) * Ey1G(g1, mm + 1);
// correct Hz along right edge
mm = lastX;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) -= Chze(mm, nn) * Ey1G(g1, mm);*/
float Chze = S/377.0;
int m = firstX-1;
Hz(m, indx) = Hz(m, indx) + Chze * Ey1D[m+1];
m = lastX;
Hz(m, indx) = Hz(m, indx) - Chze * Ey1D[m];
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) += Chze(mm, nn) * Ey1G(g1, mm + 1);
// correct Hz along right edge
mm = lastX;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) -= Chze(mm, nn) * Ey1G(g1, mm);*/
float Chze = S/377.0;
int m = firstX-1;
Hz(m, indx) = Hz(m, indx) + Chze * Ey1D[m+1];
m = lastX;
Hz(m, indx) = Hz(m, indx) - Chze * Ey1D[m];
} | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) += Chze(mm, nn) * Ey1G(g1, mm + 1);
// correct Hz along right edge
mm = lastX;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) -= Chze(mm, nn) * Ey1G(g1, mm);*/
float Chze = S/377.0;
int m = firstX-1;
Hz(m, indx) = Hz(m, indx) + Chze * Ey1D[m+1];
m = lastX;
Hz(m, indx) = Hz(m, indx) - Chze * Ey1D[m];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) += Chze(mm, nn) * Ey1G(g1, mm + 1);
// correct Hz along right edge
mm = lastX;
for (nn = firstY; nn < lastY; nn++)
Hz(mm, nn) -= Chze(mm, nn) * Ey1G(g1, mm);*/
float Chze = S/377.0;
int m = firstX-1;
Hz(m, indx) = Hz(m, indx) + Chze * Ey1D[m+1];
m = lastX;
Hz(m, indx) = Hz(m, indx) - Chze * Ey1D[m];
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | code for sm_80
Function : _Z10multVectorPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fce0003f06270 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0207 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xca0 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R9, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0150*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0160*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0170*/ LEA R12, P1, R6.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a00060c7a11 */
/* 0x040fe400078210ff */
/*0180*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0190*/ LEA.HI.X R13, R6, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b00060d7a11 */
/* 0x000fc400008f1405 */
/*01a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc60000000f00 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea8000c1e1900 */
/*0220*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R11, R14, R11, R15 ; /* 0x0000000b0e0b7224 */
/* 0x004fc800078e020f */
/*0250*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fe200078e020c */
/*0260*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD R19, R16, R17, R11 ; /* 0x0000001110137224 */
/* 0x004fc400078e020b */
/*02a0*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*02c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*02d0*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ee4000c1e1900 */
/*02e0*/ IMAD R21, R12, R13, R19 ; /* 0x0000000d0c157224 */
/* 0x008fc400078e0213 */
/*02f0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0300*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0310*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0320*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c04040b7981 */
/* 0x002f22000c1e1900 */
/*0330*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0340*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0360*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0390*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*03a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*03b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*03c0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*03d0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*03e0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0400*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0440*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0450*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0480*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*04b0*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*04d0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*04e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*04f0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0500*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002404040b7981 */
/* 0x002f22000c1e1900 */
/*0510*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0520*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0530*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0570*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0580*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0590*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000ee4000c1e1900 */
/*05b0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*05c0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*05e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R11, [R4.64+0x30] ; /* 0x00003004040b7981 */
/* 0x002f22000c1e1900 */
/*0600*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0610*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0620*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0630*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000f24000c1e1900 */
/*0650*/ IMAD R23, R18, R16, R11 ; /* 0x0000001012177224 */
/* 0x010fc400078e020b */
/*0660*/ IMAD.WIDE R18, R10, 0x4, R14 ; /* 0x000000040a127825 */
/* 0x004fc600078e020e */
/*0670*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD R21, R16, R12, R23 ; /* 0x0000000c10157224 */
/* 0x008fc400078e0217 */
/*06c0*/ IMAD.WIDE R16, R10, 0x4, R18 ; /* 0x000000040a107825 */
/* 0x000fc600078e0212 */
/*06d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x0008e2000c1e1900 */
/*0700*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0710*/ IADD3 R11, P2, R4, 0x40, RZ ; /* 0x00000040040b7810 */
/* 0x002fc40007f5e0ff */
/*0720*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3.X R14, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe400017fe4ff */
/*0740*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x010fe40000000f00 */
/*0750*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R15, R12, R15, R21 ; /* 0x0000000f0c0f7224 */
/* 0x008fe400078e0215 */
/*0770*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e2000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*07f0*/ IMAD R19, R10, R14, R15 ; /* 0x0000000e0a137224 */
/* 0x008fc800078e020f */
/*0800*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x004fe200078e020c */
/*0810*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0820*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ IMAD R21, R10, R16, R19 ; /* 0x000000100a157224 */
/* 0x004fc400078e0213 */
/*0850*/ IMAD.WIDE R16, R11, 0x4, R14 ; /* 0x000000040b107825 */
/* 0x000fc600078e020e */
/*0860*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0870*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ee8000c1e1900 */
/*0880*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee4000c1e1900 */
/*0890*/ IMAD R23, R10, R12, R21 ; /* 0x0000000c0a177224 */
/* 0x008fc400078e0215 */
/*08a0*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*08b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*08c0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000f28000c1e1900 */
/*08d0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f22000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fc800078e020c */
/*08f0*/ IMAD R25, R10, R18, R23 ; /* 0x000000120a197224 */
/* 0x010fca00078e0217 */
/*0900*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0009e8000c101904 */
/*0910*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x002fc800078e020e */
/*0940*/ IMAD R21, R10, R16, R25 ; /* 0x000000100a157224 */
/* 0x004fca00078e0219 */
/*0950*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0960*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*0980*/ IMAD R23, R10, R12, R21 ; /* 0x0000000c0a177224 */
/* 0x008fc400078e0215 */
/*0990*/ IMAD.WIDE R12, R11, 0x4, R18 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0212 */
/*09a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09b0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000f22000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R11, 0x4, R12 ; /* 0x000000040b107825 */
/* 0x000fc800078e020c */
/*09e0*/ IMAD R25, R10, R14, R23 ; /* 0x0000000e0a197224 */
/* 0x010fca00078e0217 */
/*09f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a00*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R15, [R4.64+0x1c] ; /* 0x00001c04040f7981 */
/* 0x000ea2000c1e1900 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fe200078e0210 */
/*0a40*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0a60*/ IMAD R15, R10, R15, R25 ; /* 0x0000000f0a0f7224 */
/* 0x004fe200078e0219 */
/*0a70*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0a80*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0a90*/ IADD3.X R19, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff137210 */
/* 0x000fe40000ffe4ff */
/*0aa0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0ab0*/ MOV R5, R19 ; /* 0x0000001300057202 */
/* 0x000fe40000000f00 */
/*0ac0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xca0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*0b10*/ IMAD R21, R10, R14, R15 ; /* 0x0000000e0a157224 */
/* 0x00efc800078e020f */
/*0b20*/ IMAD.WIDE R14, R11.reuse, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x040fe200078e020c */
/*0b30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0b40*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0b50*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc800078e020e */
/*0b70*/ IMAD R23, R10, R16, R21 ; /* 0x000000100a177224 */
/* 0x004fca00078e0215 */
/*0b80*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0bc0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc60007ffe0ff */
/*0bd0*/ IMAD R25, R10, R12, R23 ; /* 0x0000000c0a197224 */
/* 0x004fca00078e0217 */
/*0be0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0bf0*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0c20*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0c30*/ IMAD R15, R10, R12, R25 ; /* 0x0000000c0a0f7224 */
/* 0x004fe200078e0219 */
/*0c40*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f3e0ff */
/*0c50*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0c60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0c70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0c80*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0c90*/ @P0 BRA 0xae0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0ca0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0cb0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cc0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0207 */
/*0cd0*/ IMAD R6, R8, c[0x0][0x17c], R6 ; /* 0x00005f0008067a24 */
/* 0x000fe200078e0206 */
/*0ce0*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0cf0*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0d00*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0d10*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0d20*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000722000c1e1900 */
/*0d30*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0d40*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0d50*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0d70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d80*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0d90*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x008fc600078e0204 */
/*0da0*/ IADD3.X R10, RZ, R10, RZ, P1, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fe20000ffe4ff */
/*0db0*/ IMAD R15, R8, R6, R15 ; /* 0x00000006080f7224 */
/* 0x016fca00078e020f */
/*0dc0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0dd0*/ @P0 BRA 0xd10 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0de0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .file "tmpxft_00058c63_00000000-6_multVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multVectorPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.type _Z10multVectorPiS_S_ii, @function
_Z10multVectorPiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10multVectorPiS_S_ii, .-_Z10multVectorPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10multVectorPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multVectorPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multVectorPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.p2align 8
.type _Z10multVectorPiS_S_ii,@function
_Z10multVectorPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_cmp_lt_i32 s5, 1
global_store_b32 v[3:4], v5, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v0, v[3:4], off
s_load_b128 s[0:3], s[0:1], 0x0
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v2, v5, s[0:1]
global_load_b32 v8, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v6 :: v_dual_add_nc_u32 v1, s4, v1
global_store_b32 v[3:4], v6, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multVectorPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multVectorPiS_S_ii, .Lfunc_end0-_Z10multVectorPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multVectorPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multVectorPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .text
.file "multVector.hip"
.globl _Z25__device_stub__multVectorPiS_S_ii # -- Begin function _Z25__device_stub__multVectorPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__multVectorPiS_S_ii,@function
_Z25__device_stub__multVectorPiS_S_ii: # @_Z25__device_stub__multVectorPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multVectorPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multVectorPiS_S_ii, .Lfunc_end0-_Z25__device_stub__multVectorPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multVectorPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10multVectorPiS_S_ii,@object # @_Z10multVectorPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10multVectorPiS_S_ii
.p2align 3, 0x0
_Z10multVectorPiS_S_ii:
.quad _Z25__device_stub__multVectorPiS_S_ii
.size _Z10multVectorPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10multVectorPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multVectorPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10multVectorPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10multVectorPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fce0003f06270 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0207 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xca0 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R9, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0150*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0160*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0170*/ LEA R12, P1, R6.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a00060c7a11 */
/* 0x040fe400078210ff */
/*0180*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0190*/ LEA.HI.X R13, R6, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b00060d7a11 */
/* 0x000fc400008f1405 */
/*01a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc60000000f00 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea8000c1e1900 */
/*0220*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R11, R14, R11, R15 ; /* 0x0000000b0e0b7224 */
/* 0x004fc800078e020f */
/*0250*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fe200078e020c */
/*0260*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD R19, R16, R17, R11 ; /* 0x0000001110137224 */
/* 0x004fc400078e020b */
/*02a0*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*02c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*02d0*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ee4000c1e1900 */
/*02e0*/ IMAD R21, R12, R13, R19 ; /* 0x0000000d0c157224 */
/* 0x008fc400078e0213 */
/*02f0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0300*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0310*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0320*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c04040b7981 */
/* 0x002f22000c1e1900 */
/*0330*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0340*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0360*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0390*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*03a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*03b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*03c0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*03d0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*03e0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0400*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0440*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0450*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0480*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*04b0*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*04d0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*04e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*04f0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0500*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002404040b7981 */
/* 0x002f22000c1e1900 */
/*0510*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0520*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0530*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R19, R18, R16, R11 ; /* 0x0000001012137224 */
/* 0x004fc400078e020b */
/*0570*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0580*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0590*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000ee4000c1e1900 */
/*05b0*/ IMAD R21, R18, R12, R19 ; /* 0x0000000c12157224 */
/* 0x008fc400078e0213 */
/*05c0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*05e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R11, [R4.64+0x30] ; /* 0x00003004040b7981 */
/* 0x002f22000c1e1900 */
/*0600*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0610*/ IMAD R11, R18, R11, R21 ; /* 0x0000000b120b7224 */
/* 0x010fca00078e0215 */
/*0620*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0630*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000f24000c1e1900 */
/*0650*/ IMAD R23, R18, R16, R11 ; /* 0x0000001012177224 */
/* 0x010fc400078e020b */
/*0660*/ IMAD.WIDE R18, R10, 0x4, R14 ; /* 0x000000040a127825 */
/* 0x004fc600078e020e */
/*0670*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD R21, R16, R12, R23 ; /* 0x0000000c10157224 */
/* 0x008fc400078e0217 */
/*06c0*/ IMAD.WIDE R16, R10, 0x4, R18 ; /* 0x000000040a107825 */
/* 0x000fc600078e0212 */
/*06d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x0008e2000c1e1900 */
/*0700*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0710*/ IADD3 R11, P2, R4, 0x40, RZ ; /* 0x00000040040b7810 */
/* 0x002fc40007f5e0ff */
/*0720*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3.X R14, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe400017fe4ff */
/*0740*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x010fe40000000f00 */
/*0750*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R15, R12, R15, R21 ; /* 0x0000000f0c0f7224 */
/* 0x008fe400078e0215 */
/*0770*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e2000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*07f0*/ IMAD R19, R10, R14, R15 ; /* 0x0000000e0a137224 */
/* 0x008fc800078e020f */
/*0800*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x004fe200078e020c */
/*0810*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0820*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ IMAD R21, R10, R16, R19 ; /* 0x000000100a157224 */
/* 0x004fc400078e0213 */
/*0850*/ IMAD.WIDE R16, R11, 0x4, R14 ; /* 0x000000040b107825 */
/* 0x000fc600078e020e */
/*0860*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0870*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ee8000c1e1900 */
/*0880*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee4000c1e1900 */
/*0890*/ IMAD R23, R10, R12, R21 ; /* 0x0000000c0a177224 */
/* 0x008fc400078e0215 */
/*08a0*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*08b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*08c0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000f28000c1e1900 */
/*08d0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f22000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fc800078e020c */
/*08f0*/ IMAD R25, R10, R18, R23 ; /* 0x000000120a197224 */
/* 0x010fca00078e0217 */
/*0900*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0009e8000c101904 */
/*0910*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x002fc800078e020e */
/*0940*/ IMAD R21, R10, R16, R25 ; /* 0x000000100a157224 */
/* 0x004fca00078e0219 */
/*0950*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0960*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*0980*/ IMAD R23, R10, R12, R21 ; /* 0x0000000c0a177224 */
/* 0x008fc400078e0215 */
/*0990*/ IMAD.WIDE R12, R11, 0x4, R18 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0212 */
/*09a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09b0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000f22000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R11, 0x4, R12 ; /* 0x000000040b107825 */
/* 0x000fc800078e020c */
/*09e0*/ IMAD R25, R10, R14, R23 ; /* 0x0000000e0a197224 */
/* 0x010fca00078e0217 */
/*09f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a00*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R15, [R4.64+0x1c] ; /* 0x00001c04040f7981 */
/* 0x000ea2000c1e1900 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fe200078e0210 */
/*0a40*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0a60*/ IMAD R15, R10, R15, R25 ; /* 0x0000000f0a0f7224 */
/* 0x004fe200078e0219 */
/*0a70*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0a80*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0a90*/ IADD3.X R19, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff137210 */
/* 0x000fe40000ffe4ff */
/*0aa0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0ab0*/ MOV R5, R19 ; /* 0x0000001300057202 */
/* 0x000fe40000000f00 */
/*0ac0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xca0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*0b10*/ IMAD R21, R10, R14, R15 ; /* 0x0000000e0a157224 */
/* 0x00efc800078e020f */
/*0b20*/ IMAD.WIDE R14, R11.reuse, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x040fe200078e020c */
/*0b30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0b40*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0b50*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc800078e020e */
/*0b70*/ IMAD R23, R10, R16, R21 ; /* 0x000000100a177224 */
/* 0x004fca00078e0215 */
/*0b80*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0bc0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc60007ffe0ff */
/*0bd0*/ IMAD R25, R10, R12, R23 ; /* 0x0000000c0a197224 */
/* 0x004fca00078e0217 */
/*0be0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0bf0*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0c20*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0c30*/ IMAD R15, R10, R12, R25 ; /* 0x0000000c0a0f7224 */
/* 0x004fe200078e0219 */
/*0c40*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f3e0ff */
/*0c50*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0c60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0c70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0c80*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0c90*/ @P0 BRA 0xae0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0ca0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0cb0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cc0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0207 */
/*0cd0*/ IMAD R6, R8, c[0x0][0x17c], R6 ; /* 0x00005f0008067a24 */
/* 0x000fe200078e0206 */
/*0ce0*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0cf0*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0d00*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0d10*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0d20*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000722000c1e1900 */
/*0d30*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0d40*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0d50*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0d70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d80*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0d90*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x008fc600078e0204 */
/*0da0*/ IADD3.X R10, RZ, R10, RZ, P1, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fe20000ffe4ff */
/*0db0*/ IMAD R15, R8, R6, R15 ; /* 0x00000006080f7224 */
/* 0x016fca00078e020f */
/*0dc0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0dd0*/ @P0 BRA 0xd10 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0de0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multVectorPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.p2align 8
.type _Z10multVectorPiS_S_ii,@function
_Z10multVectorPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_cmp_lt_i32 s5, 1
global_store_b32 v[3:4], v5, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v0, v[3:4], off
s_load_b128 s[0:3], s[0:1], 0x0
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v2, v5, s[0:1]
global_load_b32 v8, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v6 :: v_dual_add_nc_u32 v1, s4, v1
global_store_b32 v[3:4], v6, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multVectorPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multVectorPiS_S_ii, .Lfunc_end0-_Z10multVectorPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multVectorPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multVectorPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058c63_00000000-6_multVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multVectorPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.type _Z10multVectorPiS_S_ii, @function
_Z10multVectorPiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10multVectorPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10multVectorPiS_S_ii, .-_Z10multVectorPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10multVectorPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multVectorPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multVector.hip"
.globl _Z25__device_stub__multVectorPiS_S_ii # -- Begin function _Z25__device_stub__multVectorPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__multVectorPiS_S_ii,@function
_Z25__device_stub__multVectorPiS_S_ii: # @_Z25__device_stub__multVectorPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multVectorPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multVectorPiS_S_ii, .Lfunc_end0-_Z25__device_stub__multVectorPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multVectorPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10multVectorPiS_S_ii,@object # @_Z10multVectorPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10multVectorPiS_S_ii
.p2align 3, 0x0
_Z10multVectorPiS_S_ii:
.quad _Z25__device_stub__multVectorPiS_S_ii
.size _Z10multVectorPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10multVectorPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multVectorPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10multVectorPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
cudaTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} | code for sm_80
Function : _Z17downSanple420_gpuyyPsS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fc600078e0203 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe40003f26070 */
/*0090*/ SHF.R.S32.HI R4, RZ, 0x1f, R0 ; /* 0x0000001fff047819 */
/* 0x000fe40000011400 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*00c0*/ ISETP.GE.U32.AND.EX P1, PT, R4, c[0x0][0x18c], PT, P1 ; /* 0x0000630004007a0c */
/* 0x000fc80003f26110 */
/*00d0*/ ISETP.GE.U32.OR.EX P0, PT, R3, c[0x0][0x184], P1, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0000f06500 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*0120*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe2000f8e00ff */
/*0130*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff0d7424 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.U64 R7, R7, 0x1, R4.reuse ; /* 0x0000000107077819 */
/* 0x100fe40000001204 */
/*0170*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011604 */
/*0180*/ I2F R15, R8 ; /* 0x00000008000f7306 */
/* 0x000e620000201400 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc80003f04070 */
/*01a0*/ ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ; /* 0x000000030400720c */
/* 0x000fc80003f04100 */
/*01b0*/ SEL R3, R7, RZ, !P0 ; /* 0x000000ff07037207 */
/* 0x000fe20004000000 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x001fe200078e0005 */
/*01d0*/ SEL R12, R12, c[0x0][0x168], P0 ; /* 0x00005a000c0c7a07 */
/* 0x000fc60000000000 */
/*01e0*/ IMAD.IADD R3, R2, 0x1, -R3 ; /* 0x0000000102037824 */
/* 0x000fe400078e0a03 */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x002fe400078e000f */
/*0200*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fc800078e00ff */
/*0210*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e220000201400 */
/*0220*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fce0007ffe0ff */
/*0230*/ I2F R6, R2 ; /* 0x0000000200067306 */
/* 0x000e620000201400 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e0004 */
/*0250*/ TEX.SCR.B.LL RZ, R4, R4, R12, 2D, 0x1 ; /* 0x3800000c04047361 */
/* 0x040f4200019e01ff */
/*0260*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x002fe200078e0006 */
/*0270*/ TEX.SCR.B.LL RZ, R7, R6, R12, 2D, 0x1 ; /* 0x3800000c06077361 */
/* 0x00016200019e01ff */
/*0280*/ TEX.SCR.B.LL RZ, R8, R14, R12, 2D, 0x1 ; /* 0x3800000c0e087361 */
/* 0x000f6400019e01ff */
/*0290*/ TEX.SCR.B.LL RZ, R9, R16, R12, 2D, 0x1 ; /* 0x3800000c10097361 */
/* 0x100f4200019e01ff */
/*02a0*/ SHF.R.S32.HI R11, RZ, 0x1, R0 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011400 */
/*02b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02c0*/ SHF.R.S32.HI R2, RZ, 0x1, R3 ; /* 0x00000001ff027819 */
/* 0x000fe40000011403 */
/*02d0*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fe4000001140b */
/*02e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc60000011402 */
/*02f0*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe400078e02ff */
/*0300*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x180], R2 ; /* 0x000060000b027a25 */
/* 0x000fc800078e0002 */
/*0310*/ IMAD R11, R11, c[0x0][0x184], R0 ; /* 0x000061000b0b7a24 */
/* 0x000fe400078e0200 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD.IADD R3, R3, 0x1, R11 ; /* 0x0000000103037824 */
/* 0x000fc600078e020b */
/*0340*/ SEL R6, R6, c[0x0][0x17c], P0 ; /* 0x00005f0006067a07 */
/* 0x000fe20000000000 */
/*0350*/ DEPBAR.LE SB5, 0x1 ; /* 0x0000d0400000791a */
/* 0x000fc80000000000 */
/*0360*/ PRMT R10, R4, 0x9910, RZ ; /* 0x00009910040a7816 */
/* 0x000fca00000000ff */
/*0370*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fe200078e000a */
/*0380*/ PRMT R5, R7, 0x9910, RZ ; /* 0x0000991007057816 */
/* 0x000fe200000000ff */
/*0390*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fe200078e00ff */
/*03a0*/ PRMT R4, R8, 0x9910, RZ ; /* 0x0000991008047816 */
/* 0x000fe400000000ff */
/*03b0*/ PRMT R9, R9, 0x9910, RZ ; /* 0x0000991009097816 */
/* 0x020fe400000000ff */
/*03c0*/ IADD3 R5, R4, R0, R5 ; /* 0x0000000004057210 */
/* 0x000fe40007ffe005 */
/*03d0*/ SEL R7, R7, c[0x0][0x178], P0 ; /* 0x00005e0007077a07 */
/* 0x000fe20000000000 */
/*03e0*/ IMAD.MOV.U32 R0, RZ, RZ, R9 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0009 */
/*03f0*/ LEA R4, P0, R2.reuse, R7, 0x1 ; /* 0x0000000702047211 */
/* 0x040fe400078008ff */
/*0400*/ IADD3 R0, R5, 0x1, R0 ; /* 0x0000000105007810 */
/* 0x000fe40007ffe000 */
/*0410*/ LEA.HI.X R5, R2, R6, R3, 0x1, P0 ; /* 0x0000000602057211 */
/* 0x000fe400000f0c03 */
/*0420*/ SHF.R.U32.HI R3, RZ, 0x2, R0 ; /* 0x00000002ff037819 */
/* 0x000fca0000011600 */
/*0430*/ STG.E.U16 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101504 */
/*0440*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0450*/ BRA 0x450; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
cudaTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} | .file "tmpxft_00061730_00000000-6_downSanple420_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.type _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, @function
_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, .-_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.globl _Z17downSanple420_gpuyyPsS_mm
.type _Z17downSanple420_gpuyyPsS_mm, @function
_Z17downSanple420_gpuyyPsS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17downSanple420_gpuyyPsS_mm, .-_Z17downSanple420_gpuyyPsS_mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17downSanple420_gpuyyPsS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
cudaTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
hipTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
hipTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 8
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[16:17], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, s14, s4, v[1:2]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[16:17], v[14:15]
s_cbranch_execz .LBB0_19
s_load_b32 s4, s[2:3], 0xc
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_lshl_u32 v12, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[12:13]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b256 s[4:11], s[0:1], 0x0
s_lshr_b64 s[0:1], s[16:17], 1
v_alignbit_b32 v18, s17, s16, 1
v_cmp_gt_u64_e64 s0, s[0:1], v[14:15]
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v18, v18, 0, s0
v_sub_nc_u32_e32 v18, v14, v18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s9 :: v_dual_mov_b32 v1, s5
v_mov_b32_e32 v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v17, s11, v0, s0
v_cndmask_b32_e64 v9, s7, v1, s0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v8, s6, v2, s0
s_clause 0x6
global_load_b32 v13, v[8:9], off offset:8
global_load_b32 v15, v[8:9], off offset:48
global_load_b32 v16, v[8:9], off offset:40
global_load_b32 v19, v[8:9], off offset:56
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[8:9], off offset:48
global_load_b128 v[8:11], v[8:9], off offset:16
s_waitcnt vmcnt(6)
v_bfe_u32 v13, v13, 14, 14
s_waitcnt vmcnt(4)
v_cvt_f32_u32_e32 v14, v16
v_and_b32_e32 v15, 0x8000, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 1, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v13, v13
v_dual_cndmask_b32 v16, 1.0, v14 :: v_dual_cndmask_b32 v21, 1.0, v13
v_cvt_f32_i32_e32 v13, v12
v_lshlrev_b32_e32 v15, 1, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v20, v16
v_mul_f32_e32 v14, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v23, v15
v_floor_f32_e32 v14, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v24, v16, v23
v_rcp_f32_e32 v22, v21
s_waitcnt vmcnt(3)
v_and_b32_e32 v19, 0x100000, v19
v_floor_f32_e32 v24, v24
s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v25, s8 :: v_dual_mul_f32 v24, v20, v24
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, v22, v14
v_cmp_eq_u32_e32 vcc_lo, 0, v19
v_cndmask_b32_e64 v19, s10, v25, s0
s_delay_alu instid0(VALU_DEP_3)
v_dual_cndmask_b32 v14, v13, v14 :: v_dual_cndmask_b32 v13, v23, v24
s_set_inst_prefetch_distance 0x1
s_waitcnt vmcnt(0)
.LBB0_3:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_4:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v23, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_4
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s18
v_or_b32_e32 v15, 1, v15
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v15, v15
v_mul_f32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v16, v16
v_mul_f32_e32 v16, v20, v16
s_waitcnt vmcnt(0)
v_bfe_i32 v20, v23, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v15, v15, v16 :: v_dual_mov_b32 v16, v14
s_set_inst_prefetch_distance 0x1
.LBB0_7:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_8:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_8
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s18
v_or_b32_e32 v16, 1, v12
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v16, v16
v_mul_f32_e32 v21, v21, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v21, v21
v_mul_f32_e32 v22, v22, v21
s_waitcnt vmcnt(0)
v_bfe_i32 v21, v14, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v14, v16, v22, vcc_lo
s_set_inst_prefetch_distance 0x1
.LBB0_11:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_12:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v16, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_12
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_11
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s3
s_waitcnt vmcnt(0)
v_bfe_i32 v13, v16, 0, 16
v_mov_b32_e32 v16, v14
s_mov_b32 s3, exec_lo
s_set_inst_prefetch_distance 0x1
.LBB0_15:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_16:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_16
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_15
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s3
v_ashrrev_i32_e32 v2, 1, v12
v_add3_u32 v5, v20, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_lo_u32 v4, v2, s17
v_mad_u64_u32 v[0:1], null, v2, s16, 0
v_bfe_i32 v2, v18, 0, 31
v_mul_lo_u32 v3, v3, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v1, v4, v3
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_bfe_i32 v4, v14, 0, 16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v4, v5, v4, 1
v_add_co_u32 v0, vcc_lo, v19, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
v_lshrrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoord.y << 1) < height)
{
int2 pixelCoord;
hipTextureObject_t *ch;
int16_t *downCh;
// Remember thread divergence happens at the wrap level only, that will parallelize well
if (threadCoord.x < (width >> 1))
{
pixelCoord = make_int2(threadCoord.x << 1, threadCoord.y << 1);
ch = &ch1;
downCh = downCh1;
}
else
{
pixelCoord = make_int2((threadCoord.x - (width >> 1)) << 1, threadCoord.y << 1);
ch = &ch2;
downCh = downCh2;
}
int16_t bias = (pixelCoord.x & 1) + 1;
int16_t pixel = (tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y)
+ tex2D<int16_t>(*ch, pixelCoord.x, pixelCoord.y + 1) + tex2D<int16_t>(*ch, pixelCoord.x + 1, pixelCoord.y + 1) + bias) >> 2;
downCh[(pixelCoord.y >> 1) * width + (pixelCoord.x >> 1)] = pixel;
}
} | .text
.file "downSanple420_gpu.hip"
.globl _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm # -- Begin function _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 4, 0x90
.type _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm: # @_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@object # @_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.section .rodata,"a",@progbits
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 3, 0x0
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
.quad _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17downSanple420_gpuyyPsS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fc600078e0203 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe40003f26070 */
/*0090*/ SHF.R.S32.HI R4, RZ, 0x1f, R0 ; /* 0x0000001fff047819 */
/* 0x000fe40000011400 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*00c0*/ ISETP.GE.U32.AND.EX P1, PT, R4, c[0x0][0x18c], PT, P1 ; /* 0x0000630004007a0c */
/* 0x000fc80003f26110 */
/*00d0*/ ISETP.GE.U32.OR.EX P0, PT, R3, c[0x0][0x184], P1, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0000f06500 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*0120*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe2000f8e00ff */
/*0130*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff0d7424 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.U64 R7, R7, 0x1, R4.reuse ; /* 0x0000000107077819 */
/* 0x100fe40000001204 */
/*0170*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011604 */
/*0180*/ I2F R15, R8 ; /* 0x00000008000f7306 */
/* 0x000e620000201400 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc80003f04070 */
/*01a0*/ ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ; /* 0x000000030400720c */
/* 0x000fc80003f04100 */
/*01b0*/ SEL R3, R7, RZ, !P0 ; /* 0x000000ff07037207 */
/* 0x000fe20004000000 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x001fe200078e0005 */
/*01d0*/ SEL R12, R12, c[0x0][0x168], P0 ; /* 0x00005a000c0c7a07 */
/* 0x000fc60000000000 */
/*01e0*/ IMAD.IADD R3, R2, 0x1, -R3 ; /* 0x0000000102037824 */
/* 0x000fe400078e0a03 */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x002fe400078e000f */
/*0200*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fc800078e00ff */
/*0210*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e220000201400 */
/*0220*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fce0007ffe0ff */
/*0230*/ I2F R6, R2 ; /* 0x0000000200067306 */
/* 0x000e620000201400 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e0004 */
/*0250*/ TEX.SCR.B.LL RZ, R4, R4, R12, 2D, 0x1 ; /* 0x3800000c04047361 */
/* 0x040f4200019e01ff */
/*0260*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x002fe200078e0006 */
/*0270*/ TEX.SCR.B.LL RZ, R7, R6, R12, 2D, 0x1 ; /* 0x3800000c06077361 */
/* 0x00016200019e01ff */
/*0280*/ TEX.SCR.B.LL RZ, R8, R14, R12, 2D, 0x1 ; /* 0x3800000c0e087361 */
/* 0x000f6400019e01ff */
/*0290*/ TEX.SCR.B.LL RZ, R9, R16, R12, 2D, 0x1 ; /* 0x3800000c10097361 */
/* 0x100f4200019e01ff */
/*02a0*/ SHF.R.S32.HI R11, RZ, 0x1, R0 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011400 */
/*02b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02c0*/ SHF.R.S32.HI R2, RZ, 0x1, R3 ; /* 0x00000001ff027819 */
/* 0x000fe40000011403 */
/*02d0*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fe4000001140b */
/*02e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc60000011402 */
/*02f0*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe400078e02ff */
/*0300*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x180], R2 ; /* 0x000060000b027a25 */
/* 0x000fc800078e0002 */
/*0310*/ IMAD R11, R11, c[0x0][0x184], R0 ; /* 0x000061000b0b7a24 */
/* 0x000fe400078e0200 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD.IADD R3, R3, 0x1, R11 ; /* 0x0000000103037824 */
/* 0x000fc600078e020b */
/*0340*/ SEL R6, R6, c[0x0][0x17c], P0 ; /* 0x00005f0006067a07 */
/* 0x000fe20000000000 */
/*0350*/ DEPBAR.LE SB5, 0x1 ; /* 0x0000d0400000791a */
/* 0x000fc80000000000 */
/*0360*/ PRMT R10, R4, 0x9910, RZ ; /* 0x00009910040a7816 */
/* 0x000fca00000000ff */
/*0370*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fe200078e000a */
/*0380*/ PRMT R5, R7, 0x9910, RZ ; /* 0x0000991007057816 */
/* 0x000fe200000000ff */
/*0390*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fe200078e00ff */
/*03a0*/ PRMT R4, R8, 0x9910, RZ ; /* 0x0000991008047816 */
/* 0x000fe400000000ff */
/*03b0*/ PRMT R9, R9, 0x9910, RZ ; /* 0x0000991009097816 */
/* 0x020fe400000000ff */
/*03c0*/ IADD3 R5, R4, R0, R5 ; /* 0x0000000004057210 */
/* 0x000fe40007ffe005 */
/*03d0*/ SEL R7, R7, c[0x0][0x178], P0 ; /* 0x00005e0007077a07 */
/* 0x000fe20000000000 */
/*03e0*/ IMAD.MOV.U32 R0, RZ, RZ, R9 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0009 */
/*03f0*/ LEA R4, P0, R2.reuse, R7, 0x1 ; /* 0x0000000702047211 */
/* 0x040fe400078008ff */
/*0400*/ IADD3 R0, R5, 0x1, R0 ; /* 0x0000000105007810 */
/* 0x000fe40007ffe000 */
/*0410*/ LEA.HI.X R5, R2, R6, R3, 0x1, P0 ; /* 0x0000000602057211 */
/* 0x000fe400000f0c03 */
/*0420*/ SHF.R.U32.HI R3, RZ, 0x2, R0 ; /* 0x00000002ff037819 */
/* 0x000fca0000011600 */
/*0430*/ STG.E.U16 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101504 */
/*0440*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0450*/ BRA 0x450; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 8
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[16:17], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, s14, s4, v[1:2]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[16:17], v[14:15]
s_cbranch_execz .LBB0_19
s_load_b32 s4, s[2:3], 0xc
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_lshl_u32 v12, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[12:13]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b256 s[4:11], s[0:1], 0x0
s_lshr_b64 s[0:1], s[16:17], 1
v_alignbit_b32 v18, s17, s16, 1
v_cmp_gt_u64_e64 s0, s[0:1], v[14:15]
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v18, v18, 0, s0
v_sub_nc_u32_e32 v18, v14, v18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s9 :: v_dual_mov_b32 v1, s5
v_mov_b32_e32 v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v17, s11, v0, s0
v_cndmask_b32_e64 v9, s7, v1, s0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v8, s6, v2, s0
s_clause 0x6
global_load_b32 v13, v[8:9], off offset:8
global_load_b32 v15, v[8:9], off offset:48
global_load_b32 v16, v[8:9], off offset:40
global_load_b32 v19, v[8:9], off offset:56
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[8:9], off offset:48
global_load_b128 v[8:11], v[8:9], off offset:16
s_waitcnt vmcnt(6)
v_bfe_u32 v13, v13, 14, 14
s_waitcnt vmcnt(4)
v_cvt_f32_u32_e32 v14, v16
v_and_b32_e32 v15, 0x8000, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 1, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v13, v13
v_dual_cndmask_b32 v16, 1.0, v14 :: v_dual_cndmask_b32 v21, 1.0, v13
v_cvt_f32_i32_e32 v13, v12
v_lshlrev_b32_e32 v15, 1, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v20, v16
v_mul_f32_e32 v14, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v23, v15
v_floor_f32_e32 v14, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v24, v16, v23
v_rcp_f32_e32 v22, v21
s_waitcnt vmcnt(3)
v_and_b32_e32 v19, 0x100000, v19
v_floor_f32_e32 v24, v24
s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v25, s8 :: v_dual_mul_f32 v24, v20, v24
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, v22, v14
v_cmp_eq_u32_e32 vcc_lo, 0, v19
v_cndmask_b32_e64 v19, s10, v25, s0
s_delay_alu instid0(VALU_DEP_3)
v_dual_cndmask_b32 v14, v13, v14 :: v_dual_cndmask_b32 v13, v23, v24
s_set_inst_prefetch_distance 0x1
s_waitcnt vmcnt(0)
.LBB0_3:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_4:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v23, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_4
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s18
v_or_b32_e32 v15, 1, v15
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v15, v15
v_mul_f32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v16, v16
v_mul_f32_e32 v16, v20, v16
s_waitcnt vmcnt(0)
v_bfe_i32 v20, v23, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v15, v15, v16 :: v_dual_mov_b32 v16, v14
s_set_inst_prefetch_distance 0x1
.LBB0_7:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_8:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_8
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s18
v_or_b32_e32 v16, 1, v12
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v16, v16
v_mul_f32_e32 v21, v21, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v21, v21
v_mul_f32_e32 v22, v22, v21
s_waitcnt vmcnt(0)
v_bfe_i32 v21, v14, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v14, v16, v22, vcc_lo
s_set_inst_prefetch_distance 0x1
.LBB0_11:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_12:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v16, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_12
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_11
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s3
s_waitcnt vmcnt(0)
v_bfe_i32 v13, v16, 0, 16
v_mov_b32_e32 v16, v14
s_mov_b32 s3, exec_lo
s_set_inst_prefetch_distance 0x1
.LBB0_15:
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_16:
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_16
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_15
s_set_inst_prefetch_distance 0x2
s_mov_b32 exec_lo, s3
v_ashrrev_i32_e32 v2, 1, v12
v_add3_u32 v5, v20, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_lo_u32 v4, v2, s17
v_mad_u64_u32 v[0:1], null, v2, s16, 0
v_bfe_i32 v2, v18, 0, 31
v_mul_lo_u32 v3, v3, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v1, v4, v3
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_bfe_i32 v4, v14, 0, 16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v4, v5, v4, 1
v_add_co_u32 v0, vcc_lo, v19, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
v_lshrrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061730_00000000-6_downSanple420_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.type _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, @function
_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, .-_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.globl _Z17downSanple420_gpuyyPsS_mm
.type _Z17downSanple420_gpuyyPsS_mm, @function
_Z17downSanple420_gpuyyPsS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17downSanple420_gpuyyPsS_mm, .-_Z17downSanple420_gpuyyPsS_mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17downSanple420_gpuyyPsS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "downSanple420_gpu.hip"
.globl _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm # -- Begin function _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 4, 0x90
.type _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm: # @_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@object # @_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.section .rodata,"a",@progbits
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 3, 0x0
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
.quad _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
cudaDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(cudaMallocManaged((void**)&fb, fb_size));
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
cudaDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(cudaMallocManaged((void**)&fb, fb_size));
return 0;
} | .file "tmpxft_0008c7bb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error = "
.LC1:
.string " at "
.LC2:
.string ":"
.LC3:
.string " '"
.LC4:
.string "' \n"
.text
.globl _Z10check_cuda9cudaErrorPKcS1_i
.type _Z10check_cuda9cudaErrorPKcS1_i, @function
_Z10check_cuda9cudaErrorPKcS1_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call cudaDeviceReset@PLT
movl $99, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10check_cuda9cudaErrorPKcS1_i, .-_Z10check_cuda9cudaErrorPKcS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Snowapril/CudaPlayground/main/Examples/RayTracer/main.cu"
.align 8
.LC6:
.string "cudaMallocManaged((void**)&fb, fb_size)"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $3145728, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $24, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
call _Z10check_cuda9cudaErrorPKcS1_i
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
cudaDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(cudaMallocManaged((void**)&fb, fb_size));
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
hipDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(hipMallocManaged((void**)&fb, fb_size));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
hipDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(hipMallocManaged((void**)&fb, fb_size));
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
//! Make sure we call CUDA device reset before exiting
hipDeviceReset();
exit(99);
}
}
int main(int argc, char* argv[])
{
int nx = 512, ny = 512;
int numPixels = nx * ny;
size_t fb_size = 3 * numPixels * sizeof(float);
//! Allocates the frame buffer
float* fb;
checkCudaErrors(hipMallocManaged((void**)&fb, fb_size));
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10check_cuda10hipError_tPKcS1_i # -- Begin function _Z10check_cuda10hipError_tPKcS1_i
.p2align 4, 0x90
.type _Z10check_cuda10hipError_tPKcS1_i,@function
_Z10check_cuda10hipError_tPKcS1_i: # @_Z10check_cuda10hipError_tPKcS1_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
movl $_ZSt4cerr, %edi
movq %rsi, %rbx
movl $.L.str, %esi
movl %ecx, %ebp
movq %rdx, %r15
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r14d, %esi
callq _ZNSolsEj
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r15, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
callq hipDeviceReset
movl $99, %edi
callq exit
.Lfunc_end0:
.size _Z10check_cuda10hipError_tPKcS1_i, .Lfunc_end0-_Z10check_cuda10hipError_tPKcS1_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $3145728, %esi # imm = 0x300000
movl $1, %edx
callq hipMallocManaged
movl $.L.str.5, %esi
movl $.L.str.6, %edx
movl %eax, %edi
movl $26, %ecx
callq _Z10check_cuda10hipError_tPKcS1_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error = "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " at "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ":"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " '"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "' \n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMallocManaged((void**)&fb, fb_size)"
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Snowapril/CudaPlayground/main/Examples/RayTracer/main.hip"
.size .L.str.6, 115
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008c7bb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error = "
.LC1:
.string " at "
.LC2:
.string ":"
.LC3:
.string " '"
.LC4:
.string "' \n"
.text
.globl _Z10check_cuda9cudaErrorPKcS1_i
.type _Z10check_cuda9cudaErrorPKcS1_i, @function
_Z10check_cuda9cudaErrorPKcS1_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call cudaDeviceReset@PLT
movl $99, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10check_cuda9cudaErrorPKcS1_i, .-_Z10check_cuda9cudaErrorPKcS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Snowapril/CudaPlayground/main/Examples/RayTracer/main.cu"
.align 8
.LC6:
.string "cudaMallocManaged((void**)&fb, fb_size)"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $3145728, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $24, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
call _Z10check_cuda9cudaErrorPKcS1_i
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10check_cuda10hipError_tPKcS1_i # -- Begin function _Z10check_cuda10hipError_tPKcS1_i
.p2align 4, 0x90
.type _Z10check_cuda10hipError_tPKcS1_i,@function
_Z10check_cuda10hipError_tPKcS1_i: # @_Z10check_cuda10hipError_tPKcS1_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
movl $_ZSt4cerr, %edi
movq %rsi, %rbx
movl $.L.str, %esi
movl %ecx, %ebp
movq %rdx, %r15
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r14d, %esi
callq _ZNSolsEj
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r15, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
callq hipDeviceReset
movl $99, %edi
callq exit
.Lfunc_end0:
.size _Z10check_cuda10hipError_tPKcS1_i, .Lfunc_end0-_Z10check_cuda10hipError_tPKcS1_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $3145728, %esi # imm = 0x300000
movl $1, %edx
callq hipMallocManaged
movl $.L.str.5, %esi
movl $.L.str.6, %edx
movl %eax, %edi
movl $26, %ecx
callq _Z10check_cuda10hipError_tPKcS1_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error = "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " at "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ":"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " '"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "' \n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMallocManaged((void**)&fb, fb_size)"
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Snowapril/CudaPlayground/main/Examples/RayTracer/main.hip"
.size .L.str.6, 115
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//Contents of the A matrix should already be in U
//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!
// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//Elimination step
int istart = ( k + 1 ) + tx * ops_per_thread;
int iend = istart + ops_per_thread;
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;
//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}
//Don't sync, will sync outside here
} | .file "tmpxft_00055097_00000000-6_chol_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11chol_kernelPfiPfi
.type _Z32__device_stub__Z11chol_kernelPfiPfi, @function
_Z32__device_stub__Z11chol_kernelPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11chol_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11chol_kernelPfiPfi, .-_Z32__device_stub__Z11chol_kernelPfiPfi
.globl _Z11chol_kernelPfi
.type _Z11chol_kernelPfi, @function
_Z11chol_kernelPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11chol_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11chol_kernelPfi, .-_Z11chol_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11chol_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11chol_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//Contents of the A matrix should already be in U
//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!
// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//Elimination step
int istart = ( k + 1 ) + tx * ops_per_thread;
int iend = istart + ops_per_thread;
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;
//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}
//Don't sync, will sync outside here
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//Contents of the A matrix should already be in U
//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!
// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//Elimination step
int istart = ( k + 1 ) + tx * ops_per_thread;
int iend = istart + ops_per_thread;
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;
//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}
//Don't sync, will sync outside here
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//Contents of the A matrix should already be in U
//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!
// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//Elimination step
int istart = ( k + 1 ) + tx * ops_per_thread;
int iend = istart + ops_per_thread;
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;
//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}
//Don't sync, will sync outside here
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11chol_kernelPfi
.globl _Z11chol_kernelPfi
.p2align 8
.type _Z11chol_kernelPfi,@function
_Z11chol_kernelPfi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s12, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_movk_i32 s1, 0x801
s_mov_b32 s5, 0
s_mov_b32 s13, -1
s_mov_b32 s14, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_add_u32 s6, s2, 4
s_addc_u32 s7, s3, 0
v_mul_lo_u32 v0, v1, s12
v_cmp_eq_u32_e64 s0, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, s12, v0
v_mad_u64_u32 v[2:3], null, v0, s1, 0x801
v_dual_mov_b32 v12, v0 :: v_dual_add_nc_u32 v11, 1, v0
v_mov_b32_e32 v13, v10
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v13, 1, v13
s_add_i32 s13, s13, 1
v_add_nc_u32_e32 v12, 1, v12
v_add_nc_u32_e32 v11, 0x801, v11
v_add_nc_u32_e32 v2, 0x801, v2
s_add_u32 s6, s6, 0x2004
s_addc_u32 s7, s7, 0
s_cmpk_lg_i32 s4, 0x800
s_mov_b32 s14, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_2:
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_5
s_mul_i32 s4, s14, 0x801
s_mov_b64 s[10:11], s[6:7]
s_lshl_b64 s[8:9], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s2, s8
s_addc_u32 s9, s3, s9
s_cmpk_gt_u32 s14, 0x7fe
global_load_b32 v3, v4, s[8:9]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_sqrt_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v5, v3
v_fma_f32 v9, -v7, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s1, 0, v8
v_cndmask_b32_e64 v5, v5, v6, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s1, 0, v9
v_cndmask_b32_e64 v5, v5, v7, s1
s_mov_b32 s1, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
global_store_b32 v4, v3, s[8:9]
s_cbranch_scc1 .LBB0_5
.p2align 6
.LBB0_4:
s_clause 0x1
global_load_b32 v3, v4, s[8:9]
global_load_b32 v5, v4, s[10:11]
s_add_i32 s1, s1, 1
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v3, v3, v5
v_div_scale_f32 v9, vcc_lo, v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v14, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v14, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_div_fixup_f32 v3, v6, v3, v5
global_store_b32 v4, v3, s[10:11]
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmpk_lt_u32 s1, 0x7fe
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
s_add_i32 s4, s14, 1
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v14, s4, v0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v3, s12, v14
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v14, v3
s_cbranch_execz .LBB0_1
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v16, v12
v_mov_b32_e32 v15, v11
s_lshl_b32 s9, s14, 11
s_mov_b32 s10, 0
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v3, 1, v14
v_cmp_eq_u32_e32 vcc_lo, v14, v13
v_add_nc_u32_e32 v16, 1, v16
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v14, v3 :: v_dual_add_nc_u32 v5, 0x801, v5
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_1
.LBB0_8:
s_mov_b32 s11, exec_lo
v_cmpx_gt_u32_e32 0x800, v14
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v15
v_or_b32_e32 v7, s9, v14
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[17:18], 2, v[5:6]
v_mov_b32_e32 v8, v6
v_add_co_u32 v6, vcc_lo, s2, v17
v_mov_b32_e32 v17, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v18, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
.p2align 6
.LBB0_10:
v_lshlrev_b64 v[18:19], 2, v[3:4]
global_load_b32 v20, v[8:9], off
global_load_b32 v21, v[6:7], off
v_add_nc_u32_e32 v17, 1, v17
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_lt_u32_e32 vcc_lo, 0x7fe, v17
global_load_b32 v18, v[18:19], off
s_or_b32 s14, vcc_lo, s14
s_waitcnt vmcnt(0)
v_fma_f32 v18, -v20, v18, v21
global_store_b32 v[6:7], v18, off
v_add_co_u32 v6, s1, v6, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s1, 0, v7, s1
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_10
s_branch .LBB0_7
.LBB0_11:
v_mul_lo_u32 v2, v1, s12
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_add_nc_u32_e32 v0, s12, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v2, v0
s_cbranch_execz .LBB0_17
v_mul_lo_u32 v0, v1, s12
v_mov_b32_e32 v1, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 11, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_14
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v3, 0x800, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, v2, v10
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_17
.LBB0_14:
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_13
s_mov_b32 s5, 0
s_mov_b32 s6, 0
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s6, v3
s_add_i32 s6, s6, 1
v_cmp_ge_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_or_b32 s5, vcc_lo, s5
v_add_co_u32 v4, s0, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
global_store_b32 v[4:5], v1, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_16
s_branch .LBB0_13
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11chol_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11chol_kernelPfi, .Lfunc_end0-_Z11chol_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11chol_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11chol_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//Contents of the A matrix should already be in U
//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!
// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//Elimination step
int istart = ( k + 1 ) + tx * ops_per_thread;
int iend = istart + ops_per_thread;
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}
//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;
//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}
//Don't sync, will sync outside here
} | .text
.file "chol_kernel.hip"
.globl _Z26__device_stub__chol_kernelPfi # -- Begin function _Z26__device_stub__chol_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__chol_kernelPfi,@function
_Z26__device_stub__chol_kernelPfi: # @_Z26__device_stub__chol_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11chol_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__chol_kernelPfi, .Lfunc_end0-_Z26__device_stub__chol_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11chol_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11chol_kernelPfi,@object # @_Z11chol_kernelPfi
.section .rodata,"a",@progbits
.globl _Z11chol_kernelPfi
.p2align 3, 0x0
_Z11chol_kernelPfi:
.quad _Z26__device_stub__chol_kernelPfi
.size _Z11chol_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11chol_kernelPfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__chol_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11chol_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00055097_00000000-6_chol_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11chol_kernelPfiPfi
.type _Z32__device_stub__Z11chol_kernelPfiPfi, @function
_Z32__device_stub__Z11chol_kernelPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11chol_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11chol_kernelPfiPfi, .-_Z32__device_stub__Z11chol_kernelPfiPfi
.globl _Z11chol_kernelPfi
.type _Z11chol_kernelPfi, @function
_Z11chol_kernelPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11chol_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11chol_kernelPfi, .-_Z11chol_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11chol_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11chol_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "chol_kernel.hip"
.globl _Z26__device_stub__chol_kernelPfi # -- Begin function _Z26__device_stub__chol_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__chol_kernelPfi,@function
_Z26__device_stub__chol_kernelPfi: # @_Z26__device_stub__chol_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11chol_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__chol_kernelPfi, .Lfunc_end0-_Z26__device_stub__chol_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11chol_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11chol_kernelPfi,@object # @_Z11chol_kernelPfi
.section .rodata,"a",@progbits
.globl _Z11chol_kernelPfi
.p2align 3, 0x0
_Z11chol_kernelPfi:
.quad _Z26__device_stub__chol_kernelPfi
.size _Z11chol_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11chol_kernelPfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__chol_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11chol_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
cudaMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
cudaDeviceSynchronize();
cudaMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
cudaFree(d_mat_A); cudaFree(d_mat_B); cudaFree(d_mat_C);
delete[] h_mat_C;
return 0;
} | code for sm_80
Function : _Z20matrixMultiplicationPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R3, 0x3e7, P0 ; /* 0x000003e70300780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, 0x3e8, R0 ; /* 0x000003e803037824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R0, 0x3e8, RZ ; /* 0x000003e800047824 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fca0000000a00 */
/*0100*/ IMAD.WIDE R2, R3, R5, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0205 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0130*/ IADD3 R10, P0, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R11, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0b7210 */
/* 0x001fe400007fe4ff */
/*0150*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0160*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0170*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fc800078e0206 */
/*01a0*/ LDG.E R11, [R4.64+-0x10] ; /* 0xfffff004040b7981 */
/* 0x004ea8000c1e1900 */
/*01b0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x024fca0000000009 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R10, [R6.64+0xfa0] ; /* 0x000fa004060a7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R9, [R4.64+-0xc] ; /* 0xfffff40404097981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FFMA R9, R10, R9, R11 ; /* 0x000000090a097223 */
/* 0x004fca000000000b */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R10, [R6.64+0x1f40] ; /* 0x001f4004060a7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R12, [R4.64+-0x8] ; /* 0xfffff804040c7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0250*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0260*/ LDG.E R10, [R6.64+0x2ee0] ; /* 0x002ee004060a7981 */
/* 0x000e28000c1e1900 */
/*0270*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc04040c7981 */
/* 0x000e24000c1e1900 */
/*0280*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R10, [R6.64+0x3e80] ; /* 0x003e8004060a7981 */
/* 0x000e68000c1e1900 */
/*02b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000e64000c1e1900 */
/*02c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R10, [R6.64+0x4e20] ; /* 0x004e2004060a7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R10, [R6.64+0x5dc0] ; /* 0x005dc004060a7981 */
/* 0x000e28000c1e1900 */
/*0330*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000e24000c1e1900 */
/*0340*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R10, [R6.64+0x6d60] ; /* 0x006d6004060a7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0390*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*03a0*/ LDG.E R10, [R6.64+0x7d00] ; /* 0x007d0004060a7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*03d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R10, [R6.64+0x8ca0] ; /* 0x008ca004060a7981 */
/* 0x000e28000c1e1900 */
/*03f0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000e24000c1e1900 */
/*0400*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0410*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0420*/ LDG.E R10, [R6.64+0x9c40] ; /* 0x009c4004060a7981 */
/* 0x000e68000c1e1900 */
/*0430*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000e64000c1e1900 */
/*0440*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R10, [R6.64+0xabe0] ; /* 0x00abe004060a7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c04040c7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0490*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R10, [R6.64+0xbb80] ; /* 0x00bb8004060a7981 */
/* 0x000e28000c1e1900 */
/*04b0*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000e24000c1e1900 */
/*04c0*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*04d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R10, [R6.64+0xcb20] ; /* 0x00cb2004060a7981 */
/* 0x000e68000c1e1900 */
/*04f0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000e64000c1e1900 */
/*0500*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R10, [R6.64+0xdac0] ; /* 0x00dac004060a7981 */
/* 0x000ea8000c1e1900 */
/*0530*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000ea4000c1e1900 */
/*0540*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0550*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0560*/ LDG.E R10, [R6.64+0xea60] ; /* 0x00ea6004060a7981 */
/* 0x000e28000c1e1900 */
/*0570*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000e24000c1e1900 */
/*0580*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0590*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R10, [R6.64+0xfa00] ; /* 0x00fa0004060a7981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000e64000c1e1900 */
/*05c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*05d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R10, [R6.64+0x109a0] ; /* 0x0109a004060a7981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0610*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R10, [R6.64+0x11940] ; /* 0x01194004060a7981 */
/* 0x000e28000c1e1900 */
/*0630*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000e24000c1e1900 */
/*0640*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0650*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0660*/ LDG.E R10, [R6.64+0x128e0] ; /* 0x0128e004060a7981 */
/* 0x000e68000c1e1900 */
/*0670*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000e64000c1e1900 */
/*0680*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0690*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*06a0*/ LDG.E R10, [R6.64+0x13880] ; /* 0x01388004060a7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R12, [R4.64+0x40] ; /* 0x00004004040c7981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*06d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R10, [R6.64+0x14820] ; /* 0x01482004060a7981 */
/* 0x000e28000c1e1900 */
/*06f0*/ LDG.E R12, [R4.64+0x44] ; /* 0x00004404040c7981 */
/* 0x000e24000c1e1900 */
/*0700*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0710*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0720*/ LDG.E R10, [R6.64+0x157c0] ; /* 0x0157c004060a7981 */
/* 0x000e68000c1e1900 */
/*0730*/ LDG.E R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x000e64000c1e1900 */
/*0740*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0750*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0760*/ LDG.E R10, [R6.64+0x16760] ; /* 0x01676004060a7981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R12, [R4.64+0x4c] ; /* 0x00004c04040c7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0790*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*07a0*/ LDG.E R10, [R6.64+0x17700] ; /* 0x01770004060a7981 */
/* 0x000e28000c1e1900 */
/*07b0*/ LDG.E R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x000e24000c1e1900 */
/*07c0*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*07d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*07e0*/ LDG.E R10, [R6.64+0x186a0] ; /* 0x0186a004060a7981 */
/* 0x000e68000c1e1900 */
/*07f0*/ LDG.E R12, [R4.64+0x54] ; /* 0x00005404040c7981 */
/* 0x000e64000c1e1900 */
/*0800*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0810*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0820*/ LDG.E R10, [R6.64+0x19640] ; /* 0x01964004060a7981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R12, [R4.64+0x58] ; /* 0x00005804040c7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0850*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0860*/ LDG.E R10, [R6.64+0x1a5e0] ; /* 0x01a5e004060a7981 */
/* 0x000e28000c1e1900 */
/*0870*/ LDG.E R12, [R4.64+0x5c] ; /* 0x00005c04040c7981 */
/* 0x000e24000c1e1900 */
/*0880*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0890*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*08a0*/ LDG.E R10, [R6.64+0x1b580] ; /* 0x01b58004060a7981 */
/* 0x000e68000c1e1900 */
/*08b0*/ LDG.E R12, [R4.64+0x60] ; /* 0x00006004040c7981 */
/* 0x000e64000c1e1900 */
/*08c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*08d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*08e0*/ LDG.E R10, [R6.64+0x1c520] ; /* 0x01c52004060a7981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R12, [R4.64+0x64] ; /* 0x00006404040c7981 */
/* 0x000ea4000c1e1900 */
/*0900*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0910*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0920*/ LDG.E R10, [R6.64+0x1d4c0] ; /* 0x01d4c004060a7981 */
/* 0x000ee8000c1e1900 */
/*0930*/ LDG.E R12, [R4.64+0x68] ; /* 0x00006804040c7981 */
/* 0x000ee4000c1e1900 */
/*0940*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0950*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe8000c101904 */
/*0960*/ LDG.E R10, [R6.64+0x1e460] ; /* 0x01e46004060a7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R11, [R4.64+0x6c] ; /* 0x00006c04040b7981 */
/* 0x001ee4000c1e1900 */
/*0980*/ FFMA R17, R10, R11, R15 ; /* 0x0000000b0a117223 */
/* 0x008fca000000000f */
/*0990*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe8000c101904 */
/*09a0*/ LDG.E R9, [R6.64+0x1f400] ; /* 0x01f4000406097981 */
/* 0x002ee8000c1e1900 */
/*09b0*/ LDG.E R10, [R4.64+0x70] ; /* 0x00007004040a7981 */
/* 0x000ee4000c1e1900 */
/*09c0*/ FFMA R9, R9, R10, R17 ; /* 0x0000000a09097223 */
/* 0x008fca0000000011 */
/*09d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R10, [R6.64+0x203a0] ; /* 0x0203a004060a7981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R11, [R4.64+0x74] ; /* 0x00007404040b7981 */
/* 0x000ee4000c1e1900 */
/*0a00*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x008fca0000000009 */
/*0a10*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R10, [R6.64+0x21340] ; /* 0x02134004060a7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R4.64+0x78] ; /* 0x00007804040c7981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0a50*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0a60*/ LDG.E R10, [R6.64+0x222e0] ; /* 0x0222e004060a7981 */
/* 0x000e28000c1e1900 */
/*0a70*/ LDG.E R12, [R4.64+0x7c] ; /* 0x00007c04040c7981 */
/* 0x000e24000c1e1900 */
/*0a80*/ FFMA R9, R10, R12, R13 ; /* 0x0000000c0a097223 */
/* 0x001fca000000000d */
/*0a90*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0aa0*/ LDG.E R10, [R6.64+0x23280] ; /* 0x02328004060a7981 */
/* 0x000e68000c1e1900 */
/*0ab0*/ LDG.E R12, [R4.64+0x80] ; /* 0x00008004040c7981 */
/* 0x000e64000c1e1900 */
/*0ac0*/ FFMA R11, R10, R12, R9 ; /* 0x0000000c0a0b7223 */
/* 0x002fca0000000009 */
/*0ad0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R10, [R6.64+0x24220] ; /* 0x02422004060a7981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R12, [R4.64+0x84] ; /* 0x00008404040c7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0b10*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0b20*/ LDG.E R10, [R6.64+0x251c0] ; /* 0x0251c004060a7981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R12, [R4.64+0x88] ; /* 0x00008804040c7981 */
/* 0x000ee2000c1e1900 */
/*0b40*/ IADD3 R8, R8, 0x28, RZ ; /* 0x0000002808087810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0b60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0b70*/ LDG.E R10, [R6.64+0x26160] ; /* 0x02616004060a7981 */
/* 0x000ee8000c1e1900 */
/*0b80*/ LDG.E R9, [R4.64+0x8c] ; /* 0x00008c0404097981 */
/* 0x001ee2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R8, 0x3e8, PT ; /* 0x000003e80800780c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x27100, URZ ; /* 0x0002710006067890 */
/* 0x000fc8000ff1e03f */
/*0bb0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bc0*/ FFMA R9, R10, R9, R15 ; /* 0x000000090a097223 */
/* 0x008fe2000000000f */
/*0bd0*/ IADD3 R10, P1, R4, 0xa0, RZ ; /* 0x000000a0040a7810 */
/* 0x000fc80007f3e0ff */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*0bf0*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fe20000ffe4ff */
/*0c00*/ @P0 BRA 0x150 ; /* 0xfffff54000000947 */
/* 0x000fea000383ffff */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14allocateMemoryPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x3e7, PT ; /* 0x000003e70300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3e7, P0 ; /* 0x000003e70000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, 0x3e8, R3 ; /* 0x000003e800007824 */
/* 0x000fe200078e0203 */
/*00c0*/ MOV R7, 0x40b00000 ; /* 0x40b0000000077802 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
cudaMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
cudaDeviceSynchronize();
cudaMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
cudaFree(d_mat_A); cudaFree(d_mat_B); cudaFree(d_mat_C);
delete[] h_mat_C;
return 0;
} | .file "tmpxft_0015e87d_00000000-6_matrix_multiplication_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14allocateMemoryPfS_PfS_
.type _Z36__device_stub__Z14allocateMemoryPfS_PfS_, @function
_Z36__device_stub__Z14allocateMemoryPfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14allocateMemoryPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z14allocateMemoryPfS_PfS_, .-_Z36__device_stub__Z14allocateMemoryPfS_PfS_
.globl _Z14allocateMemoryPfS_
.type _Z14allocateMemoryPfS_, @function
_Z14allocateMemoryPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14allocateMemoryPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14allocateMemoryPfS_, .-_Z14allocateMemoryPfS_
.globl _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
.type _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_, @function
_Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20matrixMultiplicationPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_, .-_Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.type _Z20matrixMultiplicationPfS_S_, @function
_Z20matrixMultiplicationPfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z20matrixMultiplicationPfS_S_, .-_Z20matrixMultiplicationPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.8f \t"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $256, 32(%rsp)
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $40, 44(%rsp)
movl $2500, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbp
leaq 20000(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L23
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4000, %rbp
cmpq %r15, %rbp
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14allocateMemoryPfS_PfS_
jmp .L20
.L29:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20matrixMultiplicationPfS_S_"
.section .rodata.str1.1
.LC3:
.string "_Z14allocateMemoryPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplicationPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14allocateMemoryPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
cudaMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
cudaMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
cudaDeviceSynchronize();
cudaMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
cudaFree(d_mat_A); cudaFree(d_mat_B); cudaFree(d_mat_C);
delete[] h_mat_C;
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
hipMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
hipDeviceSynchronize();
hipMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
hipFree(d_mat_A); hipFree(d_mat_B); hipFree(d_mat_C);
delete[] h_mat_C;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
hipMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
hipDeviceSynchronize();
hipMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
hipFree(d_mat_A); hipFree(d_mat_B); hipFree(d_mat_C);
delete[] h_mat_C;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14allocateMemoryPfS_
.globl _Z14allocateMemoryPfS_
.p2align 8
.type _Z14allocateMemoryPfS_,@function
_Z14allocateMemoryPfS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x3e8, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, 0x3e8, v[1:2]
v_mov_b32_e32 v4, 0x40b00000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14allocateMemoryPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14allocateMemoryPfS_, .Lfunc_end0-_Z14allocateMemoryPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20matrixMultiplicationPfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.p2align 8
.type _Z20matrixMultiplicationPfS_S_,@function
_Z20matrixMultiplicationPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, 0x3e8, v[0:1]
v_mul_lo_u32 v5, v0, 0x3e8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v4, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x3e8, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0xfa0
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v1, v7
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplicationPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20matrixMultiplicationPfS_S_, .Lfunc_end1-_Z20matrixMultiplicationPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14allocateMemoryPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14allocateMemoryPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplicationPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplicationPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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