system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Write a CUDA program to compute the sum of two arrays. Input: Number of elements in the array. Output: Array of sums
// Used the Error Handler function written by Dr. Rama in his Colab shared to us on google classroom
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#define HANDLE_E... | .text
.file "p2.hip"
.globl _Z24__device_stub__sumArraysPiS_S_ # -- Begin function _Z24__device_stub__sumArraysPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPiS_S_,@function
_Z24__device_stub__sumArraysPiS_S_: # @_Z24__device_stub__sumArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_off... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sumArraysPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumArraysPiS_S_
.globl _Z9sumArraysPiS_S_
.p2align 8
.type _Z9sumArraysPiS_S_,@function
_Z9sumArraysPiS_S_:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, n@rel32@lo+4
s_addc_u32 s3, s3, n@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_waitc... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000a25b_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 1... | .text
.file "p2.hip"
.globl _Z24__device_stub__sumArraysPiS_S_ # -- Begin function _Z24__device_stub__sumArraysPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPiS_S_,@function
_Z24__device_stub__sumArraysPiS_S_: # @_Z24__device_stub__sumArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_off... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[... | code for sm_80
Function : _Z4prodiPffS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[... | .file "tmpxft_000a8735_00000000-6_vec_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[... | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sommeiPfS_S_
.globl _Z5sommeiPfS_S_
.p2align 8
.type _Z5sommeiPfS_S_,@function
_Z5sommeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void somme( int taille, float * a, float * b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index>=taille) return;
c[index]=a[index]+b[index];
}
__global__ void prod( int taille, float * a, float b, float *c ){
int index=threadIdx.x+blockDim.x*blockIdx.x;
if(index... | .text
.file "vec_sum.hip"
.globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_
.p2align 4, 0x90
.type _Z20__device_stub__sommeiPfS_S_,@function
_Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4prodiPffS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sommeiPfS_S_
.globl _Z5sommeiPfS_S_
.p2align 8
.type _Z5sommeiPfS_S_,@function
_Z5sommeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu i... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8735_00000000-6_vec_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "vec_sum.hip"
.globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_
.p2align 4, 0x90
.type _Z20__device_stub__sommeiPfS_S_,@function
_Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------... | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels ----------------------------------------... | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels -----------... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels -----------... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Gpu_HistogramPjS_ji
.globl _Z13Gpu_HistogramPjS_ji
.p2align 8
.type _Z13Gpu_HistogramPjS_ji,@function
_Z13Gpu_HistogramPjS_ji:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1],... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstring>
#include <thrust/device_vector.h>
// ---------------------------------------------------------------------------------------------------------------------------
// -------------------------------------------------- Kernels -----------... | .text
.file "radix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Gpu_HistogramPjS_ji # -- Begin function _Z28__device_stub__Gpu_HistogramPjS_ji
.p2... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Gpu_HistogramPjS_ji
.globl _Z13Gpu_HistogramPjS_ji
.p2align 8
.type _Z13Gpu_HistogramPjS_ji,@function
_Z13Gpu_HistogramPjS_ji:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1],... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}... | code for sm_80
Function : _Z7printerv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}... | .file "tmpxft_000c1f69_00000000-6_printing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <stdio.h>
void check_cuda_errors()
{
cudaError_t rc;
rc = cudaGetLastError();
if (rc != cudaSuccess)
{
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
}... | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void check_cuda_errors()
{
hipError_t rc;
rc = hipGetLastError();
if (rc != hipSuccess)
{
printf("Last CUDA error %s\n", ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Prints Thread ID of each thread
* What to observe/ponder:
* - Any trends on how the thread IDs are printed?
* - Why are they printed like so?
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void check_cuda_errors()
{
hipError_t rc;
rc = hipGetLastError();
if (rc != hipSuccess)
{
printf("Last CUDA error %s\n", ... | .text
.file "printing.hip"
.globl _Z17check_cuda_errorsv # -- Begin function _Z17check_cuda_errorsv
.p2align 4, 0x90
.type _Z17check_cuda_errorsv,@function
_Z17check_cuda_errorsv: # @_Z17check_cuda_errorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %ea... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1f69_00000000-6_printing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "printing.hip"
.globl _Z17check_cuda_errorsv # -- Begin function _Z17check_cuda_errorsv
.p2align 4, 0x90
.type _Z17check_cuda_errorsv,@function
_Z17check_cuda_errorsv: # @_Z17check_cuda_errorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %ea... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k... | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k... | .file "tmpxft_0007658d_00000000-6_matmul2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the output MatrixMulKernel
int k... | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b3... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define Width 32
#define TILE_WIDTH 16
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int ncols){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float PValue = 0; //PValue is used to store element of the... | .text
.file "matmul2.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b3... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007658d_00000000-6_matmul2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "matmul2.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int... | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int... | .file "tmpxft_00005f0e_00000000-6_vectorAdd_um_prefetch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAdd(int *a, int *b, int *c, int... | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAd... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAd... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This program computer the sum of two N-element vectors using unified memory
// By: Nick from CoffeeBeforeArch
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>
#include <iostream>
using std::cout;
// CUDA kernel for vector addition
// No change when using CUDA unified memory
__global__ void vectorAd... | .text
.file "vectorAdd_um_prefetch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddP... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005f0e_00000000-6_vectorAdd_um_prefetch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi... | .text
.file "vectorAdd_um_prefetch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddP... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[i... | code for sm_80
Function : _Z4axpyfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[i... | .file "tmpxft_0019c537_00000000-6_multiAxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec[idx] + yVec[i... | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyfPfS_
.globl _Z4axpyfPfS_
.p2align 8
.type _Z4axpyfPfS_,@function
_Z4axpyfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__global__ void axpy(float a, float *xVec, float *yVec){
//block.Idx.x, threadIdx.x, blockDim.x
int subID;
for(subID=0; subID < 8; subID++){
int idx = subID +(threadIdx.x*8) + blockIdx.x*(blockDim.x*8);
yVec[idx] = a*xVec... | .text
.file "multiAxpy.hip"
.globl _Z19__device_stub__axpyfPfS_ # -- Begin function _Z19__device_stub__axpyfPfS_
.p2align 4, 0x90
.type _Z19__device_stub__axpyfPfS_,@function
_Z19__device_stub__axpyfPfS_: # @_Z19__device_stub__axpyfPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4axpyfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyfPfS_
.globl _Z4axpyfPfS_
.p2align 8
.type _Z4axpyfPfS_,@function
_Z4axpyfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c537_00000000-6_multiAxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "multiAxpy.hip"
.globl _Z19__device_stub__axpyfPfS_ # -- Begin function _Z19__device_stub__axpyfPfS_
.p2align 4, 0x90
.type _Z19__device_stub__axpyfPfS_,@function
_Z19__device_stub__axpyfPfS_: # @_Z19__device_stub__axpyfPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const u... | code for sm_80
Function : _Z3modPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2200000025... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const u... | .file "tmpxft_0010dbdf_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * array2,int * array3)
{
const u... | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * a... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
////////////////////////OPERATIONS//////////////////////////////////////////////
//ADD=1
__global__ void add(int * array1,int * a... | .text
.file "assignment.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3modPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2200000025... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010dbdf_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "assignment.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; ... | code for sm_80
Function : _Z20TiledMatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; ... | .file "tmpxft_00103500_00000000-6_tiledMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; ... | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = b... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = b... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20TiledMatrixMulKernelPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 8
.type _Z20TiledMatrixMulKernelPfS_S_iii,@function
_Z20TiledMatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void TiledMatrixMulKernel(float* M, float* N, float* P, int j, int k, int l)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = b... | .text
.file "tiledMatMul.hip"
.globl _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii # -- Begin function _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii,@function
_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii: # @_Z35__device_stub__TiledMatrix... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20TiledMatrixMulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20TiledMatrixMulKernelPfS_S_iii
.globl _Z20TiledMatrixMulKernelPfS_S_iii
.p2align 8
.type _Z20TiledMatrixMulKernelPfS_S_iii,@function
_Z20TiledMatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103500_00000000-6_tiledMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "tiledMatMul.hip"
.globl _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii # -- Begin function _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__TiledMatrixMulKernelPfS_S_iii,@function
_Z35__device_stub__TiledMatrixMulKernelPfS_S_iii: # @_Z35__device_stub__TiledMatrix... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 9... | code for sm_80
Function : _Z16kernel_checkHashPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS;
const int CHARACTER_SET = 9... | #include <hip/hip_runtime.h>
#include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <ctime>
#include <iostream>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <cmath>
#include <locale.h>
const int PWD_LENGTH = 4;
const int HASH_LENGTH = 64;
const int NUM_BLOCKS = 64;
const int NUM_THREADS = 256;
const int KERNEL_SIZE = NUM_BLOCKS * NUM_THREADS... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19kernel_createPwdTryiPc
.globl _Z19kernel_createPwdTryiPc
.p2align 8
.type _Z19kernel_createPwdTryiPc,@function
_Z19kernel_createPwdTryiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_w... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kernel_checkHashPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19kernel_createPwdTryiPc
.globl _Z19kernel_createPwdTryiPc
.p2align 8
.type _Z19kernel_createPwdTryiPc,@function
_Z19kernel_createPwdTryiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_w... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long lo... | code for sm_80
Function : _Z19find_maximum_kernelPyS_Piy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long lo... | .file "tmpxft_000ce53b_00000000-6_max_elem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long lo... | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *ma... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *ma... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_maximum_kernelPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 8
.type _Z19find_maximum_kernelPyS_Piy,@function
_Z19find_maximum_kernelPyS_Piy:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0,... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdlib.h>
#include <ctime>
using namespace std;
void kernel_max_wrapper(unsigned long long *arr, unsigned long long *max, int *mtx, unsigned long long int N);
__global__ void find_maximum_kernel(unsigned long long *arr, unsigned long long *ma... | .text
.file "max_elem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function mai... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19find_maximum_kernelPyS_Piy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_maximum_kernelPyS_Piy
.globl _Z19find_maximum_kernelPyS_Piy
.p2align 8
.type _Z19find_maximum_kernelPyS_Piy,@function
_Z19find_maximum_kernelPyS_Piy:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0,... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce53b_00000000-6_max_elem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... | .text
.file "max_elem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function mai... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = f... | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/*mm = firstX - 1;
for (nn = f... | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* HzUpdater.cpp
*
* Created on: 01 февр. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "HzUpdater.h"
#include "SmartIndex.h"
// indx - индекс вдоль правой или левой границы по y от firstY до lastY
__host__ __device__
void HzUpdater::operator() (const int indx) {
// correct Hz along left edge
/... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | code for sm_80
Function : _Z10multVectorPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .file "tmpxft_00058c63_00000000-6_multVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multVectorPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.p2align 8
.type _Z10multVectorPiS_S_ii,@function
_Z10multVectorPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xfff... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multVector(int *d1_in, int *d2_in, int *d_out, int n, int m){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<m){
d_out[ind]=0;
for(int i=0;i<n;i++){
d_out[ind]+= d1_in[i]*d2_in[i*m+ind];
}
}
} | .text
.file "multVector.hip"
.globl _Z25__device_stub__multVectorPiS_S_ii # -- Begin function _Z25__device_stub__multVectorPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__multVectorPiS_S_ii,@function
_Z25__device_stub__multVectorPiS_S_ii: # @_Z25__device_stub__multVectorPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10multVectorPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multVectorPiS_S_ii
.globl _Z10multVectorPiS_S_ii
.p2align 8
.type _Z10multVectorPiS_S_ii,@function
_Z10multVectorPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xfff... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058c63_00000000-6_multVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "multVector.hip"
.globl _Z25__device_stub__multVectorPiS_S_ii # -- Begin function _Z25__device_stub__multVectorPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__multVectorPiS_S_ii,@function
_Z25__device_stub__multVectorPiS_S_ii: # @_Z25__device_stub__multVectorPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoo... | code for sm_80
Function : _Z17downSanple420_gpuyyPsS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoo... | .file "tmpxft_00061730_00000000-6_downSanple420_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void downSanple420_gpu(cudaTextureObject_t ch1, cudaTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCoord.x < width && (threadCoo... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCo... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCo... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 8
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
s_clause 0x1
s_load_b32 s4, s[... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void downSanple420_gpu(hipTextureObject_t ch1, hipTextureObject_t ch2, int16_t *downCh1, int16_t *downCh2, size_t width, size_t height)
{
int2 threadCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (threadCo... | .text
.file "downSanple420_gpu.hip"
.globl _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm # -- Begin function _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 4, 0x90
.type _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z32__device_stub__downSanple420_gp... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17downSanple420_gpuyyPsS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 8
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
s_clause 0x1
s_load_b32 s4, s[... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061730_00000000-6_downSanple420_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq... | .text
.file "downSanple420_gpu.hip"
.globl _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm # -- Begin function _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 4, 0x90
.type _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z32__device_stub__downSanple420_gp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << f... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << f... | .file "tmpxft_0008c7bb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(cudaError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << f... | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(val) check_cuda((val), #val, __FILE__, __LINE__)
void check_cuda(hipError_t result, char const* const func, char const* const file, int const line)
{
if (result)
{
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file... | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10check_cuda10hipError_tPKcS1_i # -- Begin function _Z10check_cuda10hipError_tPKcS1_i
.p2align 4, 0x... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008c7bb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10check_cuda10hipError_tPKcS1_i # -- Begin function _Z10check_cuda10hipError_tPKcS1_i
.p2align 4, 0x... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//... | .file "tmpxft_00055097_00000000-6_chol_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;
//... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11chol_kernelPfi
.globl _Z11chol_kernelPfi
.p2align 8
.type _Z11chol_kernelPfi,@function
_Z11chol_kernelPfi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s12, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_movk_i32 s1, 0x801
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;
//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned i... | .text
.file "chol_kernel.hip"
.globl _Z26__device_stub__chol_kernelPfi # -- Begin function _Z26__device_stub__chol_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__chol_kernelPfi,@function
_Z26__device_stub__chol_kernelPfi: # @_Z26__device_stub__chol_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00055097_00000000-6_chol_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "chol_kernel.hip"
.globl _Z26__device_stub__chol_kernelPfi # -- Begin function _Z26__device_stub__chol_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__chol_kernelPfi,@function
_Z26__device_stub__chol_kernelPfi: # @_Z26__device_stub__chol_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE ... | code for sm_80
Function : _Z20matrixMultiplicationPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE ... | .file "tmpxft_0015e87d_00000000-6_matrix_multiplication_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip),... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE ... | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14allocateMemoryPfS_
.globl _Z14allocateMemoryPfS_
.p2align 8
.type _Z14allocateMemoryPfS_,@function
_Z14allocateMemoryPfS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 ... |
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