system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define SIZE 1000
__global__
void allocateMemory(float *d_mat_A, float *d_mat_B)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
d_mat_A[row * SIZE + col] = 5.5;
d_mat_B[row * SIZE + col] = 5.5;
}
}
__global__
void matrixMultiplication(float *d_mat_A, float *d_mat_B, float *d_mat_C)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < SIZE && col < SIZE)
{
for (int i = 0; i < SIZE; i++)
{
d_mat_C[row * SIZE + col] += d_mat_A[col * SIZE + i] * d_mat_B[i * SIZE + col];
}
}
}
int main()
{
float *h_mat_C = new float[SIZE*SIZE];
float *d_mat_A, *d_mat_B, *d_mat_C;
hipMalloc((void**)&d_mat_A, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_B, SIZE*SIZE * sizeof(float));
hipMalloc((void**)&d_mat_C, SIZE*SIZE * sizeof(float));
dim3 threadsPerBlock(256, 4);
dim3 blocksPerGrid(40, 2500);
allocateMemory<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B);
matrixMultiplication<<<blocksPerGrid, threadsPerBlock>>>(d_mat_A, d_mat_B, d_mat_C);
hipDeviceSynchronize();
hipMemcpy(h_mat_C, d_mat_C, SIZE*SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
for (int j = 0; j < 5; j++)
{
printf("%.8f \t", h_mat_C[i * SIZE + j]);
}
printf("\n");
}
hipFree(d_mat_A); hipFree(d_mat_B); hipFree(d_mat_C);
delete[] h_mat_C;
return 0;
} | .text
.file "matrix_multiplication_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__allocateMemoryPfS_ # -- Begin function _Z29__device_stub__allocateMemoryPfS_
.p2align 4, 0x90
.type _Z29__device_stub__allocateMemoryPfS_,@function
_Z29__device_stub__allocateMemoryPfS_: # @_Z29__device_stub__allocateMemoryPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14allocateMemoryPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__allocateMemoryPfS_, .Lfunc_end0-_Z29__device_stub__allocateMemoryPfS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__matrixMultiplicationPfS_S_ # -- Begin function _Z35__device_stub__matrixMultiplicationPfS_S_
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplicationPfS_S_,@function
_Z35__device_stub__matrixMultiplicationPfS_S_: # @_Z35__device_stub__matrixMultiplicationPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20matrixMultiplicationPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z35__device_stub__matrixMultiplicationPfS_S_, .Lfunc_end1-_Z35__device_stub__matrixMultiplicationPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $10737418240040, %r15 # imm = 0x9C400000028
movabsq $17179869440, %r14 # imm = 0x400000100
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14allocateMemoryPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplicationPfS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $5, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4000, %r15 # imm = 0xFA0
cmpq $5, %r14
jne .LBB2_5
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14allocateMemoryPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplicationPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14allocateMemoryPfS_,@object # @_Z14allocateMemoryPfS_
.section .rodata,"a",@progbits
.globl _Z14allocateMemoryPfS_
.p2align 3, 0x0
_Z14allocateMemoryPfS_:
.quad _Z29__device_stub__allocateMemoryPfS_
.size _Z14allocateMemoryPfS_, 8
.type _Z20matrixMultiplicationPfS_S_,@object # @_Z20matrixMultiplicationPfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.p2align 3, 0x0
_Z20matrixMultiplicationPfS_S_:
.quad _Z35__device_stub__matrixMultiplicationPfS_S_
.size _Z20matrixMultiplicationPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.8f \t"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14allocateMemoryPfS_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20matrixMultiplicationPfS_S_"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__allocateMemoryPfS_
.addrsig_sym _Z35__device_stub__matrixMultiplicationPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14allocateMemoryPfS_
.addrsig_sym _Z20matrixMultiplicationPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20matrixMultiplicationPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R3, 0x3e7, P0 ; /* 0x000003e70300780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, 0x3e8, R0 ; /* 0x000003e803037824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R0, 0x3e8, RZ ; /* 0x000003e800047824 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fca0000000a00 */
/*0100*/ IMAD.WIDE R2, R3, R5, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0205 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0130*/ IADD3 R10, P0, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R11, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0b7210 */
/* 0x001fe400007fe4ff */
/*0150*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0160*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0170*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fc800078e0206 */
/*01a0*/ LDG.E R11, [R4.64+-0x10] ; /* 0xfffff004040b7981 */
/* 0x004ea8000c1e1900 */
/*01b0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x024fca0000000009 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R10, [R6.64+0xfa0] ; /* 0x000fa004060a7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R9, [R4.64+-0xc] ; /* 0xfffff40404097981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FFMA R9, R10, R9, R11 ; /* 0x000000090a097223 */
/* 0x004fca000000000b */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R10, [R6.64+0x1f40] ; /* 0x001f4004060a7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R12, [R4.64+-0x8] ; /* 0xfffff804040c7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0250*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0260*/ LDG.E R10, [R6.64+0x2ee0] ; /* 0x002ee004060a7981 */
/* 0x000e28000c1e1900 */
/*0270*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc04040c7981 */
/* 0x000e24000c1e1900 */
/*0280*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R10, [R6.64+0x3e80] ; /* 0x003e8004060a7981 */
/* 0x000e68000c1e1900 */
/*02b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000e64000c1e1900 */
/*02c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R10, [R6.64+0x4e20] ; /* 0x004e2004060a7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R10, [R6.64+0x5dc0] ; /* 0x005dc004060a7981 */
/* 0x000e28000c1e1900 */
/*0330*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000e24000c1e1900 */
/*0340*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R10, [R6.64+0x6d60] ; /* 0x006d6004060a7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0390*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*03a0*/ LDG.E R10, [R6.64+0x7d00] ; /* 0x007d0004060a7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*03d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R10, [R6.64+0x8ca0] ; /* 0x008ca004060a7981 */
/* 0x000e28000c1e1900 */
/*03f0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000e24000c1e1900 */
/*0400*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0410*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0420*/ LDG.E R10, [R6.64+0x9c40] ; /* 0x009c4004060a7981 */
/* 0x000e68000c1e1900 */
/*0430*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000e64000c1e1900 */
/*0440*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R10, [R6.64+0xabe0] ; /* 0x00abe004060a7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c04040c7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0490*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R10, [R6.64+0xbb80] ; /* 0x00bb8004060a7981 */
/* 0x000e28000c1e1900 */
/*04b0*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000e24000c1e1900 */
/*04c0*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*04d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R10, [R6.64+0xcb20] ; /* 0x00cb2004060a7981 */
/* 0x000e68000c1e1900 */
/*04f0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000e64000c1e1900 */
/*0500*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R10, [R6.64+0xdac0] ; /* 0x00dac004060a7981 */
/* 0x000ea8000c1e1900 */
/*0530*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000ea4000c1e1900 */
/*0540*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0550*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0560*/ LDG.E R10, [R6.64+0xea60] ; /* 0x00ea6004060a7981 */
/* 0x000e28000c1e1900 */
/*0570*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000e24000c1e1900 */
/*0580*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0590*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R10, [R6.64+0xfa00] ; /* 0x00fa0004060a7981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000e64000c1e1900 */
/*05c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*05d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R10, [R6.64+0x109a0] ; /* 0x0109a004060a7981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0610*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R10, [R6.64+0x11940] ; /* 0x01194004060a7981 */
/* 0x000e28000c1e1900 */
/*0630*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000e24000c1e1900 */
/*0640*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0650*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0660*/ LDG.E R10, [R6.64+0x128e0] ; /* 0x0128e004060a7981 */
/* 0x000e68000c1e1900 */
/*0670*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000e64000c1e1900 */
/*0680*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0690*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*06a0*/ LDG.E R10, [R6.64+0x13880] ; /* 0x01388004060a7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R12, [R4.64+0x40] ; /* 0x00004004040c7981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*06d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R10, [R6.64+0x14820] ; /* 0x01482004060a7981 */
/* 0x000e28000c1e1900 */
/*06f0*/ LDG.E R12, [R4.64+0x44] ; /* 0x00004404040c7981 */
/* 0x000e24000c1e1900 */
/*0700*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0710*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0720*/ LDG.E R10, [R6.64+0x157c0] ; /* 0x0157c004060a7981 */
/* 0x000e68000c1e1900 */
/*0730*/ LDG.E R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x000e64000c1e1900 */
/*0740*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0750*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0760*/ LDG.E R10, [R6.64+0x16760] ; /* 0x01676004060a7981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R12, [R4.64+0x4c] ; /* 0x00004c04040c7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0790*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*07a0*/ LDG.E R10, [R6.64+0x17700] ; /* 0x01770004060a7981 */
/* 0x000e28000c1e1900 */
/*07b0*/ LDG.E R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x000e24000c1e1900 */
/*07c0*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*07d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*07e0*/ LDG.E R10, [R6.64+0x186a0] ; /* 0x0186a004060a7981 */
/* 0x000e68000c1e1900 */
/*07f0*/ LDG.E R12, [R4.64+0x54] ; /* 0x00005404040c7981 */
/* 0x000e64000c1e1900 */
/*0800*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*0810*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0820*/ LDG.E R10, [R6.64+0x19640] ; /* 0x01964004060a7981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R12, [R4.64+0x58] ; /* 0x00005804040c7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0850*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0860*/ LDG.E R10, [R6.64+0x1a5e0] ; /* 0x01a5e004060a7981 */
/* 0x000e28000c1e1900 */
/*0870*/ LDG.E R12, [R4.64+0x5c] ; /* 0x00005c04040c7981 */
/* 0x000e24000c1e1900 */
/*0880*/ FFMA R11, R10, R12, R13 ; /* 0x0000000c0a0b7223 */
/* 0x001fca000000000d */
/*0890*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*08a0*/ LDG.E R10, [R6.64+0x1b580] ; /* 0x01b58004060a7981 */
/* 0x000e68000c1e1900 */
/*08b0*/ LDG.E R12, [R4.64+0x60] ; /* 0x00006004040c7981 */
/* 0x000e64000c1e1900 */
/*08c0*/ FFMA R9, R10, R12, R11 ; /* 0x0000000c0a097223 */
/* 0x002fca000000000b */
/*08d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*08e0*/ LDG.E R10, [R6.64+0x1c520] ; /* 0x01c52004060a7981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R12, [R4.64+0x64] ; /* 0x00006404040c7981 */
/* 0x000ea4000c1e1900 */
/*0900*/ FFMA R13, R10, R12, R9 ; /* 0x0000000c0a0d7223 */
/* 0x004fca0000000009 */
/*0910*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0920*/ LDG.E R10, [R6.64+0x1d4c0] ; /* 0x01d4c004060a7981 */
/* 0x000ee8000c1e1900 */
/*0930*/ LDG.E R12, [R4.64+0x68] ; /* 0x00006804040c7981 */
/* 0x000ee4000c1e1900 */
/*0940*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0950*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe8000c101904 */
/*0960*/ LDG.E R10, [R6.64+0x1e460] ; /* 0x01e46004060a7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R11, [R4.64+0x6c] ; /* 0x00006c04040b7981 */
/* 0x001ee4000c1e1900 */
/*0980*/ FFMA R17, R10, R11, R15 ; /* 0x0000000b0a117223 */
/* 0x008fca000000000f */
/*0990*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe8000c101904 */
/*09a0*/ LDG.E R9, [R6.64+0x1f400] ; /* 0x01f4000406097981 */
/* 0x002ee8000c1e1900 */
/*09b0*/ LDG.E R10, [R4.64+0x70] ; /* 0x00007004040a7981 */
/* 0x000ee4000c1e1900 */
/*09c0*/ FFMA R9, R9, R10, R17 ; /* 0x0000000a09097223 */
/* 0x008fca0000000011 */
/*09d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R10, [R6.64+0x203a0] ; /* 0x0203a004060a7981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R11, [R4.64+0x74] ; /* 0x00007404040b7981 */
/* 0x000ee4000c1e1900 */
/*0a00*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x008fca0000000009 */
/*0a10*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R10, [R6.64+0x21340] ; /* 0x02134004060a7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R4.64+0x78] ; /* 0x00007804040c7981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0a50*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0a60*/ LDG.E R10, [R6.64+0x222e0] ; /* 0x0222e004060a7981 */
/* 0x000e28000c1e1900 */
/*0a70*/ LDG.E R12, [R4.64+0x7c] ; /* 0x00007c04040c7981 */
/* 0x000e24000c1e1900 */
/*0a80*/ FFMA R9, R10, R12, R13 ; /* 0x0000000c0a097223 */
/* 0x001fca000000000d */
/*0a90*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0aa0*/ LDG.E R10, [R6.64+0x23280] ; /* 0x02328004060a7981 */
/* 0x000e68000c1e1900 */
/*0ab0*/ LDG.E R12, [R4.64+0x80] ; /* 0x00008004040c7981 */
/* 0x000e64000c1e1900 */
/*0ac0*/ FFMA R11, R10, R12, R9 ; /* 0x0000000c0a0b7223 */
/* 0x002fca0000000009 */
/*0ad0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R10, [R6.64+0x24220] ; /* 0x02422004060a7981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R12, [R4.64+0x84] ; /* 0x00008404040c7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0b10*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0b20*/ LDG.E R10, [R6.64+0x251c0] ; /* 0x0251c004060a7981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R12, [R4.64+0x88] ; /* 0x00008804040c7981 */
/* 0x000ee2000c1e1900 */
/*0b40*/ IADD3 R8, R8, 0x28, RZ ; /* 0x0000002808087810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0b60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0b70*/ LDG.E R10, [R6.64+0x26160] ; /* 0x02616004060a7981 */
/* 0x000ee8000c1e1900 */
/*0b80*/ LDG.E R9, [R4.64+0x8c] ; /* 0x00008c0404097981 */
/* 0x001ee2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R8, 0x3e8, PT ; /* 0x000003e80800780c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x27100, URZ ; /* 0x0002710006067890 */
/* 0x000fc8000ff1e03f */
/*0bb0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bc0*/ FFMA R9, R10, R9, R15 ; /* 0x000000090a097223 */
/* 0x008fe2000000000f */
/*0bd0*/ IADD3 R10, P1, R4, 0xa0, RZ ; /* 0x000000a0040a7810 */
/* 0x000fc80007f3e0ff */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*0bf0*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fe20000ffe4ff */
/*0c00*/ @P0 BRA 0x150 ; /* 0xfffff54000000947 */
/* 0x000fea000383ffff */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14allocateMemoryPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x3e7, PT ; /* 0x000003e70300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3e7, P0 ; /* 0x000003e70000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, 0x3e8, R3 ; /* 0x000003e800007824 */
/* 0x000fe200078e0203 */
/*00c0*/ MOV R7, 0x40b00000 ; /* 0x40b0000000077802 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14allocateMemoryPfS_
.globl _Z14allocateMemoryPfS_
.p2align 8
.type _Z14allocateMemoryPfS_,@function
_Z14allocateMemoryPfS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x3e8, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, 0x3e8, v[1:2]
v_mov_b32_e32 v4, 0x40b00000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14allocateMemoryPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14allocateMemoryPfS_, .Lfunc_end0-_Z14allocateMemoryPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20matrixMultiplicationPfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.p2align 8
.type _Z20matrixMultiplicationPfS_S_,@function
_Z20matrixMultiplicationPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, 0x3e8, v[0:1]
v_mul_lo_u32 v5, v0, 0x3e8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v4, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x3e8, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0xfa0
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v1, v7
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplicationPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20matrixMultiplicationPfS_S_, .Lfunc_end1-_Z20matrixMultiplicationPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14allocateMemoryPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14allocateMemoryPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplicationPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplicationPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015e87d_00000000-6_matrix_multiplication_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14allocateMemoryPfS_PfS_
.type _Z36__device_stub__Z14allocateMemoryPfS_PfS_, @function
_Z36__device_stub__Z14allocateMemoryPfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14allocateMemoryPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z14allocateMemoryPfS_PfS_, .-_Z36__device_stub__Z14allocateMemoryPfS_PfS_
.globl _Z14allocateMemoryPfS_
.type _Z14allocateMemoryPfS_, @function
_Z14allocateMemoryPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14allocateMemoryPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14allocateMemoryPfS_, .-_Z14allocateMemoryPfS_
.globl _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
.type _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_, @function
_Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20matrixMultiplicationPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_, .-_Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.type _Z20matrixMultiplicationPfS_S_, @function
_Z20matrixMultiplicationPfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z20matrixMultiplicationPfS_S_, .-_Z20matrixMultiplicationPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.8f \t"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $256, 32(%rsp)
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $40, 44(%rsp)
movl $2500, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbp
leaq 20000(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L23
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4000, %rbp
cmpq %r15, %rbp
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14allocateMemoryPfS_PfS_
jmp .L20
.L29:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z20matrixMultiplicationPfS_S_PfS_S_
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20matrixMultiplicationPfS_S_"
.section .rodata.str1.1
.LC3:
.string "_Z14allocateMemoryPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplicationPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14allocateMemoryPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_multiplication_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__allocateMemoryPfS_ # -- Begin function _Z29__device_stub__allocateMemoryPfS_
.p2align 4, 0x90
.type _Z29__device_stub__allocateMemoryPfS_,@function
_Z29__device_stub__allocateMemoryPfS_: # @_Z29__device_stub__allocateMemoryPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14allocateMemoryPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__allocateMemoryPfS_, .Lfunc_end0-_Z29__device_stub__allocateMemoryPfS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__matrixMultiplicationPfS_S_ # -- Begin function _Z35__device_stub__matrixMultiplicationPfS_S_
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplicationPfS_S_,@function
_Z35__device_stub__matrixMultiplicationPfS_S_: # @_Z35__device_stub__matrixMultiplicationPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20matrixMultiplicationPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z35__device_stub__matrixMultiplicationPfS_S_, .Lfunc_end1-_Z35__device_stub__matrixMultiplicationPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $10737418240040, %r15 # imm = 0x9C400000028
movabsq $17179869440, %r14 # imm = 0x400000100
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14allocateMemoryPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplicationPfS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $5, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4000, %r15 # imm = 0xFA0
cmpq $5, %r14
jne .LBB2_5
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14allocateMemoryPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplicationPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14allocateMemoryPfS_,@object # @_Z14allocateMemoryPfS_
.section .rodata,"a",@progbits
.globl _Z14allocateMemoryPfS_
.p2align 3, 0x0
_Z14allocateMemoryPfS_:
.quad _Z29__device_stub__allocateMemoryPfS_
.size _Z14allocateMemoryPfS_, 8
.type _Z20matrixMultiplicationPfS_S_,@object # @_Z20matrixMultiplicationPfS_S_
.globl _Z20matrixMultiplicationPfS_S_
.p2align 3, 0x0
_Z20matrixMultiplicationPfS_S_:
.quad _Z35__device_stub__matrixMultiplicationPfS_S_
.size _Z20matrixMultiplicationPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.8f \t"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14allocateMemoryPfS_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20matrixMultiplicationPfS_S_"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__allocateMemoryPfS_
.addrsig_sym _Z35__device_stub__matrixMultiplicationPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14allocateMemoryPfS_
.addrsig_sym _Z20matrixMultiplicationPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256
// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;
// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);
// Main function
int main(const int argc, const char** argv) {
int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
double dt = 0.1;
int nstep = 120;
int nout = 1;
int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
double *host_memory = (double *) malloc(num_bytes);
double *device_memory;
cudaMalloc(&device_memory, num_bytes);
// Assign host memory
particles_t host_particles;
host_particles.p = (vector3*) host_memory;
host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
// Assign device memory
particles_t device_particles;
device_particles.p = (vector3*) device_memory;
device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;
// Initialize bodies
srand(time(0));
for (int i = 0; i < NUM_PARTICLES; i++) {
new_particle(&host_particles.p[i], &host_particles.v[i]);
}
// Needed to print in paralel
cudaDeviceSetLimit(cudaLimitPrintfFifoSize, NUM_PARTICLES * 400);
// Copy host to device
cudaMemcpy(device_memory, host_memory, num_bytes, cudaMemcpyHostToDevice);
// Loop leapfrog
for (int i = 0; i < nstep; i++) {
if (i % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
cudaDeviceSynchronize();
}
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
}
if (nstep % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
cudaDeviceSynchronize();
}
free(host_memory);
cudaFree(device_memory);
}
double unirandom() {
return ((double) rand())/RAND_MAX;
}
void new_particle(vector3 *p, vector3 *v) {
double X1 = unirandom();
double r = pow(pow(X1, -2.0/3) - 1, -0.5);
double X2 = unirandom();
double X3 = unirandom();
p->z = (1 - 2 * X2) * r;
p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);
#ifdef STABLE
double V_e = sqrt(2) * pow((1 + r * r), -0.25);
double X4 = unirandom();
double X5 = unirandom();
while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
X4 = unirandom();
X5 = unirandom();
}
double V = X4 * V_e;
double X6 = unirandom();
double X7 = unirandom();
v->z = (1 - 2 * X6) * V;
v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
#else
(*v) = (vector3) {0.0, 0.0, 0.0};
#endif
}
// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
}
}
// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
double ax = 0.0;
double ay = 0.0;
double az = 0.0;
for (int j = 0; j < NUM_PARTICLES; j++) {
if(i == j) {
continue;
}
double dx = p[j].x - p[i].x;
double dy = p[j].y - p[i].y;
double dz = p[j].z - p[i].z;
double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
ax += dx * accel;
ay += dy * accel;
az += dz * accel;
}
v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
}
}
// Print positions
__global__ void print_position(vector3 *p) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
}
} | .file "tmpxft_0009aba0_00000000-6_plummer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9unirandomv
.type _Z9unirandomv, @function
_Z9unirandomv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9unirandomv, .-_Z9unirandomv
.globl _Z12new_particleP7vector3S0_
.type _Z12new_particleP7vector3S0_, @function
_Z12new_particleP7vector3S0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
call _Z9unirandomv
movsd .LC1(%rip), %xmm1
call pow@PLT
subsd .LC3(%rip), %xmm0
movsd .LC2(%rip), %xmm1
call pow@PLT
movsd %xmm0, 8(%rsp)
call _Z9unirandomv
movsd %xmm0, 16(%rsp)
call _Z9unirandomv
movapd %xmm0, %xmm3
movsd %xmm0, 24(%rsp)
movsd 16(%rsp), %xmm4
addsd %xmm4, %xmm4
movsd .LC3(%rip), %xmm5
subsd %xmm4, %xmm5
movapd %xmm5, %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm1, %xmm0
movsd %xmm0, 16(%rbp)
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
subsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm1, %xmm0
ja .L10
movapd %xmm1, %xmm2
sqrtsd %xmm2, %xmm2
movsd %xmm2, 8(%rsp)
mulsd .LC5(%rip), %xmm3
movq %xmm3, %r14
movapd %xmm3, %xmm0
call cos@PLT
mulsd 8(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
.L8:
movq %r14, %xmm0
call sin@PLT
mulsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rbp)
movq $0x000000000, (%rbx)
movq $0x000000000, 8(%rbx)
movq $0x000000000, 16(%rbx)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 16(%rsp)
movsd 24(%rsp), %xmm7
mulsd .LC5(%rip), %xmm7
movq %xmm7, %r14
movapd %xmm7, %xmm0
call cos@PLT
mulsd 16(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 8(%rsp)
jmp .L8
.cfi_endproc
.LFE2059:
.size _Z12new_particleP7vector3S0_, .-_Z12new_particleP7vector3S0_
.globl _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
.type _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, @function
_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18integrate_positionP7vector3S0_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, .-_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
.globl _Z18integrate_positionP7vector3S0_d
.type _Z18integrate_positionP7vector3S0_d, @function
_Z18integrate_positionP7vector3S0_d:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18integrate_positionP7vector3S0_d, .-_Z18integrate_positionP7vector3S0_d
.globl _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.type _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, @function
_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7leapintP7vector3S0_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, .-_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.globl _Z7leapintP7vector3S0_d
.type _Z7leapintP7vector3S0_d, @function
_Z7leapintP7vector3S0_d:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7leapintP7vector3S0_d, .-_Z7leapintP7vector3S0_d
.globl _Z41__device_stub__Z14print_positionP7vector3P7vector3
.type _Z41__device_stub__Z14print_positionP7vector3P7vector3, @function
_Z41__device_stub__Z14print_positionP7vector3P7vector3:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14print_positionP7vector3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z41__device_stub__Z14print_positionP7vector3P7vector3, .-_Z41__device_stub__Z14print_positionP7vector3P7vector3
.globl _Z14print_positionP7vector3
.type _Z14print_positionP7vector3, @function
_Z14print_positionP7vector3:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z14print_positionP7vector3, .-_Z14print_positionP7vector3
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $480000, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $480000, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rbp
leaq 240000(%rbp), %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 240000(%r13), %r14
.L37:
leaq 240000(%rbx), %rsi
movq %rbx, %rdi
call _Z12new_particleP7vector3S0_
addq $24, %rbx
cmpq %r14, %rbx
jne .L37
movl $4000000, %esi
movl $1, %edi
call cudaDeviceSetLimit@PLT
movl $1, %ecx
movl $480000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $120, %ebx
jmp .L42
.L49:
movq %rbp, %rdi
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
jmp .L38
.L50:
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
jmp .L39
.L51:
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
jmp .L40
.L41:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L48
.L42:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L39:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
jmp .L41
.L48:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L43:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %rbp, %rdi
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
jmp .L43
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z14print_positionP7vector3"
.LC8:
.string "_Z7leapintP7vector3S0_d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z18integrate_positionP7vector3S0_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_positionP7vector3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7leapintP7vector3S0_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18integrate_positionP7vector3S0_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 1431655765
.long -1075489451
.align 8
.LC2:
.long 0
.long -1075838976
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC5:
.long 1405670641
.long 1075388923
.align 8
.LC6:
.long -1717986918
.long 1069128089
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256
// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;
// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);
// Main function
int main(const int argc, const char** argv) {
int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
double dt = 0.1;
int nstep = 120;
int nout = 1;
int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
double *host_memory = (double *) malloc(num_bytes);
double *device_memory;
cudaMalloc(&device_memory, num_bytes);
// Assign host memory
particles_t host_particles;
host_particles.p = (vector3*) host_memory;
host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
// Assign device memory
particles_t device_particles;
device_particles.p = (vector3*) device_memory;
device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;
// Initialize bodies
srand(time(0));
for (int i = 0; i < NUM_PARTICLES; i++) {
new_particle(&host_particles.p[i], &host_particles.v[i]);
}
// Needed to print in paralel
cudaDeviceSetLimit(cudaLimitPrintfFifoSize, NUM_PARTICLES * 400);
// Copy host to device
cudaMemcpy(device_memory, host_memory, num_bytes, cudaMemcpyHostToDevice);
// Loop leapfrog
for (int i = 0; i < nstep; i++) {
if (i % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
cudaDeviceSynchronize();
}
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
cudaDeviceSynchronize();
}
if (nstep % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
cudaDeviceSynchronize();
}
free(host_memory);
cudaFree(device_memory);
}
double unirandom() {
return ((double) rand())/RAND_MAX;
}
void new_particle(vector3 *p, vector3 *v) {
double X1 = unirandom();
double r = pow(pow(X1, -2.0/3) - 1, -0.5);
double X2 = unirandom();
double X3 = unirandom();
p->z = (1 - 2 * X2) * r;
p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);
#ifdef STABLE
double V_e = sqrt(2) * pow((1 + r * r), -0.25);
double X4 = unirandom();
double X5 = unirandom();
while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
X4 = unirandom();
X5 = unirandom();
}
double V = X4 * V_e;
double X6 = unirandom();
double X7 = unirandom();
v->z = (1 - 2 * X6) * V;
v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
#else
(*v) = (vector3) {0.0, 0.0, 0.0};
#endif
}
// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
}
}
// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
double ax = 0.0;
double ay = 0.0;
double az = 0.0;
for (int j = 0; j < NUM_PARTICLES; j++) {
if(i == j) {
continue;
}
double dx = p[j].x - p[i].x;
double dy = p[j].y - p[i].y;
double dz = p[j].z - p[i].z;
double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
ax += dx * accel;
ay += dy * accel;
az += dz * accel;
}
v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
}
}
// Print positions
__global__ void print_position(vector3 *p) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256
// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;
// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);
// Main function
int main(const int argc, const char** argv) {
int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
double dt = 0.1;
int nstep = 120;
int nout = 1;
int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
double *host_memory = (double *) malloc(num_bytes);
double *device_memory;
hipMalloc(&device_memory, num_bytes);
// Assign host memory
particles_t host_particles;
host_particles.p = (vector3*) host_memory;
host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
// Assign device memory
particles_t device_particles;
device_particles.p = (vector3*) device_memory;
device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;
// Initialize bodies
srand(time(0));
for (int i = 0; i < NUM_PARTICLES; i++) {
new_particle(&host_particles.p[i], &host_particles.v[i]);
}
// Needed to print in paralel
hipDeviceSetLimit(hipLimitPrintfFifoSize, NUM_PARTICLES * 400);
// Copy host to device
hipMemcpy(device_memory, host_memory, num_bytes, hipMemcpyHostToDevice);
// Loop leapfrog
for (int i = 0; i < nstep; i++) {
if (i % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
hipDeviceSynchronize();
}
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
}
if (nstep % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
hipDeviceSynchronize();
}
free(host_memory);
hipFree(device_memory);
}
double unirandom() {
return ((double) rand())/RAND_MAX;
}
void new_particle(vector3 *p, vector3 *v) {
double X1 = unirandom();
double r = pow(pow(X1, -2.0/3) - 1, -0.5);
double X2 = unirandom();
double X3 = unirandom();
p->z = (1 - 2 * X2) * r;
p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);
#ifdef STABLE
double V_e = sqrt(2) * pow((1 + r * r), -0.25);
double X4 = unirandom();
double X5 = unirandom();
while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
X4 = unirandom();
X5 = unirandom();
}
double V = X4 * V_e;
double X6 = unirandom();
double X7 = unirandom();
v->z = (1 - 2 * X6) * V;
v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
#else
(*v) = (vector3) {0.0, 0.0, 0.0};
#endif
}
// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
}
}
// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
double ax = 0.0;
double ay = 0.0;
double az = 0.0;
for (int j = 0; j < NUM_PARTICLES; j++) {
if(i == j) {
continue;
}
double dx = p[j].x - p[i].x;
double dy = p[j].y - p[i].y;
double dz = p[j].z - p[i].z;
double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
ax += dx * accel;
ay += dy * accel;
az += dz * accel;
}
v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
}
}
// Print positions
__global__ void print_position(vector3 *p) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256
// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;
// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);
// Main function
int main(const int argc, const char** argv) {
int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
double dt = 0.1;
int nstep = 120;
int nout = 1;
int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
double *host_memory = (double *) malloc(num_bytes);
double *device_memory;
hipMalloc(&device_memory, num_bytes);
// Assign host memory
particles_t host_particles;
host_particles.p = (vector3*) host_memory;
host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
// Assign device memory
particles_t device_particles;
device_particles.p = (vector3*) device_memory;
device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;
// Initialize bodies
srand(time(0));
for (int i = 0; i < NUM_PARTICLES; i++) {
new_particle(&host_particles.p[i], &host_particles.v[i]);
}
// Needed to print in paralel
hipDeviceSetLimit(hipLimitPrintfFifoSize, NUM_PARTICLES * 400);
// Copy host to device
hipMemcpy(device_memory, host_memory, num_bytes, hipMemcpyHostToDevice);
// Loop leapfrog
for (int i = 0; i < nstep; i++) {
if (i % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
hipDeviceSynchronize();
}
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
hipDeviceSynchronize();
}
if (nstep % nout == 0) {
print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
hipDeviceSynchronize();
}
free(host_memory);
hipFree(device_memory);
}
double unirandom() {
return ((double) rand())/RAND_MAX;
}
void new_particle(vector3 *p, vector3 *v) {
double X1 = unirandom();
double r = pow(pow(X1, -2.0/3) - 1, -0.5);
double X2 = unirandom();
double X3 = unirandom();
p->z = (1 - 2 * X2) * r;
p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);
#ifdef STABLE
double V_e = sqrt(2) * pow((1 + r * r), -0.25);
double X4 = unirandom();
double X5 = unirandom();
while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
X4 = unirandom();
X5 = unirandom();
}
double V = X4 * V_e;
double X6 = unirandom();
double X7 = unirandom();
v->z = (1 - 2 * X6) * V;
v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
#else
(*v) = (vector3) {0.0, 0.0, 0.0};
#endif
}
// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
}
}
// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
double ax = 0.0;
double ay = 0.0;
double az = 0.0;
for (int j = 0; j < NUM_PARTICLES; j++) {
if(i == j) {
continue;
}
double dx = p[j].x - p[i].x;
double dy = p[j].y - p[i].y;
double dz = p[j].z - p[i].z;
double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
ax += dx * accel;
ay += dy * accel;
az += dz * accel;
}
v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
}
}
// Print positions
__global__ void print_position(vector3 *p) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < NUM_PARTICLES) {
printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
}
} | .text
.file "plummer.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0xbfe5555555555555 # double -0.66666666666666663
.LCPI0_2:
.quad 0xbff0000000000000 # double -1
.LCPI0_3:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_4:
.quad 0x3ff0000000000000 # double 1
.LCPI0_5:
.quad 0x401921fb53c8d4f1 # double 6.2831853000000004
.LCPI0_6:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_7:
.zero 16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $480000, %edi # imm = 0x75300
callq malloc
movq %rax, %rbx
leaq 120(%rsp), %rdi
movl $480000, %esi # imm = 0x75300
callq hipMalloc
movq 120(%rsp), %r15
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_6: # %call.sqrt124
# in Loop: Header=BB0_1 Depth=1
callq sqrt
.LBB0_7: # %.split.split
# in Loop: Header=BB0_1 Depth=1
movsd %xmm0, 56(%rsp) # 8-byte Spill
leaq (%rbx,%r14), %r12
addq $240000, %r12 # imm = 0x3A980
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rbx,%r14)
xorpd %xmm0, %xmm0
movupd %xmm0, (%r12)
movq $0, 16(%r12)
addq $24, %r14
cmpq $240000, %r14 # imm = 0x3A980
je .LBB0_8
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI0_2(%rip), %xmm0
movsd .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
movsd %xmm0, 56(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq rand
movl %eax, %ebp
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm0, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%rbx,%r14)
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
movsd %xmm0, 56(%rsp) # 8-byte Spill
subsd %xmm1, %xmm0
ucomisd .LCPI0_6(%rip), %xmm0
jb .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_3: # %call.sqrt
# in Loop: Header=BB0_1 Depth=1
callq sqrt
.LBB0_4: # %.split
# in Loop: Header=BB0_1 Depth=1
movsd %xmm0, 128(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
divsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_5(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq cos
mulsd 128(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r14)
movsd 16(%rbx,%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ucomisd .LCPI0_6(%rip), %xmm1
jb .LBB0_6
# %bb.5: # in Loop: Header=BB0_1 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_7
.LBB0_8:
movabsq $4294967336, %r14 # imm = 0x100000028
leaq 240000(%r15), %r13
movl $4000000, %esi # imm = 0x3D0900
movl $1, %edi
callq hipDeviceSetLimit
movq 120(%rsp), %rdi
movl $480000, %edx # imm = 0x75300
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $120, %ebp
leaq 216(%r14), %r12
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB0_18
.LBB0_9: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=1
movq %r15, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z14print_positionP7vector3, %edi
movq %rsp, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_11: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7leapintP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z18integrate_positionP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7leapintP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_17
.LBB0_18:
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_20
# %bb.19:
movq %r15, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z14print_positionP7vector3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_20:
callq hipDeviceSynchronize
movq %rbx, %rdi
callq free
movq 120(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12new_particleP7vector3S0_
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbfe5555555555555 # double -0.66666666666666663
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x401921fb53c8d4f1 # double 6.2831853000000004
.LCPI1_6:
.quad 0x0000000000000000 # double 0
.text
.globl _Z12new_particleP7vector3S0_
.p2align 4, 0x90
.type _Z12new_particleP7vector3S0_,@function
_Z12new_particleP7vector3S0_: # @_Z12new_particleP7vector3S0_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI1_2(%rip), %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq rand
cvtsi2sd %eax, %xmm2
divsd .LCPI1_0(%rip), %xmm2
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm0, %xmm0
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%r14)
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
movsd %xmm0, (%rsp) # 8-byte Spill
subsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB1_3
.LBB1_2: # %call.sqrt
movsd %xmm2, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB1_3: # %.split
movsd %xmm0, 16(%rsp) # 8-byte Spill
mulsd .LCPI1_5(%rip), %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14)
movsd 16(%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ucomisd .LCPI1_6(%rip), %xmm1
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt17
callq sqrt
.LBB1_6: # %.split.split
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%r14)
xorpd %xmm0, %xmm0
movupd %xmm0, (%rbx)
movq $0, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12new_particleP7vector3S0_, .Lfunc_end1-_Z12new_particleP7vector3S0_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__print_positionP7vector3 # -- Begin function _Z29__device_stub__print_positionP7vector3
.p2align 4, 0x90
.type _Z29__device_stub__print_positionP7vector3,@function
_Z29__device_stub__print_positionP7vector3: # @_Z29__device_stub__print_positionP7vector3
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14print_positionP7vector3, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z29__device_stub__print_positionP7vector3, .Lfunc_end2-_Z29__device_stub__print_positionP7vector3
.cfi_endproc
# -- End function
.globl _Z22__device_stub__leapintP7vector3S0_d # -- Begin function _Z22__device_stub__leapintP7vector3S0_d
.p2align 4, 0x90
.type _Z22__device_stub__leapintP7vector3S0_d,@function
_Z22__device_stub__leapintP7vector3S0_d: # @_Z22__device_stub__leapintP7vector3S0_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7leapintP7vector3S0_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__leapintP7vector3S0_d, .Lfunc_end3-_Z22__device_stub__leapintP7vector3S0_d
.cfi_endproc
# -- End function
.globl _Z33__device_stub__integrate_positionP7vector3S0_d # -- Begin function _Z33__device_stub__integrate_positionP7vector3S0_d
.p2align 4, 0x90
.type _Z33__device_stub__integrate_positionP7vector3S0_d,@function
_Z33__device_stub__integrate_positionP7vector3S0_d: # @_Z33__device_stub__integrate_positionP7vector3S0_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18integrate_positionP7vector3S0_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z33__device_stub__integrate_positionP7vector3S0_d, .Lfunc_end4-_Z33__device_stub__integrate_positionP7vector3S0_d
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9unirandomv
.LCPI5_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z9unirandomv
.p2align 4, 0x90
.type _Z9unirandomv,@function
_Z9unirandomv: # @_Z9unirandomv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9unirandomv, .Lfunc_end5-_Z9unirandomv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18integrate_positionP7vector3S0_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7leapintP7vector3S0_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_positionP7vector3, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_positionP7vector3,@object # @_Z14print_positionP7vector3
.section .rodata,"a",@progbits
.globl _Z14print_positionP7vector3
.p2align 3, 0x0
_Z14print_positionP7vector3:
.quad _Z29__device_stub__print_positionP7vector3
.size _Z14print_positionP7vector3, 8
.type _Z7leapintP7vector3S0_d,@object # @_Z7leapintP7vector3S0_d
.globl _Z7leapintP7vector3S0_d
.p2align 3, 0x0
_Z7leapintP7vector3S0_d:
.quad _Z22__device_stub__leapintP7vector3S0_d
.size _Z7leapintP7vector3S0_d, 8
.type _Z18integrate_positionP7vector3S0_d,@object # @_Z18integrate_positionP7vector3S0_d
.globl _Z18integrate_positionP7vector3S0_d
.p2align 3, 0x0
_Z18integrate_positionP7vector3S0_d:
.quad _Z33__device_stub__integrate_positionP7vector3S0_d
.size _Z18integrate_positionP7vector3S0_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18integrate_positionP7vector3S0_d"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7leapintP7vector3S0_d"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14print_positionP7vector3"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_positionP7vector3
.addrsig_sym _Z22__device_stub__leapintP7vector3S0_d
.addrsig_sym _Z33__device_stub__integrate_positionP7vector3S0_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_positionP7vector3
.addrsig_sym _Z7leapintP7vector3S0_d
.addrsig_sym _Z18integrate_positionP7vector3S0_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009aba0_00000000-6_plummer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9unirandomv
.type _Z9unirandomv, @function
_Z9unirandomv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9unirandomv, .-_Z9unirandomv
.globl _Z12new_particleP7vector3S0_
.type _Z12new_particleP7vector3S0_, @function
_Z12new_particleP7vector3S0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
call _Z9unirandomv
movsd .LC1(%rip), %xmm1
call pow@PLT
subsd .LC3(%rip), %xmm0
movsd .LC2(%rip), %xmm1
call pow@PLT
movsd %xmm0, 8(%rsp)
call _Z9unirandomv
movsd %xmm0, 16(%rsp)
call _Z9unirandomv
movapd %xmm0, %xmm3
movsd %xmm0, 24(%rsp)
movsd 16(%rsp), %xmm4
addsd %xmm4, %xmm4
movsd .LC3(%rip), %xmm5
subsd %xmm4, %xmm5
movapd %xmm5, %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm1, %xmm0
movsd %xmm0, 16(%rbp)
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
subsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm1, %xmm0
ja .L10
movapd %xmm1, %xmm2
sqrtsd %xmm2, %xmm2
movsd %xmm2, 8(%rsp)
mulsd .LC5(%rip), %xmm3
movq %xmm3, %r14
movapd %xmm3, %xmm0
call cos@PLT
mulsd 8(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
.L8:
movq %r14, %xmm0
call sin@PLT
mulsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rbp)
movq $0x000000000, (%rbx)
movq $0x000000000, 8(%rbx)
movq $0x000000000, 16(%rbx)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 16(%rsp)
movsd 24(%rsp), %xmm7
mulsd .LC5(%rip), %xmm7
movq %xmm7, %r14
movapd %xmm7, %xmm0
call cos@PLT
mulsd 16(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 8(%rsp)
jmp .L8
.cfi_endproc
.LFE2059:
.size _Z12new_particleP7vector3S0_, .-_Z12new_particleP7vector3S0_
.globl _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
.type _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, @function
_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18integrate_positionP7vector3S0_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, .-_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
.globl _Z18integrate_positionP7vector3S0_d
.type _Z18integrate_positionP7vector3S0_d, @function
_Z18integrate_positionP7vector3S0_d:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18integrate_positionP7vector3S0_d, .-_Z18integrate_positionP7vector3S0_d
.globl _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.type _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, @function
_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7leapintP7vector3S0_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, .-_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.globl _Z7leapintP7vector3S0_d
.type _Z7leapintP7vector3S0_d, @function
_Z7leapintP7vector3S0_d:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7leapintP7vector3S0_d, .-_Z7leapintP7vector3S0_d
.globl _Z41__device_stub__Z14print_positionP7vector3P7vector3
.type _Z41__device_stub__Z14print_positionP7vector3P7vector3, @function
_Z41__device_stub__Z14print_positionP7vector3P7vector3:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14print_positionP7vector3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z41__device_stub__Z14print_positionP7vector3P7vector3, .-_Z41__device_stub__Z14print_positionP7vector3P7vector3
.globl _Z14print_positionP7vector3
.type _Z14print_positionP7vector3, @function
_Z14print_positionP7vector3:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z14print_positionP7vector3, .-_Z14print_positionP7vector3
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $480000, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $480000, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rbp
leaq 240000(%rbp), %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 240000(%r13), %r14
.L37:
leaq 240000(%rbx), %rsi
movq %rbx, %rdi
call _Z12new_particleP7vector3S0_
addq $24, %rbx
cmpq %r14, %rbx
jne .L37
movl $4000000, %esi
movl $1, %edi
call cudaDeviceSetLimit@PLT
movl $1, %ecx
movl $480000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $120, %ebx
jmp .L42
.L49:
movq %rbp, %rdi
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
jmp .L38
.L50:
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
jmp .L39
.L51:
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
jmp .L40
.L41:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L48
.L42:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L39:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movsd .LC6(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
jmp .L41
.L48:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L43:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %rbp, %rdi
call _Z41__device_stub__Z14print_positionP7vector3P7vector3
jmp .L43
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z14print_positionP7vector3"
.LC8:
.string "_Z7leapintP7vector3S0_d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z18integrate_positionP7vector3S0_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_positionP7vector3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7leapintP7vector3S0_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18integrate_positionP7vector3S0_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 1431655765
.long -1075489451
.align 8
.LC2:
.long 0
.long -1075838976
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC5:
.long 1405670641
.long 1075388923
.align 8
.LC6:
.long -1717986918
.long 1069128089
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "plummer.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0xbfe5555555555555 # double -0.66666666666666663
.LCPI0_2:
.quad 0xbff0000000000000 # double -1
.LCPI0_3:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_4:
.quad 0x3ff0000000000000 # double 1
.LCPI0_5:
.quad 0x401921fb53c8d4f1 # double 6.2831853000000004
.LCPI0_6:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_7:
.zero 16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $480000, %edi # imm = 0x75300
callq malloc
movq %rax, %rbx
leaq 120(%rsp), %rdi
movl $480000, %esi # imm = 0x75300
callq hipMalloc
movq 120(%rsp), %r15
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_6: # %call.sqrt124
# in Loop: Header=BB0_1 Depth=1
callq sqrt
.LBB0_7: # %.split.split
# in Loop: Header=BB0_1 Depth=1
movsd %xmm0, 56(%rsp) # 8-byte Spill
leaq (%rbx,%r14), %r12
addq $240000, %r12 # imm = 0x3A980
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rbx,%r14)
xorpd %xmm0, %xmm0
movupd %xmm0, (%r12)
movq $0, 16(%r12)
addq $24, %r14
cmpq $240000, %r14 # imm = 0x3A980
je .LBB0_8
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI0_2(%rip), %xmm0
movsd .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
movsd %xmm0, 56(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq rand
movl %eax, %ebp
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm0, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%rbx,%r14)
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
movsd %xmm0, 56(%rsp) # 8-byte Spill
subsd %xmm1, %xmm0
ucomisd .LCPI0_6(%rip), %xmm0
jb .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_3: # %call.sqrt
# in Loop: Header=BB0_1 Depth=1
callq sqrt
.LBB0_4: # %.split
# in Loop: Header=BB0_1 Depth=1
movsd %xmm0, 128(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
divsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_5(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq cos
mulsd 128(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r14)
movsd 16(%rbx,%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ucomisd .LCPI0_6(%rip), %xmm1
jb .LBB0_6
# %bb.5: # in Loop: Header=BB0_1 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_7
.LBB0_8:
movabsq $4294967336, %r14 # imm = 0x100000028
leaq 240000(%r15), %r13
movl $4000000, %esi # imm = 0x3D0900
movl $1, %edi
callq hipDeviceSetLimit
movq 120(%rsp), %rdi
movl $480000, %edx # imm = 0x75300
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $120, %ebp
leaq 216(%r14), %r12
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB0_18
.LBB0_9: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=1
movq %r15, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z14print_positionP7vector3, %edi
movq %rsp, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_11: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7leapintP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z18integrate_positionP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15: # in Loop: Header=BB0_9 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16: # in Loop: Header=BB0_9 Depth=1
movq %r15, 16(%rsp)
movq %r13, 8(%rsp)
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7leapintP7vector3S0_d, %edi
leaq 64(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_17
.LBB0_18:
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_20
# %bb.19:
movq %r15, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z14print_positionP7vector3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_20:
callq hipDeviceSynchronize
movq %rbx, %rdi
callq free
movq 120(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12new_particleP7vector3S0_
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbfe5555555555555 # double -0.66666666666666663
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x401921fb53c8d4f1 # double 6.2831853000000004
.LCPI1_6:
.quad 0x0000000000000000 # double 0
.text
.globl _Z12new_particleP7vector3S0_
.p2align 4, 0x90
.type _Z12new_particleP7vector3S0_,@function
_Z12new_particleP7vector3S0_: # @_Z12new_particleP7vector3S0_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI1_2(%rip), %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq rand
cvtsi2sd %eax, %xmm2
divsd .LCPI1_0(%rip), %xmm2
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm0, %xmm0
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%r14)
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
movsd %xmm0, (%rsp) # 8-byte Spill
subsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB1_3
.LBB1_2: # %call.sqrt
movsd %xmm2, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB1_3: # %.split
movsd %xmm0, 16(%rsp) # 8-byte Spill
mulsd .LCPI1_5(%rip), %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14)
movsd 16(%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ucomisd .LCPI1_6(%rip), %xmm1
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt17
callq sqrt
.LBB1_6: # %.split.split
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%r14)
xorpd %xmm0, %xmm0
movupd %xmm0, (%rbx)
movq $0, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12new_particleP7vector3S0_, .Lfunc_end1-_Z12new_particleP7vector3S0_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__print_positionP7vector3 # -- Begin function _Z29__device_stub__print_positionP7vector3
.p2align 4, 0x90
.type _Z29__device_stub__print_positionP7vector3,@function
_Z29__device_stub__print_positionP7vector3: # @_Z29__device_stub__print_positionP7vector3
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14print_positionP7vector3, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z29__device_stub__print_positionP7vector3, .Lfunc_end2-_Z29__device_stub__print_positionP7vector3
.cfi_endproc
# -- End function
.globl _Z22__device_stub__leapintP7vector3S0_d # -- Begin function _Z22__device_stub__leapintP7vector3S0_d
.p2align 4, 0x90
.type _Z22__device_stub__leapintP7vector3S0_d,@function
_Z22__device_stub__leapintP7vector3S0_d: # @_Z22__device_stub__leapintP7vector3S0_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7leapintP7vector3S0_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__leapintP7vector3S0_d, .Lfunc_end3-_Z22__device_stub__leapintP7vector3S0_d
.cfi_endproc
# -- End function
.globl _Z33__device_stub__integrate_positionP7vector3S0_d # -- Begin function _Z33__device_stub__integrate_positionP7vector3S0_d
.p2align 4, 0x90
.type _Z33__device_stub__integrate_positionP7vector3S0_d,@function
_Z33__device_stub__integrate_positionP7vector3S0_d: # @_Z33__device_stub__integrate_positionP7vector3S0_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18integrate_positionP7vector3S0_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z33__device_stub__integrate_positionP7vector3S0_d, .Lfunc_end4-_Z33__device_stub__integrate_positionP7vector3S0_d
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9unirandomv
.LCPI5_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z9unirandomv
.p2align 4, 0x90
.type _Z9unirandomv,@function
_Z9unirandomv: # @_Z9unirandomv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9unirandomv, .Lfunc_end5-_Z9unirandomv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18integrate_positionP7vector3S0_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7leapintP7vector3S0_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_positionP7vector3, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_positionP7vector3,@object # @_Z14print_positionP7vector3
.section .rodata,"a",@progbits
.globl _Z14print_positionP7vector3
.p2align 3, 0x0
_Z14print_positionP7vector3:
.quad _Z29__device_stub__print_positionP7vector3
.size _Z14print_positionP7vector3, 8
.type _Z7leapintP7vector3S0_d,@object # @_Z7leapintP7vector3S0_d
.globl _Z7leapintP7vector3S0_d
.p2align 3, 0x0
_Z7leapintP7vector3S0_d:
.quad _Z22__device_stub__leapintP7vector3S0_d
.size _Z7leapintP7vector3S0_d, 8
.type _Z18integrate_positionP7vector3S0_d,@object # @_Z18integrate_positionP7vector3S0_d
.globl _Z18integrate_positionP7vector3S0_d
.p2align 3, 0x0
_Z18integrate_positionP7vector3S0_d:
.quad _Z33__device_stub__integrate_positionP7vector3S0_d
.size _Z18integrate_positionP7vector3S0_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18integrate_positionP7vector3S0_d"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7leapintP7vector3S0_d"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14print_positionP7vector3"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_positionP7vector3
.addrsig_sym _Z22__device_stub__leapintP7vector3S0_d
.addrsig_sym _Z33__device_stub__integrate_positionP7vector3S0_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_positionP7vector3
.addrsig_sym _Z7leapintP7vector3S0_d
.addrsig_sym _Z18integrate_positionP7vector3S0_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess){
cout << endl << file << ", line" << line << ": " << cudaGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
cudaMalloc(&d_b, nbytes); CUDA_CHECK;
cudaMalloc(&d_c, nbytes); CUDA_CHECK;
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, nbytes, cudaMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, nbytes, cudaMemcpyDeviceToHost);CUDA_CHECK;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} | code for sm_80
Function : _Z10add_arraysPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess){
cout << endl << file << ", line" << line << ": " << cudaGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
cudaMalloc(&d_b, nbytes); CUDA_CHECK;
cudaMalloc(&d_c, nbytes); CUDA_CHECK;
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, nbytes, cudaMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, nbytes, cudaMemcpyDeviceToHost);CUDA_CHECK;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .file "tmpxft_00132163_00000000-6_addArrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line"
.LC1:
.string ": "
.LC2:
.string "("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z3addff
.type _Z3addff, @function
_Z3addff:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z3addff, .-_Z3addff
.globl _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_arraysPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
.globl _Z10add_arraysPfS_S_i
.type _Z10add_arraysPfS_S_i, @function
_Z10add_arraysPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z10add_arraysPfS_S_i, .-_Z10add_arraysPfS_S_i
.section .rodata.str1.1
.LC4:
.string "_Z10add_arraysPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_arraysPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4006:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L28
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L29
cmpq $1, %rax
jne .L24
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L25:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L31:
call __stack_chk_fail@PLT
.L29:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L23:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L25
.L24:
testq %rax, %rax
je .L25
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC7:
.string "CPU:"
.LC8:
.string "+"
.LC9:
.string "="
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gaow0007/GPUcode/master/basic_kernels/addArrays.cu"
.section .rodata.str1.1
.LC11:
.string "GPU"
.LC12:
.string ":"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $4096, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r15
movl $4096, %edi
call _Znam@PLT
movq %rax, %r14
movl $4096, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %ebx
.L33:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L33
movl $0, %eax
.L34:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L34
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L39
.L67:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L65:
call __stack_chk_fail@PLT
.L37:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L38:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $4096, %rbx
je .L66
.L39:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L67
cmpb $0, 56(%r12)
je .L37
movzbl 67(%r12), %esi
jmp .L38
.L66:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq 64(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movl $49, %esi
movq %rbx, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
.LEHB2:
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $50, %esi
movq %rbx, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
.LEHB4:
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $51, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
.LEHB6:
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $256, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L40:
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq 64(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $57, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
jmp .L69
.L68:
movl $1024, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
.LEHB8:
call _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
jmp .L40
.L69:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L45
.L72:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L70
call _ZSt16__throw_bad_castv@PLT
.L70:
call __stack_chk_fail@PLT
.L43:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L44:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $1024, %rbx
je .L71
.L45:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L72
cmpb $0, 56(%r12)
je .L43
movzbl 67(%r12), %esi
jmp .L44
.L71:
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L57:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L58:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L55-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L56-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L57-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L58-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess){
cout << endl << file << ", line" << line << ": " << cudaGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
cudaMalloc(&d_b, nbytes); CUDA_CHECK;
cudaMalloc(&d_c, nbytes); CUDA_CHECK;
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, nbytes, cudaMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, nbytes, cudaMemcpyDeviceToHost);CUDA_CHECK;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
hipError_t e = hipGetLastError();
if (e != hipSuccess){
cout << endl << file << ", line" << line << ": " << hipGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
hipMalloc(&d_b, nbytes); CUDA_CHECK;
hipMalloc(&d_c, nbytes); CUDA_CHECK;
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, nbytes, hipMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
hipMemcpy(c, d_c, nbytes, hipMemcpyDeviceToHost);CUDA_CHECK;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
hipError_t e = hipGetLastError();
if (e != hipSuccess){
cout << endl << file << ", line" << line << ": " << hipGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
hipMalloc(&d_b, nbytes); CUDA_CHECK;
hipMalloc(&d_c, nbytes); CUDA_CHECK;
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, nbytes, hipMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
hipMemcpy(c, d_c, nbytes, hipMemcpyDeviceToHost);CUDA_CHECK;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPfS_S_i
.globl _Z10add_arraysPfS_S_i
.p2align 8
.type _Z10add_arraysPfS_S_i,@function
_Z10add_arraysPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPfS_S_i, .Lfunc_end0-_Z10add_arraysPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
using namespace std;
const int N = 1024;
const int THREAD_SIZE = 256;
#define CUDA_CHECK cuda_check(__FILE__, __LINE__)
void cuda_check(string file, int line){
hipError_t e = hipGetLastError();
if (e != hipSuccess){
cout << endl << file << ", line" << line << ": " << hipGetErrorString(e) << "(" << e << ")" << endl;
exit(1);
}
}
__device__ float add(float a, float b){
return a + b;
}
__global__ void add_arrays(float* a, float* b, float* c, int n){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) {
c[ind] = add(a[ind], b[ind]);
}
}
int main(int argc, char** argv){
float *a = new float[N];
float *b = new float[N];
float *c = new float[N];
for (int i = 0; i < N; ++ i){
a[i] = rand();
b[i] = rand();
c[i] = 0;
}
for (int i = 0; i < N; ++ i) c[i] = a[i] + b[i];
cout << "CPU:" << endl;
for (int i = 0; i < N; ++ i)
cout << a[i] << "+" << b[i] << "=" << c[i] << endl;
cout << endl;
float *d_a = NULL;
float *d_b = NULL;
float *d_c = NULL;
size_t nbytes = N * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
hipMalloc(&d_b, nbytes); CUDA_CHECK;
hipMalloc(&d_c, nbytes); CUDA_CHECK;
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, nbytes, hipMemcpyHostToDevice);
dim3 block = dim3(THREAD_SIZE, 1, 1);
dim3 grid = dim3((N + block.x - 1) / block.x, 1, 1);
add_arrays <<<grid, block>>> (d_a, d_b, d_c, N);
hipMemcpy(c, d_c, nbytes, hipMemcpyDeviceToHost);CUDA_CHECK;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
cout << "GPU" << endl;
for (int i = 0; i < N; ++ i)
cout << i << ":" << a[i] << "+" << b[i] << "=" << c[i] << endl;
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .text
.file "addArrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_arraysPfS_S_i # -- Begin function _Z25__device_stub__add_arraysPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_arraysPfS_S_i,@function
_Z25__device_stub__add_arraysPfS_S_i: # @_Z25__device_stub__add_arraysPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_arraysPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_arraysPfS_S_i, .Lfunc_end1-_Z25__device_stub__add_arraysPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_56
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_33: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $1024, %r13 # imm = 0x400
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_10
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i119
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r12)
je .LBB2_33
# %bb.32: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_34
.LBB2_11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_57
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%r12)
je .LBB2_14
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 152(%rsp), %r12
movq %r12, 136(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 136(%rsp)
movq $108, 152(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 144(%rsp)
movb $0, 108(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $49, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.16:
movq 136(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_18
# %bb.17: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 120(%rsp), %r12
movq %r12, 104(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 104(%rsp)
movq $108, 120(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 112(%rsp)
movb $0, 108(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
movl $50, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.19:
movq 104(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_21
# %bb.20: # %.critedge.i.i78
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit80
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 88(%rsp), %r12
movq %r12, 72(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 72(%rsp)
movq $108, 88(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 80(%rsp)
movb $0, 108(%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movl $51, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp7:
# %bb.22:
movq 72(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_24
# %bb.23: # %.critedge.i.i88
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit90
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_26
# %bb.25:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 36(%rsp), %rax
movq %rax, 264(%rsp)
.cfi_escape 0x2e, 0x00
leaq 200(%rsp), %rdi
leaq 184(%rsp), %rsi
leaq 176(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 200(%rsp), %rsi
movl 208(%rsp), %edx
movq 184(%rsp), %rcx
movl 192(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 240(%rsp), %r9
movl $_Z10add_arraysPfS_S_i, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i100
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 56(%rsp), %r12
movq %r12, 40(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 40(%rsp)
movq $108, 56(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 48(%rsp)
movb $0, 108(%rax)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $57, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.27:
movq 40(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_29
# %bb.28: # %.critedge.i.i107
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit109
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_30
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
cmpb $0, 56(%r12)
je .LBB2_45
# %bb.44:
movzbl 67(%r12), %eax
jmp .LBB2_46
.LBB2_45:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_53: # in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
# in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB2_55
.LBB2_47: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_48
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r13)
je .LBB2_53
# %bb.52: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_54
.LBB2_55:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 336
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_48:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_57:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_30:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_49:
.Ltmp11:
movq %rax, %rbx
movq 40(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.50: # %.critedge.i.i110
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_41:
.Ltmp8:
movq %rax, %rbx
movq 72(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.42: # %.critedge.i.i97
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_39:
.Ltmp5:
movq %rax, %rbx
movq 104(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.40: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_35:
.Ltmp2:
movq %rax, %rbx
movq 136(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.36: # %.critedge.i.i91
.cfi_escape 0x2e, 0x00
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit93
callq _ZdlPv
.LBB2_38: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit93
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_arraysPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "("
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z10add_arraysPfS_S_i,@object # @_Z10add_arraysPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_arraysPfS_S_i
.p2align 3, 0x0
_Z10add_arraysPfS_S_i:
.quad _Z25__device_stub__add_arraysPfS_S_i
.size _Z10add_arraysPfS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "+"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "="
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gaow0007/GPUcode/master/basic_kernels/addArrays.hip"
.size .L.str.7, 109
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz ":"
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_arraysPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_arraysPfS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10add_arraysPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_arraysPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPfS_S_i
.globl _Z10add_arraysPfS_S_i
.p2align 8
.type _Z10add_arraysPfS_S_i,@function
_Z10add_arraysPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPfS_S_i, .Lfunc_end0-_Z10add_arraysPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132163_00000000-6_addArrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line"
.LC1:
.string ": "
.LC2:
.string "("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z3addff
.type _Z3addff, @function
_Z3addff:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z3addff, .-_Z3addff
.globl _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_arraysPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
.globl _Z10add_arraysPfS_S_i
.type _Z10add_arraysPfS_S_i, @function
_Z10add_arraysPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z10add_arraysPfS_S_i, .-_Z10add_arraysPfS_S_i
.section .rodata.str1.1
.LC4:
.string "_Z10add_arraysPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_arraysPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4006:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L28
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L29
cmpq $1, %rax
jne .L24
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L25:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L31:
call __stack_chk_fail@PLT
.L29:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L23:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L25
.L24:
testq %rax, %rax
je .L25
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC7:
.string "CPU:"
.LC8:
.string "+"
.LC9:
.string "="
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gaow0007/GPUcode/master/basic_kernels/addArrays.cu"
.section .rodata.str1.1
.LC11:
.string "GPU"
.LC12:
.string ":"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $4096, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r15
movl $4096, %edi
call _Znam@PLT
movq %rax, %r14
movl $4096, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %ebx
.L33:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L33
movl $0, %eax
.L34:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L34
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L39
.L67:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L65:
call __stack_chk_fail@PLT
.L37:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L38:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $4096, %rbx
je .L66
.L39:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L67
cmpb $0, 56(%r12)
je .L37
movzbl 67(%r12), %esi
jmp .L38
.L66:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq 64(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movl $49, %esi
movq %rbx, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
.LEHB2:
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $50, %esi
movq %rbx, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
.LEHB4:
call cudaMalloc@PLT
leaq 52(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $51, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
.LEHB6:
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $256, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L40:
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq 64(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $57, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
jmp .L69
.L68:
movl $1024, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
.LEHB8:
call _Z35__device_stub__Z10add_arraysPfS_S_iPfS_S_i
jmp .L40
.L69:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L45
.L72:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L70
call _ZSt16__throw_bad_castv@PLT
.L70:
call __stack_chk_fail@PLT
.L43:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L44:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $1024, %rbx
je .L71
.L45:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L72
cmpb $0, 56(%r12)
je .L43
movzbl 67(%r12), %esi
jmp .L44
.L71:
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L57:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L58:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L55-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L56-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L57-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L58-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addArrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_arraysPfS_S_i # -- Begin function _Z25__device_stub__add_arraysPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_arraysPfS_S_i,@function
_Z25__device_stub__add_arraysPfS_S_i: # @_Z25__device_stub__add_arraysPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_arraysPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_arraysPfS_S_i, .Lfunc_end1-_Z25__device_stub__add_arraysPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_56
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_33: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $1024, %r13 # imm = 0x400
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_10
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i119
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r12)
je .LBB2_33
# %bb.32: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_34
.LBB2_11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_57
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%r12)
je .LBB2_14
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 152(%rsp), %r12
movq %r12, 136(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 136(%rsp)
movq $108, 152(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 144(%rsp)
movb $0, 108(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $49, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.16:
movq 136(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_18
# %bb.17: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 120(%rsp), %r12
movq %r12, 104(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 104(%rsp)
movq $108, 120(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 112(%rsp)
movb $0, 108(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
movl $50, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.19:
movq 104(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_21
# %bb.20: # %.critedge.i.i78
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit80
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 88(%rsp), %r12
movq %r12, 72(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 72(%rsp)
movq $108, 88(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 80(%rsp)
movb $0, 108(%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movl $51, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp7:
# %bb.22:
movq 72(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_24
# %bb.23: # %.critedge.i.i88
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit90
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_26
# %bb.25:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 36(%rsp), %rax
movq %rax, 264(%rsp)
.cfi_escape 0x2e, 0x00
leaq 200(%rsp), %rdi
leaq 184(%rsp), %rsi
leaq 176(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 200(%rsp), %rsi
movl 208(%rsp), %edx
movq 184(%rsp), %rcx
movl 192(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 240(%rsp), %r9
movl $_Z10add_arraysPfS_S_i, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i100
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 56(%rsp), %r12
movq %r12, 40(%rsp)
.cfi_escape 0x2e, 0x00
movl $109, %edi
callq _Znwm
movq %rax, 40(%rsp)
movq $108, 56(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+92(%rip), %xmm0
movups %xmm0, 92(%rax)
movq $108, 48(%rsp)
movb $0, 108(%rax)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $57, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.27:
movq 40(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_29
# %bb.28: # %.critedge.i.i107
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit109
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_30
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
cmpb $0, 56(%r12)
je .LBB2_45
# %bb.44:
movzbl 67(%r12), %eax
jmp .LBB2_46
.LBB2_45:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_53: # in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
# in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB2_55
.LBB2_47: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_48
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r13)
je .LBB2_53
# %bb.52: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_54
.LBB2_55:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 336
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_48:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_57:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_30:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_49:
.Ltmp11:
movq %rax, %rbx
movq 40(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.50: # %.critedge.i.i110
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_41:
.Ltmp8:
movq %rax, %rbx
movq 72(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.42: # %.critedge.i.i97
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_39:
.Ltmp5:
movq %rax, %rbx
movq 104(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.40: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
jmp .LBB2_37
.LBB2_35:
.Ltmp2:
movq %rax, %rbx
movq 136(%rsp), %rdi
cmpq %r12, %rdi
je .LBB2_38
# %bb.36: # %.critedge.i.i91
.cfi_escape 0x2e, 0x00
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit93
callq _ZdlPv
.LBB2_38: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit93
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_arraysPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "("
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z10add_arraysPfS_S_i,@object # @_Z10add_arraysPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_arraysPfS_S_i
.p2align 3, 0x0
_Z10add_arraysPfS_S_i:
.quad _Z25__device_stub__add_arraysPfS_S_i
.size _Z10add_arraysPfS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "+"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "="
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gaow0007/GPUcode/master/basic_kernels/addArrays.hip"
.size .L.str.7, 109
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz ":"
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_arraysPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_arraysPfS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10add_arraysPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
cudaDeviceSynchronize();
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
cudaDeviceSynchronize();
}
#endif | .file "tmpxft_0004b501_00000000-6_cp_0_nhwc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
cudaDeviceSynchronize();
}
#endif | #include <hip/hip_runtime.h>
#if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
hipDeviceSynchronize();
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
hipDeviceSynchronize();
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#if GOOGLE_CUDA
#define EIGEN_USE_GPU
__global__ void default_function_kernel0(const float* __restrict__ U, const float* __restrict__ K0, float* __restrict__ U0) {
float U0_local[1];
__shared__ float U_shared[128];
__shared__ float K0_shared[4];
for (int n_inner_outer = 0; n_inner_outer < 2; ++n_inner_outer) {
for (int h_inner_outer = 0; h_inner_outer < 2; ++h_inner_outer) {
for (int r_inner_outer = 0; r_inner_outer < 6; ++r_inner_outer) {
U0_local[0] = 0.000000e+00f;
for (int k0_c_outer = 0; k0_c_outer < 4; ++k0_c_outer) {
__syncthreads();
for (int ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner = 0; ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner < 4; ++ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) {
U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)] = U[(((((((((((((int)blockIdx.z) / 8) * 32768) + (((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 128) * 16384)) + (n_inner_outer * 16384)) + ((((int)blockIdx.z) % 8) * 2048)) + (h_inner_outer * 1024)) + ((((((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) % 128) / 64) * 512)) + (((int)blockIdx.y) * 256)) + ((((((int)threadIdx.y) * 4) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner) / 4) * 16)) + (k0_c_outer * 4)) + ax0_ax1_ax2_ax3_fused_fused_fused_inner_inner_inner)];
}
if ((((int)threadIdx.z) * 2) < (4 - ((int)threadIdx.y))) {
if (((int)threadIdx.y) < 2) {
if (((k0_c_outer * 4) + (((int)threadIdx.z) * 2)) < (16 - ((int)threadIdx.y))) {
K0_shared[((((int)threadIdx.z) * 2) + ((int)threadIdx.y))] = K0[((((k0_c_outer * 24) + (((int)threadIdx.z) * 12)) + (((int)threadIdx.y) * 6)) + r_inner_outer)];
}
}
}
__syncthreads();
for (int k0_c_inner = 0; k0_c_inner < 4; ++k0_c_inner) {
U0_local[0] = (U0_local[0] + (U_shared[(((((int)threadIdx.z) * 64) + (((int)threadIdx.y) * 4)) + k0_c_inner)] * K0_shared[k0_c_inner]));
}
}
U0[(((((((((((int)blockIdx.z) / 8) * 12288) + (n_inner_outer * 6144)) + ((((int)blockIdx.z) % 8) * 768)) + (h_inner_outer * 384)) + (((int)threadIdx.z) * 192)) + (((int)blockIdx.y) * 96)) + (((int)threadIdx.y) * 6)) + r_inner_outer)] = U0_local[0];
}
}
}
}
void Cp0NhwcKernelLauncher(const float* U, const float* K0, float* U0){
dim3 gridDim0(1, 2, 32);
dim3 blockDim0(1, 16, 2);
default_function_kernel0<<<gridDim0, blockDim0>>>(U, K0, U0);
hipDeviceSynchronize();
}
#endif | .text
.file "cp_0_nhwc.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b501_00000000-6_cp_0_nhwc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cp_0_nhwc.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} | code for sm_80
Function : copy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : matrix_sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R7.reuse, c[0x0][0x170], R0.reuse ; /* 0x00005c0007027a24 */
/* 0x140fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x180], R0 ; /* 0x0000600007047a24 */
/* 0x000fce00078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R7, R7, c[0x0][0x190], R0 ; /* 0x0000640007077a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : hadamard
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R7.reuse, c[0x0][0x170], R0.reuse ; /* 0x00005c0007027a24 */
/* 0x140fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x180], R0 ; /* 0x0000600007047a24 */
/* 0x000fce00078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R7, R7, c[0x0][0x190], R0 ; /* 0x0000640007077a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0140*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} | .file "tmpxft_000f581a_00000000-6_elemWiseFloat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
.type _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i, @function
_Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq hadamard(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i, .-_Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
.globl hadamard
.type hadamard, @function
hadamard:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size hadamard, .-hadamard
.globl _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
.type _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i, @function
_Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrix_sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i, .-_Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
.globl matrix_sum
.type matrix_sum, @function
matrix_sum:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size matrix_sum, .-matrix_sum
.globl _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
.type _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i, @function
_Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq copy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i, .-_Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
.globl copy
.type copy, @function
copy:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size copy, .-copy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copy"
.LC1:
.string "matrix_sum"
.LC2:
.string "hadamard"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq copy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq matrix_sum(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq hadamard(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} | #include <hip/hip_runtime.h>
/*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected hadamard
.globl hadamard
.p2align 8
.type hadamard,@function
hadamard:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_mad_u64_u32 v[4:5], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel hadamard
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size hadamard, .Lfunc_end0-hadamard
.section .AMDGPU.csdata,"",@progbits
.text
.protected matrix_sum
.globl matrix_sum
.p2align 8
.type matrix_sum,@function
matrix_sum:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_clause 0x3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_mad_u64_u32 v[4:5], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrix_sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size matrix_sum, .Lfunc_end1-matrix_sum
.section .AMDGPU.csdata,"",@progbits
.text
.protected copy
.globl copy
.p2align 8
.type copy,@function
copy:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel copy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size copy, .Lfunc_end2-copy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: hadamard
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: hadamard.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrix_sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrix_sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: copy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: copy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Kernel for calulating the element-wise product of two matrices
* m, n --> dimensions of matrices A, B, C
*/
extern "C" {
__global__ void hadamard(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] * B[i + j*ldb];
}
}
/*
* Matrix sum, parameters as above
*/
extern "C" {
__global__ void matrix_sum(int m, int n, float *A, int lda, float *B, int ldb, float *C, int ldc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
C[i + j*ldc] = A[i + j*lda] + B[i + j*ldb];
}
}
/*
* Copy of elements
*/
extern "C" {
__global__ void copy(int m, int n, float *dst, int lddst, float *src, int ldsrc)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= m || j >= n) return;
dst[i + j*lddst] = src[i + j*ldsrc];
}
} | .text
.file "elemWiseFloat.hip"
.globl __device_stub__hadamard # -- Begin function __device_stub__hadamard
.p2align 4, 0x90
.type __device_stub__hadamard,@function
__device_stub__hadamard: # @__device_stub__hadamard
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $hadamard, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__hadamard, .Lfunc_end0-__device_stub__hadamard
.cfi_endproc
# -- End function
.globl __device_stub__matrix_sum # -- Begin function __device_stub__matrix_sum
.p2align 4, 0x90
.type __device_stub__matrix_sum,@function
__device_stub__matrix_sum: # @__device_stub__matrix_sum
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_sum, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__matrix_sum, .Lfunc_end1-__device_stub__matrix_sum
.cfi_endproc
# -- End function
.globl __device_stub__copy # -- Begin function __device_stub__copy
.p2align 4, 0x90
.type __device_stub__copy,@function
__device_stub__copy: # @__device_stub__copy
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $copy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__copy, .Lfunc_end2-__device_stub__copy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $hadamard, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_sum, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copy, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type hadamard,@object # @hadamard
.section .rodata,"a",@progbits
.globl hadamard
.p2align 3, 0x0
hadamard:
.quad __device_stub__hadamard
.size hadamard, 8
.type matrix_sum,@object # @matrix_sum
.globl matrix_sum
.p2align 3, 0x0
matrix_sum:
.quad __device_stub__matrix_sum
.size matrix_sum, 8
.type copy,@object # @copy
.globl copy
.p2align 3, 0x0
copy:
.quad __device_stub__copy
.size copy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "hadamard"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "matrix_sum"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "copy"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__hadamard
.addrsig_sym __device_stub__matrix_sum
.addrsig_sym __device_stub__copy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hadamard
.addrsig_sym matrix_sum
.addrsig_sym copy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : copy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : matrix_sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R7.reuse, c[0x0][0x170], R0.reuse ; /* 0x00005c0007027a24 */
/* 0x140fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x180], R0 ; /* 0x0000600007047a24 */
/* 0x000fce00078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R7, R7, c[0x0][0x190], R0 ; /* 0x0000640007077a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : hadamard
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R7.reuse, c[0x0][0x170], R0.reuse ; /* 0x00005c0007027a24 */
/* 0x140fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x180], R0 ; /* 0x0000600007047a24 */
/* 0x000fce00078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R7, R7, c[0x0][0x190], R0 ; /* 0x0000640007077a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0140*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected hadamard
.globl hadamard
.p2align 8
.type hadamard,@function
hadamard:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_mad_u64_u32 v[4:5], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel hadamard
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size hadamard, .Lfunc_end0-hadamard
.section .AMDGPU.csdata,"",@progbits
.text
.protected matrix_sum
.globl matrix_sum
.p2align 8
.type matrix_sum,@function
matrix_sum:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_clause 0x3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_mad_u64_u32 v[4:5], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrix_sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size matrix_sum, .Lfunc_end1-matrix_sum
.section .AMDGPU.csdata,"",@progbits
.text
.protected copy
.globl copy
.p2align 8
.type copy,@function
copy:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel copy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size copy, .Lfunc_end2-copy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: hadamard
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: hadamard.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrix_sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrix_sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: copy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: copy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f581a_00000000-6_elemWiseFloat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
.type _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i, @function
_Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq hadamard(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i, .-_Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
.globl hadamard
.type hadamard, @function
hadamard:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z8hadamardiiPfiS_iS_iiiPfiS_iS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size hadamard, .-hadamard
.globl _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
.type _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i, @function
_Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrix_sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i, .-_Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
.globl matrix_sum
.type matrix_sum, @function
matrix_sum:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z10matrix_sumiiPfiS_iS_iiiPfiS_iS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size matrix_sum, .-matrix_sum
.globl _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
.type _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i, @function
_Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq copy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i, .-_Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
.globl copy
.type copy, @function
copy:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4copyiiPfiS_iiiPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size copy, .-copy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copy"
.LC1:
.string "matrix_sum"
.LC2:
.string "hadamard"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq copy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq matrix_sum(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq hadamard(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "elemWiseFloat.hip"
.globl __device_stub__hadamard # -- Begin function __device_stub__hadamard
.p2align 4, 0x90
.type __device_stub__hadamard,@function
__device_stub__hadamard: # @__device_stub__hadamard
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $hadamard, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__hadamard, .Lfunc_end0-__device_stub__hadamard
.cfi_endproc
# -- End function
.globl __device_stub__matrix_sum # -- Begin function __device_stub__matrix_sum
.p2align 4, 0x90
.type __device_stub__matrix_sum,@function
__device_stub__matrix_sum: # @__device_stub__matrix_sum
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_sum, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__matrix_sum, .Lfunc_end1-__device_stub__matrix_sum
.cfi_endproc
# -- End function
.globl __device_stub__copy # -- Begin function __device_stub__copy
.p2align 4, 0x90
.type __device_stub__copy,@function
__device_stub__copy: # @__device_stub__copy
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $copy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__copy, .Lfunc_end2-__device_stub__copy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $hadamard, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_sum, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copy, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type hadamard,@object # @hadamard
.section .rodata,"a",@progbits
.globl hadamard
.p2align 3, 0x0
hadamard:
.quad __device_stub__hadamard
.size hadamard, 8
.type matrix_sum,@object # @matrix_sum
.globl matrix_sum
.p2align 3, 0x0
matrix_sum:
.quad __device_stub__matrix_sum
.size matrix_sum, 8
.type copy,@object # @copy
.globl copy
.p2align 3, 0x0
copy:
.quad __device_stub__copy
.size copy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "hadamard"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "matrix_sum"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "copy"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__hadamard
.addrsig_sym __device_stub__matrix_sum
.addrsig_sym __device_stub__copy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hadamard
.addrsig_sym matrix_sum
.addrsig_sym copy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS+2], /* values at time t */
oldval[MAXPOINTS+2], /* values at time (t-dt) */
newval[MAXPOINTS+2]; /* values at time (t+dt) */
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, fac, k, tmp;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
k = 0.0;
tmp = tpoints - 1;
for (j = 1; j <= tpoints; j++) {
x = k/tmp;
values[j] = sin (fac * x);
k = k + 1.0;
}
/* Initialize old values array */
for (i = 1; i <= tpoints; i++)
oldval[i] = values[i];
}
/**********************************************************************
* Calculate new values using wave equation
*********************************************************************/
void do_math(int i)
{
float dtime, c, dx, tau, sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[i] = (2.0 * values[i]) - oldval[i] + (sqtau * (-2.0)*values[i]);
}
/**********************************************************************
* Update all values along line a specified number of times
*********************************************************************/
__device__ inline unsigned global_thread_id() {
/* Get global thread idx */
return blockIdx.x * blockDim.x + threadIdx.x;
}
__global__ void update_parallel(float *t_values, int nsteps, int tpoints) {
float l_value, lo_value, ln_value;
unsigned idx = global_thread_id();
/* Initailize */
lo_value = l_value = sin((2.0 * PI) * ((float)idx / (float)(tpoints - 1)));
for (int i = 0; i < nsteps; ++i) {
/* Calculate Math */
ln_value = 1.82 * l_value - lo_value;
lo_value = l_value;
l_value = ln_value;
}
if (idx == 0 || idx == tpoints - 1) {
t_values[idx] = 0;
} else if (idx < tpoints - 1 && idx > 0) {
t_values[idx] = l_value;
}
}
void update()
{
int i, j;
/* Update values for each time step */
for (i = 1; i<= nsteps; i++) {
/* Update points along line for this time step */
for (j = 1; j <= tpoints; j++) {
/* global endpoints */
if ((j == 1) || (j == tpoints))
newval[j] = 0.0;
else
do_math(j);
}
/* Update old values with new values */
for (j = 1; j <= tpoints; j++) {
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
for (i = 0; i < tpoints; i++) {
printf("%6.4f ", values[i]);
if (i % 10 == 9)
printf("\n");
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
float *t_values;
cudaMalloc(&t_values, sizeof(values));
printf("Initializing points on the line...\n");
//init_line();
printf("Updating all points for all time steps...\n");
//update();
update_parallel<<<((tpoints + 1023) >> 10), 1024>>>(t_values, nsteps, tpoints);
cudaMemcpy(values, t_values, sizeof(values), cudaMemcpyDeviceToHost);
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .file "tmpxft_000d16a4_00000000-6_wave.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.globl _Z9init_linev
.type _Z9init_linev, @function
_Z9init_linev:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl tpoints(%rip), %eax
leal -1(%rax), %edx
pxor %xmm3, %xmm3
cvtsi2ssl %edx, %xmm3
movss %xmm3, 12(%rsp)
testl %eax, %eax
jle .L17
leaq 4+values(%rip), %rbx
leal -1(%rax), %r12d
leaq 4(%rbx), %rax
leaq (%rax,%r12,4), %r13
movl $0x00000000, %ebp
.L19:
movd %ebp, %xmm0
divss 12(%rsp), %xmm0
mulss .LC7(%rip), %xmm0
call sinf@PLT
movss %xmm0, (%rbx)
movd %ebp, %xmm1
addss .LC8(%rip), %xmm1
movd %xmm1, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L19
addq $2, %r12
movl $1, %eax
leaq oldval(%rip), %rcx
leaq values(%rip), %rdx
.L20:
movss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq %r12, %rax
jne .L20
.L17:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9init_linev, .-_Z9init_linev
.globl _Z7do_mathi
.type _Z7do_mathi, @function
_Z7do_mathi:
.LFB2059:
.cfi_startproc
endbr64
movslq %edi, %rdi
leaq values(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rdi,4), %xmm1
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
leaq oldval(%rip), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rdi,4), %xmm2
subsd %xmm2, %xmm0
mulsd .LC9(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
leaq newval(%rip), %rax
movss %xmm0, (%rax,%rdi,4)
ret
.cfi_endproc
.LFE2059:
.size _Z7do_mathi, .-_Z7do_mathi
.globl _Z6updatev
.type _Z6updatev, @function
_Z6updatev:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $1, %r14d
leaq newval(%rip), %r12
leaq oldval(%rip), %r13
leaq values(%rip), %rbp
cmpl $0, nsteps(%rip)
jg .L26
.L25:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $0x00000000, (%r12,%rbx,4)
.L30:
movl tpoints(%rip), %eax
addq $1, %rbx
cmpl %ebx, %eax
jl .L42
.L31:
cmpl %ebx, %eax
je .L36
cmpl $1, %ebx
je .L36
movl %ebx, %edi
call _Z7do_mathi
jmp .L30
.L42:
testl %eax, %eax
jle .L32
leal 1(%rax), %edx
movl $1, %eax
.L33:
movss 0(%rbp,%rax,4), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movss (%r12,%rax,4), %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L33
.L32:
addl $1, %r14d
cmpl %r14d, nsteps(%rip)
jl .L25
.L26:
movl tpoints(%rip), %eax
movl $1, %ebx
testl %eax, %eax
jg .L31
jmp .L32
.cfi_endproc
.LFE2061:
.size _Z6updatev, .-_Z6updatev
.section .rodata.str1.1
.LC10:
.string "%6.4f "
.LC11:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB2062:
.cfi_startproc
endbr64
cmpl $0, tpoints(%rip)
jle .L49
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %ebx
leaq values(%rip), %r12
leaq .LC10(%rip), %rbp
leaq .LC11(%rip), %r13
jmp .L46
.L45:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jle .L52
.L46:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
jne .L45
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L52:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2062:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z37__device_stub__Z15update_parallelPfiiPfii
.type _Z37__device_stub__Z15update_parallelPfiiPfii, @function
_Z37__device_stub__Z15update_parallelPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15update_parallelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z37__device_stub__Z15update_parallelPfiiPfii, .-_Z37__device_stub__Z15update_parallelPfiiPfii
.globl _Z15update_parallelPfii
.type _Z15update_parallelPfii, @function
_Z15update_parallelPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15update_parallelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15update_parallelPfii, .-_Z15update_parallelPfii
.section .rodata.str1.1
.LC12:
.string "%d"
.section .rodata.str1.8
.align 8
.LC13:
.string "Initializing points on the line...\n"
.align 8
.LC14:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC15:
.string "Printing final results...\n"
.LC16:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC12(%rip), %rbp
movq %rbp, %rsi
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
leaq 8(%rsp), %rdi
movl $4000008, %esi
call cudaMalloc@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl tpoints(%rip), %eax
addl $1023, %eax
sarl $10, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L62:
movl $2, %ecx
movl $4000008, %edx
movq 8(%rsp), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printfinalv
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L66
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl tpoints(%rip), %edx
movl nsteps(%rip), %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z15update_parallelPfiiPfii
jmp .L62
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z15update_parallelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15update_parallelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl newval
.bss
.align 32
.type newval, @object
.size newval, 4000008
newval:
.zero 4000008
.globl oldval
.align 32
.type oldval, @object
.size oldval, 4000008
oldval:
.zero 4000008
.globl values
.align 32
.type values, @object
.size values, 4000008
values:
.zero 4000008
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1086918619
.align 4
.LC8:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -2147483648
.long -1077474755
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS+2], /* values at time t */
oldval[MAXPOINTS+2], /* values at time (t-dt) */
newval[MAXPOINTS+2]; /* values at time (t+dt) */
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, fac, k, tmp;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
k = 0.0;
tmp = tpoints - 1;
for (j = 1; j <= tpoints; j++) {
x = k/tmp;
values[j] = sin (fac * x);
k = k + 1.0;
}
/* Initialize old values array */
for (i = 1; i <= tpoints; i++)
oldval[i] = values[i];
}
/**********************************************************************
* Calculate new values using wave equation
*********************************************************************/
void do_math(int i)
{
float dtime, c, dx, tau, sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[i] = (2.0 * values[i]) - oldval[i] + (sqtau * (-2.0)*values[i]);
}
/**********************************************************************
* Update all values along line a specified number of times
*********************************************************************/
__device__ inline unsigned global_thread_id() {
/* Get global thread idx */
return blockIdx.x * blockDim.x + threadIdx.x;
}
__global__ void update_parallel(float *t_values, int nsteps, int tpoints) {
float l_value, lo_value, ln_value;
unsigned idx = global_thread_id();
/* Initailize */
lo_value = l_value = sin((2.0 * PI) * ((float)idx / (float)(tpoints - 1)));
for (int i = 0; i < nsteps; ++i) {
/* Calculate Math */
ln_value = 1.82 * l_value - lo_value;
lo_value = l_value;
l_value = ln_value;
}
if (idx == 0 || idx == tpoints - 1) {
t_values[idx] = 0;
} else if (idx < tpoints - 1 && idx > 0) {
t_values[idx] = l_value;
}
}
void update()
{
int i, j;
/* Update values for each time step */
for (i = 1; i<= nsteps; i++) {
/* Update points along line for this time step */
for (j = 1; j <= tpoints; j++) {
/* global endpoints */
if ((j == 1) || (j == tpoints))
newval[j] = 0.0;
else
do_math(j);
}
/* Update old values with new values */
for (j = 1; j <= tpoints; j++) {
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
for (i = 0; i < tpoints; i++) {
printf("%6.4f ", values[i]);
if (i % 10 == 9)
printf("\n");
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
float *t_values;
cudaMalloc(&t_values, sizeof(values));
printf("Initializing points on the line...\n");
//init_line();
printf("Updating all points for all time steps...\n");
//update();
update_parallel<<<((tpoints + 1023) >> 10), 1024>>>(t_values, nsteps, tpoints);
cudaMemcpy(values, t_values, sizeof(values), cudaMemcpyDeviceToHost);
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS+2], /* values at time t */
oldval[MAXPOINTS+2], /* values at time (t-dt) */
newval[MAXPOINTS+2]; /* values at time (t+dt) */
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, fac, k, tmp;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
k = 0.0;
tmp = tpoints - 1;
for (j = 1; j <= tpoints; j++) {
x = k/tmp;
values[j] = sin (fac * x);
k = k + 1.0;
}
/* Initialize old values array */
for (i = 1; i <= tpoints; i++)
oldval[i] = values[i];
}
/**********************************************************************
* Calculate new values using wave equation
*********************************************************************/
void do_math(int i)
{
float dtime, c, dx, tau, sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[i] = (2.0 * values[i]) - oldval[i] + (sqtau * (-2.0)*values[i]);
}
/**********************************************************************
* Update all values along line a specified number of times
*********************************************************************/
__device__ inline unsigned global_thread_id() {
/* Get global thread idx */
return blockIdx.x * blockDim.x + threadIdx.x;
}
__global__ void update_parallel(float *t_values, int nsteps, int tpoints) {
float l_value, lo_value, ln_value;
unsigned idx = global_thread_id();
/* Initailize */
lo_value = l_value = sin((2.0 * PI) * ((float)idx / (float)(tpoints - 1)));
for (int i = 0; i < nsteps; ++i) {
/* Calculate Math */
ln_value = 1.82 * l_value - lo_value;
lo_value = l_value;
l_value = ln_value;
}
if (idx == 0 || idx == tpoints - 1) {
t_values[idx] = 0;
} else if (idx < tpoints - 1 && idx > 0) {
t_values[idx] = l_value;
}
}
void update()
{
int i, j;
/* Update values for each time step */
for (i = 1; i<= nsteps; i++) {
/* Update points along line for this time step */
for (j = 1; j <= tpoints; j++) {
/* global endpoints */
if ((j == 1) || (j == tpoints))
newval[j] = 0.0;
else
do_math(j);
}
/* Update old values with new values */
for (j = 1; j <= tpoints; j++) {
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
for (i = 0; i < tpoints; i++) {
printf("%6.4f ", values[i]);
if (i % 10 == 9)
printf("\n");
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
float *t_values;
hipMalloc(&t_values, sizeof(values));
printf("Initializing points on the line...\n");
//init_line();
printf("Updating all points for all time steps...\n");
//update();
update_parallel<<<((tpoints + 1023) >> 10), 1024>>>(t_values, nsteps, tpoints);
hipMemcpy(values, t_values, sizeof(values), hipMemcpyDeviceToHost);
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS+2], /* values at time t */
oldval[MAXPOINTS+2], /* values at time (t-dt) */
newval[MAXPOINTS+2]; /* values at time (t+dt) */
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, fac, k, tmp;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
k = 0.0;
tmp = tpoints - 1;
for (j = 1; j <= tpoints; j++) {
x = k/tmp;
values[j] = sin (fac * x);
k = k + 1.0;
}
/* Initialize old values array */
for (i = 1; i <= tpoints; i++)
oldval[i] = values[i];
}
/**********************************************************************
* Calculate new values using wave equation
*********************************************************************/
void do_math(int i)
{
float dtime, c, dx, tau, sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[i] = (2.0 * values[i]) - oldval[i] + (sqtau * (-2.0)*values[i]);
}
/**********************************************************************
* Update all values along line a specified number of times
*********************************************************************/
__device__ inline unsigned global_thread_id() {
/* Get global thread idx */
return blockIdx.x * blockDim.x + threadIdx.x;
}
__global__ void update_parallel(float *t_values, int nsteps, int tpoints) {
float l_value, lo_value, ln_value;
unsigned idx = global_thread_id();
/* Initailize */
lo_value = l_value = sin((2.0 * PI) * ((float)idx / (float)(tpoints - 1)));
for (int i = 0; i < nsteps; ++i) {
/* Calculate Math */
ln_value = 1.82 * l_value - lo_value;
lo_value = l_value;
l_value = ln_value;
}
if (idx == 0 || idx == tpoints - 1) {
t_values[idx] = 0;
} else if (idx < tpoints - 1 && idx > 0) {
t_values[idx] = l_value;
}
}
void update()
{
int i, j;
/* Update values for each time step */
for (i = 1; i<= nsteps; i++) {
/* Update points along line for this time step */
for (j = 1; j <= tpoints; j++) {
/* global endpoints */
if ((j == 1) || (j == tpoints))
newval[j] = 0.0;
else
do_math(j);
}
/* Update old values with new values */
for (j = 1; j <= tpoints; j++) {
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
for (i = 0; i < tpoints; i++) {
printf("%6.4f ", values[i]);
if (i % 10 == 9)
printf("\n");
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
float *t_values;
hipMalloc(&t_values, sizeof(values));
printf("Initializing points on the line...\n");
//init_line();
printf("Updating all points for all time steps...\n");
//update();
update_parallel<<<((tpoints + 1023) >> 10), 1024>>>(t_values, nsteps, tpoints);
hipMemcpy(values, t_values, sizeof(values), hipMemcpyDeviceToHost);
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15update_parallelPfii
.globl _Z15update_parallelPfii
.p2align 8
.type _Z15update_parallelPfii,@function
_Z15update_parallelPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0xc
s_mov_b32 s3, 0x401921fb
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s4, -1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_i32_e32 v0, s4
s_mov_b32 s2, 0x53c8d4f1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, v1
v_div_scale_f32 v3, null, v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v0, v3, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v0
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f64_e64 0x41d00000, |v[2:3]|
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_2
v_ldexp_f64 v[4:5], |v[2:3]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
v_trig_preop_f64 v[6:7], |v[2:3]|, 0
v_and_b32_e32 v0, 0x7fffffff, v3
v_trig_preop_f64 v[8:9], |v[2:3]|, 1
v_trig_preop_f64 v[18:19], |v[2:3]|, 2
v_mov_b32_e32 v26, 0
s_mov_b32 s7, 0x3ff921fb
s_mov_b32 s6, 0x54442d18
s_mov_b32 s9, 0x3c91a626
s_mov_b32 s8, 0x33145c07
v_dual_cndmask_b32 v5, v0, v5 :: v_dual_cndmask_b32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[10:11], v[6:7], v[4:5]
v_mul_f64 v[12:13], v[8:9], v[4:5]
v_mul_f64 v[24:25], v[18:19], v[4:5]
v_fma_f64 v[6:7], v[6:7], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[8:9], v[4:5], -v[12:13]
v_fma_f64 v[4:5], v[18:19], v[4:5], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], v[6:7]
v_add_f64 v[16:17], v[14:15], -v[12:13]
v_add_f64 v[22:23], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[14:15], -v[16:17]
v_add_f64 v[6:7], v[6:7], -v[16:17]
v_ldexp_f64 v[16:17], v[22:23], -2
v_add_f64 v[10:11], v[22:23], -v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[12:13], v[12:13], -v[20:21]
v_add_f64 v[20:21], v[24:25], v[8:9]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[14:15], -v[10:11]
v_add_f64 v[6:7], v[6:7], v[12:13]
v_fract_f64_e32 v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[20:21], v[6:7]
v_dual_cndmask_b32 v13, 0, v13 :: v_dual_cndmask_b32 v12, 0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[12:13], v[12:13], 2
v_add_f64 v[16:17], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[22:23], v[16:17], v[12:13]
v_add_f64 v[10:11], v[16:17], -v[10:11]
v_cmp_gt_f64_e32 vcc_lo, 0, v[22:23]
v_add_f64 v[22:23], v[20:21], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[14:15], -v[10:11]
v_cndmask_b32_e64 v27, 0, 0x40100000, vcc_lo
v_add_f64 v[31:32], v[20:21], -v[22:23]
v_add_f64 v[8:9], v[8:9], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[12:13], v[12:13], v[26:27]
v_add_f64 v[27:28], v[14:15], -v[20:21]
v_add_f64 v[22:23], v[24:25], -v[31:32]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[29:30], v[16:17], v[12:13]
v_add_f64 v[33:34], v[14:15], -v[27:28]
v_add_f64 v[6:7], v[6:7], -v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[8:9], v[22:23]
v_cvt_i32_f64_e32 v0, v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[20:21], -v[33:34]
v_cvt_f64_i32_e32 v[27:28], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[20:21]
v_add_f64 v[12:13], v[12:13], -v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[8:9], v[6:7]
v_add_f64 v[8:9], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[8:9], -v[12:13]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[10:11], v[4:5]
v_add_f64 v[6:7], v[16:17], -v[6:7]
v_cndmask_b32_e64 v27, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v0, s2, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[8:9], -v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[6:7], v[4:5]
v_mul_f64 v[10:11], v[8:9], s[6:7]
v_add_f64 v[6:7], v[8:9], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], s[6:7], -v[10:11]
v_add_f64 v[4:5], v[4:5], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[8:9], s[8:9], v[12:13]
v_fma_f64 v[6:7], v[4:5], s[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], v[6:7]
v_add_f64 v[8:9], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[8:9]
.LBB0_2:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_mov_b32 s7, 0x3fe45f30
s_mov_b32 s6, 0x6dc9c883
s_mov_b32 s9, 0xbc91a626
v_mul_f64 v[4:5], |v[2:3]|, s[6:7]
s_mov_b32 s7, 0xbff921fb
s_mov_b32 s6, 0x54442d18
s_mov_b32 s8, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[8:9], v[4:5]
v_fma_f64 v[4:5], v[8:9], s[6:7], |v[2:3]|
v_mul_f64 v[6:7], v[8:9], s[8:9]
s_mov_b32 s7, 0xb97b839a
s_mov_b32 s6, 0x252049c0
v_cvt_i32_f64_e32 v0, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[8:9], s[8:9], v[4:5]
v_add_f64 v[10:11], v[4:5], v[6:7]
s_mov_b32 s9, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[10:11]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_fma_f64 v[6:7], v[8:9], s[8:9], v[6:7]
v_add_f64 v[4:5], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_fma_f64 v[6:7], v[8:9], s[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[12:13], v[6:7]
v_add_f64 v[10:11], v[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[10:11]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f64 v[8:9], v[4:5], v[4:5]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s7, 0x3de5e0b2
s_mov_b32 s6, 0xf9a43bb8
s_mov_b32 s9, 0x3ec71de3
s_mov_b32 s8, 0x796cde01
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[6:7], 0.5
s_load_b32 s5, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
v_fma_f64 v[10:11], v[8:9], s[6:7], s[2:3]
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
s_mov_b32 s7, 0xbda907db
s_mov_b32 s6, 0x46cc5e42
v_mul_f64 v[14:15], v[8:9], 0.5
v_fma_f64 v[12:13], v[8:9], s[6:7], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_mov_b32 s7, 0xbf2a01a0
s_mov_b32 s6, 0x19e83e5c
v_mul_f64 v[20:21], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[8:9]
v_add_f64 v[16:17], -v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
v_fma_f64 v[10:11], v[8:9], v[10:11], s[6:7]
s_mov_b32 s7, 0x3f811111
s_mov_b32 s6, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], -v[16:17], 1.0
v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[6:7]
v_add_f64 v[14:15], v[22:23], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[10:11], v[20:21], v[10:11], v[18:19]
v_mul_f64 v[18:19], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[4:5], -v[6:7], v[14:15]
v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[8:9], v[10:11], -v[6:7]
v_fma_f64 v[8:9], v[18:19], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[20:21], s[2:3], v[6:7]
v_cmp_class_f64_e64 s2, v[2:3], 0x1f8
v_add_f64 v[8:9], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_and_b32_e32 v6, 1, v0
v_lshlrev_b32_e32 v0, 30, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_and_b32_e32 v0, 0x80000000, v0
v_cndmask_b32_e32 v2, v9, v5, vcc_lo
v_cndmask_b32_e32 v4, v8, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v2, v0
v_cndmask_b32_e64 v2, 0, v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x7ff80000, v0, s2
v_cvt_f32_f64_e32 v0, v[2:3]
s_cbranch_scc1 .LBB0_7
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v0
s_mov_b32 s3, 0x3ffd1eb8
s_mov_b32 s2, 0x51eb851f
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v0
v_cvt_f64_f32_e32 v[5:6], v2
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s5, 0
v_cvt_f64_f32_e32 v[3:4], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[3:4], s[2:3], -v[5:6]
v_cvt_f32_f64_e32 v0, v[2:3]
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_6
.LBB0_7:
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cmp_eq_u32_e64 s2, s4, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_xor_b32 s5, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s5
v_cmp_gt_u32_e32 vcc_lo, s4, v1
v_mov_b32_e32 v3, v0
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s4
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15update_parallelPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15update_parallelPfii, .Lfunc_end0-_Z15update_parallelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15update_parallelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15update_parallelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS+2], /* values at time t */
oldval[MAXPOINTS+2], /* values at time (t-dt) */
newval[MAXPOINTS+2]; /* values at time (t+dt) */
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, fac, k, tmp;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
k = 0.0;
tmp = tpoints - 1;
for (j = 1; j <= tpoints; j++) {
x = k/tmp;
values[j] = sin (fac * x);
k = k + 1.0;
}
/* Initialize old values array */
for (i = 1; i <= tpoints; i++)
oldval[i] = values[i];
}
/**********************************************************************
* Calculate new values using wave equation
*********************************************************************/
void do_math(int i)
{
float dtime, c, dx, tau, sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[i] = (2.0 * values[i]) - oldval[i] + (sqtau * (-2.0)*values[i]);
}
/**********************************************************************
* Update all values along line a specified number of times
*********************************************************************/
__device__ inline unsigned global_thread_id() {
/* Get global thread idx */
return blockIdx.x * blockDim.x + threadIdx.x;
}
__global__ void update_parallel(float *t_values, int nsteps, int tpoints) {
float l_value, lo_value, ln_value;
unsigned idx = global_thread_id();
/* Initailize */
lo_value = l_value = sin((2.0 * PI) * ((float)idx / (float)(tpoints - 1)));
for (int i = 0; i < nsteps; ++i) {
/* Calculate Math */
ln_value = 1.82 * l_value - lo_value;
lo_value = l_value;
l_value = ln_value;
}
if (idx == 0 || idx == tpoints - 1) {
t_values[idx] = 0;
} else if (idx < tpoints - 1 && idx > 0) {
t_values[idx] = l_value;
}
}
void update()
{
int i, j;
/* Update values for each time step */
for (i = 1; i<= nsteps; i++) {
/* Update points along line for this time step */
for (j = 1; j <= tpoints; j++) {
/* global endpoints */
if ((j == 1) || (j == tpoints))
newval[j] = 0.0;
else
do_math(j);
}
/* Update old values with new values */
for (j = 1; j <= tpoints; j++) {
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
for (i = 0; i < tpoints; i++) {
printf("%6.4f ", values[i]);
if (i % 10 == 9)
printf("\n");
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
float *t_values;
hipMalloc(&t_values, sizeof(values));
printf("Initializing points on the line...\n");
//init_line();
printf("Updating all points for all time steps...\n");
//update();
update_parallel<<<((tpoints + 1023) >> 10), 1024>>>(t_values, nsteps, tpoints);
hipMemcpy(values, t_values, sizeof(values), hipMemcpyDeviceToHost);
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.file "wave.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9init_linev
.LCPI1_0:
.long 0x40c90fdb # float 6.28318548
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z9init_linev
.p2align 4, 0x90
.type _Z9init_linev,@function
_Z9init_linev: # @_Z9init_linev
.cfi_startproc
# %bb.0:
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_0(%rip), %xmm0
callq sinf
movss %xmm0, values+4(,%rbx,4)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI1_1(%rip), %xmm0
movslq tpoints(%rip), %rax
incq %rbx
cmpq %rax, %rbx
jl .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_4: # %.preheader
testl %eax, %eax
jle .LBB1_5
# %bb.6: # %.lr.ph19.preheader
movl %eax, %edx
shlq $2, %rdx
movl $oldval+4, %edi
movl $values+4, %esi
jmp memcpy@PLT # TAILCALL
.LBB1_5: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9init_linev, .Lfunc_end1-_Z9init_linev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7do_mathi
.LCPI2_0:
.quad 0xbfc70a3d80000000 # double -0.18000000715255737
.text
.globl _Z7do_mathi
.p2align 4, 0x90
.type _Z7do_mathi,@function
_Z7do_mathi: # @_Z7do_mathi
.cfi_startproc
# %bb.0:
movslq %edi, %rax
movss values(,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm0, %xmm1
movss oldval(,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
subsd %xmm2, %xmm1
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, newval(,%rax,4)
retq
.Lfunc_end2:
.size _Z7do_mathi, .Lfunc_end2-_Z7do_mathi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__update_parallelPfii # -- Begin function _Z30__device_stub__update_parallelPfii
.p2align 4, 0x90
.type _Z30__device_stub__update_parallelPfii,@function
_Z30__device_stub__update_parallelPfii: # @_Z30__device_stub__update_parallelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15update_parallelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z30__device_stub__update_parallelPfii, .Lfunc_end3-_Z30__device_stub__update_parallelPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6updatev
.LCPI4_0:
.quad 0xbfc70a3d80000000 # double -0.18000000715255737
.text
.globl _Z6updatev
.p2align 4, 0x90
.type _Z6updatev,@function
_Z6updatev: # @_Z6updatev
.cfi_startproc
# %bb.0:
movl nsteps(%rip), %eax
testl %eax, %eax
jle .LBB4_12
# %bb.1: # %.preheader18.lr.ph
movl tpoints(%rip), %ecx
leal 1(%rcx), %edx
leaq -4(,%rcx,4), %rsi
leaq -4(,%rdx,4), %rdi
shlq $2, %rdx
movl $1, %r8d
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_11: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
leal 1(%r8), %r9d
cmpl %eax, %r8d
movl %r9d, %r8d
je .LBB4_12
.LBB4_2: # %.preheader18
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_10 Depth 2
testl %ecx, %ecx
jle .LBB4_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
xorl %r9d, %r9d
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_4 Depth=2
movss %xmm1, newval+4(%r9)
addq $4, %r9
cmpq %r9, %rdi
je .LBB4_8
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
testq %r9, %r9
je .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=2
cmpq %r9, %rsi
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_4 Depth=2
movss values+4(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movaps %xmm1, %xmm2
addsd %xmm1, %xmm2
movss oldval+4(%r9), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
subsd %xmm3, %xmm2
mulsd %xmm0, %xmm1
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_8: # %.preheader
# in Loop: Header=BB4_2 Depth=1
testl %ecx, %ecx
jle .LBB4_11
# %bb.9: # %.lr.ph23.preheader
# in Loop: Header=BB4_2 Depth=1
movl $4, %r9d
.p2align 4, 0x90
.LBB4_10: # %.lr.ph23
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss values(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, oldval(%r9)
movss newval(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, values(%r9)
addq $4, %r9
cmpq %r9, %rdx
jne .LBB4_10
jmp .LBB4_11
.LBB4_12: # %._crit_edge26
retq
.Lfunc_end4:
.size _Z6updatev, .Lfunc_end4-_Z6updatev
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
cmpl $0, tpoints(%rip)
jle .LBB5_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r14 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB5_5
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r14
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB5_4
.LBB5_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB5_6: # %._crit_edge
retq
.Lfunc_end5:
.size _Z10printfinalv, .Lfunc_end5-_Z10printfinalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
leaq 16(%rsp), %rdi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1023, %edi # imm = 0x3FF
addl tpoints(%rip), %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 16(%rsp), %rax
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movq %rax, 72(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15update_parallelPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 16(%rsp), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, tpoints(%rip)
jle .LBB6_7
# %bb.3: # %.lr.ph.i.preheader
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r14 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB6_7
.LBB6_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r14
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB6_6
.LBB6_7: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15update_parallelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000008
.size values, 4000008
.type oldval,@object # @oldval
.globl oldval
.p2align 4, 0x0
oldval:
.zero 4000008
.size oldval, 4000008
.type newval,@object # @newval
.globl newval
.p2align 4, 0x0
newval:
.zero 4000008
.size newval, 4000008
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z15update_parallelPfii,@object # @_Z15update_parallelPfii
.section .rodata,"a",@progbits
.globl _Z15update_parallelPfii
.p2align 3, 0x0
_Z15update_parallelPfii:
.quad _Z30__device_stub__update_parallelPfii
.size _Z15update_parallelPfii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15update_parallelPfii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__update_parallelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym _Z15update_parallelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d16a4_00000000-6_wave.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.globl _Z9init_linev
.type _Z9init_linev, @function
_Z9init_linev:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl tpoints(%rip), %eax
leal -1(%rax), %edx
pxor %xmm3, %xmm3
cvtsi2ssl %edx, %xmm3
movss %xmm3, 12(%rsp)
testl %eax, %eax
jle .L17
leaq 4+values(%rip), %rbx
leal -1(%rax), %r12d
leaq 4(%rbx), %rax
leaq (%rax,%r12,4), %r13
movl $0x00000000, %ebp
.L19:
movd %ebp, %xmm0
divss 12(%rsp), %xmm0
mulss .LC7(%rip), %xmm0
call sinf@PLT
movss %xmm0, (%rbx)
movd %ebp, %xmm1
addss .LC8(%rip), %xmm1
movd %xmm1, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L19
addq $2, %r12
movl $1, %eax
leaq oldval(%rip), %rcx
leaq values(%rip), %rdx
.L20:
movss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq %r12, %rax
jne .L20
.L17:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9init_linev, .-_Z9init_linev
.globl _Z7do_mathi
.type _Z7do_mathi, @function
_Z7do_mathi:
.LFB2059:
.cfi_startproc
endbr64
movslq %edi, %rdi
leaq values(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rdi,4), %xmm1
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
leaq oldval(%rip), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rdi,4), %xmm2
subsd %xmm2, %xmm0
mulsd .LC9(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
leaq newval(%rip), %rax
movss %xmm0, (%rax,%rdi,4)
ret
.cfi_endproc
.LFE2059:
.size _Z7do_mathi, .-_Z7do_mathi
.globl _Z6updatev
.type _Z6updatev, @function
_Z6updatev:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $1, %r14d
leaq newval(%rip), %r12
leaq oldval(%rip), %r13
leaq values(%rip), %rbp
cmpl $0, nsteps(%rip)
jg .L26
.L25:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $0x00000000, (%r12,%rbx,4)
.L30:
movl tpoints(%rip), %eax
addq $1, %rbx
cmpl %ebx, %eax
jl .L42
.L31:
cmpl %ebx, %eax
je .L36
cmpl $1, %ebx
je .L36
movl %ebx, %edi
call _Z7do_mathi
jmp .L30
.L42:
testl %eax, %eax
jle .L32
leal 1(%rax), %edx
movl $1, %eax
.L33:
movss 0(%rbp,%rax,4), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movss (%r12,%rax,4), %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L33
.L32:
addl $1, %r14d
cmpl %r14d, nsteps(%rip)
jl .L25
.L26:
movl tpoints(%rip), %eax
movl $1, %ebx
testl %eax, %eax
jg .L31
jmp .L32
.cfi_endproc
.LFE2061:
.size _Z6updatev, .-_Z6updatev
.section .rodata.str1.1
.LC10:
.string "%6.4f "
.LC11:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB2062:
.cfi_startproc
endbr64
cmpl $0, tpoints(%rip)
jle .L49
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %ebx
leaq values(%rip), %r12
leaq .LC10(%rip), %rbp
leaq .LC11(%rip), %r13
jmp .L46
.L45:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jle .L52
.L46:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
jne .L45
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L52:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2062:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z37__device_stub__Z15update_parallelPfiiPfii
.type _Z37__device_stub__Z15update_parallelPfiiPfii, @function
_Z37__device_stub__Z15update_parallelPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15update_parallelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z37__device_stub__Z15update_parallelPfiiPfii, .-_Z37__device_stub__Z15update_parallelPfiiPfii
.globl _Z15update_parallelPfii
.type _Z15update_parallelPfii, @function
_Z15update_parallelPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15update_parallelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15update_parallelPfii, .-_Z15update_parallelPfii
.section .rodata.str1.1
.LC12:
.string "%d"
.section .rodata.str1.8
.align 8
.LC13:
.string "Initializing points on the line...\n"
.align 8
.LC14:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC15:
.string "Printing final results...\n"
.LC16:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC12(%rip), %rbp
movq %rbp, %rsi
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
leaq 8(%rsp), %rdi
movl $4000008, %esi
call cudaMalloc@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl tpoints(%rip), %eax
addl $1023, %eax
sarl $10, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L62:
movl $2, %ecx
movl $4000008, %edx
movq 8(%rsp), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printfinalv
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L66
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl tpoints(%rip), %edx
movl nsteps(%rip), %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z15update_parallelPfiiPfii
jmp .L62
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z15update_parallelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15update_parallelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl newval
.bss
.align 32
.type newval, @object
.size newval, 4000008
newval:
.zero 4000008
.globl oldval
.align 32
.type oldval, @object
.size oldval, 4000008
oldval:
.zero 4000008
.globl values
.align 32
.type values, @object
.size values, 4000008
values:
.zero 4000008
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1086918619
.align 4
.LC8:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -2147483648
.long -1077474755
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wave.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9init_linev
.LCPI1_0:
.long 0x40c90fdb # float 6.28318548
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z9init_linev
.p2align 4, 0x90
.type _Z9init_linev,@function
_Z9init_linev: # @_Z9init_linev
.cfi_startproc
# %bb.0:
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_0(%rip), %xmm0
callq sinf
movss %xmm0, values+4(,%rbx,4)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI1_1(%rip), %xmm0
movslq tpoints(%rip), %rax
incq %rbx
cmpq %rax, %rbx
jl .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_4: # %.preheader
testl %eax, %eax
jle .LBB1_5
# %bb.6: # %.lr.ph19.preheader
movl %eax, %edx
shlq $2, %rdx
movl $oldval+4, %edi
movl $values+4, %esi
jmp memcpy@PLT # TAILCALL
.LBB1_5: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9init_linev, .Lfunc_end1-_Z9init_linev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7do_mathi
.LCPI2_0:
.quad 0xbfc70a3d80000000 # double -0.18000000715255737
.text
.globl _Z7do_mathi
.p2align 4, 0x90
.type _Z7do_mathi,@function
_Z7do_mathi: # @_Z7do_mathi
.cfi_startproc
# %bb.0:
movslq %edi, %rax
movss values(,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm0, %xmm1
movss oldval(,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
subsd %xmm2, %xmm1
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, newval(,%rax,4)
retq
.Lfunc_end2:
.size _Z7do_mathi, .Lfunc_end2-_Z7do_mathi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__update_parallelPfii # -- Begin function _Z30__device_stub__update_parallelPfii
.p2align 4, 0x90
.type _Z30__device_stub__update_parallelPfii,@function
_Z30__device_stub__update_parallelPfii: # @_Z30__device_stub__update_parallelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15update_parallelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z30__device_stub__update_parallelPfii, .Lfunc_end3-_Z30__device_stub__update_parallelPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6updatev
.LCPI4_0:
.quad 0xbfc70a3d80000000 # double -0.18000000715255737
.text
.globl _Z6updatev
.p2align 4, 0x90
.type _Z6updatev,@function
_Z6updatev: # @_Z6updatev
.cfi_startproc
# %bb.0:
movl nsteps(%rip), %eax
testl %eax, %eax
jle .LBB4_12
# %bb.1: # %.preheader18.lr.ph
movl tpoints(%rip), %ecx
leal 1(%rcx), %edx
leaq -4(,%rcx,4), %rsi
leaq -4(,%rdx,4), %rdi
shlq $2, %rdx
movl $1, %r8d
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_11: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
leal 1(%r8), %r9d
cmpl %eax, %r8d
movl %r9d, %r8d
je .LBB4_12
.LBB4_2: # %.preheader18
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_10 Depth 2
testl %ecx, %ecx
jle .LBB4_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
xorl %r9d, %r9d
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_4 Depth=2
movss %xmm1, newval+4(%r9)
addq $4, %r9
cmpq %r9, %rdi
je .LBB4_8
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
testq %r9, %r9
je .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=2
cmpq %r9, %rsi
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_4 Depth=2
movss values+4(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movaps %xmm1, %xmm2
addsd %xmm1, %xmm2
movss oldval+4(%r9), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
subsd %xmm3, %xmm2
mulsd %xmm0, %xmm1
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_8: # %.preheader
# in Loop: Header=BB4_2 Depth=1
testl %ecx, %ecx
jle .LBB4_11
# %bb.9: # %.lr.ph23.preheader
# in Loop: Header=BB4_2 Depth=1
movl $4, %r9d
.p2align 4, 0x90
.LBB4_10: # %.lr.ph23
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss values(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, oldval(%r9)
movss newval(%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, values(%r9)
addq $4, %r9
cmpq %r9, %rdx
jne .LBB4_10
jmp .LBB4_11
.LBB4_12: # %._crit_edge26
retq
.Lfunc_end4:
.size _Z6updatev, .Lfunc_end4-_Z6updatev
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
cmpl $0, tpoints(%rip)
jle .LBB5_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r14 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB5_5
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r14
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB5_4
.LBB5_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB5_6: # %._crit_edge
retq
.Lfunc_end5:
.size _Z10printfinalv, .Lfunc_end5-_Z10printfinalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
leaq 16(%rsp), %rdi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1023, %edi # imm = 0x3FF
addl tpoints(%rip), %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 16(%rsp), %rax
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movq %rax, 72(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15update_parallelPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 16(%rsp), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, tpoints(%rip)
jle .LBB6_7
# %bb.3: # %.lr.ph.i.preheader
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r14 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB6_7
.LBB6_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r14
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB6_6
.LBB6_7: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15update_parallelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000008
.size values, 4000008
.type oldval,@object # @oldval
.globl oldval
.p2align 4, 0x0
oldval:
.zero 4000008
.size oldval, 4000008
.type newval,@object # @newval
.globl newval
.p2align 4, 0x0
newval:
.zero 4000008
.size newval, 4000008
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z15update_parallelPfii,@object # @_Z15update_parallelPfii
.section .rodata,"a",@progbits
.globl _Z15update_parallelPfii
.p2align 3, 0x0
_Z15update_parallelPfii:
.quad _Z30__device_stub__update_parallelPfii
.size _Z15update_parallelPfii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15update_parallelPfii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__update_parallelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym _Z15update_parallelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x3, R3 ; /* 0x0000000300007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P1, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x040fe40007f3e0ff */
/*00c0*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f1e0ff */
/*00d0*/ IADD3.X R3, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x040fe40000ffe4ff */
/*00e0*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fc600007fe4ff */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1b00 */
/*0110*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*0120*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} | .file "tmpxft_000a2669_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addlPdS_lPdS_
.type _Z25__device_stub__Z3addlPdS_lPdS_, @function
_Z25__device_stub__Z3addlPdS_lPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addlPdS_lPdS_, .-_Z25__device_stub__Z3addlPdS_lPdS_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addlPdS_lPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void add (long n, double *a, double *b){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
a[i] += b[i];
}
} | .text
.file "vectorAdd.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x3, R3 ; /* 0x0000000300007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P1, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x040fe40007f3e0ff */
/*00c0*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f1e0ff */
/*00d0*/ IADD3.X R3, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x040fe40000ffe4ff */
/*00e0*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fc600007fe4ff */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1b00 */
/*0110*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*0120*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a2669_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addlPdS_lPdS_
.type _Z25__device_stub__Z3addlPdS_lPdS_, @function
_Z25__device_stub__Z3addlPdS_lPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addlPdS_lPdS_, .-_Z25__device_stub__Z3addlPdS_lPdS_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addlPdS_lPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
cudaMalloc((void**)&gpu_array_A, width*width*sizeof(float));
cudaMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_array_B, width*width*sizeof(float));
cudaMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} | code for sm_80
Function : _Z8mat_multPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e0006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e0006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
cudaMalloc((void**)&gpu_array_A, width*width*sizeof(float));
cudaMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_array_B, width*width*sizeof(float));
cudaMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} | .file "tmpxft_0014649d_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initCudai
.type _Z8initCudai, @function
_Z8initCudai:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
imull %edi, %edi
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rsi
leaq gpu_array_A(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rbp
movq %rbp, %rsi
movq gpu_array_A(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq gpu_array_B(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq gpu_array_B(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq gpu_output_array(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z8initCudai, .-_Z8initCudai
.globl _Z11cpu_mat_addPfS_S_i
.type _Z11cpu_mat_addPfS_S_i, @function
_Z11cpu_mat_addPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
movq %rdi, %r8
testl %ecx, %ecx
jle .L5
movslq %ecx, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
.L7:
leaq 0(,%r10,4), %rax
movl $0, %edi
.L8:
movss (%r8,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %ecx
jne .L8
addq $1, %r10
cmpq %r11, %r10
jne .L7
.L5:
ret
.cfi_endproc
.LFE3670:
.size _Z11cpu_mat_addPfS_S_i, .-_Z11cpu_mat_addPfS_S_i
.globl _Z11cpu_mat_subPfS_S_i
.type _Z11cpu_mat_subPfS_S_i, @function
_Z11cpu_mat_subPfS_S_i:
.LFB3671:
.cfi_startproc
endbr64
movq %rdi, %r8
testl %ecx, %ecx
jle .L10
movslq %ecx, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
.L12:
leaq 0(,%r10,4), %rax
movl $0, %edi
.L13:
movss (%r8,%rax), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %ecx
jne .L13
addq $1, %r10
cmpq %r11, %r10
jne .L12
.L10:
ret
.cfi_endproc
.LFE3671:
.size _Z11cpu_mat_subPfS_S_i, .-_Z11cpu_mat_subPfS_S_i
.globl _Z12cpu_mat_multPfS_S_i
.type _Z12cpu_mat_multPfS_S_i, @function
_Z12cpu_mat_multPfS_S_i:
.LFB3672:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L23
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r12
movq %rsi, %r9
movq %rdx, %rbx
movl %ecx, %r11d
movslq %ecx, %rax
leaq 0(,%rax,4), %rsi
addq %rsi, %r12
negq %rax
leaq 0(,%rax,4), %r10
movl $0, %ebp
movl $0, %r13d
jmp .L17
.L19:
leal 1(%rbp), %eax
addq $4, %r9
addq $4, %rbx
cmpl %r8d, %ebp
je .L15
movl %eax, %ebp
.L17:
movq %r12, %rcx
movq %rbx, %rdi
movl %r13d, %r8d
.L20:
leaq (%rcx,%r10), %rax
movq %r9, %rdx
pxor %xmm1, %xmm1
.L18:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rcx, %rax
jne .L18
movss %xmm1, (%rdi)
leal 1(%r8), %eax
addq %rsi, %rdi
addq %rsi, %rcx
cmpl %eax, %r11d
je .L19
movl %eax, %r8d
jmp .L20
.L15:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3672:
.size _Z12cpu_mat_multPfS_S_i, .-_Z12cpu_mat_multPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl _Z11printMatrixPfi
.type _Z11printMatrixPfi, @function
_Z11printMatrixPfi:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L26
movl %esi, %eax
cltq
leaq 0(,%rax,4), %r15
leaq cpu_output_array(%rip), %rbp
addq %r15, %rbp
negq %rax
salq $2, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L28
.L35:
call _ZSt16__throw_bad_castv@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L32:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
je .L26
.L28:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
jmp .L32
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z11printMatrixPfi, .-_Z11printMatrixPfi
.globl _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.globl _Z7mat_addPfS_S_i
.type _Z7mat_addPfS_S_i, @function
_Z7mat_addPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7mat_addPfS_S_i, .-_Z7mat_addPfS_S_i
.globl _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.globl _Z7mat_subPfS_S_i
.type _Z7mat_subPfS_S_i, @function
_Z7mat_subPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z7mat_subPfS_S_i, .-_Z7mat_subPfS_S_i
.globl _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.globl _Z8mat_multPfS_S_i
.type _Z8mat_multPfS_S_i, @function
_Z8mat_multPfS_S_i:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z8mat_multPfS_S_i, .-_Z8mat_multPfS_S_i
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq cpu_array(%rip), %rdx
.L61:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L61
movl $5, %edi
call _Z8initCudai
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L62:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z11cpu_mat_addPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L63:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z11cpu_mat_subPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L64:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z12cpu_mat_multPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
jmp .L62
.L69:
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
jmp .L63
.L70:
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
jmp .L64
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8mat_multPfS_S_i"
.LC3:
.string "_Z7mat_subPfS_S_i"
.LC4:
.string "_Z7mat_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimGrid
.data
.align 8
.type dimGrid, @object
.size dimGrid, 12
dimGrid:
.long 1
.long 1
.long 1
.globl dimBlock
.align 8
.type dimBlock, @object
.size dimBlock, 12
dimBlock:
.long 5
.long 5
.long 1
.globl gpu_output_array
.bss
.align 8
.type gpu_output_array, @object
.size gpu_output_array, 8
gpu_output_array:
.zero 8
.globl gpu_array_B
.align 8
.type gpu_array_B, @object
.size gpu_array_B, 8
gpu_array_B:
.zero 8
.globl gpu_array_A
.align 8
.type gpu_array_A, @object
.size gpu_array_A, 8
gpu_array_A:
.zero 8
.globl cpu_output_array
.align 32
.type cpu_output_array, @object
.size cpu_output_array, 100
cpu_output_array:
.zero 100
.globl cpu_array
.align 32
.type cpu_array, @object
.size cpu_array, 100
cpu_array:
.zero 100
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
cudaMalloc((void**)&gpu_array_A, width*width*sizeof(float));
cudaMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_array_B, width*width*sizeof(float));
cudaMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
cudaMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
hipMalloc((void**)&gpu_array_A, width*width*sizeof(float));
hipMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_array_B, width*width*sizeof(float));
hipMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
hipMalloc((void**)&gpu_array_A, width*width*sizeof(float));
hipMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_array_B, width*width*sizeof(float));
hipMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_i, .Lfunc_end0-_Z7mat_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 8
.type _Z7mat_subPfS_S_i,@function
_Z7mat_subPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_i, .Lfunc_end1-_Z7mat_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 8
.type _Z8mat_multPfS_S_i,@function
_Z8mat_multPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v6, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_i, .Lfunc_end2-_Z8mat_multPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
float cpu_array [25];
float cpu_output_array [25];
float *gpu_array_A;
float *gpu_array_B;
float *gpu_output_array;
const int mat_width = 5;
dim3 dimBlock(mat_width, mat_width);
dim3 dimGrid(1, 1);
void initCuda(int width) {
hipMalloc((void**)&gpu_array_A, width*width*sizeof(float));
hipMemcpy(gpu_array_A, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_array_B, width*width*sizeof(float));
hipMemcpy(gpu_array_B, cpu_array, width*width*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&gpu_output_array, width*width*sizeof(float));
}
__global__ void mat_add (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] + Bd[index];
}
__global__ void mat_sub (float* Ad, float* Bd, float* Pd, int width) {
int index = threadIdx.y * width + threadIdx.x;
Pd[index] = Ad[index] - Bd[index];
}
__global__ void mat_mult (float* Ad, float* Bd, float* Pd, int width) {
int tx = threadIdx.x;
int ty = threadIdx.y;
float Pvalue = 0;
for (int k = 0; k < width; k++) {
Pvalue += Ad[ty * width + k] * Bd[k * width + tx];
}
Pd[ty * width + tx] = Pvalue;
}
void cpu_mat_add (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] + B[j * width + i];
}
}
}
void cpu_mat_sub (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
P[j * width + i] = A[j * width + i] - B[j * width + i];
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void cpu_mat_mult (float* A, float* B, float* P, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
float Psum = 0;
for (int k = 0; k < width; k++) {
Psum += A[j * width + k] * B[k * width + i];
}
P[j * width + i] = Psum;
}
}
}
/***
* Simple helper function for printing a matrix.
***/
void printMatrix (float* M, int width) {
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
std::cout << cpu_output_array[i * width + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char** argv) {
for (int i = 0; i < 25; i++) {
cpu_array[i] = i;
}
initCuda(mat_width);
mat_add<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_add(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_sub<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_sub(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
mat_mult<<<dimGrid, dimBlock>>>(gpu_array_A, gpu_array_B, gpu_output_array, mat_width);
hipMemcpy(cpu_output_array, gpu_output_array, mat_width*mat_width*sizeof(float), hipMemcpyDeviceToHost);
printMatrix(cpu_output_array, mat_width);
cpu_mat_mult(cpu_array, cpu_array, cpu_output_array, mat_width);
printMatrix(cpu_output_array, mat_width);
int a;
std::cin>>a;
} | .text
.file "matrix_math.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCudai # -- Begin function _Z8initCudai
.p2align 4, 0x90
.type _Z8initCudai,@function
_Z8initCudai: # @_Z8initCudai
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edi killed $edi def $rdi
imull %edi, %edi
leaq (,%rdi,4), %rbx
movl $gpu_array_A, %edi
movq %rbx, %rsi
callq hipMalloc
movq gpu_array_A(%rip), %rdi
movl $cpu_array, %esi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $gpu_array_B, %edi
movq %rbx, %rsi
callq hipMalloc
movq gpu_array_B(%rip), %rdi
movl $cpu_array, %esi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $gpu_output_array, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size _Z8initCudai, .Lfunc_end0-_Z8initCudai
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_i # -- Begin function _Z22__device_stub__mat_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_i,@function
_Z22__device_stub__mat_addPfS_S_i: # @_Z22__device_stub__mat_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__mat_addPfS_S_i, .Lfunc_end1-_Z22__device_stub__mat_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_i # -- Begin function _Z22__device_stub__mat_subPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_i,@function
_Z22__device_stub__mat_subPfS_S_i: # @_Z22__device_stub__mat_subPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_subPfS_S_i, .Lfunc_end2-_Z22__device_stub__mat_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mat_multPfS_S_i # -- Begin function _Z23__device_stub__mat_multPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__mat_multPfS_S_i,@function
_Z23__device_stub__mat_multPfS_S_i: # @_Z23__device_stub__mat_multPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__mat_multPfS_S_i, .Lfunc_end3-_Z23__device_stub__mat_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11cpu_mat_addPfS_S_i # -- Begin function _Z11cpu_mat_addPfS_S_i
.p2align 4, 0x90
.type _Z11cpu_mat_addPfS_S_i,@function
_Z11cpu_mat_addPfS_S_i: # @_Z11cpu_mat_addPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%r10), %xmm0
movss %xmm0, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB4_2
.LBB4_5: # %._crit_edge21
retq
.Lfunc_end4:
.size _Z11cpu_mat_addPfS_S_i, .Lfunc_end4-_Z11cpu_mat_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11cpu_mat_subPfS_S_i # -- Begin function _Z11cpu_mat_subPfS_S_i
.p2align 4, 0x90
.type _Z11cpu_mat_subPfS_S_i,@function
_Z11cpu_mat_subPfS_S_i: # @_Z11cpu_mat_subPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%r10), %xmm0
movss %xmm0, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB5_2
.LBB5_5: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z11cpu_mat_subPfS_S_i, .Lfunc_end5-_Z11cpu_mat_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z12cpu_mat_multPfS_S_i # -- Begin function _Z12cpu_mat_multPfS_S_i
.p2align 4, 0x90
.type _Z12cpu_mat_multPfS_S_i,@function
_Z12cpu_mat_multPfS_S_i: # @_Z12cpu_mat_multPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB6_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
# Child Loop BB6_4 Depth 3
leaq (%rdx,%r9,4), %r10
xorl %r11d, %r11d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_3: # %.preheader
# Parent Loop BB6_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_4 Depth 3
movl %r11d, %r14d
leaq (%rdi,%r14,4), %r14
xorps %xmm0, %xmm0
movq %rsi, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# Parent Loop BB6_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
incq %r12
addq %r8, %r15
cmpq %r12, %rax
jne .LBB6_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB6_3 Depth=2
movq %rbx, %r14
imulq %rax, %r14
movss %xmm0, (%r10,%r14,4)
incq %rbx
addl %ecx, %r11d
cmpq %rax, %rbx
jne .LBB6_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB6_2 Depth=1
incq %r9
addq $4, %rsi
cmpq %rax, %r9
jne .LBB6_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB6_8: # %._crit_edge32
retq
.Lfunc_end6:
.size _Z12cpu_mat_multPfS_S_i, .Lfunc_end6-_Z12cpu_mat_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11printMatrixPfi # -- Begin function _Z11printMatrixPfi
.p2align 4, 0x90
.type _Z11printMatrixPfi,@function
_Z11printMatrixPfi: # @_Z11printMatrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %esi, %esi
jle .LBB7_9
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # in Loop: Header=BB7_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB7_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
je .LBB7_9
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
movl %r12d, %r12d
leaq (,%r12,4), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_output_array(%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r15
jne .LBB7_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB7_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB7_2 Depth=1
cmpb $0, 56(%r14)
je .LBB7_7
# %bb.6: # in Loop: Header=BB7_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB7_8
.LBB7_9: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_10:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size _Z11printMatrixPfi, .Lfunc_end7-_Z11printMatrixPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, cpu_array(,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB8_1
# %bb.2:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl $gpu_array_A, %edi
movl $100, %esi
callq hipMalloc
movq gpu_array_A(%rip), %rdi
movl $cpu_array, %esi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $gpu_array_B, %edi
movl $100, %esi
callq hipMalloc
movq gpu_array_B(%rip), %rdi
movl $cpu_array, %esi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $gpu_output_array, %edi
movl $100, %esi
callq hipMalloc
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_4
# %bb.3:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_4:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
movq $-100, %rdx
.p2align 4, 0x90
.LBB8_6: # %.lr.ph.i
# Parent Loop BB8_5 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_array+100(%rax,%rdx), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
movss %xmm0, cpu_output_array+100(%rax,%rdx)
addq $20, %rdx
jne .LBB8_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB8_5 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_5
# %bb.8: # %_Z11cpu_mat_addPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_10
# %bb.9:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_10:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_11: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB8_12 Depth 2
movq $-100, %rdx
.p2align 4, 0x90
.LBB8_12: # %.lr.ph.i37
# Parent Loop BB8_11 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_array+100(%rax,%rdx), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss %xmm0, %xmm0
movss %xmm0, cpu_output_array+100(%rax,%rdx)
addq $20, %rdx
jne .LBB8_12
# %bb.13: # %._crit_edge.i41
# in Loop: Header=BB8_11 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_11
# %bb.14: # %_Z11cpu_mat_subPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_16
# %bb.15:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_16:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
movl $cpu_array, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_17: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB8_18 Depth 2
# Child Loop BB8_19 Depth 3
leaq cpu_output_array(,%rcx,4), %rdx
movl $cpu_array, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_18: # %.preheader.i50
# Parent Loop BB8_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_19 Depth 3
xorps %xmm0, %xmm0
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB8_19: # Parent Loop BB8_17 Depth=1
# Parent Loop BB8_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r8), %xmm1
addss %xmm1, %xmm0
incq %r9
addq $20, %r8
cmpq $5, %r9
jne .LBB8_19
# %bb.20: # %._crit_edge.i54
# in Loop: Header=BB8_18 Depth=2
leaq (%rdi,%rdi,4), %r8
movss %xmm0, (%rdx,%r8,4)
incq %rdi
addq $20, %rsi
cmpq $5, %rdi
jne .LBB8_18
# %bb.21: # %._crit_edge30.i
# in Loop: Header=BB8_17 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_17
# %bb.22: # %_Z12cpu_mat_multPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
leaq 80(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpu_array,@object # @cpu_array
.bss
.globl cpu_array
.p2align 4, 0x0
cpu_array:
.zero 100
.size cpu_array, 100
.type cpu_output_array,@object # @cpu_output_array
.globl cpu_output_array
.p2align 4, 0x0
cpu_output_array:
.zero 100
.size cpu_output_array, 100
.type gpu_array_A,@object # @gpu_array_A
.globl gpu_array_A
.p2align 3, 0x0
gpu_array_A:
.quad 0
.size gpu_array_A, 8
.type gpu_array_B,@object # @gpu_array_B
.globl gpu_array_B
.p2align 3, 0x0
gpu_array_B:
.quad 0
.size gpu_array_B, 8
.type gpu_output_array,@object # @gpu_output_array
.globl gpu_output_array
.p2align 3, 0x0
gpu_output_array:
.quad 0
.size gpu_output_array, 8
.type dimBlock,@object # @dimBlock
.data
.globl dimBlock
.p2align 3, 0x0
dimBlock:
.long 5 # 0x5
.long 5 # 0x5
.long 1 # 0x1
.size dimBlock, 12
.type dimGrid,@object # @dimGrid
.globl dimGrid
.p2align 3, 0x0
dimGrid:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size dimGrid, 12
.type _Z7mat_addPfS_S_i,@object # @_Z7mat_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_i
.p2align 3, 0x0
_Z7mat_addPfS_S_i:
.quad _Z22__device_stub__mat_addPfS_S_i
.size _Z7mat_addPfS_S_i, 8
.type _Z7mat_subPfS_S_i,@object # @_Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 3, 0x0
_Z7mat_subPfS_S_i:
.quad _Z22__device_stub__mat_subPfS_S_i
.size _Z7mat_subPfS_S_i, 8
.type _Z8mat_multPfS_S_i,@object # @_Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 3, 0x0
_Z8mat_multPfS_S_i:
.quad _Z23__device_stub__mat_multPfS_S_i
.size _Z8mat_multPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_i"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8mat_multPfS_S_i"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_i
.addrsig_sym _Z22__device_stub__mat_subPfS_S_i
.addrsig_sym _Z23__device_stub__mat_multPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpu_array
.addrsig_sym cpu_output_array
.addrsig_sym gpu_array_A
.addrsig_sym gpu_array_B
.addrsig_sym gpu_output_array
.addrsig_sym _Z7mat_addPfS_S_i
.addrsig_sym _Z7mat_subPfS_S_i
.addrsig_sym _Z8mat_multPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mat_multPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e0006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e0006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_i, .Lfunc_end0-_Z7mat_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 8
.type _Z7mat_subPfS_S_i,@function
_Z7mat_subPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_i, .Lfunc_end1-_Z7mat_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 8
.type _Z8mat_multPfS_S_i,@function
_Z8mat_multPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v6, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_i, .Lfunc_end2-_Z8mat_multPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014649d_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initCudai
.type _Z8initCudai, @function
_Z8initCudai:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
imull %edi, %edi
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rsi
leaq gpu_array_A(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rbp
movq %rbp, %rsi
movq gpu_array_A(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq gpu_array_B(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq gpu_array_B(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq gpu_output_array(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z8initCudai, .-_Z8initCudai
.globl _Z11cpu_mat_addPfS_S_i
.type _Z11cpu_mat_addPfS_S_i, @function
_Z11cpu_mat_addPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
movq %rdi, %r8
testl %ecx, %ecx
jle .L5
movslq %ecx, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
.L7:
leaq 0(,%r10,4), %rax
movl $0, %edi
.L8:
movss (%r8,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %ecx
jne .L8
addq $1, %r10
cmpq %r11, %r10
jne .L7
.L5:
ret
.cfi_endproc
.LFE3670:
.size _Z11cpu_mat_addPfS_S_i, .-_Z11cpu_mat_addPfS_S_i
.globl _Z11cpu_mat_subPfS_S_i
.type _Z11cpu_mat_subPfS_S_i, @function
_Z11cpu_mat_subPfS_S_i:
.LFB3671:
.cfi_startproc
endbr64
movq %rdi, %r8
testl %ecx, %ecx
jle .L10
movslq %ecx, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
.L12:
leaq 0(,%r10,4), %rax
movl $0, %edi
.L13:
movss (%r8,%rax), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %ecx
jne .L13
addq $1, %r10
cmpq %r11, %r10
jne .L12
.L10:
ret
.cfi_endproc
.LFE3671:
.size _Z11cpu_mat_subPfS_S_i, .-_Z11cpu_mat_subPfS_S_i
.globl _Z12cpu_mat_multPfS_S_i
.type _Z12cpu_mat_multPfS_S_i, @function
_Z12cpu_mat_multPfS_S_i:
.LFB3672:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L23
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r12
movq %rsi, %r9
movq %rdx, %rbx
movl %ecx, %r11d
movslq %ecx, %rax
leaq 0(,%rax,4), %rsi
addq %rsi, %r12
negq %rax
leaq 0(,%rax,4), %r10
movl $0, %ebp
movl $0, %r13d
jmp .L17
.L19:
leal 1(%rbp), %eax
addq $4, %r9
addq $4, %rbx
cmpl %r8d, %ebp
je .L15
movl %eax, %ebp
.L17:
movq %r12, %rcx
movq %rbx, %rdi
movl %r13d, %r8d
.L20:
leaq (%rcx,%r10), %rax
movq %r9, %rdx
pxor %xmm1, %xmm1
.L18:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rcx, %rax
jne .L18
movss %xmm1, (%rdi)
leal 1(%r8), %eax
addq %rsi, %rdi
addq %rsi, %rcx
cmpl %eax, %r11d
je .L19
movl %eax, %r8d
jmp .L20
.L15:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3672:
.size _Z12cpu_mat_multPfS_S_i, .-_Z12cpu_mat_multPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl _Z11printMatrixPfi
.type _Z11printMatrixPfi, @function
_Z11printMatrixPfi:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L26
movl %esi, %eax
cltq
leaq 0(,%rax,4), %r15
leaq cpu_output_array(%rip), %rbp
addq %r15, %rbp
negq %rax
salq $2, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L28
.L35:
call _ZSt16__throw_bad_castv@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L32:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
je .L26
.L28:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
jmp .L32
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z11printMatrixPfi, .-_Z11printMatrixPfi
.globl _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.globl _Z7mat_addPfS_S_i
.type _Z7mat_addPfS_S_i, @function
_Z7mat_addPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7mat_addPfS_S_i, .-_Z7mat_addPfS_S_i
.globl _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.globl _Z7mat_subPfS_S_i
.type _Z7mat_subPfS_S_i, @function
_Z7mat_subPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z7mat_subPfS_S_i, .-_Z7mat_subPfS_S_i
.globl _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.globl _Z8mat_multPfS_S_i
.type _Z8mat_multPfS_S_i, @function
_Z8mat_multPfS_S_i:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z8mat_multPfS_S_i, .-_Z8mat_multPfS_S_i
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq cpu_array(%rip), %rdx
.L61:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L61
movl $5, %edi
call _Z8initCudai
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L62:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z11cpu_mat_addPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L63:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z11cpu_mat_subPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L64:
movl $2, %ecx
movl $100, %edx
movq gpu_output_array(%rip), %rsi
leaq cpu_output_array(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
movl $5, %ecx
movq %rbx, %rdx
leaq cpu_array(%rip), %rdi
movq %rdi, %rsi
call _Z12cpu_mat_multPfS_S_i
movl $5, %esi
movq %rbx, %rdi
call _Z11printMatrixPfi
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
jmp .L62
.L69:
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
jmp .L63
.L70:
movl $5, %ecx
movq gpu_output_array(%rip), %rdx
movq gpu_array_B(%rip), %rsi
movq gpu_array_A(%rip), %rdi
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
jmp .L64
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8mat_multPfS_S_i"
.LC3:
.string "_Z7mat_subPfS_S_i"
.LC4:
.string "_Z7mat_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimGrid
.data
.align 8
.type dimGrid, @object
.size dimGrid, 12
dimGrid:
.long 1
.long 1
.long 1
.globl dimBlock
.align 8
.type dimBlock, @object
.size dimBlock, 12
dimBlock:
.long 5
.long 5
.long 1
.globl gpu_output_array
.bss
.align 8
.type gpu_output_array, @object
.size gpu_output_array, 8
gpu_output_array:
.zero 8
.globl gpu_array_B
.align 8
.type gpu_array_B, @object
.size gpu_array_B, 8
gpu_array_B:
.zero 8
.globl gpu_array_A
.align 8
.type gpu_array_A, @object
.size gpu_array_A, 8
gpu_array_A:
.zero 8
.globl cpu_output_array
.align 32
.type cpu_output_array, @object
.size cpu_output_array, 100
cpu_output_array:
.zero 100
.globl cpu_array
.align 32
.type cpu_array, @object
.size cpu_array, 100
cpu_array:
.zero 100
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_math.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCudai # -- Begin function _Z8initCudai
.p2align 4, 0x90
.type _Z8initCudai,@function
_Z8initCudai: # @_Z8initCudai
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edi killed $edi def $rdi
imull %edi, %edi
leaq (,%rdi,4), %rbx
movl $gpu_array_A, %edi
movq %rbx, %rsi
callq hipMalloc
movq gpu_array_A(%rip), %rdi
movl $cpu_array, %esi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $gpu_array_B, %edi
movq %rbx, %rsi
callq hipMalloc
movq gpu_array_B(%rip), %rdi
movl $cpu_array, %esi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $gpu_output_array, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size _Z8initCudai, .Lfunc_end0-_Z8initCudai
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_i # -- Begin function _Z22__device_stub__mat_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_i,@function
_Z22__device_stub__mat_addPfS_S_i: # @_Z22__device_stub__mat_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__mat_addPfS_S_i, .Lfunc_end1-_Z22__device_stub__mat_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_i # -- Begin function _Z22__device_stub__mat_subPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_i,@function
_Z22__device_stub__mat_subPfS_S_i: # @_Z22__device_stub__mat_subPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_subPfS_S_i, .Lfunc_end2-_Z22__device_stub__mat_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mat_multPfS_S_i # -- Begin function _Z23__device_stub__mat_multPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__mat_multPfS_S_i,@function
_Z23__device_stub__mat_multPfS_S_i: # @_Z23__device_stub__mat_multPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__mat_multPfS_S_i, .Lfunc_end3-_Z23__device_stub__mat_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11cpu_mat_addPfS_S_i # -- Begin function _Z11cpu_mat_addPfS_S_i
.p2align 4, 0x90
.type _Z11cpu_mat_addPfS_S_i,@function
_Z11cpu_mat_addPfS_S_i: # @_Z11cpu_mat_addPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%r10), %xmm0
movss %xmm0, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB4_2
.LBB4_5: # %._crit_edge21
retq
.Lfunc_end4:
.size _Z11cpu_mat_addPfS_S_i, .Lfunc_end4-_Z11cpu_mat_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11cpu_mat_subPfS_S_i # -- Begin function _Z11cpu_mat_subPfS_S_i
.p2align 4, 0x90
.type _Z11cpu_mat_subPfS_S_i,@function
_Z11cpu_mat_subPfS_S_i: # @_Z11cpu_mat_subPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%r10), %xmm0
movss %xmm0, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB5_2
.LBB5_5: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z11cpu_mat_subPfS_S_i, .Lfunc_end5-_Z11cpu_mat_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z12cpu_mat_multPfS_S_i # -- Begin function _Z12cpu_mat_multPfS_S_i
.p2align 4, 0x90
.type _Z12cpu_mat_multPfS_S_i,@function
_Z12cpu_mat_multPfS_S_i: # @_Z12cpu_mat_multPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB6_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
# Child Loop BB6_4 Depth 3
leaq (%rdx,%r9,4), %r10
xorl %r11d, %r11d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_3: # %.preheader
# Parent Loop BB6_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_4 Depth 3
movl %r11d, %r14d
leaq (%rdi,%r14,4), %r14
xorps %xmm0, %xmm0
movq %rsi, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# Parent Loop BB6_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
incq %r12
addq %r8, %r15
cmpq %r12, %rax
jne .LBB6_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB6_3 Depth=2
movq %rbx, %r14
imulq %rax, %r14
movss %xmm0, (%r10,%r14,4)
incq %rbx
addl %ecx, %r11d
cmpq %rax, %rbx
jne .LBB6_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB6_2 Depth=1
incq %r9
addq $4, %rsi
cmpq %rax, %r9
jne .LBB6_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB6_8: # %._crit_edge32
retq
.Lfunc_end6:
.size _Z12cpu_mat_multPfS_S_i, .Lfunc_end6-_Z12cpu_mat_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11printMatrixPfi # -- Begin function _Z11printMatrixPfi
.p2align 4, 0x90
.type _Z11printMatrixPfi,@function
_Z11printMatrixPfi: # @_Z11printMatrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %esi, %esi
jle .LBB7_9
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # in Loop: Header=BB7_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB7_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
je .LBB7_9
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
movl %r12d, %r12d
leaq (,%r12,4), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_output_array(%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r15
jne .LBB7_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB7_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB7_2 Depth=1
cmpb $0, 56(%r14)
je .LBB7_7
# %bb.6: # in Loop: Header=BB7_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB7_8
.LBB7_9: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_10:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size _Z11printMatrixPfi, .Lfunc_end7-_Z11printMatrixPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, cpu_array(,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB8_1
# %bb.2:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl $gpu_array_A, %edi
movl $100, %esi
callq hipMalloc
movq gpu_array_A(%rip), %rdi
movl $cpu_array, %esi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $gpu_array_B, %edi
movl $100, %esi
callq hipMalloc
movq gpu_array_B(%rip), %rdi
movl $cpu_array, %esi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $gpu_output_array, %edi
movl $100, %esi
callq hipMalloc
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_4
# %bb.3:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_4:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
movq $-100, %rdx
.p2align 4, 0x90
.LBB8_6: # %.lr.ph.i
# Parent Loop BB8_5 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_array+100(%rax,%rdx), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
movss %xmm0, cpu_output_array+100(%rax,%rdx)
addq $20, %rdx
jne .LBB8_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB8_5 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_5
# %bb.8: # %_Z11cpu_mat_addPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_10
# %bb.9:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_10:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_11: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB8_12 Depth 2
movq $-100, %rdx
.p2align 4, 0x90
.LBB8_12: # %.lr.ph.i37
# Parent Loop BB8_11 Depth=1
# => This Inner Loop Header: Depth=2
movss cpu_array+100(%rax,%rdx), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss %xmm0, %xmm0
movss %xmm0, cpu_output_array+100(%rax,%rdx)
addq $20, %rdx
jne .LBB8_12
# %bb.13: # %._crit_edge.i41
# in Loop: Header=BB8_11 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_11
# %bb.14: # %_Z11cpu_mat_subPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_16
# %bb.15:
movq gpu_array_A(%rip), %rax
movq gpu_array_B(%rip), %rcx
movq gpu_output_array(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $5, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_16:
movq gpu_output_array(%rip), %rsi
movl $cpu_output_array, %edi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movl $5, %esi
callq _Z11printMatrixPfi
movl $cpu_array, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_17: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB8_18 Depth 2
# Child Loop BB8_19 Depth 3
leaq cpu_output_array(,%rcx,4), %rdx
movl $cpu_array, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_18: # %.preheader.i50
# Parent Loop BB8_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_19 Depth 3
xorps %xmm0, %xmm0
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB8_19: # Parent Loop BB8_17 Depth=1
# Parent Loop BB8_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r8), %xmm1
addss %xmm1, %xmm0
incq %r9
addq $20, %r8
cmpq $5, %r9
jne .LBB8_19
# %bb.20: # %._crit_edge.i54
# in Loop: Header=BB8_18 Depth=2
leaq (%rdi,%rdi,4), %r8
movss %xmm0, (%rdx,%r8,4)
incq %rdi
addq $20, %rsi
cmpq $5, %rdi
jne .LBB8_18
# %bb.21: # %._crit_edge30.i
# in Loop: Header=BB8_17 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_17
# %bb.22: # %_Z12cpu_mat_multPfS_S_i.exit
movl $5, %esi
callq _Z11printMatrixPfi
leaq 80(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpu_array,@object # @cpu_array
.bss
.globl cpu_array
.p2align 4, 0x0
cpu_array:
.zero 100
.size cpu_array, 100
.type cpu_output_array,@object # @cpu_output_array
.globl cpu_output_array
.p2align 4, 0x0
cpu_output_array:
.zero 100
.size cpu_output_array, 100
.type gpu_array_A,@object # @gpu_array_A
.globl gpu_array_A
.p2align 3, 0x0
gpu_array_A:
.quad 0
.size gpu_array_A, 8
.type gpu_array_B,@object # @gpu_array_B
.globl gpu_array_B
.p2align 3, 0x0
gpu_array_B:
.quad 0
.size gpu_array_B, 8
.type gpu_output_array,@object # @gpu_output_array
.globl gpu_output_array
.p2align 3, 0x0
gpu_output_array:
.quad 0
.size gpu_output_array, 8
.type dimBlock,@object # @dimBlock
.data
.globl dimBlock
.p2align 3, 0x0
dimBlock:
.long 5 # 0x5
.long 5 # 0x5
.long 1 # 0x1
.size dimBlock, 12
.type dimGrid,@object # @dimGrid
.globl dimGrid
.p2align 3, 0x0
dimGrid:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size dimGrid, 12
.type _Z7mat_addPfS_S_i,@object # @_Z7mat_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_i
.p2align 3, 0x0
_Z7mat_addPfS_S_i:
.quad _Z22__device_stub__mat_addPfS_S_i
.size _Z7mat_addPfS_S_i, 8
.type _Z7mat_subPfS_S_i,@object # @_Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 3, 0x0
_Z7mat_subPfS_S_i:
.quad _Z22__device_stub__mat_subPfS_S_i
.size _Z7mat_subPfS_S_i, 8
.type _Z8mat_multPfS_S_i,@object # @_Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 3, 0x0
_Z8mat_multPfS_S_i:
.quad _Z23__device_stub__mat_multPfS_S_i
.size _Z8mat_multPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_i"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8mat_multPfS_S_i"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_i
.addrsig_sym _Z22__device_stub__mat_subPfS_S_i
.addrsig_sym _Z23__device_stub__mat_multPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpu_array
.addrsig_sym cpu_output_array
.addrsig_sym gpu_array_A
.addrsig_sym gpu_array_B
.addrsig_sym gpu_output_array
.addrsig_sym _Z7mat_addPfS_S_i
.addrsig_sym _Z7mat_subPfS_S_i
.addrsig_sym _Z8mat_multPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/transform.h>
#include <thrust/inner_product.h>
#include <thrust/sequence.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <iostream>
#include <iterator>
#include <algorithm>
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
thrust::fill(temp.begin(), temp.end(), A);
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
struct saxpy_functor : public thrust::binary_function<float,float,float>
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
extern "C"
__global__ void saxpy ( const float *X, float *Y, float A, int N)
{
int i= threadIdx.x+blockDim.x*blockIdx.x;
int T= blockDim.x*gridDim.x;
#pragma unroll 4
for (; i<N; i+=T)
Y[i] = A*X[i] + Y[i];
}
#ifndef BLK_SZ
#define BLK_SZ 512
#endif
#ifndef THR
#define THR (BLK_SZ*6)
#endif
void saxpy_cuda(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
saxpy <<< (THR-1)/BLK_SZ + 1, BLK_SZ >>> ( thrust::raw_pointer_cast(&(X[0])),
thrust::raw_pointer_cast(&(Y[0])), A, X.size());
}
int main(int argc, char **argv)
{
// Default Size of input vectors
int N=1000000;
// Modify size of input vectors using program argument
if (argc>1) { N = atoi(argv[1]); }
thrust::host_vector<float> x_h(N);
thrust::host_vector<float> y_h(N);
thrust::host_vector<float> y_result(N);
thrust::sequence(x_h.begin(), x_h.end(), 10.0f, 1.5f);
thrust::fill (y_h.begin(), y_h.end(), -2.0f);
thrust::device_vector<float> x(x_h.begin(), x_h.end());
thrust::device_vector<float> y(y_h.begin(), y_h.end());
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_slow(2.0f, x, y);
y_result = y;
float R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Slow. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_fast(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Fast. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_cuda(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy CUDA. Sum of Differences is " << R << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/transform.h>
#include <thrust/inner_product.h>
#include <thrust/sequence.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <iostream>
#include <iterator>
#include <algorithm>
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
thrust::fill(temp.begin(), temp.end(), A);
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
struct saxpy_functor : public thrust::binary_function<float,float,float>
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
extern "C"
__global__ void saxpy ( const float *X, float *Y, float A, int N)
{
int i= threadIdx.x+blockDim.x*blockIdx.x;
int T= blockDim.x*gridDim.x;
#pragma unroll 4
for (; i<N; i+=T)
Y[i] = A*X[i] + Y[i];
}
#ifndef BLK_SZ
#define BLK_SZ 512
#endif
#ifndef THR
#define THR (BLK_SZ*6)
#endif
void saxpy_cuda(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
saxpy <<< (THR-1)/BLK_SZ + 1, BLK_SZ >>> ( thrust::raw_pointer_cast(&(X[0])),
thrust::raw_pointer_cast(&(Y[0])), A, X.size());
}
int main(int argc, char **argv)
{
// Default Size of input vectors
int N=1000000;
// Modify size of input vectors using program argument
if (argc>1) { N = atoi(argv[1]); }
thrust::host_vector<float> x_h(N);
thrust::host_vector<float> y_h(N);
thrust::host_vector<float> y_result(N);
thrust::sequence(x_h.begin(), x_h.end(), 10.0f, 1.5f);
thrust::fill (y_h.begin(), y_h.end(), -2.0f);
thrust::device_vector<float> x(x_h.begin(), x_h.end());
thrust::device_vector<float> y(y_h.begin(), y_h.end());
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_slow(2.0f, x, y);
y_result = y;
float R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Slow. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_fast(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Fast. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_cuda(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy CUDA. Sum of Differences is " << R << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/transform.h>
#include <thrust/inner_product.h>
#include <thrust/sequence.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <iostream>
#include <iterator>
#include <algorithm>
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::device_vector<float> temp(X.size());
thrust::fill(temp.begin(), temp.end(), A);
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
struct saxpy_functor : public thrust::binary_function<float,float,float>
{
const float a;
saxpy_functor(float _a) : a(_a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return a * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
extern "C"
__global__ void saxpy ( const float *X, float *Y, float A, int N)
{
int i= threadIdx.x+blockDim.x*blockIdx.x;
int T= blockDim.x*gridDim.x;
#pragma unroll 4
for (; i<N; i+=T)
Y[i] = A*X[i] + Y[i];
}
#ifndef BLK_SZ
#define BLK_SZ 512
#endif
#ifndef THR
#define THR (BLK_SZ*6)
#endif
void saxpy_cuda(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
saxpy <<< (THR-1)/BLK_SZ + 1, BLK_SZ >>> ( thrust::raw_pointer_cast(&(X[0])),
thrust::raw_pointer_cast(&(Y[0])), A, X.size());
}
int main(int argc, char **argv)
{
// Default Size of input vectors
int N=1000000;
// Modify size of input vectors using program argument
if (argc>1) { N = atoi(argv[1]); }
thrust::host_vector<float> x_h(N);
thrust::host_vector<float> y_h(N);
thrust::host_vector<float> y_result(N);
thrust::sequence(x_h.begin(), x_h.end(), 10.0f, 1.5f);
thrust::fill (y_h.begin(), y_h.end(), -2.0f);
thrust::device_vector<float> x(x_h.begin(), x_h.end());
thrust::device_vector<float> y(y_h.begin(), y_h.end());
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_slow(2.0f, x, y);
y_result = y;
float R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Slow. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_fast(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy Fast. Sum of Differences is " << R << std::endl;
thrust::transform(x_h.begin(), x_h.end(), y_h.begin(), y_h.begin(), saxpy_functor(2.0f));
saxpy_cuda(2.0f, x, y);
y_result = y;
R = thrust::inner_product( y_h.begin(), y_h.end(), y_result.begin(), 0.0f,
thrust::plus<float>(), thrust::minus<float>());
std::cout << "Saxpy CUDA. Sum of Differences is " << R << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected saxpy
.globl saxpy
.p2align 8
.type saxpy,@function
saxpy:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x14
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s13, 0
s_mov_b32 s12, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s4
s_add_i32 s2, s15, s2
v_cvt_f32_u32_e32 v2, s8
s_sub_i32 s3, 0, s8
s_mul_i32 s2, s2, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s11, s[0:1], 0x10
v_add_nc_u32_e32 v4, s2, v0
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s10, v4
v_max_i32_e32 v5, s10, v4
v_add_co_ci_u32_e64 v0, s2, s2, v0, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_mul_lo_u32 v3, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v3, 1, v2
v_subrev_nc_u32_e32 v4, s8, v0
v_cmp_le_u32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s2
v_cndmask_b32_e64 v0, v0, v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v2
v_cmp_le_u32_e64 s0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v2, v3, s0
v_add_co_ci_u32_e64 v2, s0, 1, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 3, v2
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[8:9], 2
v_lshlrev_b64 v[2:3], 2, v[1:2]
.p2align 6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v2
v_add_co_ci_u32_e64 v6, s0, s5, v3, s0
v_add_co_u32 v7, s0, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s7, v3, s0
v_add_nc_u32_e32 v4, -1, v4
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
v_add_co_u32 v2, s0, v2, s2
v_cmp_eq_u32_e64 s1, 0, v4
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_delay_alu instid0(VALU_DEP_3)
s_or_b32 s13, s1, s13
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, s11, v5
global_store_b32 v[7:8], v6, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s13
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s12
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_mul_i32 s0, s8, 3
s_lshl_b32 s1, s8, 1
s_mov_b32 s2, 0
s_add_i32 s3, s8, s8
.LBB0_7:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_nc_u32_e32 v4, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, s11, v0
global_store_b32 v[2:3], v8, off
global_load_b32 v0, v[6:7], off
global_load_b32 v8, v[4:5], off
v_add_nc_u32_e32 v2, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, s11, v0
global_store_b32 v[4:5], v8, off
global_load_b32 v0, v[6:7], off
global_load_b32 v8, v[2:3], off
v_add_nc_u32_e32 v4, s0, v1
v_add3_u32 v1, s3, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, s11, v0
global_store_b32 v[2:3], v8, off
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s11, v0
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel saxpy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size saxpy, .Lfunc_end0-saxpy
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB3_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end3:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB4_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB4_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end4:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end4-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB5_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s0, v2
flat_store_b32 v[0:1], v3
.LBB5_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end5:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end5-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: saxpy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: saxpy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} | code for sm_80
Function : _Z17MatrixMulKernelV1PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} | .file "tmpxft_0004da21_00000000-6_MatrixMulKernelV1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
.type _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17MatrixMulKernelV1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i, .-_Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
.globl _Z17MatrixMulKernelV1PfS_S_i
.type _Z17MatrixMulKernelV1PfS_S_i, @function
_Z17MatrixMulKernelV1PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17MatrixMulKernelV1PfS_S_i, .-_Z17MatrixMulKernelV1PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17MatrixMulKernelV1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17MatrixMulKernelV1PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17MatrixMulKernelV1PfS_S_i
.globl _Z17MatrixMulKernelV1PfS_S_i
.p2align 8
.type _Z17MatrixMulKernelV1PfS_S_i,@function
_Z17MatrixMulKernelV1PfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17MatrixMulKernelV1PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17MatrixMulKernelV1PfS_S_i, .Lfunc_end0-_Z17MatrixMulKernelV1PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17MatrixMulKernelV1PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17MatrixMulKernelV1PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernelV1(float* M, float* N, float* P, int Width)
{
int Row = blockIdx.y*blockDim.y+threadIdx.y;
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue += M[Row*Width+k]*N[k*Width+Col];
P[Row*Width+Col] = Pvalue;
}
} | .text
.file "MatrixMulKernelV1.hip"
.globl _Z32__device_stub__MatrixMulKernelV1PfS_S_i # -- Begin function _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__MatrixMulKernelV1PfS_S_i,@function
_Z32__device_stub__MatrixMulKernelV1PfS_S_i: # @_Z32__device_stub__MatrixMulKernelV1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17MatrixMulKernelV1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__MatrixMulKernelV1PfS_S_i, .Lfunc_end0-_Z32__device_stub__MatrixMulKernelV1PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17MatrixMulKernelV1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17MatrixMulKernelV1PfS_S_i,@object # @_Z17MatrixMulKernelV1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z17MatrixMulKernelV1PfS_S_i
.p2align 3, 0x0
_Z17MatrixMulKernelV1PfS_S_i:
.quad _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.size _Z17MatrixMulKernelV1PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17MatrixMulKernelV1PfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17MatrixMulKernelV1PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17MatrixMulKernelV1PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17MatrixMulKernelV1PfS_S_i
.globl _Z17MatrixMulKernelV1PfS_S_i
.p2align 8
.type _Z17MatrixMulKernelV1PfS_S_i,@function
_Z17MatrixMulKernelV1PfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17MatrixMulKernelV1PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17MatrixMulKernelV1PfS_S_i, .Lfunc_end0-_Z17MatrixMulKernelV1PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17MatrixMulKernelV1PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17MatrixMulKernelV1PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004da21_00000000-6_MatrixMulKernelV1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
.type _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17MatrixMulKernelV1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i, .-_Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
.globl _Z17MatrixMulKernelV1PfS_S_i
.type _Z17MatrixMulKernelV1PfS_S_i, @function
_Z17MatrixMulKernelV1PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17MatrixMulKernelV1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17MatrixMulKernelV1PfS_S_i, .-_Z17MatrixMulKernelV1PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17MatrixMulKernelV1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17MatrixMulKernelV1PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMulKernelV1.hip"
.globl _Z32__device_stub__MatrixMulKernelV1PfS_S_i # -- Begin function _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__MatrixMulKernelV1PfS_S_i,@function
_Z32__device_stub__MatrixMulKernelV1PfS_S_i: # @_Z32__device_stub__MatrixMulKernelV1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17MatrixMulKernelV1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__MatrixMulKernelV1PfS_S_i, .Lfunc_end0-_Z32__device_stub__MatrixMulKernelV1PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17MatrixMulKernelV1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17MatrixMulKernelV1PfS_S_i,@object # @_Z17MatrixMulKernelV1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z17MatrixMulKernelV1PfS_S_i
.p2align 3, 0x0
_Z17MatrixMulKernelV1PfS_S_i:
.quad _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.size _Z17MatrixMulKernelV1PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17MatrixMulKernelV1PfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__MatrixMulKernelV1PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17MatrixMulKernelV1PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
cudaMalloc((void**)&din, ARRAY_BITES);
cudaMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
cudaMemcpy(din,hin, ARRAY_BITES, cudaMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
cudaMemcpy(hout,dout, ARRAY_BITES, cudaMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
cudaFree(din);
cudaFree(dout);
return 0;
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8VectoAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
cudaMalloc((void**)&din, ARRAY_BITES);
cudaMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
cudaMemcpy(din,hin, ARRAY_BITES, cudaMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
cudaMemcpy(hout,dout, ARRAY_BITES, cudaMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
cudaFree(din);
cudaFree(dout);
return 0;
} | .file "tmpxft_0003e21e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8VectoAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
.globl _Z8VectoAddPiS_S_i
.type _Z8VectoAddPiS_S_i, @function
_Z8VectoAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8VectoAddPiS_S_i, .-_Z8VectoAddPiS_S_i
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $576, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L20
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
leaq 304(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 304(%rsp), %r14
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
movq %rbp, %rsi
cmove %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $64, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6squarePfS_"
.LC4:
.string "_Z8VectoAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8VectoAddPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
cudaMalloc((void**)&din, ARRAY_BITES);
cudaMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
cudaMemcpy(din,hin, ARRAY_BITES, cudaMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
cudaMemcpy(hout,dout, ARRAY_BITES, cudaMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
cudaFree(din);
cudaFree(dout);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
hipMalloc((void**)&din, ARRAY_BITES);
hipMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
hipMemcpy(din,hin, ARRAY_BITES, hipMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
hipMemcpy(hout,dout, ARRAY_BITES, hipMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
hipFree(din);
hipFree(dout);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
hipMalloc((void**)&din, ARRAY_BITES);
hipMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
hipMemcpy(din,hin, ARRAY_BITES, hipMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
hipMemcpy(hout,dout, ARRAY_BITES, hipMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
hipFree(din);
hipFree(dout);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8VectoAddPiS_S_i
.globl _Z8VectoAddPiS_S_i
.p2align 8
.type _Z8VectoAddPiS_S_i,@function
_Z8VectoAddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8VectoAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8VectoAddPiS_S_i, .Lfunc_end0-_Z8VectoAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6squarePfS_, .Lfunc_end1-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8VectoAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8VectoAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define SIZE 1024
__global__ void VectoAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if (i<n)
{
c[i] = a[i] + b[i];
}
}
__global__ void square(float *dout, float* din)
{
int idx = threadIdx.x;
float f = din[idx];
dout[idx] = f*f;
}
int main()
{
const int ARRAY_SIZE = 64;
const int ARRAY_BITES = ARRAY_SIZE*sizeof(float);
// generate the input array on the host
float hin[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++)
{
hin[i] = float(i);
}
float hout[ARRAY_SIZE];
// declare GPU memory pointers
float* din;
float* dout;
// allocalte GPU memory
hipMalloc((void**)&din, ARRAY_BITES);
hipMalloc((void**)&dout, ARRAY_BITES);
// transfer the array to the GPU
hipMemcpy(din,hin, ARRAY_BITES, hipMemcpyHostToDevice);
// launch the kernel
square<<<1,ARRAY_SIZE>>>(dout,din);
// copy back the result array to the CPU
hipMemcpy(hout,dout, ARRAY_BITES, hipMemcpyDeviceToHost);
// print out the resulting array
for(int i =0; i<ARRAY_SIZE;i++)
{
printf("%f", hout[i]);
printf(((i%4) !=3)? "\t":"\n");
}
// free GPU memory allocation
hipFree(din);
hipFree(dout);
return 0;
} | .text
.file "kernel.hip"
.globl _Z23__device_stub__VectoAddPiS_S_i # -- Begin function _Z23__device_stub__VectoAddPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__VectoAddPiS_S_i,@function
_Z23__device_stub__VectoAddPiS_S_i: # @_Z23__device_stub__VectoAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8VectoAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__VectoAddPiS_S_i, .Lfunc_end0-_Z23__device_stub__VectoAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__squarePfS_, .Lfunc_end1-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 336(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
notl %eax
testb $3, %al
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $64, %r14
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8VectoAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8VectoAddPiS_S_i,@object # @_Z8VectoAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8VectoAddPiS_S_i
.p2align 3, 0x0
_Z8VectoAddPiS_S_i:
.quad _Z23__device_stub__VectoAddPiS_S_i
.size _Z8VectoAddPiS_S_i, 8
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8VectoAddPiS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6squarePfS_"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__VectoAddPiS_S_i
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8VectoAddPiS_S_i
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8VectoAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8VectoAddPiS_S_i
.globl _Z8VectoAddPiS_S_i
.p2align 8
.type _Z8VectoAddPiS_S_i,@function
_Z8VectoAddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8VectoAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8VectoAddPiS_S_i, .Lfunc_end0-_Z8VectoAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6squarePfS_, .Lfunc_end1-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8VectoAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8VectoAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003e21e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8VectoAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
.globl _Z8VectoAddPiS_S_i
.type _Z8VectoAddPiS_S_i, @function
_Z8VectoAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8VectoAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8VectoAddPiS_S_i, .-_Z8VectoAddPiS_S_i
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $576, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L20
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
leaq 304(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 304(%rsp), %r14
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
movq %rbp, %rsi
cmove %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $64, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6squarePfS_"
.LC4:
.string "_Z8VectoAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8VectoAddPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z23__device_stub__VectoAddPiS_S_i # -- Begin function _Z23__device_stub__VectoAddPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__VectoAddPiS_S_i,@function
_Z23__device_stub__VectoAddPiS_S_i: # @_Z23__device_stub__VectoAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8VectoAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__VectoAddPiS_S_i, .Lfunc_end0-_Z23__device_stub__VectoAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__squarePfS_, .Lfunc_end1-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 336(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
notl %eax
testb $3, %al
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $64, %r14
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8VectoAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8VectoAddPiS_S_i,@object # @_Z8VectoAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8VectoAddPiS_S_i
.p2align 3, 0x0
_Z8VectoAddPiS_S_i:
.quad _Z23__device_stub__VectoAddPiS_S_i
.size _Z8VectoAddPiS_S_i, 8
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8VectoAddPiS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6squarePfS_"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__VectoAddPiS_S_i
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8VectoAddPiS_S_i
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
cudaMalloc((void **)&d_vec, size);
//SUM
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
cudaMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
cudaMemcpy(d_float_vec, float_vec, N*sizeof(float), cudaMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
cudaMemcpy(&res, d_float_vec, sizeof(res), cudaMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
cudaFree(d_vec);
printf("\\n");
return 0;
} | code for sm_80
Function : _Z12mean_diff_sqPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ FADD R0, R0, -c[0x0][0x168] ; /* 0x80005a0000007621 */
/* 0x004fc80000000000 */
/*0070*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x000fca0000400000 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10sum_floatsPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R6, R8, 0x1, RZ ; /* 0x0000000108067819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R8, 0x2, RZ ; /* 0x0000000208067824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3maxPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x190 ; /* 0x000000b000001947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R6, R0, R9, RZ ; /* 0x0000000900067224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GE.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f26270 */
/*0150*/ @!P1 IADD3 R6, R6, R9, RZ ; /* 0x0000000906069210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e020b */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e4000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3minPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x190 ; /* 0x000000b000001947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R6, R0, R9, RZ ; /* 0x0000000900067224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f24270 */
/*0150*/ @P1 IADD3 R6, R6, R9, RZ ; /* 0x0000000906061210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e020b */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e4000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
cudaMalloc((void **)&d_vec, size);
//SUM
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
cudaMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
cudaMemcpy(d_float_vec, float_vec, N*sizeof(float), cudaMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
cudaMemcpy(&res, d_float_vec, sizeof(res), cudaMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
cudaFree(d_vec);
printf("\\n");
return 0;
} | .file "tmpxft_0018901a_00000000-6_ParallelReductionCUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z17copy_int_to_floatPfPii
.type _Z17copy_int_to_floatPfPii, @function
_Z17copy_int_to_floatPfPii:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl (%rsi,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3670:
.size _Z17copy_int_to_floatPfPii, .-_Z17copy_int_to_floatPfPii
.globl _Z22__device_stub__Z3minPiPi
.type _Z22__device_stub__Z3minPiPi, @function
_Z22__device_stub__Z3minPiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z22__device_stub__Z3minPiPi, .-_Z22__device_stub__Z3minPiPi
.globl _Z3minPi
.type _Z3minPi, @function
_Z3minPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3minPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3minPi, .-_Z3minPi
.globl _Z22__device_stub__Z3maxPiPi
.type _Z22__device_stub__Z3maxPiPi, @function
_Z22__device_stub__Z3maxPiPi:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3maxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z22__device_stub__Z3maxPiPi, .-_Z22__device_stub__Z3maxPiPi
.globl _Z3maxPi
.type _Z3maxPi, @function
_Z3maxPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3maxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z3maxPi, .-_Z3maxPi
.globl _Z22__device_stub__Z3sumPiPi
.type _Z22__device_stub__Z3sumPiPi, @function
_Z22__device_stub__Z3sumPiPi:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z22__device_stub__Z3sumPiPi, .-_Z22__device_stub__Z3sumPiPi
.globl _Z3sumPi
.type _Z3sumPi, @function
_Z3sumPi:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z3sumPi, .-_Z3sumPi
.globl _Z30__device_stub__Z10sum_floatsPfPf
.type _Z30__device_stub__Z10sum_floatsPfPf, @function
_Z30__device_stub__Z10sum_floatsPfPf:
.LFB3702:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10sum_floatsPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z30__device_stub__Z10sum_floatsPfPf, .-_Z30__device_stub__Z10sum_floatsPfPf
.globl _Z10sum_floatsPf
.type _Z10sum_floatsPf, @function
_Z10sum_floatsPf:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10sum_floatsPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z10sum_floatsPf, .-_Z10sum_floatsPf
.globl _Z33__device_stub__Z12mean_diff_sqPffPff
.type _Z33__device_stub__Z12mean_diff_sqPffPff, @function
_Z33__device_stub__Z12mean_diff_sqPffPff:
.LFB3704:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mean_diff_sqPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z33__device_stub__Z12mean_diff_sqPffPff, .-_Z33__device_stub__Z12mean_diff_sqPffPff
.globl _Z12mean_diff_sqPff
.type _Z12mean_diff_sqPff, @function
_Z12mean_diff_sqPff:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12mean_diff_sqPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z12mean_diff_sqPff, .-_Z12mean_diff_sqPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Sum is: %d"
.LC1:
.string "\\nMin is: %d"
.LC2:
.string "\\nMax is: %d"
.LC4:
.string "\\nMean is: %f"
.LC5:
.string "\\nVariance: %f"
.LC7:
.string "\\nStd. Dev: %f"
.LC8:
.string "\\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L56:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L57:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L58:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L59:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $2048, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17copy_int_to_floatPfPii
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $2048, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L60:
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L61:
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movss .LC3(%rip), %xmm0
mulss 60(%rsp), %xmm0
movss %xmm0, 60(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 60(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L67
sqrtss %xmm0, %xmm0
.L64:
movss %xmm0, 60(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L56
.L70:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3minPiPi
jmp .L57
.L71:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3maxPiPi
jmp .L58
.L72:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L59
.L73:
movss 12(%rsp), %xmm0
movq 40(%rsp), %rdi
call _Z33__device_stub__Z12mean_diff_sqPffPff
jmp .L60
.L74:
movq 40(%rsp), %rdi
call _Z30__device_stub__Z10sum_floatsPfPf
jmp .L61
.L67:
call sqrtf@PLT
jmp .L64
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12mean_diff_sqPff"
.LC10:
.string "_Z10sum_floatsPf"
.LC11:
.string "_Z3sumPi"
.LC12:
.string "_Z3maxPi"
.LC13:
.string "_Z3minPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mean_diff_sqPff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_floatsPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3maxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 973078528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
cudaMalloc((void **)&d_vec, size);
//SUM
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
cudaMemcpy(d_vec, vec, size, cudaMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
cudaMemcpy(&result, d_vec, sizeof(int), cudaMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
cudaMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
cudaMemcpy(d_float_vec, float_vec, N*sizeof(float), cudaMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
cudaMemcpy(&res, d_float_vec, sizeof(res), cudaMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
cudaFree(d_vec);
printf("\\n");
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
hipMalloc((void **)&d_vec, size);
//SUM
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
hipMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
hipMemcpy(d_float_vec, float_vec, N*sizeof(float), hipMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
hipMemcpy(&res, d_float_vec, sizeof(res), hipMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
hipFree(d_vec);
printf("\\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
hipMalloc((void **)&d_vec, size);
//SUM
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
hipMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
hipMemcpy(d_float_vec, float_vec, N*sizeof(float), hipMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
hipMemcpy(&res, d_float_vec, sizeof(res), hipMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
hipFree(d_vec);
printf("\\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPi
.globl _Z3minPi
.p2align 8
.type _Z3minPi,@function
_Z3minPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v4, v6, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPi, .Lfunc_end0-_Z3minPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3maxPi
.globl _Z3maxPi
.p2align 8
.type _Z3maxPi,@function
_Z3maxPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v4, v6, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3maxPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3maxPi, .Lfunc_end1-_Z3maxPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB2_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB2_5
.LBB2_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB2_2
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3sumPi, .Lfunc_end2-_Z3sumPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10sum_floatsPf
.globl _Z10sum_floatsPf
.p2align 8
.type _Z10sum_floatsPf,@function
_Z10sum_floatsPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB3_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB3_5
.LBB3_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB3_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
s_branch .LBB3_2
.LBB3_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_floatsPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10sum_floatsPf, .Lfunc_end3-_Z10sum_floatsPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12mean_diff_sqPff
.globl _Z12mean_diff_sqPff
.p2align 8
.type _Z12mean_diff_sqPff,@function
_Z12mean_diff_sqPff:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mean_diff_sqPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z12mean_diff_sqPff, .Lfunc_end4-_Z12mean_diff_sqPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3minPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3maxPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3maxPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3sumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_floatsPf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z10sum_floatsPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mean_diff_sqPff
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12mean_diff_sqPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<math.h>
#include<stdlib.h>
#include<time.h>
#define N 2048
using namespace std;
void random_ints(int *vector, int size){
for(int i=0; i<size; i++)
vector[i] = rand()%10;
}
void copy_int_to_float(float *dest, int *src, int size){
for(int i=0; i<size; i++)
dest[i] = float(src[i]);
}
__global__ void min(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] > vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void max(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){
int first_index = tid * step_size *2;
int second_index = first_index + step_size;
vector[first_index] = vector[first_index] < vector[second_index] ? vector[second_index] : vector[first_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum(int *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void sum_floats(float *vector){
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0){
if(tid < number_of_threads){ //If thread is alive
int first_index = tid * step_size * 2; //As each thread operates on 2 elements.
int second_index = first_index + step_size;
vector[first_index] += vector[second_index];
}
step_size <<= 1;
number_of_threads >>= 1;
}
}
__global__ void mean_diff_sq(float *vector, float mean){ //Calculates (x - x')^2
vector[threadIdx.x] -= mean;
vector[threadIdx.x] *= vector[threadIdx.x];
}
int main(void){
int size = N * sizeof(int);
int *vec; //Host copy of vec
int *d_vec; //Device copy of vec
int result;
srand(time(0));
vec = (int *)malloc(size);
random_ints(vec, N);
hipMalloc((void **)&d_vec, size);
//SUM
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("Sum is: %d", result);
//MIN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
min<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMin is: %d", result);
//MAX
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
max<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
printf("\\nMax is: %d", result);
//MEAN
hipMemcpy(d_vec, vec, size, hipMemcpyHostToDevice);
sum<<<1, N/2>>>(d_vec);
//Copy the first element of array back to result
hipMemcpy(&result, d_vec, sizeof(int), hipMemcpyDeviceToHost);
float mean = float(result)/N;
printf("\\nMean is: %f", mean);
//STD. DEV
float *float_vec;
float *d_float_vec;
float_vec = (float *)malloc(N*sizeof(float));
hipMalloc((void **)&d_float_vec, N*sizeof(float));
copy_int_to_float(float_vec, vec, N);
hipMemcpy(d_float_vec, float_vec, N*sizeof(float), hipMemcpyHostToDevice);
mean_diff_sq<<<1, N>>>(d_float_vec, mean);
sum_floats<<<1, N/2>>>(d_float_vec);
float res;
hipMemcpy(&res, d_float_vec, sizeof(res), hipMemcpyDeviceToHost);
res /= N;
printf("\\nVariance: %f", res);
res = sqrt(res);
printf("\\nStd. Dev: %f", res);
//Free allocated memory
hipFree(d_vec);
printf("\\n");
return 0;
} | .text
.file "ParallelReductionCUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z17copy_int_to_floatPfPii # -- Begin function _Z17copy_int_to_floatPfPii
.p2align 4, 0x90
.type _Z17copy_int_to_floatPfPii,@function
_Z17copy_int_to_floatPfPii: # @_Z17copy_int_to_floatPfPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17copy_int_to_floatPfPii, .Lfunc_end1-_Z17copy_int_to_floatPfPii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__minPi # -- Begin function _Z18__device_stub__minPi
.p2align 4, 0x90
.type _Z18__device_stub__minPi,@function
_Z18__device_stub__minPi: # @_Z18__device_stub__minPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3minPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z18__device_stub__minPi, .Lfunc_end2-_Z18__device_stub__minPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__maxPi # -- Begin function _Z18__device_stub__maxPi
.p2align 4, 0x90
.type _Z18__device_stub__maxPi,@function
_Z18__device_stub__maxPi: # @_Z18__device_stub__maxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3maxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z18__device_stub__maxPi, .Lfunc_end3-_Z18__device_stub__maxPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z18__device_stub__sumPi, .Lfunc_end4-_Z18__device_stub__sumPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__sum_floatsPf # -- Begin function _Z25__device_stub__sum_floatsPf
.p2align 4, 0x90
.type _Z25__device_stub__sum_floatsPf,@function
_Z25__device_stub__sum_floatsPf: # @_Z25__device_stub__sum_floatsPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10sum_floatsPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__sum_floatsPf, .Lfunc_end5-_Z25__device_stub__sum_floatsPf
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mean_diff_sqPff # -- Begin function _Z27__device_stub__mean_diff_sqPff
.p2align 4, 0x90
.type _Z27__device_stub__mean_diff_sqPff,@function
_Z27__device_stub__mean_diff_sqPff: # @_Z27__device_stub__mean_diff_sqPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mean_diff_sqPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z27__device_stub__mean_diff_sqPff, .Lfunc_end6-_Z27__device_stub__mean_diff_sqPff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB7_1
# %bb.2: # %_Z11random_intsPii.exit
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_4:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3minPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3maxPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_8:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_10:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
cvtsi2ssl 4(%rsp), %xmm0
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r12
leaq 104(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_11: # %.lr.ph.i60
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%r15,%rax,4), %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB7_11
# %bb.12: # %_Z17copy_int_to_floatPfPii.exit
movq 104(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2047(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_14
# %bb.13:
movq 104(%rsp), %rax
movq %rax, 40(%rsp)
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 116(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 116(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mean_diff_sqPff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_14:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15:
movq 104(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10sum_floatsPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_16:
movq 104(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, 64(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB7_18
# %bb.17:
sqrtss %xmm0, %xmm0
jmp .LBB7_19
.LBB7_18: # %call.sqrt
callq sqrtf
.LBB7_19: # %.split
movss %xmm0, 64(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3maxPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_floatsPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mean_diff_sqPff, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPi,@object # @_Z3minPi
.section .rodata,"a",@progbits
.globl _Z3minPi
.p2align 3, 0x0
_Z3minPi:
.quad _Z18__device_stub__minPi
.size _Z3minPi, 8
.type _Z3maxPi,@object # @_Z3maxPi
.globl _Z3maxPi
.p2align 3, 0x0
_Z3maxPi:
.quad _Z18__device_stub__maxPi
.size _Z3maxPi, 8
.type _Z3sumPi,@object # @_Z3sumPi
.globl _Z3sumPi
.p2align 3, 0x0
_Z3sumPi:
.quad _Z18__device_stub__sumPi
.size _Z3sumPi, 8
.type _Z10sum_floatsPf,@object # @_Z10sum_floatsPf
.globl _Z10sum_floatsPf
.p2align 3, 0x0
_Z10sum_floatsPf:
.quad _Z25__device_stub__sum_floatsPf
.size _Z10sum_floatsPf, 8
.type _Z12mean_diff_sqPff,@object # @_Z12mean_diff_sqPff
.globl _Z12mean_diff_sqPff
.p2align 3, 0x0
_Z12mean_diff_sqPff:
.quad _Z27__device_stub__mean_diff_sqPff
.size _Z12mean_diff_sqPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is: %d"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\\nMin is: %d"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\\nMax is: %d"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\\nMean is: %f"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\\nVariance: %f"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\\nStd. Dev: %f"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\\n"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3minPi"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3maxPi"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3sumPi"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10sum_floatsPf"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z12mean_diff_sqPff"
.size .L__unnamed_5, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPi
.addrsig_sym _Z18__device_stub__maxPi
.addrsig_sym _Z18__device_stub__sumPi
.addrsig_sym _Z25__device_stub__sum_floatsPf
.addrsig_sym _Z27__device_stub__mean_diff_sqPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPi
.addrsig_sym _Z3maxPi
.addrsig_sym _Z3sumPi
.addrsig_sym _Z10sum_floatsPf
.addrsig_sym _Z12mean_diff_sqPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mean_diff_sqPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ FADD R0, R0, -c[0x0][0x168] ; /* 0x80005a0000007621 */
/* 0x004fc80000000000 */
/*0070*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x000fca0000400000 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10sum_floatsPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R6, R8, 0x1, RZ ; /* 0x0000000108067819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R8, 0x2, RZ ; /* 0x0000000208067824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3maxPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x190 ; /* 0x000000b000001947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R6, R0, R9, RZ ; /* 0x0000000900067224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GE.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f26270 */
/*0150*/ @!P1 IADD3 R6, R6, R9, RZ ; /* 0x0000000906069210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e020b */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e4000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3minPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x001fe400000006ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x190 ; /* 0x000000b000001947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R6, R0, R9, RZ ; /* 0x0000000900067224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f24270 */
/*0150*/ @P1 IADD3 R6, R6, R9, RZ ; /* 0x0000000906061210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e020b */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e4000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPi
.globl _Z3minPi
.p2align 8
.type _Z3minPi,@function
_Z3minPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v4, v6, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPi, .Lfunc_end0-_Z3minPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3maxPi
.globl _Z3maxPi
.p2align 8
.type _Z3maxPi,@function
_Z3maxPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v4, v6, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3maxPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3maxPi, .Lfunc_end1-_Z3maxPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB2_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB2_5
.LBB2_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB2_2
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3sumPi, .Lfunc_end2-_Z3sumPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10sum_floatsPf
.globl _Z10sum_floatsPf
.p2align 8
.type _Z10sum_floatsPf,@function
_Z10sum_floatsPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB3_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB3_5
.LBB3_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB3_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
s_branch .LBB3_2
.LBB3_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_floatsPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10sum_floatsPf, .Lfunc_end3-_Z10sum_floatsPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12mean_diff_sqPff
.globl _Z12mean_diff_sqPff
.p2align 8
.type _Z12mean_diff_sqPff,@function
_Z12mean_diff_sqPff:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mean_diff_sqPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z12mean_diff_sqPff, .Lfunc_end4-_Z12mean_diff_sqPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3minPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3maxPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3maxPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3sumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_floatsPf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z10sum_floatsPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mean_diff_sqPff
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12mean_diff_sqPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018901a_00000000-6_ParallelReductionCUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z17copy_int_to_floatPfPii
.type _Z17copy_int_to_floatPfPii, @function
_Z17copy_int_to_floatPfPii:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl (%rsi,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3670:
.size _Z17copy_int_to_floatPfPii, .-_Z17copy_int_to_floatPfPii
.globl _Z22__device_stub__Z3minPiPi
.type _Z22__device_stub__Z3minPiPi, @function
_Z22__device_stub__Z3minPiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z22__device_stub__Z3minPiPi, .-_Z22__device_stub__Z3minPiPi
.globl _Z3minPi
.type _Z3minPi, @function
_Z3minPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3minPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3minPi, .-_Z3minPi
.globl _Z22__device_stub__Z3maxPiPi
.type _Z22__device_stub__Z3maxPiPi, @function
_Z22__device_stub__Z3maxPiPi:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3maxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z22__device_stub__Z3maxPiPi, .-_Z22__device_stub__Z3maxPiPi
.globl _Z3maxPi
.type _Z3maxPi, @function
_Z3maxPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3maxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z3maxPi, .-_Z3maxPi
.globl _Z22__device_stub__Z3sumPiPi
.type _Z22__device_stub__Z3sumPiPi, @function
_Z22__device_stub__Z3sumPiPi:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z22__device_stub__Z3sumPiPi, .-_Z22__device_stub__Z3sumPiPi
.globl _Z3sumPi
.type _Z3sumPi, @function
_Z3sumPi:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z3sumPi, .-_Z3sumPi
.globl _Z30__device_stub__Z10sum_floatsPfPf
.type _Z30__device_stub__Z10sum_floatsPfPf, @function
_Z30__device_stub__Z10sum_floatsPfPf:
.LFB3702:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10sum_floatsPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z30__device_stub__Z10sum_floatsPfPf, .-_Z30__device_stub__Z10sum_floatsPfPf
.globl _Z10sum_floatsPf
.type _Z10sum_floatsPf, @function
_Z10sum_floatsPf:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10sum_floatsPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z10sum_floatsPf, .-_Z10sum_floatsPf
.globl _Z33__device_stub__Z12mean_diff_sqPffPff
.type _Z33__device_stub__Z12mean_diff_sqPffPff, @function
_Z33__device_stub__Z12mean_diff_sqPffPff:
.LFB3704:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mean_diff_sqPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z33__device_stub__Z12mean_diff_sqPffPff, .-_Z33__device_stub__Z12mean_diff_sqPffPff
.globl _Z12mean_diff_sqPff
.type _Z12mean_diff_sqPff, @function
_Z12mean_diff_sqPff:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12mean_diff_sqPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z12mean_diff_sqPff, .-_Z12mean_diff_sqPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Sum is: %d"
.LC1:
.string "\\nMin is: %d"
.LC2:
.string "\\nMax is: %d"
.LC4:
.string "\\nMean is: %f"
.LC5:
.string "\\nVariance: %f"
.LC7:
.string "\\nStd. Dev: %f"
.LC8:
.string "\\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L56:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L57:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L58:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L59:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $2048, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17copy_int_to_floatPfPii
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $2048, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L60:
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L61:
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movss .LC3(%rip), %xmm0
mulss 60(%rsp), %xmm0
movss %xmm0, 60(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 60(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L67
sqrtss %xmm0, %xmm0
.L64:
movss %xmm0, 60(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L56
.L70:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3minPiPi
jmp .L57
.L71:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3maxPiPi
jmp .L58
.L72:
movq 32(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L59
.L73:
movss 12(%rsp), %xmm0
movq 40(%rsp), %rdi
call _Z33__device_stub__Z12mean_diff_sqPffPff
jmp .L60
.L74:
movq 40(%rsp), %rdi
call _Z30__device_stub__Z10sum_floatsPfPf
jmp .L61
.L67:
call sqrtf@PLT
jmp .L64
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12mean_diff_sqPff"
.LC10:
.string "_Z10sum_floatsPf"
.LC11:
.string "_Z3sumPi"
.LC12:
.string "_Z3maxPi"
.LC13:
.string "_Z3minPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mean_diff_sqPff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_floatsPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3maxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 973078528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ParallelReductionCUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z17copy_int_to_floatPfPii # -- Begin function _Z17copy_int_to_floatPfPii
.p2align 4, 0x90
.type _Z17copy_int_to_floatPfPii,@function
_Z17copy_int_to_floatPfPii: # @_Z17copy_int_to_floatPfPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17copy_int_to_floatPfPii, .Lfunc_end1-_Z17copy_int_to_floatPfPii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__minPi # -- Begin function _Z18__device_stub__minPi
.p2align 4, 0x90
.type _Z18__device_stub__minPi,@function
_Z18__device_stub__minPi: # @_Z18__device_stub__minPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3minPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z18__device_stub__minPi, .Lfunc_end2-_Z18__device_stub__minPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__maxPi # -- Begin function _Z18__device_stub__maxPi
.p2align 4, 0x90
.type _Z18__device_stub__maxPi,@function
_Z18__device_stub__maxPi: # @_Z18__device_stub__maxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3maxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z18__device_stub__maxPi, .Lfunc_end3-_Z18__device_stub__maxPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z18__device_stub__sumPi, .Lfunc_end4-_Z18__device_stub__sumPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__sum_floatsPf # -- Begin function _Z25__device_stub__sum_floatsPf
.p2align 4, 0x90
.type _Z25__device_stub__sum_floatsPf,@function
_Z25__device_stub__sum_floatsPf: # @_Z25__device_stub__sum_floatsPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10sum_floatsPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__sum_floatsPf, .Lfunc_end5-_Z25__device_stub__sum_floatsPf
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mean_diff_sqPff # -- Begin function _Z27__device_stub__mean_diff_sqPff
.p2align 4, 0x90
.type _Z27__device_stub__mean_diff_sqPff,@function
_Z27__device_stub__mean_diff_sqPff: # @_Z27__device_stub__mean_diff_sqPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mean_diff_sqPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z27__device_stub__mean_diff_sqPff, .Lfunc_end6-_Z27__device_stub__mean_diff_sqPff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB7_1
# %bb.2: # %_Z11random_intsPii.exit
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_4:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3minPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3maxPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_8:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_10:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
cvtsi2ssl 4(%rsp), %xmm0
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r12
leaq 104(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_11: # %.lr.ph.i60
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%r15,%rax,4), %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB7_11
# %bb.12: # %_Z17copy_int_to_floatPfPii.exit
movq 104(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2047(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_14
# %bb.13:
movq 104(%rsp), %rax
movq %rax, 40(%rsp)
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 116(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 116(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mean_diff_sqPff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_14:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15:
movq 104(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10sum_floatsPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_16:
movq 104(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, 64(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB7_18
# %bb.17:
sqrtss %xmm0, %xmm0
jmp .LBB7_19
.LBB7_18: # %call.sqrt
callq sqrtf
.LBB7_19: # %.split
movss %xmm0, 64(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3maxPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_floatsPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mean_diff_sqPff, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPi,@object # @_Z3minPi
.section .rodata,"a",@progbits
.globl _Z3minPi
.p2align 3, 0x0
_Z3minPi:
.quad _Z18__device_stub__minPi
.size _Z3minPi, 8
.type _Z3maxPi,@object # @_Z3maxPi
.globl _Z3maxPi
.p2align 3, 0x0
_Z3maxPi:
.quad _Z18__device_stub__maxPi
.size _Z3maxPi, 8
.type _Z3sumPi,@object # @_Z3sumPi
.globl _Z3sumPi
.p2align 3, 0x0
_Z3sumPi:
.quad _Z18__device_stub__sumPi
.size _Z3sumPi, 8
.type _Z10sum_floatsPf,@object # @_Z10sum_floatsPf
.globl _Z10sum_floatsPf
.p2align 3, 0x0
_Z10sum_floatsPf:
.quad _Z25__device_stub__sum_floatsPf
.size _Z10sum_floatsPf, 8
.type _Z12mean_diff_sqPff,@object # @_Z12mean_diff_sqPff
.globl _Z12mean_diff_sqPff
.p2align 3, 0x0
_Z12mean_diff_sqPff:
.quad _Z27__device_stub__mean_diff_sqPff
.size _Z12mean_diff_sqPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is: %d"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\\nMin is: %d"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\\nMax is: %d"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\\nMean is: %f"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\\nVariance: %f"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\\nStd. Dev: %f"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\\n"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3minPi"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3maxPi"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3sumPi"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10sum_floatsPf"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z12mean_diff_sqPff"
.size .L__unnamed_5, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPi
.addrsig_sym _Z18__device_stub__maxPi
.addrsig_sym _Z18__device_stub__sumPi
.addrsig_sym _Z25__device_stub__sum_floatsPf
.addrsig_sym _Z27__device_stub__mean_diff_sqPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPi
.addrsig_sym _Z3maxPi
.addrsig_sym _Z3sumPi
.addrsig_sym _Z10sum_floatsPf
.addrsig_sym _Z12mean_diff_sqPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} | code for sm_80
Function : _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x188], P0 ; /* 0x0000620000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x168], R0 ; /* 0x00005a0003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0100*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0200 */
/*0120*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0202 */
/*0130*/ I2F.U16 R6, R4 ; /* 0x0000000400067306 */
/* 0x004e260000101000 */
/*0140*/ FFMA R7, R6, R7, c[0x0][0x184] ; /* 0x0000610006077623 */
/* 0x001fca0000000007 */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} | .file "tmpxft_0005ee12_00000000-6_cuConvert8uC1To32fC1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
.type _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii, @function
_Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii, .-_Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, @function
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, .-_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 8
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii,@function
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x4
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_u8 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v4, s0, s1
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, .Lfunc_end0-_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuConvert8uC1To32fC1Kernel(const unsigned char *src, size_t src_stride, float* dst, size_t dst_stride, float mul_constant, float add_constant, int width, int height)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
int src_c = y*src_stride + x;
int dst_c = y*dst_stride + x;
if (x<width && y<height)
{
dst[dst_c] = src[src_c] * mul_constant + add_constant;
}
} | .text
.file "cuConvert8uC1To32fC1Kernel.hip"
.globl _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii # -- Begin function _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 4, 0x90
.type _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii,@function
_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii: # @_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii, .Lfunc_end0-_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii,@object # @_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .rodata,"a",@progbits
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 3, 0x0
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
.quad _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x188], P0 ; /* 0x0000620000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x168], R0 ; /* 0x00005a0003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0100*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0200 */
/*0120*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0202 */
/*0130*/ I2F.U16 R6, R4 ; /* 0x0000000400067306 */
/* 0x004e260000101000 */
/*0140*/ FFMA R7, R6, R7, c[0x0][0x184] ; /* 0x0000610006077623 */
/* 0x001fca0000000007 */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 8
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii,@function
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x4
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_u8 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v4, s0, s1
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, .Lfunc_end0-_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005ee12_00000000-6_cuConvert8uC1To32fC1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
.type _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii, @function
_Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii, .-_Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, @function
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z26cuConvert8uC1To32fC1KernelPKhmPfmffiiPKhmPfmffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, .-_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuConvert8uC1To32fC1Kernel.hip"
.globl _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii # -- Begin function _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 4, 0x90
.type _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii,@function
_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii: # @_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii, .Lfunc_end0-_Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii,@object # @_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.section .rodata,"a",@progbits
.globl _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.p2align 3, 0x0
_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii:
.quad _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.size _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26cuConvert8uC1To32fC1KernelPKhmPfmffii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__cuConvert8uC1To32fC1KernelPKhmPfmffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26cuConvert8uC1To32fC1KernelPKhmPfmffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d(int* data)
{
int thread_id = threadIdx.x;
int block_offset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int grid_id = row_offset + block_offset + thread_id;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(2, 2);
unique_grid_id_calculation_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/ | code for sm_80
Function : _Z29unique_grid_id_calculation_2dPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002600 */
/*0060*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R13, R11, c[0x0][0xc], R10 ; /* 0x000003000b0d7a24 */
/* 0x001fc800078e020a */
/*0080*/ IMAD R13, R13, c[0x0][0x0], R12 ; /* 0x000000000d0d7a24 */
/* 0x002fc800078e020c */
/*0090*/ IMAD.WIDE R2, R13, R2, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x000fcc00078e0202 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00e0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*00f0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0110*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0001e20000100a00 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc600000e06ff */
/*0130*/ STL [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0041e80000100800 */
/*0140*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*0150*/ MOV R11, 0x1c0 ; /* 0x000001c0000b7802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*01a0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01b0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d(int* data)
{
int thread_id = threadIdx.x;
int block_offset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int grid_id = row_offset + block_offset + thread_id;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(2, 2);
unique_grid_id_calculation_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/ | .file "tmpxft_000daff2_00000000-6_6.index_calculation_for_2D_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
.type _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi, @function
_Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29unique_grid_id_calculation_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi, .-_Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
.globl _Z29unique_grid_id_calculation_2dPi
.type _Z29unique_grid_id_calculation_2dPi, @function
_Z29unique_grid_id_calculation_2dPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z29unique_grid_id_calculation_2dPi, .-_Z29unique_grid_id_calculation_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29unique_grid_id_calculation_2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29unique_grid_id_calculation_2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d(int* data)
{
int thread_id = threadIdx.x;
int block_offset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int grid_id = row_offset + block_offset + thread_id;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(2, 2);
unique_grid_id_calculation_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/ | #include "hip/hip_runtime.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d(int* data)
{
int thread_id = threadIdx.x;
int block_offset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int grid_id = row_offset + block_offset + thread_id;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(2, 2);
unique_grid_id_calculation_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d(int* data)
{
int thread_id = threadIdx.x;
int block_offset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int grid_id = row_offset + block_offset + thread_id;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(2, 2);
unique_grid_id_calculation_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/ | .text
.file "6.index_calculation_for_2D_grid.hip"
.globl _Z44__device_stub__unique_grid_id_calculation_2dPi # -- Begin function _Z44__device_stub__unique_grid_id_calculation_2dPi
.p2align 4, 0x90
.type _Z44__device_stub__unique_grid_id_calculation_2dPi,@function
_Z44__device_stub__unique_grid_id_calculation_2dPi: # @_Z44__device_stub__unique_grid_id_calculation_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z29unique_grid_id_calculation_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z44__device_stub__unique_grid_id_calculation_2dPi, .Lfunc_end0-_Z44__device_stub__unique_grid_id_calculation_2dPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29unique_grid_id_calculation_2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29unique_grid_id_calculation_2dPi,@object # @_Z29unique_grid_id_calculation_2dPi
.section .rodata,"a",@progbits
.globl _Z29unique_grid_id_calculation_2dPi
.p2align 3, 0x0
_Z29unique_grid_id_calculation_2dPi:
.quad _Z44__device_stub__unique_grid_id_calculation_2dPi
.size _Z29unique_grid_id_calculation_2dPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29unique_grid_id_calculation_2dPi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__unique_grid_id_calculation_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29unique_grid_id_calculation_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000daff2_00000000-6_6.index_calculation_for_2D_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
.type _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi, @function
_Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29unique_grid_id_calculation_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi, .-_Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
.globl _Z29unique_grid_id_calculation_2dPi
.type _Z29unique_grid_id_calculation_2dPi, @function
_Z29unique_grid_id_calculation_2dPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z29unique_grid_id_calculation_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z29unique_grid_id_calculation_2dPi, .-_Z29unique_grid_id_calculation_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29unique_grid_id_calculation_2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29unique_grid_id_calculation_2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "6.index_calculation_for_2D_grid.hip"
.globl _Z44__device_stub__unique_grid_id_calculation_2dPi # -- Begin function _Z44__device_stub__unique_grid_id_calculation_2dPi
.p2align 4, 0x90
.type _Z44__device_stub__unique_grid_id_calculation_2dPi,@function
_Z44__device_stub__unique_grid_id_calculation_2dPi: # @_Z44__device_stub__unique_grid_id_calculation_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z29unique_grid_id_calculation_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z44__device_stub__unique_grid_id_calculation_2dPi, .Lfunc_end0-_Z44__device_stub__unique_grid_id_calculation_2dPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29unique_grid_id_calculation_2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29unique_grid_id_calculation_2dPi,@object # @_Z29unique_grid_id_calculation_2dPi
.section .rodata,"a",@progbits
.globl _Z29unique_grid_id_calculation_2dPi
.p2align 3, 0x0
_Z29unique_grid_id_calculation_2dPi:
.quad _Z44__device_stub__unique_grid_id_calculation_2dPi
.size _Z29unique_grid_id_calculation_2dPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29unique_grid_id_calculation_2dPi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__unique_grid_id_calculation_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29unique_grid_id_calculation_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif | .file "tmpxft_00043578_00000000-6_util.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef _UTIL_CU
#define _UTIL_CU
template<int N> __device__ void zero(unsigned int *x)
{
#pragma unroll
for(int i = 0; i < N; i++) {
x[i] = 0;
}
}
template<int N> __device__ void copy(const unsigned int *a, unsigned int *b)
{
#pragma unroll
for(int i = 0; i < N; i++) {
b[i] = a[i];
}
}
#endif | .text
.file "util.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00043578_00000000-6_util.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "util.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel(){
int gId = blockIdx.x * blockDim.x + threadIdx.x;
printf("bId=%d,tId=%d,gId=%d¥n", blockIdx.x, threadIdx.x, gId);
}
int main(void){
kernel<<<3, 4>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00a0*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fe200078e0209 */
/*00b0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e80000100a00 */
/*00c0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0001e40000100800 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel(){
int gId = blockIdx.x * blockDim.x + threadIdx.x;
printf("bId=%d,tId=%d,gId=%d¥n", blockIdx.x, threadIdx.x, gId);
}
int main(void){
kernel<<<3, 4>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000b94bb_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel(){
int gId = blockIdx.x * blockDim.x + threadIdx.x;
printf("bId=%d,tId=%d,gId=%d¥n", blockIdx.x, threadIdx.x, gId);
}
int main(void){
kernel<<<3, 4>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(){
int gId = blockIdx.x * blockDim.x + threadIdx.x;
printf("bId=%d,tId=%d,gId=%d¥n", blockIdx.x, threadIdx.x, gId);
}
int main(void){
kernel<<<3, 4>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel(){
int gId = blockIdx.x * blockDim.x + threadIdx.x;
printf("bId=%d,tId=%d,gId=%d¥n", blockIdx.x, threadIdx.x, gId);
}
int main(void){
kernel<<<3, 4>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "index.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b94bb_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "index.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} | .file "tmpxft_001b59db_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*-----This is a vector addition--*/
/*---- @ Cuda/c ------*/
/*---- __NS__Bologna__2020__*/
__global__ void vectorAdd(int* a, int* b, int* c, int n){
// calculate index thread
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we stay in-bounds
if(tid < n)
// Vector add
c[tid] = a[tid] + b[tid];
} | .text
.file "vectorAdd.hip"
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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