system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(cudaStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} | #include <hip/hip_runtime.h>
namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(hipStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(hipStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN12_GLOBAL__N_16kernelEx,"axG",@progbits,_ZN12_GLOBAL__N_16kernelEx,comdat
.globl _ZN12_GLOBAL__N_16kernelEx
.p2align 8
.type _ZN12_GLOBAL__N_16kernelEx,@function
_ZN12_GLOBAL__N_16kernelEx:
s_load_b64 s[0:1], s[0:1], 0x0
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s3, 0
.LBB0_1:
s_getreg_b32 s4, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_u32 s4, s4, s2
s_subb_u32 s5, 0, s3
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e64 s4, s[4:5], s[0:1]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_1
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN12_GLOBAL__N_16kernelEx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN12_GLOBAL__N_16kernelEx,"axG",@progbits,_ZN12_GLOBAL__N_16kernelEx,comdat
.Lfunc_end0:
.size _ZN12_GLOBAL__N_16kernelEx, .Lfunc_end0-_ZN12_GLOBAL__N_16kernelEx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN12_GLOBAL__N_16kernelEx
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _ZN12_GLOBAL__N_16kernelEx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(hipStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} | .text
.file "test_util_cuda.hip"
.globl _Z11spin_deviceP12ihipStream_ti # -- Begin function _Z11spin_deviceP12ihipStream_ti
.p2align 4, 0x90
.type _Z11spin_deviceP12ihipStream_ti,@function
_Z11spin_deviceP12ihipStream_ti: # @_Z11spin_deviceP12ihipStream_ti
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl %esi, %ebx
movq %rdi, %r9
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movslq %ebx, %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_ZN12_GLOBAL__N_16kernelEx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11spin_deviceP12ihipStream_ti, .Lfunc_end0-_Z11spin_deviceP12ihipStream_ti
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZN12_GLOBAL__N_121__device_stub__kernelEx
.type _ZN12_GLOBAL__N_121__device_stub__kernelEx,@function
_ZN12_GLOBAL__N_121__device_stub__kernelEx: # @_ZN12_GLOBAL__N_121__device_stub__kernelEx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_ZN12_GLOBAL__N_16kernelEx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _ZN12_GLOBAL__N_121__device_stub__kernelEx, .Lfunc_end1-_ZN12_GLOBAL__N_121__device_stub__kernelEx
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN12_GLOBAL__N_16kernelEx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN12_GLOBAL__N_16kernelEx,@object # @_ZN12_GLOBAL__N_16kernelEx
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZN12_GLOBAL__N_16kernelEx:
.quad _ZN12_GLOBAL__N_121__device_stub__kernelEx
.size _ZN12_GLOBAL__N_16kernelEx, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN12_GLOBAL__N_16kernelEx"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN12_GLOBAL__N_121__device_stub__kernelEx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN12_GLOBAL__N_16kernelEx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0000015000 */
/*0020*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0030*/ IADD3 R0, P0, -R2, R4, RZ ; /* 0x0000000402007210 */
/* 0x000fca0007f1e1ff */
/*0040*/ IMAD.X R4, R5, 0x1, ~R3, P0 ; /* 0x0000000105047824 */
/* 0x000fe200000e0e03 */
/*0050*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f04070 */
/*0060*/ ISETP.GT.AND.EX P0, PT, R4, c[0x0][0x164], PT, P0 ; /* 0x0000590004007a0c */
/* 0x000fda0003f04300 */
/*0070*/ @!P0 BRA 0x20 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN12_GLOBAL__N_16kernelEx,"axG",@progbits,_ZN12_GLOBAL__N_16kernelEx,comdat
.globl _ZN12_GLOBAL__N_16kernelEx
.p2align 8
.type _ZN12_GLOBAL__N_16kernelEx,@function
_ZN12_GLOBAL__N_16kernelEx:
s_load_b64 s[0:1], s[0:1], 0x0
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s3, 0
.LBB0_1:
s_getreg_b32 s4, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_u32 s4, s4, s2
s_subb_u32 s5, 0, s3
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e64 s4, s[4:5], s[0:1]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_1
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN12_GLOBAL__N_16kernelEx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN12_GLOBAL__N_16kernelEx,"axG",@progbits,_ZN12_GLOBAL__N_16kernelEx,comdat
.Lfunc_end0:
.size _ZN12_GLOBAL__N_16kernelEx, .Lfunc_end0-_ZN12_GLOBAL__N_16kernelEx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN12_GLOBAL__N_16kernelEx
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _ZN12_GLOBAL__N_16kernelEx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000122e7_00000000-6_test_util_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.hidden _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.type _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx, @function
_Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx, .-_Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.globl _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.hidden _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.type _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx, @function
_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx, .-_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.globl _Z11spin_deviceP11CUstream_sti
.type _Z11spin_deviceP11CUstream_sti, @function
_Z11spin_deviceP11CUstream_sti:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r9
movl %esi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movslq %ebx, %rsi
imulq $1000000000, %rsi, %rdi
call _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11spin_deviceP11CUstream_sti, .-_Z11spin_deviceP11CUstream_sti
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_util_cuda.hip"
.globl _Z11spin_deviceP12ihipStream_ti # -- Begin function _Z11spin_deviceP12ihipStream_ti
.p2align 4, 0x90
.type _Z11spin_deviceP12ihipStream_ti,@function
_Z11spin_deviceP12ihipStream_ti: # @_Z11spin_deviceP12ihipStream_ti
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl %esi, %ebx
movq %rdi, %r9
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movslq %ebx, %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_ZN12_GLOBAL__N_16kernelEx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11spin_deviceP12ihipStream_ti, .Lfunc_end0-_Z11spin_deviceP12ihipStream_ti
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZN12_GLOBAL__N_121__device_stub__kernelEx
.type _ZN12_GLOBAL__N_121__device_stub__kernelEx,@function
_ZN12_GLOBAL__N_121__device_stub__kernelEx: # @_ZN12_GLOBAL__N_121__device_stub__kernelEx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_ZN12_GLOBAL__N_16kernelEx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _ZN12_GLOBAL__N_121__device_stub__kernelEx, .Lfunc_end1-_ZN12_GLOBAL__N_121__device_stub__kernelEx
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN12_GLOBAL__N_16kernelEx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN12_GLOBAL__N_16kernelEx,@object # @_ZN12_GLOBAL__N_16kernelEx
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZN12_GLOBAL__N_16kernelEx:
.quad _ZN12_GLOBAL__N_121__device_stub__kernelEx
.size _ZN12_GLOBAL__N_16kernelEx, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN12_GLOBAL__N_16kernelEx"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN12_GLOBAL__N_121__device_stub__kernelEx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN12_GLOBAL__N_16kernelEx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} | .file "tmpxft_001884e9_00000000-6_math.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11revert_signPfmm
.type _Z11revert_signPfmm, @function
_Z11revert_signPfmm:
.LFB2027:
.cfi_startproc
endbr64
imulq %rdx, %rsi
testq %rsi, %rsi
je .L3
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
movss .LC0(%rip), %xmm1
.L5:
movss (%rax), %xmm0
xorps %xmm1, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11revert_signPfmm, .-_Z11revert_signPfmm
.globl _Z11sum_vectorsPfS_S_mm
.type _Z11sum_vectorsPfS_S_mm, @function
_Z11sum_vectorsPfS_S_mm:
.LFB2028:
.cfi_startproc
endbr64
imulq %r8, %rcx
testq %rcx, %rcx
je .L7
movl $0, %eax
.L9:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE2028:
.size _Z11sum_vectorsPfS_S_mm, .-_Z11sum_vectorsPfS_S_mm
.globl _Z13sum_vectors_vPVfS0_S0_mm
.type _Z13sum_vectors_vPVfS0_S0_mm, @function
_Z13sum_vectors_vPVfS0_S0_mm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sum_vectors_vPVfS0_S0_mm, .-_Z13sum_vectors_vPVfS0_S0_mm
.globl _Z11mul_vectorsPfS_S_mmm
.type _Z11mul_vectorsPfS_S_mmm, @function
_Z11mul_vectorsPfS_S_mmm:
.LFB2030:
.cfi_startproc
endbr64
testq %r9, %r9
je .L24
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %rbx
movq %rsi, %r11
movq %rdx, %rax
movq %rcx, %rbp
movq %r8, %r10
movq %r9, %r14
leaq 0(,%r9,4), %rsi
leaq 0(,%r8,4), %r12
leaq (%rdi,%r12), %r15
movl $0, %r13d
movq %r15, %rdx
jmp .L15
.L28:
leaq (%rbx,%r15,4), %rcx
movq %r11, %r13
pxor %xmm1, %xmm1
.L16:
movss (%rcx), %xmm0
mulss 0(%r13), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq %rsi, %r13
cmpq %rdi, %rcx
jne .L16
.L19:
movss %xmm1, (%r9)
addq $1, %r8
addq %rsi, %r9
addq %r10, %r15
addq %r12, %rdi
cmpq %r8, %rbp
je .L27
.L20:
pxor %xmm1, %xmm1
testq %r10, %r10
jne .L28
jmp .L19
.L27:
movq -8(%rsp), %r13
.L17:
addq $1, %r13
addq $4, %rax
addq $4, %r11
cmpq %r13, %r14
je .L13
.L15:
testq %rbp, %rbp
je .L17
movq %rdx, %rdi
movq %rax, %r9
movl $0, %r15d
movl $0, %r8d
movq %r13, -8(%rsp)
jmp .L20
.L13:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2030:
.size _Z11mul_vectorsPfS_S_mmm, .-_Z11mul_vectorsPfS_S_mmm
.globl _Z11matrix_normPfmm
.type _Z11matrix_normPfmm, @function
_Z11matrix_normPfmm:
.LFB2031:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L37
leaq 0(,%rdx,4), %r9
leaq (%rdi,%r9), %rcx
movq %rdx, %r8
negq %r8
salq $2, %r8
movl $0, %edi
pxor %xmm3, %xmm3
movss .LC2(%rip), %xmm2
jmp .L31
.L32:
movss (%rax), %xmm0
andps %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rcx, %rax
jne .L32
.L36:
maxss %xmm3, %xmm1
movaps %xmm1, %xmm3
addq $1, %rdi
addq %r9, %rcx
cmpq %rdi, %rsi
je .L29
.L31:
leaq (%rcx,%r8), %rax
pxor %xmm1, %xmm1
testq %rdx, %rdx
jne .L32
jmp .L36
.L37:
pxor %xmm3, %xmm3
.L29:
movaps %xmm3, %xmm0
ret
.cfi_endproc
.LFE2031:
.size _Z11matrix_normPfmm, .-_Z11matrix_normPfmm
.globl _Z14inverse_matrixPfS_m
.type _Z14inverse_matrixPfS_m, @function
_Z14inverse_matrixPfS_m:
.LFB2032:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rdx, %rcx
imulq %rdx, %rcx
leaq 0(,%rcx,4), %rdx
leaq 15(%rdx), %rsi
movq %rsi, %rax
andq $-16, %rax
andq $-4096, %rsi
movq %rsp, %r8
subq %rsi, %r8
.L42:
cmpq %r8, %rsp
je .L43
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L42
.L43:
movq %rax, %rsi
andl $4095, %esi
subq %rsi, %rsp
testq %rsi, %rsi
je .L44
orq $0, -8(%rsp,%rsi)
.L44:
movq %rsp, %rax
addq $15, %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %r8
subq %rdx, %r8
.L45:
cmpq %r8, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L46:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L47
orq $0, -8(%rsp,%rdx)
.L47:
movq %rsp, %r9
movq %r9, -88(%rbp)
testq %r12, %r12
je .L41
leaq 0(,%r12,4), %r8
movq %r9, %r15
movq %rax, %r10
movq %rax, %rbx
movl $0, %esi
movl $0, %r14d
movss .LC3(%rip), %xmm1
movq %rcx, -72(%rbp)
jmp .L49
.L81:
movss %xmm1, (%rbx,%rdx,4)
.L51:
movss (%rdi,%rdx,4), %xmm0
movss %xmm0, (%r9,%rdx,4)
leaq 1(%rdx), %r11
cmpq %r11, %r12
je .L80
movq %r11, %rdx
.L52:
cmpq %rdx, %rsi
je .L81
movl $0x00000000, (%rbx,%rdx,4)
jmp .L51
.L80:
leaq 1(%rsi), %rcx
addq %r8, %rdi
addq %r8, %r9
addq %r8, %rbx
cmpq %rdx, %rsi
je .L53
movq %rcx, %rsi
.L49:
movq %r14, %rdx
jmp .L52
.L53:
movq -72(%rbp), %rcx
leaq 4(%r8), %rdi
movq -88(%rbp), %r9
movl $0, %r14d
movl $0, %esi
movq %rcx, -96(%rbp)
movq %r13, -104(%rbp)
movq %rax, -112(%rbp)
jmp .L62
.L70:
movq %rax, %r12
.L58:
movq %rbx, %rsi
movss (%rbx,%r13,4), %xmm1
divss (%r15), %xmm1
cmpq %r11, %r14
jnb .L55
movq %r13, %rax
.L56:
movaps %xmm1, %xmm2
mulss (%r9,%rax,4), %xmm2
movss (%rsi,%rax,4), %xmm0
subss %xmm2, %xmm0
movss %xmm0, (%rsi,%rax,4)
movq %rax, %rdi
addq $1, %rax
cmpq %rdi, %rdx
jne .L56
.L55:
movl $0, %eax
.L57:
movaps %xmm1, %xmm2
mulss (%r10,%rax,4), %xmm2
movss (%rcx,%rax,4), %xmm0
subss %xmm2, %xmm0
movss %xmm0, (%rcx,%rax,4)
movq %rax, %rsi
addq $1, %rax
cmpq %rsi, %rdx
jne .L57
leaq 1(%r12), %rax
addq %r8, %rcx
addq %r8, %rbx
cmpq %r12, %rdx
jne .L70
movq -72(%rbp), %rsi
movq -80(%rbp), %rdi
.L54:
movss (%r15), %xmm1
cmpq %r11, %r14
jnb .L59
movq %r13, %rax
.L60:
movss (%r9,%rax,4), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r9,%rax,4)
movq %rax, %rcx
addq $1, %rax
cmpq %rcx, %rdx
jne .L60
.L59:
movl $0, %eax
.L61:
movss (%r10,%rax,4), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r10,%rax,4)
movq %rax, %rcx
addq $1, %rax
cmpq %rcx, %rdx
jne .L61
addq $1, %r14
addq %r8, %r10
addq %rdi, %r15
addq %r8, %r9
cmpq %r13, %rdx
je .L82
.L62:
movq %rsi, %r13
addq $1, %rsi
cmpq %r11, %rsi
jnb .L54
leaq (%r10,%r8), %rcx
leaq (%r9,%r8), %rbx
movq %rsi, %r12
movq %rsi, -72(%rbp)
movq %rdi, -80(%rbp)
jmp .L58
.L82:
movq -96(%rbp), %rcx
movq -104(%rbp), %r13
movq -112(%rbp), %rax
movq %r11, %rbx
negq %rbx
salq $2, %rbx
imulq %rdx, %r8
addq %rax, %r8
movq %r11, %r14
notq %r14
salq $2, %r14
movq %r11, %rsi
imulq %rdx, %rsi
movq -88(%rbp), %rdi
leaq -4(%rdi,%rsi,4), %r12
movl $1, %edi
movq %rcx, -80(%rbp)
movq %r13, %r15
.L66:
addq $1, %rdi
cmpq %rdi, %r11
jb .L63
leaq (%rbx,%r8), %r9
movq %r9, %rsi
movq %r12, %r10
movq %rdi, %r13
movq %rdi, -72(%rbp)
.L65:
movss (%r10), %xmm2
movaps %xmm2, %xmm1
mulss (%r12,%r11,4), %xmm1
movaps %xmm2, %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%r10)
movl $0, %ecx
.L64:
movaps %xmm2, %xmm1
mulss (%r8,%rcx,4), %xmm1
movss (%rsi,%rcx,4), %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%rsi,%rcx,4)
movq %rcx, %rdi
addq $1, %rcx
cmpq %rdi, %rdx
jne .L64
addq $1, %r13
addq %rbx, %r10
addq %rbx, %rsi
cmpq %r13, %r11
jnb .L65
movq -72(%rbp), %rdi
addq %r14, %r12
movq %r9, %r8
jmp .L66
.L63:
movq -80(%rbp), %rcx
movq %r15, %r13
testq %rcx, %rcx
je .L41
movl $0, %edx
.L67:
movss (%rax,%rdx,4), %xmm0
movss %xmm0, 0(%r13,%rdx,4)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L67
.L41:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L83
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L83:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2032:
.size _Z14inverse_matrixPfS_m, .-_Z14inverse_matrixPfS_m
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -2147483648
.long 0
.long 0
.long 0
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} | #include <hip/hip_runtime.h>
#include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__host__ __device__
void revert_sign(float *a, size_t dim1, size_t dim2)
{
for (size_t i = 0; i < dim1 * dim2; ++i)
a[i] = -a[i];
}
__host__ __device__
void sum_vectors(
float *a,
float *b,
float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__device__
void sum_vectors_v(
volatile float *a,
volatile float *b,
volatile float *result,
size_t dim1,
size_t dim2
)
{
for (size_t i = 0; i < dim1*dim2; ++i)
result[i] = a[i] + b[i];
}
__host__ __device__
void mul_vectors(
float *a,
float *b,
float *result,
size_t a_dim1,
size_t a_dim2,
size_t b_dim2
)
{
for (size_t i = 0; i < b_dim2; ++i)
for (size_t j = 0; j < a_dim1; ++j)
{
float current_value = 0;
for (size_t k = 0; k < a_dim2; ++k)
current_value += a[j * a_dim2 + k] * b[k * b_dim2 + i];
result[j * b_dim2 + i] = current_value;
}
}
float matrix_norm(float *m, size_t dim1, size_t dim2)
{
float max_column_norm = 0;
for (size_t i = 0; i < dim1; ++i)
{
float column_norm = 0;
for (size_t j = 0; j < dim2; ++j)
column_norm += std::fabs(m[i * dim2 + j]);
max_column_norm = column_norm > max_column_norm ? column_norm : max_column_norm;
}
return max_column_norm;
}
void inverse_matrix(float *m_, float *result, size_t dim)
{
float inverse_matrix[dim * dim], m[dim * dim];
// init accessory matrices
for (size_t i = 0; i < dim; ++i)
for (size_t j = 0; j < dim; ++j)
{
if (i == j)
inverse_matrix[i * dim + j] = 1;
else
inverse_matrix[i * dim + j] = 0;
m[i * dim + j] = m_[i * dim + j];
}
// forward stroke
for (size_t i = 0; i < dim; ++i)
{
for (size_t j = i + 1; j < dim; ++j)
{
float multiplier = m[j * dim + i] / m[i * dim + i];
for (size_t k = i; k < dim; ++k)
m[j * dim + k] -= m[i * dim + k] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[j * dim + k] -= inverse_matrix[i * dim + k] * multiplier;
}
float divisor = m[i * dim + i];
for (size_t j = i; j < dim; ++j)
m[i * dim + j] /= divisor;
for (size_t j = 0; j < dim; ++j)
inverse_matrix[i * dim + j] /= divisor;
}
// return stroke
for (size_t i = 1; i <= dim; ++i)
for (size_t j = i + 1; j <= dim; ++j)
{
float multiplier = m[(dim - j) * dim + dim - i];
m[(dim - j) * dim + dim - i] -= m[(dim - i) * dim + dim - i] * multiplier;
for (size_t k = 0; k < dim; ++k)
inverse_matrix[(dim - j) * dim + k] -= inverse_matrix[(dim - i) * dim + k] * multiplier;
}
// copy inverse matrix to result
for (size_t i = 0; i < dim*dim; ++i)
result[i] = inverse_matrix[i];
} | .text
.file "math.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11revert_signPfmm
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z11revert_signPfmm
.p2align 4, 0x90
.type _Z11revert_signPfmm,@function
_Z11revert_signPfmm: # @_Z11revert_signPfmm
.cfi_startproc
# %bb.0:
imulq %rdx, %rsi
testq %rsi, %rsi
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm1
movss %xmm1, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11revert_signPfmm, .Lfunc_end0-_Z11revert_signPfmm
.cfi_endproc
# -- End function
.globl _Z11sum_vectorsPfS_S_mm # -- Begin function _Z11sum_vectorsPfS_S_mm
.p2align 4, 0x90
.type _Z11sum_vectorsPfS_S_mm,@function
_Z11sum_vectorsPfS_S_mm: # @_Z11sum_vectorsPfS_S_mm
.cfi_startproc
# %bb.0:
imulq %r8, %rcx
testq %rcx, %rcx
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11sum_vectorsPfS_S_mm, .Lfunc_end1-_Z11sum_vectorsPfS_S_mm
.cfi_endproc
# -- End function
.globl _Z11mul_vectorsPfS_S_mmm # -- Begin function _Z11mul_vectorsPfS_S_mmm
.p2align 4, 0x90
.type _Z11mul_vectorsPfS_S_mmm,@function
_Z11mul_vectorsPfS_S_mmm: # @_Z11mul_vectorsPfS_S_mmm
.cfi_startproc
# %bb.0:
testq %r9, %r9
je .LBB2_8
# %bb.1: # %.preheader27.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq (,%r9,4), %rax
leaq (,%r8,4), %r10
xorl %r11d, %r11d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge33
# in Loop: Header=BB2_2 Depth=1
incq %r11
addq $4, %rsi
cmpq %r9, %r11
je .LBB2_7
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_10 Depth 3
testq %rcx, %rcx
je .LBB2_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
leaq (%rdx,%r11,4), %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movq %r15, %r12
imulq %r9, %r12
movss %xmm0, (%rbx,%r12,4)
incq %r15
addq %r10, %r14
cmpq %rcx, %r15
je .LBB2_6
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_10 Depth 3
xorps %xmm0, %xmm0
testq %r8, %r8
je .LBB2_5
# %bb.9: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %rax, %r12
cmpq %r13, %r8
jne .LBB2_10
jmp .LBB2_5
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge35
retq
.Lfunc_end2:
.size _Z11mul_vectorsPfS_S_mmm, .Lfunc_end2-_Z11mul_vectorsPfS_S_mmm
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11matrix_normPfmm
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z11matrix_normPfmm
.p2align 4, 0x90
.type _Z11matrix_normPfmm,@function
_Z11matrix_normPfmm: # @_Z11matrix_normPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_1
# %bb.3: # %.preheader.lr.ph
leaq (,%rdx,4), %rax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
maxss %xmm2, %xmm0
incq %rcx
addq %rax, %rdi
movaps %xmm0, %xmm2
cmpq %rsi, %rcx
je .LBB3_2
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorps %xmm0, %xmm0
testq %rdx, %rdx
je .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=1
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm1, %xmm3
addss %xmm3, %xmm0
incq %r8
cmpq %r8, %rdx
jne .LBB3_6
jmp .LBB3_7
.LBB3_1:
xorps %xmm0, %xmm0
.LBB3_2: # %._crit_edge23
retq
.Lfunc_end3:
.size _Z11matrix_normPfmm, .Lfunc_end3-_Z11matrix_normPfmm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14inverse_matrixPfS_m
.LCPI4_0:
.long 0x3f800000 # float 1
.text
.globl _Z14inverse_matrixPfS_m
.p2align 4, 0x90
.type _Z14inverse_matrixPfS_m,@function
_Z14inverse_matrixPfS_m: # @_Z14inverse_matrixPfS_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rdx, %r15
movq %rsi, -72(%rbp) # 8-byte Spill
movq %rdi, -56(%rbp) # 8-byte Spill
imulq %rdx, %rdx
movq %rsp, %rcx
leaq 15(,%rdx,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rbx
subq %rax, %rbx
movq %rbx, %rsp
testq %r15, %r15
je .LBB4_27
# %bb.1: # %.preheader137.lr.ph
movq %rdx, -64(%rbp) # 8-byte Spill
leaq (,%r15,4), %r13
xorl %r12d, %r12d
movq -48(%rbp), %r14 # 8-byte Reload
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r12
addq %r13, %r14
cmpq %r15, %r12
je .LBB4_7
.LBB4_2: # %.preheader137
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %r13, %rdi
imulq %r12, %rdi
movq -56(%rbp), %rax # 8-byte Reload
leaq (%rax,%rdi), %rsi
addq %rbx, %rdi
movq %r13, %rdx
callq memcpy@PLT
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq %rax, %r15
je .LBB4_6
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm1, %xmm0
cmpq %rax, %r12
je .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=2
xorps %xmm0, %xmm0
jmp .LBB4_5
.LBB4_7: # %.lr.ph156.preheader
leaq 4(,%r15,4), %rax
movq %rax, -80(%rbp) # 8-byte Spill
leaq (%rbx,%r15,4), %rcx
movq -48(%rbp), %rsi # 8-byte Reload
leaq (%rsi,%r15,4), %rdx
xorl %r9d, %r9d
movq %rbx, %rdi
.p2align 4, 0x90
.LBB4_8: # %.lr.ph156
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_13 Depth 3
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
leaq 1(%r9), %rax
movq %rax, -56(%rbp) # 8-byte Spill
cmpq %r15, %rax
jae .LBB4_15
# %bb.9: # %.lr.ph148
# in Loop: Header=BB4_8 Depth=1
movq %r9, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %r10
movq %rdx, %r11
movq %rcx, %r14
movq -56(%rbp), %r8 # 8-byte Reload
.p2align 4, 0x90
.LBB4_10: # %.lr.ph142.preheader
# Parent Loop BB4_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_13 Depth 3
movq %r8, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %rax
movss (%rax,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r10,%r9,4), %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_11: # %.lr.ph142
# Parent Loop BB4_8 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r14,%rax,4)
leaq (%r9,%rax), %r12
incq %r12
incq %rax
cmpq %r15, %r12
jb .LBB4_11
# %bb.12: # %.preheader133
# in Loop: Header=BB4_10 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_8 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r11,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r11,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB4_13
# %bb.14: # %._crit_edge145
# in Loop: Header=BB4_10 Depth=2
incq %r8
addq %r13, %r14
addq %r13, %r11
cmpq %r15, %r8
jb .LBB4_10
.LBB4_15: # %._crit_edge149
# in Loop: Header=BB4_8 Depth=1
movq %r9, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %rax
movss (%rax,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_16: # %.lr.ph152
# Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rdi,%rax,4)
leaq (%r9,%rax), %r8
incq %r8
incq %rax
cmpq %r15, %r8
jb .LBB4_16
# %bb.17: # %.lr.ph154
# in Loop: Header=BB4_8 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rsi,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB4_18
# %bb.19: # %.loopexit135
# in Loop: Header=BB4_8 Depth=1
movq -80(%rbp), %rax # 8-byte Reload
addq %rax, %rdi
addq %rax, %rcx
addq %r13, %rsi
addq %r13, %rdx
movq -56(%rbp), %rax # 8-byte Reload
movq %rax, %r9
cmpq %r15, %rax
jne .LBB4_8
# %bb.20: # %.lr.ph168
leaq 1(%r15), %rcx
cmpq $3, %rcx
movl $2, %eax
cmovaeq %rcx, %rax
leaq (%rbx,%r15,4), %rcx
leaq -1(%r15), %rdx
imulq %r15, %rdx
movq -48(%rbp), %rdi # 8-byte Reload
leaq (%rdi,%rdx,4), %r12
negq %r13
leaq -2(%r15), %rsi
imulq %r15, %rsi
leaq (%rdi,%rsi,4), %rsi
movl $1, %edi
movq $-1, %r10
movq -64(%rbp), %rdx # 8-byte Reload
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_26: # %.loopexit
# in Loop: Header=BB4_21 Depth=1
notq %r8
addq %r13, %r12
addq %r13, %rsi
movq %r8, %r10
cmpq %rax, %rdi
je .LBB4_27
.LBB4_21: # =>This Loop Header: Depth=1
# Child Loop BB4_23 Depth 2
# Child Loop BB4_24 Depth 3
movq %rdi, %r8
incq %rdi
movq %r15, %r9
subq %r8, %r9
jbe .LBB4_26
# %bb.22: # %.lr.ph164
# in Loop: Header=BB4_21 Depth=1
imulq %r15, %r9
leaq (%rcx,%r10,4), %r10
movq %rsi, %r11
movq %rdi, %rbx
.p2align 4, 0x90
.LBB4_23: # %.lr.ph159
# Parent Loop BB4_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_24 Depth 3
movq %r15, %r14
subq %rbx, %r14
imulq %r15, %r14
movss (%r10,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r10,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
movss %xmm2, (%r10,%r14,4)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_21 Depth=1
# Parent Loop BB4_23 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r11,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r11,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB4_24
# %bb.25: # %._crit_edge160
# in Loop: Header=BB4_23 Depth=2
incq %rbx
addq %r13, %r11
cmpq %r15, %rbx
jbe .LBB4_23
jmp .LBB4_26
.LBB4_27: # %.preheader
testq %rdx, %rdx
je .LBB4_29
# %bb.28: # %.lr.ph170.preheader
shlq $2, %rdx
movq -72(%rbp), %rdi # 8-byte Reload
movq -48(%rbp), %rsi # 8-byte Reload
callq memcpy@PLT
.LBB4_29: # %._crit_edge171
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size _Z14inverse_matrixPfS_m, .Lfunc_end4-_Z14inverse_matrixPfS_m
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001884e9_00000000-6_math.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11revert_signPfmm
.type _Z11revert_signPfmm, @function
_Z11revert_signPfmm:
.LFB2027:
.cfi_startproc
endbr64
imulq %rdx, %rsi
testq %rsi, %rsi
je .L3
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
movss .LC0(%rip), %xmm1
.L5:
movss (%rax), %xmm0
xorps %xmm1, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11revert_signPfmm, .-_Z11revert_signPfmm
.globl _Z11sum_vectorsPfS_S_mm
.type _Z11sum_vectorsPfS_S_mm, @function
_Z11sum_vectorsPfS_S_mm:
.LFB2028:
.cfi_startproc
endbr64
imulq %r8, %rcx
testq %rcx, %rcx
je .L7
movl $0, %eax
.L9:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE2028:
.size _Z11sum_vectorsPfS_S_mm, .-_Z11sum_vectorsPfS_S_mm
.globl _Z13sum_vectors_vPVfS0_S0_mm
.type _Z13sum_vectors_vPVfS0_S0_mm, @function
_Z13sum_vectors_vPVfS0_S0_mm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sum_vectors_vPVfS0_S0_mm, .-_Z13sum_vectors_vPVfS0_S0_mm
.globl _Z11mul_vectorsPfS_S_mmm
.type _Z11mul_vectorsPfS_S_mmm, @function
_Z11mul_vectorsPfS_S_mmm:
.LFB2030:
.cfi_startproc
endbr64
testq %r9, %r9
je .L24
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %rbx
movq %rsi, %r11
movq %rdx, %rax
movq %rcx, %rbp
movq %r8, %r10
movq %r9, %r14
leaq 0(,%r9,4), %rsi
leaq 0(,%r8,4), %r12
leaq (%rdi,%r12), %r15
movl $0, %r13d
movq %r15, %rdx
jmp .L15
.L28:
leaq (%rbx,%r15,4), %rcx
movq %r11, %r13
pxor %xmm1, %xmm1
.L16:
movss (%rcx), %xmm0
mulss 0(%r13), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq %rsi, %r13
cmpq %rdi, %rcx
jne .L16
.L19:
movss %xmm1, (%r9)
addq $1, %r8
addq %rsi, %r9
addq %r10, %r15
addq %r12, %rdi
cmpq %r8, %rbp
je .L27
.L20:
pxor %xmm1, %xmm1
testq %r10, %r10
jne .L28
jmp .L19
.L27:
movq -8(%rsp), %r13
.L17:
addq $1, %r13
addq $4, %rax
addq $4, %r11
cmpq %r13, %r14
je .L13
.L15:
testq %rbp, %rbp
je .L17
movq %rdx, %rdi
movq %rax, %r9
movl $0, %r15d
movl $0, %r8d
movq %r13, -8(%rsp)
jmp .L20
.L13:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2030:
.size _Z11mul_vectorsPfS_S_mmm, .-_Z11mul_vectorsPfS_S_mmm
.globl _Z11matrix_normPfmm
.type _Z11matrix_normPfmm, @function
_Z11matrix_normPfmm:
.LFB2031:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L37
leaq 0(,%rdx,4), %r9
leaq (%rdi,%r9), %rcx
movq %rdx, %r8
negq %r8
salq $2, %r8
movl $0, %edi
pxor %xmm3, %xmm3
movss .LC2(%rip), %xmm2
jmp .L31
.L32:
movss (%rax), %xmm0
andps %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rcx, %rax
jne .L32
.L36:
maxss %xmm3, %xmm1
movaps %xmm1, %xmm3
addq $1, %rdi
addq %r9, %rcx
cmpq %rdi, %rsi
je .L29
.L31:
leaq (%rcx,%r8), %rax
pxor %xmm1, %xmm1
testq %rdx, %rdx
jne .L32
jmp .L36
.L37:
pxor %xmm3, %xmm3
.L29:
movaps %xmm3, %xmm0
ret
.cfi_endproc
.LFE2031:
.size _Z11matrix_normPfmm, .-_Z11matrix_normPfmm
.globl _Z14inverse_matrixPfS_m
.type _Z14inverse_matrixPfS_m, @function
_Z14inverse_matrixPfS_m:
.LFB2032:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rdx, %rcx
imulq %rdx, %rcx
leaq 0(,%rcx,4), %rdx
leaq 15(%rdx), %rsi
movq %rsi, %rax
andq $-16, %rax
andq $-4096, %rsi
movq %rsp, %r8
subq %rsi, %r8
.L42:
cmpq %r8, %rsp
je .L43
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L42
.L43:
movq %rax, %rsi
andl $4095, %esi
subq %rsi, %rsp
testq %rsi, %rsi
je .L44
orq $0, -8(%rsp,%rsi)
.L44:
movq %rsp, %rax
addq $15, %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %r8
subq %rdx, %r8
.L45:
cmpq %r8, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L46:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L47
orq $0, -8(%rsp,%rdx)
.L47:
movq %rsp, %r9
movq %r9, -88(%rbp)
testq %r12, %r12
je .L41
leaq 0(,%r12,4), %r8
movq %r9, %r15
movq %rax, %r10
movq %rax, %rbx
movl $0, %esi
movl $0, %r14d
movss .LC3(%rip), %xmm1
movq %rcx, -72(%rbp)
jmp .L49
.L81:
movss %xmm1, (%rbx,%rdx,4)
.L51:
movss (%rdi,%rdx,4), %xmm0
movss %xmm0, (%r9,%rdx,4)
leaq 1(%rdx), %r11
cmpq %r11, %r12
je .L80
movq %r11, %rdx
.L52:
cmpq %rdx, %rsi
je .L81
movl $0x00000000, (%rbx,%rdx,4)
jmp .L51
.L80:
leaq 1(%rsi), %rcx
addq %r8, %rdi
addq %r8, %r9
addq %r8, %rbx
cmpq %rdx, %rsi
je .L53
movq %rcx, %rsi
.L49:
movq %r14, %rdx
jmp .L52
.L53:
movq -72(%rbp), %rcx
leaq 4(%r8), %rdi
movq -88(%rbp), %r9
movl $0, %r14d
movl $0, %esi
movq %rcx, -96(%rbp)
movq %r13, -104(%rbp)
movq %rax, -112(%rbp)
jmp .L62
.L70:
movq %rax, %r12
.L58:
movq %rbx, %rsi
movss (%rbx,%r13,4), %xmm1
divss (%r15), %xmm1
cmpq %r11, %r14
jnb .L55
movq %r13, %rax
.L56:
movaps %xmm1, %xmm2
mulss (%r9,%rax,4), %xmm2
movss (%rsi,%rax,4), %xmm0
subss %xmm2, %xmm0
movss %xmm0, (%rsi,%rax,4)
movq %rax, %rdi
addq $1, %rax
cmpq %rdi, %rdx
jne .L56
.L55:
movl $0, %eax
.L57:
movaps %xmm1, %xmm2
mulss (%r10,%rax,4), %xmm2
movss (%rcx,%rax,4), %xmm0
subss %xmm2, %xmm0
movss %xmm0, (%rcx,%rax,4)
movq %rax, %rsi
addq $1, %rax
cmpq %rsi, %rdx
jne .L57
leaq 1(%r12), %rax
addq %r8, %rcx
addq %r8, %rbx
cmpq %r12, %rdx
jne .L70
movq -72(%rbp), %rsi
movq -80(%rbp), %rdi
.L54:
movss (%r15), %xmm1
cmpq %r11, %r14
jnb .L59
movq %r13, %rax
.L60:
movss (%r9,%rax,4), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r9,%rax,4)
movq %rax, %rcx
addq $1, %rax
cmpq %rcx, %rdx
jne .L60
.L59:
movl $0, %eax
.L61:
movss (%r10,%rax,4), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r10,%rax,4)
movq %rax, %rcx
addq $1, %rax
cmpq %rcx, %rdx
jne .L61
addq $1, %r14
addq %r8, %r10
addq %rdi, %r15
addq %r8, %r9
cmpq %r13, %rdx
je .L82
.L62:
movq %rsi, %r13
addq $1, %rsi
cmpq %r11, %rsi
jnb .L54
leaq (%r10,%r8), %rcx
leaq (%r9,%r8), %rbx
movq %rsi, %r12
movq %rsi, -72(%rbp)
movq %rdi, -80(%rbp)
jmp .L58
.L82:
movq -96(%rbp), %rcx
movq -104(%rbp), %r13
movq -112(%rbp), %rax
movq %r11, %rbx
negq %rbx
salq $2, %rbx
imulq %rdx, %r8
addq %rax, %r8
movq %r11, %r14
notq %r14
salq $2, %r14
movq %r11, %rsi
imulq %rdx, %rsi
movq -88(%rbp), %rdi
leaq -4(%rdi,%rsi,4), %r12
movl $1, %edi
movq %rcx, -80(%rbp)
movq %r13, %r15
.L66:
addq $1, %rdi
cmpq %rdi, %r11
jb .L63
leaq (%rbx,%r8), %r9
movq %r9, %rsi
movq %r12, %r10
movq %rdi, %r13
movq %rdi, -72(%rbp)
.L65:
movss (%r10), %xmm2
movaps %xmm2, %xmm1
mulss (%r12,%r11,4), %xmm1
movaps %xmm2, %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%r10)
movl $0, %ecx
.L64:
movaps %xmm2, %xmm1
mulss (%r8,%rcx,4), %xmm1
movss (%rsi,%rcx,4), %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%rsi,%rcx,4)
movq %rcx, %rdi
addq $1, %rcx
cmpq %rdi, %rdx
jne .L64
addq $1, %r13
addq %rbx, %r10
addq %rbx, %rsi
cmpq %r13, %r11
jnb .L65
movq -72(%rbp), %rdi
addq %r14, %r12
movq %r9, %r8
jmp .L66
.L63:
movq -80(%rbp), %rcx
movq %r15, %r13
testq %rcx, %rcx
je .L41
movl $0, %edx
.L67:
movss (%rax,%rdx,4), %xmm0
movss %xmm0, 0(%r13,%rdx,4)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L67
.L41:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L83
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L83:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2032:
.size _Z14inverse_matrixPfS_m, .-_Z14inverse_matrixPfS_m
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -2147483648
.long 0
.long 0
.long 0
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "math.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11revert_signPfmm
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z11revert_signPfmm
.p2align 4, 0x90
.type _Z11revert_signPfmm,@function
_Z11revert_signPfmm: # @_Z11revert_signPfmm
.cfi_startproc
# %bb.0:
imulq %rdx, %rsi
testq %rsi, %rsi
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm1
movss %xmm1, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11revert_signPfmm, .Lfunc_end0-_Z11revert_signPfmm
.cfi_endproc
# -- End function
.globl _Z11sum_vectorsPfS_S_mm # -- Begin function _Z11sum_vectorsPfS_S_mm
.p2align 4, 0x90
.type _Z11sum_vectorsPfS_S_mm,@function
_Z11sum_vectorsPfS_S_mm: # @_Z11sum_vectorsPfS_S_mm
.cfi_startproc
# %bb.0:
imulq %r8, %rcx
testq %rcx, %rcx
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11sum_vectorsPfS_S_mm, .Lfunc_end1-_Z11sum_vectorsPfS_S_mm
.cfi_endproc
# -- End function
.globl _Z11mul_vectorsPfS_S_mmm # -- Begin function _Z11mul_vectorsPfS_S_mmm
.p2align 4, 0x90
.type _Z11mul_vectorsPfS_S_mmm,@function
_Z11mul_vectorsPfS_S_mmm: # @_Z11mul_vectorsPfS_S_mmm
.cfi_startproc
# %bb.0:
testq %r9, %r9
je .LBB2_8
# %bb.1: # %.preheader27.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq (,%r9,4), %rax
leaq (,%r8,4), %r10
xorl %r11d, %r11d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge33
# in Loop: Header=BB2_2 Depth=1
incq %r11
addq $4, %rsi
cmpq %r9, %r11
je .LBB2_7
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_10 Depth 3
testq %rcx, %rcx
je .LBB2_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
leaq (%rdx,%r11,4), %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movq %r15, %r12
imulq %r9, %r12
movss %xmm0, (%rbx,%r12,4)
incq %r15
addq %r10, %r14
cmpq %rcx, %r15
je .LBB2_6
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_10 Depth 3
xorps %xmm0, %xmm0
testq %r8, %r8
je .LBB2_5
# %bb.9: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %rax, %r12
cmpq %r13, %r8
jne .LBB2_10
jmp .LBB2_5
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge35
retq
.Lfunc_end2:
.size _Z11mul_vectorsPfS_S_mmm, .Lfunc_end2-_Z11mul_vectorsPfS_S_mmm
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11matrix_normPfmm
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z11matrix_normPfmm
.p2align 4, 0x90
.type _Z11matrix_normPfmm,@function
_Z11matrix_normPfmm: # @_Z11matrix_normPfmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_1
# %bb.3: # %.preheader.lr.ph
leaq (,%rdx,4), %rax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
maxss %xmm2, %xmm0
incq %rcx
addq %rax, %rdi
movaps %xmm0, %xmm2
cmpq %rsi, %rcx
je .LBB3_2
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorps %xmm0, %xmm0
testq %rdx, %rdx
je .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=1
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm1, %xmm3
addss %xmm3, %xmm0
incq %r8
cmpq %r8, %rdx
jne .LBB3_6
jmp .LBB3_7
.LBB3_1:
xorps %xmm0, %xmm0
.LBB3_2: # %._crit_edge23
retq
.Lfunc_end3:
.size _Z11matrix_normPfmm, .Lfunc_end3-_Z11matrix_normPfmm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14inverse_matrixPfS_m
.LCPI4_0:
.long 0x3f800000 # float 1
.text
.globl _Z14inverse_matrixPfS_m
.p2align 4, 0x90
.type _Z14inverse_matrixPfS_m,@function
_Z14inverse_matrixPfS_m: # @_Z14inverse_matrixPfS_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rdx, %r15
movq %rsi, -72(%rbp) # 8-byte Spill
movq %rdi, -56(%rbp) # 8-byte Spill
imulq %rdx, %rdx
movq %rsp, %rcx
leaq 15(,%rdx,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rbx
subq %rax, %rbx
movq %rbx, %rsp
testq %r15, %r15
je .LBB4_27
# %bb.1: # %.preheader137.lr.ph
movq %rdx, -64(%rbp) # 8-byte Spill
leaq (,%r15,4), %r13
xorl %r12d, %r12d
movq -48(%rbp), %r14 # 8-byte Reload
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r12
addq %r13, %r14
cmpq %r15, %r12
je .LBB4_7
.LBB4_2: # %.preheader137
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %r13, %rdi
imulq %r12, %rdi
movq -56(%rbp), %rax # 8-byte Reload
leaq (%rax,%rdi), %rsi
addq %rbx, %rdi
movq %r13, %rdx
callq memcpy@PLT
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq %rax, %r15
je .LBB4_6
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm1, %xmm0
cmpq %rax, %r12
je .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=2
xorps %xmm0, %xmm0
jmp .LBB4_5
.LBB4_7: # %.lr.ph156.preheader
leaq 4(,%r15,4), %rax
movq %rax, -80(%rbp) # 8-byte Spill
leaq (%rbx,%r15,4), %rcx
movq -48(%rbp), %rsi # 8-byte Reload
leaq (%rsi,%r15,4), %rdx
xorl %r9d, %r9d
movq %rbx, %rdi
.p2align 4, 0x90
.LBB4_8: # %.lr.ph156
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_13 Depth 3
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
leaq 1(%r9), %rax
movq %rax, -56(%rbp) # 8-byte Spill
cmpq %r15, %rax
jae .LBB4_15
# %bb.9: # %.lr.ph148
# in Loop: Header=BB4_8 Depth=1
movq %r9, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %r10
movq %rdx, %r11
movq %rcx, %r14
movq -56(%rbp), %r8 # 8-byte Reload
.p2align 4, 0x90
.LBB4_10: # %.lr.ph142.preheader
# Parent Loop BB4_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_13 Depth 3
movq %r8, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %rax
movss (%rax,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r10,%r9,4), %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_11: # %.lr.ph142
# Parent Loop BB4_8 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r14,%rax,4)
leaq (%r9,%rax), %r12
incq %r12
incq %rax
cmpq %r15, %r12
jb .LBB4_11
# %bb.12: # %.preheader133
# in Loop: Header=BB4_10 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_8 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r11,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r11,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB4_13
# %bb.14: # %._crit_edge145
# in Loop: Header=BB4_10 Depth=2
incq %r8
addq %r13, %r14
addq %r13, %r11
cmpq %r15, %r8
jb .LBB4_10
.LBB4_15: # %._crit_edge149
# in Loop: Header=BB4_8 Depth=1
movq %r9, %rax
imulq %r15, %rax
leaq (%rbx,%rax,4), %rax
movss (%rax,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_16: # %.lr.ph152
# Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rdi,%rax,4)
leaq (%r9,%rax), %r8
incq %r8
incq %rax
cmpq %r15, %r8
jb .LBB4_16
# %bb.17: # %.lr.ph154
# in Loop: Header=BB4_8 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rsi,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB4_18
# %bb.19: # %.loopexit135
# in Loop: Header=BB4_8 Depth=1
movq -80(%rbp), %rax # 8-byte Reload
addq %rax, %rdi
addq %rax, %rcx
addq %r13, %rsi
addq %r13, %rdx
movq -56(%rbp), %rax # 8-byte Reload
movq %rax, %r9
cmpq %r15, %rax
jne .LBB4_8
# %bb.20: # %.lr.ph168
leaq 1(%r15), %rcx
cmpq $3, %rcx
movl $2, %eax
cmovaeq %rcx, %rax
leaq (%rbx,%r15,4), %rcx
leaq -1(%r15), %rdx
imulq %r15, %rdx
movq -48(%rbp), %rdi # 8-byte Reload
leaq (%rdi,%rdx,4), %r12
negq %r13
leaq -2(%r15), %rsi
imulq %r15, %rsi
leaq (%rdi,%rsi,4), %rsi
movl $1, %edi
movq $-1, %r10
movq -64(%rbp), %rdx # 8-byte Reload
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_26: # %.loopexit
# in Loop: Header=BB4_21 Depth=1
notq %r8
addq %r13, %r12
addq %r13, %rsi
movq %r8, %r10
cmpq %rax, %rdi
je .LBB4_27
.LBB4_21: # =>This Loop Header: Depth=1
# Child Loop BB4_23 Depth 2
# Child Loop BB4_24 Depth 3
movq %rdi, %r8
incq %rdi
movq %r15, %r9
subq %r8, %r9
jbe .LBB4_26
# %bb.22: # %.lr.ph164
# in Loop: Header=BB4_21 Depth=1
imulq %r15, %r9
leaq (%rcx,%r10,4), %r10
movq %rsi, %r11
movq %rdi, %rbx
.p2align 4, 0x90
.LBB4_23: # %.lr.ph159
# Parent Loop BB4_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_24 Depth 3
movq %r15, %r14
subq %rbx, %r14
imulq %r15, %r14
movss (%r10,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r10,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
movss %xmm2, (%r10,%r14,4)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_21 Depth=1
# Parent Loop BB4_23 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss (%r11,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
movss %xmm2, (%r11,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB4_24
# %bb.25: # %._crit_edge160
# in Loop: Header=BB4_23 Depth=2
incq %rbx
addq %r13, %r11
cmpq %r15, %rbx
jbe .LBB4_23
jmp .LBB4_26
.LBB4_27: # %.preheader
testq %rdx, %rdx
je .LBB4_29
# %bb.28: # %.lr.ph170.preheader
shlq $2, %rdx
movq -72(%rbp), %rdi # 8-byte Reload
movq -48(%rbp), %rsi # 8-byte Reload
callq memcpy@PLT
.LBB4_29: # %._crit_edge171
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size _Z14inverse_matrixPfS_m, .Lfunc_end4-_Z14inverse_matrixPfS_m
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World! from thread [%d,%d] \
From device\n",
threadIdx.x, blockIdx.x);
}
int main(void) {
printf("Hello World from host!\n");
print_from_gpu<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z14print_from_gpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World! from thread [%d,%d] \
From device\n",
threadIdx.x, blockIdx.x);
}
int main(void) {
printf("Hello World from host!\n");
print_from_gpu<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0000bcc9_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World! from thread [%d,%d] \
From device\n",
threadIdx.x, blockIdx.x);
}
int main(void) {
printf("Hello World from host!\n");
print_from_gpu<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World! from thread [%d,%d] \
From device\n",
threadIdx.x, blockIdx.x);
}
int main(void) {
printf("Hello World from host!\n");
print_from_gpu<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World! from thread [%d,%d] \
From device\n",
threadIdx.x, blockIdx.x);
}
int main(void) {
printf("Hello World from host!\n");
print_from_gpu<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello_world.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000bcc9_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
cudaMemset(cresult_head,0,sizeof(cresult_head));
cudaMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,cudaMemcpyHostToDevice);
cudaMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,cudaMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
cudaMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,cudaMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
cudaMalloc((void**)&cresult,sizeof(int*)*Array_i);
cudaMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
cudaMemcpy(cresult,temp3,sizeof(int*)*Array_i,cudaMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} | code for sm_80
Function : _Z4CompPPiS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fe200078e0209 */
/*00e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x002fc60000011400 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0209 */
/*0100*/ @!P1 BRA 0x590 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R13, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080d7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ SHF.L.U64.HI R12, R0.reuse, 0x2, R11 ; /* 0x00000002000c7819 */
/* 0x040fe2000001020b */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe20000000000 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ IMAD.SHL.U32 R10, R0, 0x4, RZ ; /* 0x00000004000a7824 */
/* 0x000fe400078e00ff */
/*0190*/ LDG.E.64 R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R16, [R6.64] ; /* 0x0000000606107981 */
/* 0x001f22000c1e1b00 */
/*01c0*/ IADD3 R22, P1, R20, UR5, RZ ; /* 0x0000000514167c10 */
/* 0x004fc4000ff3e0ff */
/*01d0*/ IADD3 R20, P3, R18, R10.reuse, RZ ; /* 0x0000000a12147210 */
/* 0x088fe40007f7e0ff */
/*01e0*/ IADD3.X R23, R21, UR4, RZ, P1, !PT ; /* 0x0000000415177c10 */
/* 0x000fe40008ffe4ff */
/*01f0*/ IADD3 R26, P2, R16, R10, RZ ; /* 0x0000000a101a7210 */
/* 0x010fe20007f5e0ff */
/*0200*/ IMAD.X R21, R19, 0x1, R12, P3 ; /* 0x0000000113157824 */
/* 0x000fc600018e060c */
/*0210*/ LDG.E R23, [R22.64+-0x8] ; /* 0xfffff80616177981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.X R27, R17, 0x1, R12, P2 ; /* 0x00000001111b7824 */
/* 0x000fc600010e060c */
/*0230*/ LDG.E R15, [R20.64] ; /* 0x00000006140f7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IMAD R15, R26, R23, R15 ; /* 0x000000171a0f7224 */
/* 0x004fca00078e020f */
/*0260*/ STG.E [R20.64], R15 ; /* 0x0000000f14007986 */
/* 0x0001e8000c101906 */
/*0270*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000602127981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R24, [R6.64+0x8] ; /* 0x0000080606187981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*02a0*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x004fc4000ff3e0ff */
/*02b0*/ IADD3 R24, P2, R24, R10.reuse, RZ ; /* 0x0000000a18187210 */
/* 0x088fe40007f5e0ff */
/*02c0*/ IADD3 R28, P3, R16, R10, RZ ; /* 0x0000000a101c7210 */
/* 0x010fc60007f7e0ff */
/*02d0*/ IMAD.X R25, R25, 0x1, R12.reuse, P2 ; /* 0x0000000119197824 */
/* 0x100fe200010e060c */
/*02e0*/ IADD3.X R19, R19, UR4, RZ, P1, !PT ; /* 0x0000000413137c10 */
/* 0x000fe20008ffe4ff */
/*02f0*/ IMAD.X R29, R17, 0x1, R12, P3 ; /* 0x00000001111d7824 */
/* 0x000fc600018e060c */
/*0300*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R19, [R18.64+-0x4] ; /* 0xfffffc0612137981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R15, [R28.64] ; /* 0x000000061c0f7981 */
/* 0x001ea4000c1e1900 */
/*0330*/ IMAD R15, R24, R19, R15 ; /* 0x00000013180f7224 */
/* 0x004fca00078e020f */
/*0340*/ STG.E [R28.64], R15 ; /* 0x0000000f1c007986 */
/* 0x0001e8000c101906 */
/*0350*/ LDG.E.64 R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100606167981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*0380*/ IADD3 R20, P1, R20, UR5, RZ ; /* 0x0000000514147c10 */
/* 0x004fc4000ff3e0ff */
/*0390*/ IADD3 R22, P2, R22, R10.reuse, RZ ; /* 0x0000000a16167210 */
/* 0x088fe40007f5e0ff */
/*03a0*/ IADD3 R26, P3, R16, R10, RZ ; /* 0x0000000a101a7210 */
/* 0x010fc60007f7e0ff */
/*03b0*/ IMAD.X R23, R23, 0x1, R12.reuse, P2 ; /* 0x0000000117177824 */
/* 0x100fe200010e060c */
/*03c0*/ IADD3.X R21, R21, UR4, RZ, P1, !PT ; /* 0x0000000415157c10 */
/* 0x000fe20008ffe4ff */
/*03d0*/ IMAD.X R27, R17, 0x1, R12, P3 ; /* 0x00000001111b7824 */
/* 0x000fc600018e060c */
/*03e0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R15, [R26.64] ; /* 0x000000061a0f7981 */
/* 0x001ea4000c1e1900 */
/*0410*/ IMAD R15, R22, R21, R15 ; /* 0x00000015160f7224 */
/* 0x004fca00078e020f */
/*0420*/ STG.E [R26.64], R15 ; /* 0x0000000f1a007986 */
/* 0x0001e8000c101906 */
/*0430*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000602127981 */
/* 0x000ea8000c1e1b00 */
/*0440*/ LDG.E.64 R24, [R6.64+0x18] ; /* 0x0000180606187981 */
/* 0x000ee8000c1e1b00 */
/*0450*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*0460*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x004fc4000ff3e0ff */
/*0470*/ IADD3 R24, P2, R24, R10.reuse, RZ ; /* 0x0000000a18187210 */
/* 0x088fe40007f5e0ff */
/*0480*/ IADD3 R16, P3, R16, R10, RZ ; /* 0x0000000a10107210 */
/* 0x010fc60007f7e0ff */
/*0490*/ IMAD.X R25, R25, 0x1, R12.reuse, P2 ; /* 0x0000000119197824 */
/* 0x100fe200010e060c */
/*04a0*/ IADD3.X R19, R19, UR4, RZ, P1, !PT ; /* 0x0000000413137c10 */
/* 0x000fe20008ffe4ff */
/*04b0*/ IMAD.X R17, R17, 0x1, R12, P3 ; /* 0x0000000111117824 */
/* 0x000fc600018e060c */
/*04c0*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R19, [R18.64+0x4] ; /* 0x0000040612137981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R15, [R16.64] ; /* 0x00000006100f7981 */
/* 0x001ea2000c1e1900 */
/*04f0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0510*/ UIADD3 UR5, UP0, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000ff1e03f */
/*0520*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fc60007f5e0ff */
/*0530*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0540*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0560*/ IMAD R15, R24, R19, R15 ; /* 0x00000013180f7224 */
/* 0x004fca00078e020f */
/*0570*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0001e2000c101906 */
/*0580*/ @P1 BRA 0x190 ; /* 0xfffffc0000001947 */
/* 0x000fea000383ffff */
/*0590*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.WIDE R6, R14, R9, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fe200078e0209 */
/*05b0*/ SHF.L.U64.HI R11, R0, 0x2, R11 ; /* 0x00000002000b7819 */
/* 0x000fc6000001020b */
/*05c0*/ IMAD.WIDE R14, R14, 0x4, RZ ; /* 0x000000040e0e7825 */
/* 0x001fc800078e02ff */
/*05d0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*05e0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*05f0*/ IMAD.SHL.U32 R21, R0, 0x4, RZ ; /* 0x0000000400157824 */
/* 0x000fe400078e00ff */
/*0600*/ LDG.E.64 R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000ee8000c1e1b00 */
/*0620*/ LDG.E.64 R14, [R6.64] ; /* 0x00000006060e7981 */
/* 0x000f22000c1e1b00 */
/*0630*/ IADD3 R18, P0, R12, R10, RZ ; /* 0x0000000a0c127210 */
/* 0x004fc40007f1e0ff */
/*0640*/ IADD3 R12, P2, R16, R21, RZ ; /* 0x00000015100c7210 */
/* 0x008fc60007f5e0ff */
/*0650*/ IMAD.X R19, R13, 0x1, R9, P0 ; /* 0x000000010d137824 */
/* 0x000fe200000e0609 */
/*0660*/ IADD3 R14, P1, R14, R21, RZ ; /* 0x000000150e0e7210 */
/* 0x010fe20007f3e0ff */
/*0670*/ IMAD.X R13, R17, 0x1, R11, P2 ; /* 0x00000001110d7824 */
/* 0x000fc800010e060b */
/*0680*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.X R15, R15, 0x1, R11, P1 ; /* 0x000000010f0f7824 */
/* 0x000fc600008e060b */
/*06a0*/ LDG.E R0, [R12.64] ; /* 0x000000060c007981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*06e0*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f3e0ff */
/*06f0*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007f5e0ff */
/*0700*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0710*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0609 */
/*0720*/ IMAD R17, R14, R19, R0 ; /* 0x000000130e117224 */
/* 0x004fca00078e0200 */
/*0730*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0001e2000c101906 */
/*0740*/ @P0 BRA 0x600 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
cudaMemset(cresult_head,0,sizeof(cresult_head));
cudaMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,cudaMemcpyHostToDevice);
cudaMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,cudaMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
cudaMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,cudaMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
cudaMalloc((void**)&cresult,sizeof(int*)*Array_i);
cudaMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
cudaMemcpy(cresult,temp3,sizeof(int*)*Array_i,cudaMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} | .file "tmpxft_00195337_00000000-6_\347\237\251\351\230\265\347\233\270\344\271\230.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23MallocDeviceDoubleArrayPPiii
.type _Z23MallocDeviceDoubleArrayPPiii, @function
_Z23MallocDeviceDoubleArrayPPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movslq %esi, %r14
leaq 0(,%r14,8), %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbx
salq $2, %rbx
movq %r14, %rsi
imulq %rbx, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rsi
testl %r13d, %r13d
jle .L4
movq 16(%rsp), %rcx
movq %rax, %rdx
leaq 0(%rbp,%rax), %rdi
.L5:
movq %rcx, (%rdx)
addq %rbx, %rcx
addq $8, %rdx
cmpq %rdi, %rdx
jne .L5
.L4:
movq 16(%rsp), %rax
movq %rax, (%r12)
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z23MallocDeviceDoubleArrayPPiii, .-_Z23MallocDeviceDoubleArrayPPiii
.globl _Z21MallocHostDoubleArrayii
.type _Z21MallocHostDoubleArrayii, @function
_Z21MallocHostDoubleArrayii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movslq %edi, %rbp
movslq %esi, %r12
salq $2, %r12
movq %rbp, %rdi
imulq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
testl %r13d, %r13d
jle .L10
movq %rbx, %rcx
movq %rax, %rdx
leaq 0(%rbp,%rax), %rsi
.L12:
movq %rcx, (%rdx)
addq %r12, %rcx
addq $8, %rdx
cmpq %rsi, %rdx
jne .L12
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z21MallocHostDoubleArrayii, .-_Z21MallocHostDoubleArrayii
.globl _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
.type _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i, @function
_Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4CompPPiS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i, .-_Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
.globl _Z4CompPPiS0_S0_i
.type _Z4CompPPiS0_S0_i, @function
_Z4CompPPiS0_S0_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4CompPPiS0_S0_i, .-_Z4CompPPiS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\350\277\231\346\230\257\344\270\200\344\270\252\347\237\251\351\230\265\347\233\270\344\271\230\347\232\204\347\250\213\345\272\217\n"
.align 8
.LC1:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d"
.LC3:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\347\232\204\346\225\260\346\215\256\n"
.LC4:
.string "%d"
.section .rodata.str1.8
.align 8
.LC5:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)\n"
.section .rodata.str1.1
.LC6:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\347\232\204\346\225\260\346\215\256\n"
.LC7:
.string "%d "
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdx
leaq 28(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %esi
movl 24(%rsp), %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 24(%rsp)
jle .L24
movq %r12, %rbp
movl $0, %r14d
leaq .LC4(%rip), %r13
jmp .L25
.L26:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 28(%rsp)
jg .L26
.L27:
addl $1, %r14d
addq $8, %rbp
cmpl %r14d, 24(%rsp)
jle .L24
.L25:
movl $0, %ebx
cmpl $0, 28(%rsp)
jg .L26
jmp .L27
.L24:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq 36(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %esi
movl 32(%rsp), %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %rbp
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L28
movq %rbp, %r13
movl $0, %r15d
leaq .LC4(%rip), %r14
jmp .L29
.L30:
movq 0(%r13), %rax
leaq (%rax,%rbx,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 36(%rsp)
jg .L30
.L31:
addl $1, %r15d
addq $8, %r13
cmpl %r15d, 32(%rsp)
jle .L28
.L29:
movl $0, %ebx
cmpl $0, 36(%rsp)
jg .L30
jmp .L31
.L28:
movl 24(%rsp), %r13d
movl 36(%rsp), %esi
movl %r13d, %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl 28(%rsp), %edx
movl %r13d, %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, 8(%rsp)
leaq 48(%rsp), %rdi
movl 36(%rsp), %edx
movl 32(%rsp), %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, %r13
leaq 56(%rsp), %rdi
movl 36(%rsp), %edx
movl 24(%rsp), %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, %r14
movq 56(%rsp), %r15
movl $8, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
movslq 24(%rsp), %rdx
movslq 28(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq (%r12), %rsi
movl $1, %ecx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq 0(%rbp), %rsi
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 72(%rsp)
movl 24(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %eax
movl %eax, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L32:
movslq 24(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq (%rbx), %rdi
movl $2, %ecx
movq %r15, %rsi
call cudaMemcpy@PLT
cmpl $0, 24(%rsp)
jle .L33
movl $0, %r13d
leaq .LC7(%rip), %r12
leaq .LC8(%rip), %r14
jmp .L34
.L48:
movl 28(%rsp), %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
jmp .L32
.L35:
movq (%rbx), %rax
movl (%rax,%rbp,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpl %ebp, 36(%rsp)
jg .L35
.L36:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $8, %rbx
cmpl %r13d, 24(%rsp)
jle .L33
.L34:
movl $0, %ebp
cmpl $0, 36(%rsp)
jg .L35
jmp .L36
.L33:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4CompPPiS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4CompPPiS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
cudaMemset(cresult_head,0,sizeof(cresult_head));
cudaMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,cudaMemcpyHostToDevice);
cudaMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,cudaMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
cudaMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,cudaMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
cudaMalloc((void**)&cresult,sizeof(int*)*Array_i);
cudaMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
cudaMemcpy(cresult,temp3,sizeof(int*)*Array_i,cudaMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
hipMemset(cresult_head,0,sizeof(cresult_head));
hipMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,hipMemcpyHostToDevice);
hipMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,hipMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
hipMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,hipMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
hipMalloc((void**)&cresult,sizeof(int*)*Array_i);
hipMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
hipMemcpy(cresult,temp3,sizeof(int*)*Array_i,hipMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
hipMemset(cresult_head,0,sizeof(cresult_head));
hipMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,hipMemcpyHostToDevice);
hipMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,hipMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
hipMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,hipMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
hipMalloc((void**)&cresult,sizeof(int*)*Array_i);
hipMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
hipMemcpy(cresult,temp3,sizeof(int*)*Array_i,hipMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4CompPPiS0_S0_i
.globl _Z4CompPPiS0_S0_i
.p2align 8
.type _Z4CompPPiS0_S0_i,@function
_Z4CompPPiS0_S0_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 3, v1
v_lshlrev_b32_e32 v0, 2, v5
v_lshlrev_b32_e32 v5, 2, v5
s_waitcnt lgkmcnt(0)
global_load_b64 v[1:2], v3, s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v1, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[2:3], v3, s[0:1]
flat_load_b32 v4, v[0:1]
.p2align 6
.LBB0_2:
s_load_b64 s[0:1], s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s0, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, null, s1, 0, s0
s_waitcnt vmcnt(1)
flat_load_b32 v8, v[2:3]
flat_load_b32 v9, v[6:7]
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v6
flat_store_b32 v[0:1], v6
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4CompPPiS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4CompPPiS0_S0_i, .Lfunc_end0-_Z4CompPPiS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4CompPPiS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4CompPPiS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<stdlib.h>
__global__ void Comp(int**ctable1,int **ctable2,int **cresult,int j_N)
{
int i=threadIdx.x;
int j=threadIdx.y;
for(int z=0;z<j_N;z++)
cresult[i][j]+=ctable1[i][z]*ctable2[z][j];
}
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j);
int** MallocHostDoubleArray(int Array_i,int Array_j);
int main()
{
int i1_max,j1_max,i2_max,j2_max;
printf("这是一个矩阵相乘的程序\n");
printf("请输入矩阵A大小(行列大小)\n");
scanf("%d %d",&j1_max,&i1_max); //设置矩阵的大小
int **table1=MallocHostDoubleArray(i1_max,j1_max);
printf("请输入矩阵A的数据\n");
for(int i=0;i<i1_max;i++)
for(int j=0;j<j1_max;j++)
scanf("%d",&table1[i][j]);
printf("请输入矩阵B大小(行列大小)\n");
scanf("%d %d",&j2_max,&i2_max); //设置矩阵的大小
int **table2=MallocHostDoubleArray(i2_max,j2_max); //为两个矩阵分配host空间
printf("请输入矩阵B的数据\n");
for(int i=0;i<i2_max;i++)
for(int j=0;j<j2_max;j++)
scanf("%d",&table2[i][j]);
/*
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j1_max;j++)
printf("%d ",table1[i][j]);
printf("\n");
}
for(int i=0;i<i2_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",table2[i][j]);
printf("\n");
}*/
int **result=MallocHostDoubleArray(i1_max,j2_max); //分配储存结果的host空间
int *ctable1_head,*ctable2_head,*cresult_head;
int **ctable1=MallocDeviceDoubleArray(&ctable1_head,i1_max,j1_max),**ctable2=MallocDeviceDoubleArray(&ctable2_head,i2_max,j2_max),**cresult=MallocDeviceDoubleArray(&cresult_head,i1_max,j2_max); //为两个矩阵分配显存空间
hipMemset(cresult_head,0,sizeof(cresult_head));
hipMemcpy(ctable1_head,*table1,sizeof(int)*i1_max*j1_max,hipMemcpyHostToDevice);
hipMemcpy(ctable2_head,*table2,sizeof(int)*i2_max*j2_max,hipMemcpyHostToDevice); //为table1，2赋值到显存
dim3 threadmax;
threadmax.x=i1_max;
threadmax.y=j2_max;
Comp<<<1,threadmax>>>(ctable1,ctable2,cresult,j1_max);
hipMemcpy(*result,cresult_head,sizeof(int)*i1_max*j2_max,hipMemcpyDeviceToHost);
for(int i=0;i<i1_max;i++)
{
for(int j=0;j<j2_max;j++)
printf("%d ",result[i][j]);
printf("\n");
}
return 0;
}
/*
*@用二维数组的形式访问一维数组
*@（二维数组访问，一维数组存储）
*@Device端生成动态二维数组，head返回一维数组的地址（以便memcpy使用）
*@返回值为二维数组指针
*/
int** MallocDeviceDoubleArray(int** head,int Array_i,int Array_j)
{
int** cresult,*temp,**temp3;
hipMalloc((void**)&cresult,sizeof(int*)*Array_i);
hipMalloc((void**)&temp,sizeof(int)*Array_i*Array_j);
temp3=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
temp3[i]=i*Array_j+temp;
*head=temp;
hipMemcpy(cresult,temp3,sizeof(int*)*Array_i,hipMemcpyHostToDevice);
return cresult;
}
int **MallocHostDoubleArray(int Array_i,int Array_j)
{
int **table,*table2;
table2=(int*)malloc(sizeof(int)*Array_i*Array_j);
table=(int**)malloc(sizeof(int*)*Array_i);
for(int i=0;i<Array_i;i++)
{
table[i]=Array_j*i+table2;
}
return table;
} | .text
.file "\347\237\251\351\230\265\347\233\270\344\271\230.hip"
.globl _Z19__device_stub__CompPPiS0_S0_i # -- Begin function _Z19__device_stub__CompPPiS0_S0_i
.p2align 4, 0x90
.type _Z19__device_stub__CompPPiS0_S0_i,@function
_Z19__device_stub__CompPPiS0_S0_i: # @_Z19__device_stub__CompPPiS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4CompPPiS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__CompPPiS0_S0_i, .Lfunc_end0-_Z19__device_stub__CompPPiS0_S0_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r12
movslq 16(%rsp), %r15
movq %r12, %rdi
imulq %r15, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %rbx
testq %r12, %r12
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader.i
movl %r12d, %eax
shlq $2, %r15
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, (%rbx,%rcx,8)
incq %rcx
addq %r15, %r14
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %_Z21MallocHostDoubleArrayii.exit
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_9
# %bb.4: # %.preheader82.preheader
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r15
movslq 12(%rsp), %rax
cmpq %rax, %r15
jge .LBB1_9
.LBB1_5: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
cmpl $0, 16(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
movq (%rbx,%r15,8), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 16(%rsp), %rax
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_7
jmp .LBB1_8
.LBB1_9: # %._crit_edge85
movl $.Lstr.3, %edi
callq puts@PLT
leaq 8(%rsp), %rsi
leaq 20(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 20(%rsp), %r13
movslq 8(%rsp), %r12
movq %r13, %rdi
imulq %r12, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
leaq (,%r13,8), %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader.i40
movl %r13d, %eax
shlq $2, %r12
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph.i42
# =>This Inner Loop Header: Depth=1
movq %r14, (%r15,%rcx,8)
incq %rcx
addq %r12, %r14
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %_Z21MallocHostDoubleArrayii.exit46
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, 20(%rsp)
jle .LBB1_18
# %bb.13: # %.preheader81.preheader
xorl %r12d, %r12d
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_17: # %._crit_edge88
# in Loop: Header=BB1_14 Depth=1
incq %r12
movslq 20(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_18
.LBB1_14: # %.preheader81
# =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.15: # %.lr.ph87
# in Loop: Header=BB1_14 Depth=1
movq (%r15,%r12,8), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_14 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %r13
jl .LBB1_16
jmp .LBB1_17
.LBB1_18: # %._crit_edge90
movq %rbx, 120(%rsp) # 8-byte Spill
movslq 12(%rsp), %rbx
movslq 8(%rsp), %r12
leaq (,%rbx,4), %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
imulq %r12, %rdi
callq malloc
movq %rax, %rbp
leaq (,%rbx,8), %rdi
movq %rdi, 40(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r14
movl %ebx, %r13d
testq %rbx, %rbx
jle .LBB1_21
# %bb.19: # %.lr.ph.preheader.i47
shlq $2, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_20: # %.lr.ph.i49
# =>This Inner Loop Header: Depth=1
movq %rbp, (%r14,%rax,8)
incq %rax
addq %r12, %rbp
cmpq %rax, %r13
jne .LBB1_20
.LBB1_21: # %_Z21MallocHostDoubleArrayii.exit53
movslq 16(%rsp), %r12
leaq 64(%rsp), %rdi
movq 40(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rsi # 8-byte Reload
imulq %r12, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %rbp, %rdi
callq malloc
testl %r13d, %r13d
movq 120(%rsp), %rbx # 8-byte Reload
jle .LBB1_24
# %bb.22: # %.lr.ph.i54
movq 24(%rsp), %rcx
shlq $2, %r12
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rdx,8)
incq %rdx
addq %r12, %rcx
cmpq %rdx, %r13
jne .LBB1_23
.LBB1_24: # %_Z23MallocDeviceDoubleArrayPPiii.exit
movq 24(%rsp), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movslq 20(%rsp), %rbp
movslq 8(%rsp), %r12
leaq (,%rbp,8), %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rbp, %rsi
imulq %r12, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %r13, %rdi
callq malloc
testq %rbp, %rbp
jle .LBB1_27
# %bb.25: # %.lr.ph.i59
movl %ebp, %ecx
movq 24(%rsp), %rdx
shlq $2, %r12
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_26: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq %r12, %rdx
cmpq %rsi, %rcx
jne .LBB1_26
.LBB1_27: # %_Z23MallocDeviceDoubleArrayPPiii.exit64
movq 24(%rsp), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movslq 12(%rsp), %rbp
movslq 8(%rsp), %r13
leaq (,%rbp,8), %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rbp, %rsi
imulq %r13, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %r12, %rdi
callq malloc
testq %rbp, %rbp
jle .LBB1_30
# %bb.28: # %.lr.ph.i65
movl %ebp, %ecx
movq 24(%rsp), %rdx
shlq $2, %r13
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_29: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq %r13, %rdx
cmpq %rsi, %rcx
jne .LBB1_29
.LBB1_30: # %_Z23MallocDeviceDoubleArrayPPiii.exit70
movq 24(%rsp), %r13
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %r12
movl $8, %edx
movq %r13, %rdi
xorl %esi, %esi
callq hipMemset
movq (%rbx), %rsi
movslq 12(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 48(%rsp), %rdi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq (%r15), %rsi
movslq 20(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl 8(%rsp), %edx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movl 16(%rsp), %eax
movq 112(%rsp), %rcx # 8-byte Reload
movq %rcx, 176(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 168(%rsp)
movq %r12, 160(%rsp)
movl %eax, 60(%rsp)
leaq 176(%rsp), %rax
movq %rax, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 60(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4CompPPiS0_S0_i, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
movq (%r14), %rdi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_38
# %bb.33: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_37: # %._crit_edge93
# in Loop: Header=BB1_34 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_38
.LBB1_34: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_37
# %bb.35: # %.lr.ph92
# in Loop: Header=BB1_34 Depth=1
movq (%r14,%rbx,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq 8(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_36
jmp .LBB1_37
.LBB1_38: # %._crit_edge95
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z21MallocHostDoubleArrayii # -- Begin function _Z21MallocHostDoubleArrayii
.p2align 4, 0x90
.type _Z21MallocHostDoubleArrayii,@function
_Z21MallocHostDoubleArrayii: # @_Z21MallocHostDoubleArrayii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %r15
movslq %esi, %r14
movq %r15, %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
leaq (,%r15,8), %rdi
callq malloc
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
shlq $2, %r14
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, (%rax,%rdx,8)
incq %rdx
addq %r14, %rbx
cmpq %rdx, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21MallocHostDoubleArrayii, .Lfunc_end2-_Z21MallocHostDoubleArrayii
.cfi_endproc
# -- End function
.globl _Z23MallocDeviceDoubleArrayPPiii # -- Begin function _Z23MallocDeviceDoubleArrayPPiii
.p2align 4, 0x90
.type _Z23MallocDeviceDoubleArrayPPiii,@function
_Z23MallocDeviceDoubleArrayPPiii: # @_Z23MallocDeviceDoubleArrayPPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r12
leaq (,%r12,8), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %r15d, %r15
movq %r12, %rsi
imulq %r15, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
movq %rbx, %rdi
callq malloc
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph
movq (%rsp), %rcx
movl %ebp, %edx
shlq $2, %r15
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rsi,8)
incq %rsi
addq %r15, %rcx
cmpq %rsi, %rdx
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq (%rsp), %rcx
movq %rcx, (%r14)
movq 8(%rsp), %rdi
movq %rax, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z23MallocDeviceDoubleArrayPPiii, .Lfunc_end3-_Z23MallocDeviceDoubleArrayPPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4CompPPiS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4CompPPiS0_S0_i,@object # @_Z4CompPPiS0_S0_i
.section .rodata,"a",@progbits
.globl _Z4CompPPiS0_S0_i
.p2align 3, 0x0
_Z4CompPPiS0_S0_i:
.quad _Z19__device_stub__CompPPiS0_S0_i
.size _Z4CompPPiS0_S0_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4CompPPiS0_S0_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\350\277\231\346\230\257\344\270\200\344\270\252\347\237\251\351\230\265\347\233\270\344\271\230\347\232\204\347\250\213\345\272\217"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)"
.size .Lstr.1, 37
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\347\232\204\346\225\260\346\215\256"
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)"
.size .Lstr.3, 37
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\347\232\204\346\225\260\346\215\256"
.size .Lstr.4, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__CompPPiS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4CompPPiS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4CompPPiS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fe200078e0209 */
/*00e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x002fc60000011400 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0209 */
/*0100*/ @!P1 BRA 0x590 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R13, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080d7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ SHF.L.U64.HI R12, R0.reuse, 0x2, R11 ; /* 0x00000002000c7819 */
/* 0x040fe2000001020b */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe20000000000 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ IMAD.SHL.U32 R10, R0, 0x4, RZ ; /* 0x00000004000a7824 */
/* 0x000fe400078e00ff */
/*0190*/ LDG.E.64 R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R16, [R6.64] ; /* 0x0000000606107981 */
/* 0x001f22000c1e1b00 */
/*01c0*/ IADD3 R22, P1, R20, UR5, RZ ; /* 0x0000000514167c10 */
/* 0x004fc4000ff3e0ff */
/*01d0*/ IADD3 R20, P3, R18, R10.reuse, RZ ; /* 0x0000000a12147210 */
/* 0x088fe40007f7e0ff */
/*01e0*/ IADD3.X R23, R21, UR4, RZ, P1, !PT ; /* 0x0000000415177c10 */
/* 0x000fe40008ffe4ff */
/*01f0*/ IADD3 R26, P2, R16, R10, RZ ; /* 0x0000000a101a7210 */
/* 0x010fe20007f5e0ff */
/*0200*/ IMAD.X R21, R19, 0x1, R12, P3 ; /* 0x0000000113157824 */
/* 0x000fc600018e060c */
/*0210*/ LDG.E R23, [R22.64+-0x8] ; /* 0xfffff80616177981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.X R27, R17, 0x1, R12, P2 ; /* 0x00000001111b7824 */
/* 0x000fc600010e060c */
/*0230*/ LDG.E R15, [R20.64] ; /* 0x00000006140f7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IMAD R15, R26, R23, R15 ; /* 0x000000171a0f7224 */
/* 0x004fca00078e020f */
/*0260*/ STG.E [R20.64], R15 ; /* 0x0000000f14007986 */
/* 0x0001e8000c101906 */
/*0270*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000602127981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R24, [R6.64+0x8] ; /* 0x0000080606187981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*02a0*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x004fc4000ff3e0ff */
/*02b0*/ IADD3 R24, P2, R24, R10.reuse, RZ ; /* 0x0000000a18187210 */
/* 0x088fe40007f5e0ff */
/*02c0*/ IADD3 R28, P3, R16, R10, RZ ; /* 0x0000000a101c7210 */
/* 0x010fc60007f7e0ff */
/*02d0*/ IMAD.X R25, R25, 0x1, R12.reuse, P2 ; /* 0x0000000119197824 */
/* 0x100fe200010e060c */
/*02e0*/ IADD3.X R19, R19, UR4, RZ, P1, !PT ; /* 0x0000000413137c10 */
/* 0x000fe20008ffe4ff */
/*02f0*/ IMAD.X R29, R17, 0x1, R12, P3 ; /* 0x00000001111d7824 */
/* 0x000fc600018e060c */
/*0300*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R19, [R18.64+-0x4] ; /* 0xfffffc0612137981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R15, [R28.64] ; /* 0x000000061c0f7981 */
/* 0x001ea4000c1e1900 */
/*0330*/ IMAD R15, R24, R19, R15 ; /* 0x00000013180f7224 */
/* 0x004fca00078e020f */
/*0340*/ STG.E [R28.64], R15 ; /* 0x0000000f1c007986 */
/* 0x0001e8000c101906 */
/*0350*/ LDG.E.64 R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100606167981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*0380*/ IADD3 R20, P1, R20, UR5, RZ ; /* 0x0000000514147c10 */
/* 0x004fc4000ff3e0ff */
/*0390*/ IADD3 R22, P2, R22, R10.reuse, RZ ; /* 0x0000000a16167210 */
/* 0x088fe40007f5e0ff */
/*03a0*/ IADD3 R26, P3, R16, R10, RZ ; /* 0x0000000a101a7210 */
/* 0x010fc60007f7e0ff */
/*03b0*/ IMAD.X R23, R23, 0x1, R12.reuse, P2 ; /* 0x0000000117177824 */
/* 0x100fe200010e060c */
/*03c0*/ IADD3.X R21, R21, UR4, RZ, P1, !PT ; /* 0x0000000415157c10 */
/* 0x000fe20008ffe4ff */
/*03d0*/ IMAD.X R27, R17, 0x1, R12, P3 ; /* 0x00000001111b7824 */
/* 0x000fc600018e060c */
/*03e0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R15, [R26.64] ; /* 0x000000061a0f7981 */
/* 0x001ea4000c1e1900 */
/*0410*/ IMAD R15, R22, R21, R15 ; /* 0x00000015160f7224 */
/* 0x004fca00078e020f */
/*0420*/ STG.E [R26.64], R15 ; /* 0x0000000f1a007986 */
/* 0x0001e8000c101906 */
/*0430*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000602127981 */
/* 0x000ea8000c1e1b00 */
/*0440*/ LDG.E.64 R24, [R6.64+0x18] ; /* 0x0000180606187981 */
/* 0x000ee8000c1e1b00 */
/*0450*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000f22000c1e1b00 */
/*0460*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x004fc4000ff3e0ff */
/*0470*/ IADD3 R24, P2, R24, R10.reuse, RZ ; /* 0x0000000a18187210 */
/* 0x088fe40007f5e0ff */
/*0480*/ IADD3 R16, P3, R16, R10, RZ ; /* 0x0000000a10107210 */
/* 0x010fc60007f7e0ff */
/*0490*/ IMAD.X R25, R25, 0x1, R12.reuse, P2 ; /* 0x0000000119197824 */
/* 0x100fe200010e060c */
/*04a0*/ IADD3.X R19, R19, UR4, RZ, P1, !PT ; /* 0x0000000413137c10 */
/* 0x000fe20008ffe4ff */
/*04b0*/ IMAD.X R17, R17, 0x1, R12, P3 ; /* 0x0000000111117824 */
/* 0x000fc600018e060c */
/*04c0*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R19, [R18.64+0x4] ; /* 0x0000040612137981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R15, [R16.64] ; /* 0x00000006100f7981 */
/* 0x001ea2000c1e1900 */
/*04f0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0510*/ UIADD3 UR5, UP0, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000ff1e03f */
/*0520*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fc60007f5e0ff */
/*0530*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0540*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0560*/ IMAD R15, R24, R19, R15 ; /* 0x00000013180f7224 */
/* 0x004fca00078e020f */
/*0570*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0001e2000c101906 */
/*0580*/ @P1 BRA 0x190 ; /* 0xfffffc0000001947 */
/* 0x000fea000383ffff */
/*0590*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.WIDE R6, R14, R9, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fe200078e0209 */
/*05b0*/ SHF.L.U64.HI R11, R0, 0x2, R11 ; /* 0x00000002000b7819 */
/* 0x000fc6000001020b */
/*05c0*/ IMAD.WIDE R14, R14, 0x4, RZ ; /* 0x000000040e0e7825 */
/* 0x001fc800078e02ff */
/*05d0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*05e0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*05f0*/ IMAD.SHL.U32 R21, R0, 0x4, RZ ; /* 0x0000000400157824 */
/* 0x000fe400078e00ff */
/*0600*/ LDG.E.64 R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000ee8000c1e1b00 */
/*0620*/ LDG.E.64 R14, [R6.64] ; /* 0x00000006060e7981 */
/* 0x000f22000c1e1b00 */
/*0630*/ IADD3 R18, P0, R12, R10, RZ ; /* 0x0000000a0c127210 */
/* 0x004fc40007f1e0ff */
/*0640*/ IADD3 R12, P2, R16, R21, RZ ; /* 0x00000015100c7210 */
/* 0x008fc60007f5e0ff */
/*0650*/ IMAD.X R19, R13, 0x1, R9, P0 ; /* 0x000000010d137824 */
/* 0x000fe200000e0609 */
/*0660*/ IADD3 R14, P1, R14, R21, RZ ; /* 0x000000150e0e7210 */
/* 0x010fe20007f3e0ff */
/*0670*/ IMAD.X R13, R17, 0x1, R11, P2 ; /* 0x00000001110d7824 */
/* 0x000fc800010e060b */
/*0680*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.X R15, R15, 0x1, R11, P1 ; /* 0x000000010f0f7824 */
/* 0x000fc600008e060b */
/*06a0*/ LDG.E R0, [R12.64] ; /* 0x000000060c007981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*06e0*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f3e0ff */
/*06f0*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007f5e0ff */
/*0700*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0710*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0609 */
/*0720*/ IMAD R17, R14, R19, R0 ; /* 0x000000130e117224 */
/* 0x004fca00078e0200 */
/*0730*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0001e2000c101906 */
/*0740*/ @P0 BRA 0x600 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4CompPPiS0_S0_i
.globl _Z4CompPPiS0_S0_i
.p2align 8
.type _Z4CompPPiS0_S0_i,@function
_Z4CompPPiS0_S0_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 3, v1
v_lshlrev_b32_e32 v0, 2, v5
v_lshlrev_b32_e32 v5, 2, v5
s_waitcnt lgkmcnt(0)
global_load_b64 v[1:2], v3, s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v1, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[2:3], v3, s[0:1]
flat_load_b32 v4, v[0:1]
.p2align 6
.LBB0_2:
s_load_b64 s[0:1], s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s0, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, null, s1, 0, s0
s_waitcnt vmcnt(1)
flat_load_b32 v8, v[2:3]
flat_load_b32 v9, v[6:7]
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v6
flat_store_b32 v[0:1], v6
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4CompPPiS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4CompPPiS0_S0_i, .Lfunc_end0-_Z4CompPPiS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4CompPPiS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4CompPPiS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00195337_00000000-6_\347\237\251\351\230\265\347\233\270\344\271\230.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23MallocDeviceDoubleArrayPPiii
.type _Z23MallocDeviceDoubleArrayPPiii, @function
_Z23MallocDeviceDoubleArrayPPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movslq %esi, %r14
leaq 0(,%r14,8), %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbx
salq $2, %rbx
movq %r14, %rsi
imulq %rbx, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rsi
testl %r13d, %r13d
jle .L4
movq 16(%rsp), %rcx
movq %rax, %rdx
leaq 0(%rbp,%rax), %rdi
.L5:
movq %rcx, (%rdx)
addq %rbx, %rcx
addq $8, %rdx
cmpq %rdi, %rdx
jne .L5
.L4:
movq 16(%rsp), %rax
movq %rax, (%r12)
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z23MallocDeviceDoubleArrayPPiii, .-_Z23MallocDeviceDoubleArrayPPiii
.globl _Z21MallocHostDoubleArrayii
.type _Z21MallocHostDoubleArrayii, @function
_Z21MallocHostDoubleArrayii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movslq %edi, %rbp
movslq %esi, %r12
salq $2, %r12
movq %rbp, %rdi
imulq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
testl %r13d, %r13d
jle .L10
movq %rbx, %rcx
movq %rax, %rdx
leaq 0(%rbp,%rax), %rsi
.L12:
movq %rcx, (%rdx)
addq %r12, %rcx
addq $8, %rdx
cmpq %rsi, %rdx
jne .L12
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z21MallocHostDoubleArrayii, .-_Z21MallocHostDoubleArrayii
.globl _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
.type _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i, @function
_Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4CompPPiS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i, .-_Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
.globl _Z4CompPPiS0_S0_i
.type _Z4CompPPiS0_S0_i, @function
_Z4CompPPiS0_S0_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4CompPPiS0_S0_i, .-_Z4CompPPiS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\350\277\231\346\230\257\344\270\200\344\270\252\347\237\251\351\230\265\347\233\270\344\271\230\347\232\204\347\250\213\345\272\217\n"
.align 8
.LC1:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d"
.LC3:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\347\232\204\346\225\260\346\215\256\n"
.LC4:
.string "%d"
.section .rodata.str1.8
.align 8
.LC5:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)\n"
.section .rodata.str1.1
.LC6:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\347\232\204\346\225\260\346\215\256\n"
.LC7:
.string "%d "
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdx
leaq 28(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %esi
movl 24(%rsp), %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 24(%rsp)
jle .L24
movq %r12, %rbp
movl $0, %r14d
leaq .LC4(%rip), %r13
jmp .L25
.L26:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 28(%rsp)
jg .L26
.L27:
addl $1, %r14d
addq $8, %rbp
cmpl %r14d, 24(%rsp)
jle .L24
.L25:
movl $0, %ebx
cmpl $0, 28(%rsp)
jg .L26
jmp .L27
.L24:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq 36(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %esi
movl 32(%rsp), %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %rbp
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L28
movq %rbp, %r13
movl $0, %r15d
leaq .LC4(%rip), %r14
jmp .L29
.L30:
movq 0(%r13), %rax
leaq (%rax,%rbx,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 36(%rsp)
jg .L30
.L31:
addl $1, %r15d
addq $8, %r13
cmpl %r15d, 32(%rsp)
jle .L28
.L29:
movl $0, %ebx
cmpl $0, 36(%rsp)
jg .L30
jmp .L31
.L28:
movl 24(%rsp), %r13d
movl 36(%rsp), %esi
movl %r13d, %edi
call _Z21MallocHostDoubleArrayii
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl 28(%rsp), %edx
movl %r13d, %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, 8(%rsp)
leaq 48(%rsp), %rdi
movl 36(%rsp), %edx
movl 32(%rsp), %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, %r13
leaq 56(%rsp), %rdi
movl 36(%rsp), %edx
movl 24(%rsp), %esi
call _Z23MallocDeviceDoubleArrayPPiii
movq %rax, %r14
movq 56(%rsp), %r15
movl $8, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
movslq 24(%rsp), %rdx
movslq 28(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq (%r12), %rsi
movl $1, %ecx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq 0(%rbp), %rsi
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 72(%rsp)
movl 24(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %eax
movl %eax, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L32:
movslq 24(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movq (%rbx), %rdi
movl $2, %ecx
movq %r15, %rsi
call cudaMemcpy@PLT
cmpl $0, 24(%rsp)
jle .L33
movl $0, %r13d
leaq .LC7(%rip), %r12
leaq .LC8(%rip), %r14
jmp .L34
.L48:
movl 28(%rsp), %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z4CompPPiS0_S0_iPPiS0_S0_i
jmp .L32
.L35:
movq (%rbx), %rax
movl (%rax,%rbp,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpl %ebp, 36(%rsp)
jg .L35
.L36:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $8, %rbx
cmpl %r13d, 24(%rsp)
jle .L33
.L34:
movl $0, %ebp
cmpl $0, 36(%rsp)
jg .L35
jmp .L36
.L33:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4CompPPiS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4CompPPiS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "\347\237\251\351\230\265\347\233\270\344\271\230.hip"
.globl _Z19__device_stub__CompPPiS0_S0_i # -- Begin function _Z19__device_stub__CompPPiS0_S0_i
.p2align 4, 0x90
.type _Z19__device_stub__CompPPiS0_S0_i,@function
_Z19__device_stub__CompPPiS0_S0_i: # @_Z19__device_stub__CompPPiS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4CompPPiS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__CompPPiS0_S0_i, .Lfunc_end0-_Z19__device_stub__CompPPiS0_S0_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r12
movslq 16(%rsp), %r15
movq %r12, %rdi
imulq %r15, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %rbx
testq %r12, %r12
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader.i
movl %r12d, %eax
shlq $2, %r15
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, (%rbx,%rcx,8)
incq %rcx
addq %r15, %r14
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %_Z21MallocHostDoubleArrayii.exit
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_9
# %bb.4: # %.preheader82.preheader
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r15
movslq 12(%rsp), %rax
cmpq %rax, %r15
jge .LBB1_9
.LBB1_5: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
cmpl $0, 16(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
movq (%rbx,%r15,8), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 16(%rsp), %rax
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_7
jmp .LBB1_8
.LBB1_9: # %._crit_edge85
movl $.Lstr.3, %edi
callq puts@PLT
leaq 8(%rsp), %rsi
leaq 20(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 20(%rsp), %r13
movslq 8(%rsp), %r12
movq %r13, %rdi
imulq %r12, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
leaq (,%r13,8), %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader.i40
movl %r13d, %eax
shlq $2, %r12
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph.i42
# =>This Inner Loop Header: Depth=1
movq %r14, (%r15,%rcx,8)
incq %rcx
addq %r12, %r14
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %_Z21MallocHostDoubleArrayii.exit46
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, 20(%rsp)
jle .LBB1_18
# %bb.13: # %.preheader81.preheader
xorl %r12d, %r12d
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_17: # %._crit_edge88
# in Loop: Header=BB1_14 Depth=1
incq %r12
movslq 20(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_18
.LBB1_14: # %.preheader81
# =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.15: # %.lr.ph87
# in Loop: Header=BB1_14 Depth=1
movq (%r15,%r12,8), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_14 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %r13
jl .LBB1_16
jmp .LBB1_17
.LBB1_18: # %._crit_edge90
movq %rbx, 120(%rsp) # 8-byte Spill
movslq 12(%rsp), %rbx
movslq 8(%rsp), %r12
leaq (,%rbx,4), %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
imulq %r12, %rdi
callq malloc
movq %rax, %rbp
leaq (,%rbx,8), %rdi
movq %rdi, 40(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r14
movl %ebx, %r13d
testq %rbx, %rbx
jle .LBB1_21
# %bb.19: # %.lr.ph.preheader.i47
shlq $2, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_20: # %.lr.ph.i49
# =>This Inner Loop Header: Depth=1
movq %rbp, (%r14,%rax,8)
incq %rax
addq %r12, %rbp
cmpq %rax, %r13
jne .LBB1_20
.LBB1_21: # %_Z21MallocHostDoubleArrayii.exit53
movslq 16(%rsp), %r12
leaq 64(%rsp), %rdi
movq 40(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rsi # 8-byte Reload
imulq %r12, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %rbp, %rdi
callq malloc
testl %r13d, %r13d
movq 120(%rsp), %rbx # 8-byte Reload
jle .LBB1_24
# %bb.22: # %.lr.ph.i54
movq 24(%rsp), %rcx
shlq $2, %r12
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rdx,8)
incq %rdx
addq %r12, %rcx
cmpq %rdx, %r13
jne .LBB1_23
.LBB1_24: # %_Z23MallocDeviceDoubleArrayPPiii.exit
movq 24(%rsp), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movslq 20(%rsp), %rbp
movslq 8(%rsp), %r12
leaq (,%rbp,8), %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rbp, %rsi
imulq %r12, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %r13, %rdi
callq malloc
testq %rbp, %rbp
jle .LBB1_27
# %bb.25: # %.lr.ph.i59
movl %ebp, %ecx
movq 24(%rsp), %rdx
shlq $2, %r12
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_26: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq %r12, %rdx
cmpq %rsi, %rcx
jne .LBB1_26
.LBB1_27: # %_Z23MallocDeviceDoubleArrayPPiii.exit64
movq 24(%rsp), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movslq 12(%rsp), %rbp
movslq 8(%rsp), %r13
leaq (,%rbp,8), %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rbp, %rsi
imulq %r13, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq %r12, %rdi
callq malloc
testq %rbp, %rbp
jle .LBB1_30
# %bb.28: # %.lr.ph.i65
movl %ebp, %ecx
movq 24(%rsp), %rdx
shlq $2, %r13
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_29: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq %r13, %rdx
cmpq %rsi, %rcx
jne .LBB1_29
.LBB1_30: # %_Z23MallocDeviceDoubleArrayPPiii.exit70
movq 24(%rsp), %r13
movq 64(%rsp), %rdi
movq %rax, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %r12
movl $8, %edx
movq %r13, %rdi
xorl %esi, %esi
callq hipMemset
movq (%rbx), %rsi
movslq 12(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 48(%rsp), %rdi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq (%r15), %rsi
movslq 20(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl 8(%rsp), %edx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movl 16(%rsp), %eax
movq 112(%rsp), %rcx # 8-byte Reload
movq %rcx, 176(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 168(%rsp)
movq %r12, 160(%rsp)
movl %eax, 60(%rsp)
leaq 176(%rsp), %rax
movq %rax, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 60(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4CompPPiS0_S0_i, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
movq (%r14), %rdi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_38
# %bb.33: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_37: # %._crit_edge93
# in Loop: Header=BB1_34 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_38
.LBB1_34: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_37
# %bb.35: # %.lr.ph92
# in Loop: Header=BB1_34 Depth=1
movq (%r14,%rbx,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq 8(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_36
jmp .LBB1_37
.LBB1_38: # %._crit_edge95
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z21MallocHostDoubleArrayii # -- Begin function _Z21MallocHostDoubleArrayii
.p2align 4, 0x90
.type _Z21MallocHostDoubleArrayii,@function
_Z21MallocHostDoubleArrayii: # @_Z21MallocHostDoubleArrayii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %r15
movslq %esi, %r14
movq %r15, %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
leaq (,%r15,8), %rdi
callq malloc
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
shlq $2, %r14
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, (%rax,%rdx,8)
incq %rdx
addq %r14, %rbx
cmpq %rdx, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21MallocHostDoubleArrayii, .Lfunc_end2-_Z21MallocHostDoubleArrayii
.cfi_endproc
# -- End function
.globl _Z23MallocDeviceDoubleArrayPPiii # -- Begin function _Z23MallocDeviceDoubleArrayPPiii
.p2align 4, 0x90
.type _Z23MallocDeviceDoubleArrayPPiii,@function
_Z23MallocDeviceDoubleArrayPPiii: # @_Z23MallocDeviceDoubleArrayPPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r12
leaq (,%r12,8), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %r15d, %r15
movq %r12, %rsi
imulq %r15, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
movq %rbx, %rdi
callq malloc
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph
movq (%rsp), %rcx
movl %ebp, %edx
shlq $2, %r15
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rsi,8)
incq %rsi
addq %r15, %rcx
cmpq %rsi, %rdx
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq (%rsp), %rcx
movq %rcx, (%r14)
movq 8(%rsp), %rdi
movq %rax, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z23MallocDeviceDoubleArrayPPiii, .Lfunc_end3-_Z23MallocDeviceDoubleArrayPPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4CompPPiS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4CompPPiS0_S0_i,@object # @_Z4CompPPiS0_S0_i
.section .rodata,"a",@progbits
.globl _Z4CompPPiS0_S0_i
.p2align 3, 0x0
_Z4CompPPiS0_S0_i:
.quad _Z19__device_stub__CompPPiS0_S0_i
.size _Z4CompPPiS0_S0_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4CompPPiS0_S0_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\350\277\231\346\230\257\344\270\200\344\270\252\347\237\251\351\230\265\347\233\270\344\271\230\347\232\204\347\250\213\345\272\217"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)"
.size .Lstr.1, 37
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265A\347\232\204\346\225\260\346\215\256"
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\345\244\247\345\260\217(\350\241\214\345\210\227\345\244\247\345\260\217)"
.size .Lstr.3, 37
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265B\347\232\204\346\225\260\346\215\256"
.size .Lstr.4, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__CompPPiS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4CompPPiS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <getopt.h>
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
/* Original permuation code due to D. Jimenez, UT Austin
* http://faculty.cse.tamu.edu/djimenez/ut/utsa/cs3343/
*/
/* Requires C99 compiler (gcc: -std=c99) */
#define ONE_BILLION (double)1000000000.0
#define debug_printf(fmt, ...) do { if (DEBUG) fprintf(stderr, fmt, __VA_ARGS__); } while (0)
/* Action function for each permuation. */
typedef void (*perm_action_t)(int *v, int n);
/* Reference an element in the TSP distance array. */
#define TSP_ELT(tsp, n, i, j) *(tsp + (i * n) + j)
__host__ double
now(void)
{
struct timespec current_time;
clock_gettime(CLOCK_REALTIME, ¤t_time);
return current_time.tv_sec + (current_time.tv_nsec / ONE_BILLION);
}
/* Swap array elements. */
__device__ __host__ void
swap(int *v, int i, int j)
{
int t = v[i];
v[i] = v[j];
v[j] = t;
}
/* Trivial action to pass to permutations--print out each one. */
__device__ void
print_perm(int *perm, int n, char *msge)
{
for (int j = 0; j < n; j++) {
printf("%2d ", perm[j]);
}
printf(" - %s\n", msge);
}
__host__ void
smallest_in_list(int *list, int *num_short, int n, int *shortest_length, int *num_as_short)
{
int min_path = INT_MAX;
int num = 0;
for (int j = 0; j < n; j++) {
int tmp = list[j];
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num += num_short[j];
}
}
*shortest_length = min_path;
*num_as_short = num;
}
/* Create an instance of a symmetric TSP. */
__host__ int *
create_tsp(int n, int random_seed)
{
int *tsp = (int *) malloc(n * n * sizeof(int));
srandom(random_seed);
for (int i = 0; i < n; i++) {
for (int j = 0; j <= i; j++) {
int val = (int)(random() / (RAND_MAX / 100));
TSP_ELT(tsp, n, i, j) = val;
TSP_ELT(tsp, n, j, i) = val;
}
}
return tsp;
}
/* Print a TSP distance matrix. */
__host__ __device__ void
print_tsp(int *tsp, int n)
{
// printf("TSP (%d cities - seed %d)\n ", n, random_seed);
for (int j = 0; j < n; j++) {
printf("%3d|", j);
}
printf("\n");
for (int i = 0; i < n; i++) {
printf("%2d|", i);
for (int j = 0; j < n; j++) {
printf("%4d", TSP_ELT(tsp, n, i, j));
}
printf("\n");
}
printf("\n");
}
/* Evaluate a single instance of the TSP. */
__device__ int
eval_tsp(int *perm, int n, int* distances)
{
/* Calculate the length of the tour for the current permutation. */
int total = 0;
for (int i = 0; i < n; i++) {
int j = (i + 1) % n;
int from = perm[i];
int to = perm[j];
int val = TSP_ELT(distances, n, from, to);
total += val;
}
return total;
}
/**** List ADT ****************/
typedef struct {
int *values; /* Values stored in list */
int max_size; /* Maximum size allocated */
int cur_size; /* Size currently in use */
} list_t;
/* Dump list, including sizes */
__device__ void
list_dump(list_t *list)
{
printf("%2d/%2d", list->cur_size, list->max_size);
for (int i = 0; i < list->cur_size; i++) {
printf(" %d", list->values[i]);
}
printf("\n");
}
/* Allocate list that can store up to 'max_size' elements */
__device__ list_t *
list_alloc(int max_size)
{
list_t *list = (list_t *)malloc(sizeof(list_t));
list->values = (int *)malloc(max_size * sizeof(int));
list->max_size = max_size;
list->cur_size = 0;
return list;
}
/* Free a list; call this to avoid leaking memory! */
__device__ void
list_free(list_t *list)
{
free(list->values);
free(list);
}
/* Add a value to the end of the list */
__device__ void
list_add(list_t *list, int value)
{
if (list->cur_size >= list->max_size) {
printf("List full");
list_dump(list);
// exit(1);
}
list->values[list->cur_size++] = value;
}
/* Return the current size of the list */
__device__ int
list_size(list_t *list)
{
return list->cur_size;
}
/* Validate index */
__device__ void
_list_check_index(list_t *list, int index)
{
if (index < 0 || index > list->cur_size - 1) {
printf("Invalid index %d\n", index);
list_dump(list);
// exit(1);
}
}
/* Get the value at given index */
__device__ int
list_get(list_t *list, int index)
{
_list_check_index(list, index);
return list->values[index];
}
/* Remove the value at the given index */
__device__ void
list_remove_at(list_t *list, int index)
{
_list_check_index(list, index);
for (int i = index; i < list->cur_size - 1; i++) {
list->values[i] = list->values[i + 1];
}
list->cur_size--;
}
/* Retrieve a copy of the values as a simple array of integers. The returned
array is allocated dynamically; the caller must free the space when no
longer needed.
*/
__device__ int *
list_as_array(list_t *list)
{
int *rtn = (int *)malloc(list->max_size * sizeof(int));
for (int i = 0; i < list->max_size; i++) {
rtn[i] = list_get(list, i);
}
return rtn;
}
/**** Permutation ****************/
/* Permutation algorithms based on code found at:
http://www.mathblog.dk/project-euler-24-millionth-lexicographic-permutation/
which references:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
/* Calculate n! iteratively */
__device__ __host__ long
factorial(int n)
{
if (n < 1) {
return 0;
}
long rtn = 1;
for (int i = 1; i <= n; i++) {
rtn *= i;
}
return rtn;
}
/* Return the kth lexographically ordered permuation of an array of k integers
in the range [0 .. size - 1]. The integers are allocated dynamically and
should be free'd by the caller when no longer needed.
*/
__device__ int *
kth_perm(int k, int size)
{
long remain = k - 1;
list_t *numbers = list_alloc(size);
for (int i = 0; i < size; i++) {
list_add(numbers, i);
}
list_t *perm = list_alloc(size);
for (int i = 1; i < size; i++) {
long f = factorial(size - i);
long j = remain / f;
remain = remain % f;
list_add(perm, list_get(numbers, j));
list_remove_at(numbers, j);
if (remain == 0) {
break;
}
}
/* Append remaining digits */
for (int i = 0; i < list_size(numbers); i++) {
list_add(perm, list_get(numbers, i));
}
int *rtn = list_as_array(perm);
list_free(perm);
return rtn;
}
/* Given an array of size elements at perm, update the array in place to
contain the lexographically next permutation. It is originally due to
Dijkstra. The present version is discussed at:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
__device__ void
next_perm(int *perm, int size)
{
int i = size - 1;
while (perm[i - 1] >= perm[i]) {
i = i - 1;
}
int j = size;
while (perm[j - 1] <= perm[i - 1]) {
j = j - 1;
}
swap(perm, i - 1, j - 1);
i++;
j = size;
while (i < j) {
swap(perm, i - 1, j - 1);
i++;
j--;
}
}
__global__
void tsp_go(int* perm, int num_cities, int num_threads, int* cperm, int* output, int* num_as_short){
long one_index = threadIdx.x + 1;
long cur_idx = (factorial(num_cities)/num_threads) * (threadIdx.x)+1;
long end_idx = (factorial(num_cities)/num_threads) * (one_index);
int min_path = INT_MAX;
int num = 0;
__syncthreads();
perm = kth_perm(cur_idx, num_cities);
while( cur_idx <= end_idx){
// printf("Hello from %d, end_idx: %ld, cur_idx: %ld, perms: %ld\n", threadIdx.x, end_idx, cur_idx, factorial(num_cities));
int tmp = eval_tsp(perm, num_cities, cperm);
// printf("Hello from %d, cost: %d\n", threadIdx.x, tmp);
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num++;
}
cur_idx++;
// MAKING SURE NOT OUT OF RANGE
if( cur_idx <= end_idx){
next_perm(perm, num_cities);
}
// __syncthreads();
}
__syncthreads();
output[threadIdx.x] = min_path;
num_as_short[threadIdx.x] = num;
}
void
usage(char *prog_name)
{
fprintf(stderr, "usage: %s [flags]\n", prog_name);
fprintf(stderr, " -h\n");
fprintf(stderr, " -c <number of cities>\n");
fprintf(stderr, " -s <random seed>\n");
exit(1);
}
int
main(int argc, char **argv)
{
int num_cities = 5;
int shortest_length;
int num_as_short = -1;
long num_trials = 0;
int num_threads = 1;
int random_seed = 42;
/* Use "random" random seed by default. */
random_seed = time(NULL);
int ch;
while ((ch = getopt(argc, argv, "c:hn:s:")) != -1) {
switch (ch) {
case 'c':
num_cities = atoi(optarg);
break;
case 'n':
num_threads = atoi(optarg);
if(num_threads < 1){
usage(argv[0]);
}
break;
case 's':
random_seed = atoi(optarg);
break;
case 'h':
default:
usage(argv[0]);
}
}
num_trials = factorial(num_cities);
if(num_trials < num_threads){
num_threads = num_trials;
}
double start_time = now();
// cost array
int* h_cperm = create_tsp(num_cities, random_seed);
// print_tsp(h_cperm, num_cities);
int* d_cperm;
// output Array
int h_output[num_threads];
int* d_output;
// perm array
int *d_perm;
// num_as_short array
int h_num_short[num_threads];
int *d_num_short;
cudaMalloc((void **)&d_perm, sizeof(int)*num_cities);
cudaMalloc((void **)&d_cperm, sizeof(int)*num_cities*num_cities);
cudaMalloc((void **)&d_output, sizeof(int)*num_threads);
cudaMalloc((void **)&d_num_short, sizeof(int)*num_threads);
cudaMemcpy(d_cperm, h_cperm, sizeof(int)*num_cities*num_cities, cudaMemcpyHostToDevice);
/* "Travel, salesman!" */
tsp_go<<<1, num_threads>>>(d_perm, num_cities, num_threads, d_cperm, d_output, d_num_short);
cudaDeviceSynchronize();
// collect results
cudaMemcpy(h_output, d_output, num_threads * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(h_num_short, d_num_short, num_threads * sizeof(int), cudaMemcpyDeviceToHost);
smallest_in_list(h_output, h_num_short, num_threads, &shortest_length, &num_as_short);
double time_took = now() - start_time;
FILE *f = fopen("time.txt", "a");
fprintf(f, "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n", num_threads, time_took, num_cities, random_seed, shortest_length);
fclose(f);
/* Report. */
printf("\n");
printf("Trials %ld\n", num_trials);
float percent_as_short = (float)num_as_short / (float)num_trials * 100.0;
printf("Shortest %d - %d tours - %.6f%%\n",
shortest_length, num_as_short, percent_as_short);
printf("\n");
free(h_cperm);
// free(h_output);
cudaFree(d_perm);
cudaFree(d_cperm);
cudaFree(d_output);
} | .file "tmpxft_0013b443_00000000-6_parallel-tsp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3nowv
.type _Z3nowv, @function
_Z3nowv:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z3nowv, .-_Z3nowv
.globl _Z4swapPiii
.type _Z4swapPiii, @function
_Z4swapPiii:
.LFB2071:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl (%rcx), %esi
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %rax
movl (%rax), %edx
movl %edx, (%rcx)
movl %esi, (%rax)
ret
.cfi_endproc
.LFE2071:
.size _Z4swapPiii, .-_Z4swapPiii
.globl _Z10print_permPiiPc
.type _Z10print_permPiiPc, @function
_Z10print_permPiiPc:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z10print_permPiiPc, .-_Z10print_permPiiPc
.globl _Z16smallest_in_listPiS_iS_S_
.type _Z16smallest_in_listPiS_iS_S_, @function
_Z16smallest_in_listPiS_iS_S_:
.LFB2073:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L15
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movq %rsi, %r11
movslq %edx, %rdx
leaq 0(,%rdx,4), %rdi
movl $0, %eax
movl $0, %r9d
movl $2147483647, %esi
movl $0, %ebx
jmp .L14
.L24:
je .L22
.L13:
addq $4, %rax
cmpq %rdi, %rax
je .L23
.L14:
movl (%r10,%rax), %edx
cmpl %esi, %edx
jge .L24
movl %ebx, %r9d
.L12:
addl (%r11,%rax), %r9d
movl %edx, %esi
jmp .L13
.L22:
movl %esi, %edx
jmp .L12
.L15:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r9d
movl $2147483647, %esi
movl %esi, (%rcx)
movl %r9d, (%r8)
ret
.L23:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, (%rcx)
movl %r9d, (%r8)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z16smallest_in_listPiS_iS_S_, .-_Z16smallest_in_listPiS_iS_S_
.globl _Z10create_tspii
.type _Z10create_tspii, @function
_Z10create_tspii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r14d
movl %edi, 20(%rsp)
movl %esi, %ebx
imull %edi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl %ebx, %edi
call srandom@PLT
testl %r14d, %r14d
jle .L25
movslq %r14d, %rax
movq %rax, 24(%rsp)
leaq 0(,%rax,4), %r15
movl $0, 16(%rsp)
movq $0, (%rsp)
movabsq $-4035224944001410015, %r14
.L27:
movq (%rsp), %rax
movl %eax, %r12d
testl %eax, %eax
js .L34
movq 8(%rsp), %rsi
movq (%rsp), %rax
leaq (%rsi,%rax,4), %rbp
movslq 16(%rsp), %rax
leaq (%rsi,%rax,4), %r13
movl $0, %ebx
.L28:
call random@PLT
movq %rax, %rcx
imulq %r14
addq %rcx, %rdx
sarq $24, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movl %edx, 0(%r13,%rbx,4)
movl %edx, 0(%rbp)
addq $1, %rbx
addq %r15, %rbp
cmpl %ebx, %r12d
jge .L28
addq $1, (%rsp)
movq (%rsp), %rax
movl 20(%rsp), %esi
addl %esi, 16(%rsp)
movq 24(%rsp), %rdi
cmpq %rdi, %rax
jne .L27
.L25:
movq 8(%rsp), %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addq $1, (%rsp)
movl 20(%rsp), %edi
addl %edi, 16(%rsp)
jmp .L27
.cfi_endproc
.LFE2074:
.size _Z10create_tspii, .-_Z10create_tspii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%3d|"
.LC2:
.string "\n"
.LC3:
.string "%2d|"
.LC4:
.string "%4d"
.text
.globl _Z9print_tspPii
.type _Z9print_tspPii, @function
_Z9print_tspPii:
.LFB2075:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
testl %esi, %esi
jle .L36
movl %esi, %ebx
movl $0, %r13d
leaq .LC1(%rip), %rbp
.L37:
movl %r13d, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 12(%rsp)
addl $1, %r13d
cmpl %r13d, %ebx
jne .L37
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %r13
leaq 0(,%r13,4), %rax
movq %rax, 24(%rsp)
movq 16(%rsp), %rcx
leaq (%rcx,%rax), %rbp
movl $0, %r15d
movl $0, %r14d
leaq .LC4(%rip), %r12
jmp .L39
.L41:
movl %eax, %r14d
.L39:
movl %r14d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
leaq (%rax,%r15,4), %rbx
.L38:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L38
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %eax
addq %r13, %r15
movq 24(%rsp), %rcx
addq %rcx, %rbp
cmpl %r14d, 12(%rsp)
jne .L41
.L40:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.cfi_endproc
.LFE2075:
.size _Z9print_tspPii, .-_Z9print_tspPii
.globl _Z8eval_tspPiiS_
.type _Z8eval_tspPiiS_, @function
_Z8eval_tspPiiS_:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z8eval_tspPiiS_, .-_Z8eval_tspPiiS_
.globl _Z9list_dumpP6list_t
.type _Z9list_dumpP6list_t, @function
_Z9list_dumpP6list_t:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Z9list_dumpP6list_t, .-_Z9list_dumpP6list_t
.globl _Z10list_alloci
.type _Z10list_alloci, @function
_Z10list_alloci:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Z10list_alloci, .-_Z10list_alloci
.globl _Z9list_freeP6list_t
.type _Z9list_freeP6list_t, @function
_Z9list_freeP6list_t:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z9list_freeP6list_t, .-_Z9list_freeP6list_t
.globl _Z8list_addP6list_ti
.type _Z8list_addP6list_ti, @function
_Z8list_addP6list_ti:
.LFB2080:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z8list_addP6list_ti, .-_Z8list_addP6list_ti
.globl _Z9list_sizeP6list_t
.type _Z9list_sizeP6list_t, @function
_Z9list_sizeP6list_t:
.LFB2081:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2081:
.size _Z9list_sizeP6list_t, .-_Z9list_sizeP6list_t
.globl _Z17_list_check_indexP6list_ti
.type _Z17_list_check_indexP6list_ti, @function
_Z17_list_check_indexP6list_ti:
.LFB2082:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2082:
.size _Z17_list_check_indexP6list_ti, .-_Z17_list_check_indexP6list_ti
.globl _Z8list_getP6list_ti
.type _Z8list_getP6list_ti, @function
_Z8list_getP6list_ti:
.LFB2083:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size _Z8list_getP6list_ti, .-_Z8list_getP6list_ti
.globl _Z14list_remove_atP6list_ti
.type _Z14list_remove_atP6list_ti, @function
_Z14list_remove_atP6list_ti:
.LFB2084:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2084:
.size _Z14list_remove_atP6list_ti, .-_Z14list_remove_atP6list_ti
.globl _Z13list_as_arrayP6list_t
.type _Z13list_as_arrayP6list_t, @function
_Z13list_as_arrayP6list_t:
.LFB2085:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2085:
.size _Z13list_as_arrayP6list_t, .-_Z13list_as_arrayP6list_t
.globl _Z9factoriali
.type _Z9factoriali, @function
_Z9factoriali:
.LFB2086:
.cfi_startproc
endbr64
movl $0, %edx
testl %edi, %edi
jle .L66
leal 1(%rdi), %ecx
movl $1, %eax
movl $1, %edx
.L68:
imulq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rax
jne .L68
.L66:
movq %rdx, %rax
ret
.cfi_endproc
.LFE2086:
.size _Z9factoriali, .-_Z9factoriali
.globl _Z8kth_permii
.type _Z8kth_permii, @function
_Z8kth_permii:
.LFB2087:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2087:
.size _Z8kth_permii, .-_Z8kth_permii
.globl _Z9next_permPii
.type _Z9next_permPii, @function
_Z9next_permPii:
.LFB2088:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2088:
.size _Z9next_permPii, .-_Z9next_permPii
.section .rodata.str1.1
.LC5:
.string "usage: %s [flags]\n"
.LC6:
.string " -h\n"
.LC7:
.string " -c <number of cities>\n"
.LC8:
.string " -s <random seed>\n"
.text
.globl _Z5usagePc
.type _Z5usagePc, @function
_Z5usagePc:
.LFB2089:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2089:
.size _Z5usagePc, .-_Z5usagePc
.globl _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.type _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_, @function
_Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_:
.LFB2115:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6tsp_goPiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2115:
.size _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_, .-_Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.globl _Z6tsp_goPiiiS_S_S_
.type _Z6tsp_goPiiiS_S_S_, @function
_Z6tsp_goPiiiS_S_S_:
.LFB2116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2116:
.size _Z6tsp_goPiiiS_S_S_, .-_Z6tsp_goPiiiS_S_S_
.section .rodata.str1.1
.LC9:
.string "c:hn:s:"
.LC10:
.string "a"
.LC11:
.string "time.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC12:
.string "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n"
.section .rodata.str1.1
.LC13:
.string "Trials %ld\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Shortest %d - %d tours - %.6f%%\n"
.text
.globl main
.type main, @function
main:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, %r13d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $-1, -116(%rbp)
movl $0, %edi
call time@PLT
movl %eax, -132(%rbp)
movl $1, %r15d
movl $5, %ebx
leaq .LC9(%rip), %r14
jmp .L86
.L87:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
testl %eax, %eax
jg .L86
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
movq (%r12), %rdi
call _Z5usagePc
.L104:
call __stack_chk_fail@PLT
.L88:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, -132(%rbp)
.L86:
movq %r14, %rdx
movq %r12, %rsi
movl %r13d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L105
cmpl $110, %eax
je .L87
cmpl $115, %eax
je .L88
cmpl $99, %eax
jne .L89
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L86
.L89:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L106
movq (%r12), %rdi
call _Z5usagePc
.L106:
call __stack_chk_fail@PLT
.L105:
movl %ebx, %edi
call _Z9factoriali
movq %rax, %r14
movslq %r15d, %rax
cmpq %r14, %rax
cmovg %r14d, %r15d
call _Z3nowv
movsd %xmm0, -152(%rbp)
movl -132(%rbp), %esi
movl %ebx, %edi
call _Z10create_tspii
movq %rax, -144(%rbp)
movslq %r15d, %r12
salq $2, %r12
leaq 15(%r12), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L95:
cmpq %rdx, %rsp
je .L96
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L95
.L96:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L97
orq $0, -8(%rsp,%rax)
.L97:
movq %rsp, %r13
leaq 15(%r12), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L98:
cmpq %rdx, %rsp
je .L99
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L98
.L99:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L100
orq $0, -8(%rsp,%rax)
.L100:
movq %rsp, -160(%rbp)
movslq %ebx, %rax
movq %rax, -168(%rbp)
leaq 0(,%rax,4), %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
movq -168(%rbp), %rax
imulq %rax, %rax
salq $2, %rax
leaq -112(%rbp), %rdi
movq %rax, -168(%rbp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq -168(%rbp), %rdx
movq -144(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl %r15d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L101
movq -88(%rbp), %r9
movq -104(%rbp), %r8
movq -112(%rbp), %rcx
movl %r15d, %edx
movl %ebx, %esi
movq -96(%rbp), %rdi
call _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.L101:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq -104(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq -88(%rbp), %rsi
movq -160(%rbp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
leaq -68(%rbp), %rcx
leaq -116(%rbp), %r8
movl %r15d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z16smallest_in_listPiS_iS_S_
call _Z3nowv
subsd -152(%rbp), %xmm0
movsd %xmm0, -152(%rbp)
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl -68(%rbp), %r13d
subq $8, %rsp
pushq %r13
movl -132(%rbp), %r9d
movl %ebx, %r8d
movsd -152(%rbp), %xmm0
movl %r15d, %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $16, %rsp
movq %r12, %rdi
call fclose@PLT
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -116(%rbp), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r14, %xmm1
divss %xmm1, %xmm0
mulss .LC14(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r13d, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -144(%rbp), %rdi
call free@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L107
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L107:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6tsp_goPiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2118:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6tsp_goPiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2118:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC14:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <getopt.h>
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
/* Original permuation code due to D. Jimenez, UT Austin
* http://faculty.cse.tamu.edu/djimenez/ut/utsa/cs3343/
*/
/* Requires C99 compiler (gcc: -std=c99) */
#define ONE_BILLION (double)1000000000.0
#define debug_printf(fmt, ...) do { if (DEBUG) fprintf(stderr, fmt, __VA_ARGS__); } while (0)
/* Action function for each permuation. */
typedef void (*perm_action_t)(int *v, int n);
/* Reference an element in the TSP distance array. */
#define TSP_ELT(tsp, n, i, j) *(tsp + (i * n) + j)
__host__ double
now(void)
{
struct timespec current_time;
clock_gettime(CLOCK_REALTIME, ¤t_time);
return current_time.tv_sec + (current_time.tv_nsec / ONE_BILLION);
}
/* Swap array elements. */
__device__ __host__ void
swap(int *v, int i, int j)
{
int t = v[i];
v[i] = v[j];
v[j] = t;
}
/* Trivial action to pass to permutations--print out each one. */
__device__ void
print_perm(int *perm, int n, char *msge)
{
for (int j = 0; j < n; j++) {
printf("%2d ", perm[j]);
}
printf(" - %s\n", msge);
}
__host__ void
smallest_in_list(int *list, int *num_short, int n, int *shortest_length, int *num_as_short)
{
int min_path = INT_MAX;
int num = 0;
for (int j = 0; j < n; j++) {
int tmp = list[j];
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num += num_short[j];
}
}
*shortest_length = min_path;
*num_as_short = num;
}
/* Create an instance of a symmetric TSP. */
__host__ int *
create_tsp(int n, int random_seed)
{
int *tsp = (int *) malloc(n * n * sizeof(int));
srandom(random_seed);
for (int i = 0; i < n; i++) {
for (int j = 0; j <= i; j++) {
int val = (int)(random() / (RAND_MAX / 100));
TSP_ELT(tsp, n, i, j) = val;
TSP_ELT(tsp, n, j, i) = val;
}
}
return tsp;
}
/* Print a TSP distance matrix. */
__host__ __device__ void
print_tsp(int *tsp, int n)
{
// printf("TSP (%d cities - seed %d)\n ", n, random_seed);
for (int j = 0; j < n; j++) {
printf("%3d|", j);
}
printf("\n");
for (int i = 0; i < n; i++) {
printf("%2d|", i);
for (int j = 0; j < n; j++) {
printf("%4d", TSP_ELT(tsp, n, i, j));
}
printf("\n");
}
printf("\n");
}
/* Evaluate a single instance of the TSP. */
__device__ int
eval_tsp(int *perm, int n, int* distances)
{
/* Calculate the length of the tour for the current permutation. */
int total = 0;
for (int i = 0; i < n; i++) {
int j = (i + 1) % n;
int from = perm[i];
int to = perm[j];
int val = TSP_ELT(distances, n, from, to);
total += val;
}
return total;
}
/**** List ADT ****************/
typedef struct {
int *values; /* Values stored in list */
int max_size; /* Maximum size allocated */
int cur_size; /* Size currently in use */
} list_t;
/* Dump list, including sizes */
__device__ void
list_dump(list_t *list)
{
printf("%2d/%2d", list->cur_size, list->max_size);
for (int i = 0; i < list->cur_size; i++) {
printf(" %d", list->values[i]);
}
printf("\n");
}
/* Allocate list that can store up to 'max_size' elements */
__device__ list_t *
list_alloc(int max_size)
{
list_t *list = (list_t *)malloc(sizeof(list_t));
list->values = (int *)malloc(max_size * sizeof(int));
list->max_size = max_size;
list->cur_size = 0;
return list;
}
/* Free a list; call this to avoid leaking memory! */
__device__ void
list_free(list_t *list)
{
free(list->values);
free(list);
}
/* Add a value to the end of the list */
__device__ void
list_add(list_t *list, int value)
{
if (list->cur_size >= list->max_size) {
printf("List full");
list_dump(list);
// exit(1);
}
list->values[list->cur_size++] = value;
}
/* Return the current size of the list */
__device__ int
list_size(list_t *list)
{
return list->cur_size;
}
/* Validate index */
__device__ void
_list_check_index(list_t *list, int index)
{
if (index < 0 || index > list->cur_size - 1) {
printf("Invalid index %d\n", index);
list_dump(list);
// exit(1);
}
}
/* Get the value at given index */
__device__ int
list_get(list_t *list, int index)
{
_list_check_index(list, index);
return list->values[index];
}
/* Remove the value at the given index */
__device__ void
list_remove_at(list_t *list, int index)
{
_list_check_index(list, index);
for (int i = index; i < list->cur_size - 1; i++) {
list->values[i] = list->values[i + 1];
}
list->cur_size--;
}
/* Retrieve a copy of the values as a simple array of integers. The returned
array is allocated dynamically; the caller must free the space when no
longer needed.
*/
__device__ int *
list_as_array(list_t *list)
{
int *rtn = (int *)malloc(list->max_size * sizeof(int));
for (int i = 0; i < list->max_size; i++) {
rtn[i] = list_get(list, i);
}
return rtn;
}
/**** Permutation ****************/
/* Permutation algorithms based on code found at:
http://www.mathblog.dk/project-euler-24-millionth-lexicographic-permutation/
which references:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
/* Calculate n! iteratively */
__device__ __host__ long
factorial(int n)
{
if (n < 1) {
return 0;
}
long rtn = 1;
for (int i = 1; i <= n; i++) {
rtn *= i;
}
return rtn;
}
/* Return the kth lexographically ordered permuation of an array of k integers
in the range [0 .. size - 1]. The integers are allocated dynamically and
should be free'd by the caller when no longer needed.
*/
__device__ int *
kth_perm(int k, int size)
{
long remain = k - 1;
list_t *numbers = list_alloc(size);
for (int i = 0; i < size; i++) {
list_add(numbers, i);
}
list_t *perm = list_alloc(size);
for (int i = 1; i < size; i++) {
long f = factorial(size - i);
long j = remain / f;
remain = remain % f;
list_add(perm, list_get(numbers, j));
list_remove_at(numbers, j);
if (remain == 0) {
break;
}
}
/* Append remaining digits */
for (int i = 0; i < list_size(numbers); i++) {
list_add(perm, list_get(numbers, i));
}
int *rtn = list_as_array(perm);
list_free(perm);
return rtn;
}
/* Given an array of size elements at perm, update the array in place to
contain the lexographically next permutation. It is originally due to
Dijkstra. The present version is discussed at:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
__device__ void
next_perm(int *perm, int size)
{
int i = size - 1;
while (perm[i - 1] >= perm[i]) {
i = i - 1;
}
int j = size;
while (perm[j - 1] <= perm[i - 1]) {
j = j - 1;
}
swap(perm, i - 1, j - 1);
i++;
j = size;
while (i < j) {
swap(perm, i - 1, j - 1);
i++;
j--;
}
}
__global__
void tsp_go(int* perm, int num_cities, int num_threads, int* cperm, int* output, int* num_as_short){
long one_index = threadIdx.x + 1;
long cur_idx = (factorial(num_cities)/num_threads) * (threadIdx.x)+1;
long end_idx = (factorial(num_cities)/num_threads) * (one_index);
int min_path = INT_MAX;
int num = 0;
__syncthreads();
perm = kth_perm(cur_idx, num_cities);
while( cur_idx <= end_idx){
// printf("Hello from %d, end_idx: %ld, cur_idx: %ld, perms: %ld\n", threadIdx.x, end_idx, cur_idx, factorial(num_cities));
int tmp = eval_tsp(perm, num_cities, cperm);
// printf("Hello from %d, cost: %d\n", threadIdx.x, tmp);
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num++;
}
cur_idx++;
// MAKING SURE NOT OUT OF RANGE
if( cur_idx <= end_idx){
next_perm(perm, num_cities);
}
// __syncthreads();
}
__syncthreads();
output[threadIdx.x] = min_path;
num_as_short[threadIdx.x] = num;
}
void
usage(char *prog_name)
{
fprintf(stderr, "usage: %s [flags]\n", prog_name);
fprintf(stderr, " -h\n");
fprintf(stderr, " -c <number of cities>\n");
fprintf(stderr, " -s <random seed>\n");
exit(1);
}
int
main(int argc, char **argv)
{
int num_cities = 5;
int shortest_length;
int num_as_short = -1;
long num_trials = 0;
int num_threads = 1;
int random_seed = 42;
/* Use "random" random seed by default. */
random_seed = time(NULL);
int ch;
while ((ch = getopt(argc, argv, "c:hn:s:")) != -1) {
switch (ch) {
case 'c':
num_cities = atoi(optarg);
break;
case 'n':
num_threads = atoi(optarg);
if(num_threads < 1){
usage(argv[0]);
}
break;
case 's':
random_seed = atoi(optarg);
break;
case 'h':
default:
usage(argv[0]);
}
}
num_trials = factorial(num_cities);
if(num_trials < num_threads){
num_threads = num_trials;
}
double start_time = now();
// cost array
int* h_cperm = create_tsp(num_cities, random_seed);
// print_tsp(h_cperm, num_cities);
int* d_cperm;
// output Array
int h_output[num_threads];
int* d_output;
// perm array
int *d_perm;
// num_as_short array
int h_num_short[num_threads];
int *d_num_short;
cudaMalloc((void **)&d_perm, sizeof(int)*num_cities);
cudaMalloc((void **)&d_cperm, sizeof(int)*num_cities*num_cities);
cudaMalloc((void **)&d_output, sizeof(int)*num_threads);
cudaMalloc((void **)&d_num_short, sizeof(int)*num_threads);
cudaMemcpy(d_cperm, h_cperm, sizeof(int)*num_cities*num_cities, cudaMemcpyHostToDevice);
/* "Travel, salesman!" */
tsp_go<<<1, num_threads>>>(d_perm, num_cities, num_threads, d_cperm, d_output, d_num_short);
cudaDeviceSynchronize();
// collect results
cudaMemcpy(h_output, d_output, num_threads * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(h_num_short, d_num_short, num_threads * sizeof(int), cudaMemcpyDeviceToHost);
smallest_in_list(h_output, h_num_short, num_threads, &shortest_length, &num_as_short);
double time_took = now() - start_time;
FILE *f = fopen("time.txt", "a");
fprintf(f, "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n", num_threads, time_took, num_cities, random_seed, shortest_length);
fclose(f);
/* Report. */
printf("\n");
printf("Trials %ld\n", num_trials);
float percent_as_short = (float)num_as_short / (float)num_trials * 100.0;
printf("Shortest %d - %d tours - %.6f%%\n",
shortest_length, num_as_short, percent_as_short);
printf("\n");
free(h_cperm);
// free(h_output);
cudaFree(d_perm);
cudaFree(d_cperm);
cudaFree(d_output);
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <getopt.h>
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
/* Original permuation code due to D. Jimenez, UT Austin
* http://faculty.cse.tamu.edu/djimenez/ut/utsa/cs3343/
*/
/* Requires C99 compiler (gcc: -std=c99) */
#define ONE_BILLION (double)1000000000.0
#define debug_printf(fmt, ...) do { if (DEBUG) fprintf(stderr, fmt, __VA_ARGS__); } while (0)
/* Action function for each permuation. */
typedef void (*perm_action_t)(int *v, int n);
/* Reference an element in the TSP distance array. */
#define TSP_ELT(tsp, n, i, j) *(tsp + (i * n) + j)
__host__ double
now(void)
{
struct timespec current_time;
clock_gettime(CLOCK_REALTIME, ¤t_time);
return current_time.tv_sec + (current_time.tv_nsec / ONE_BILLION);
}
/* Swap array elements. */
__device__ __host__ void
swap(int *v, int i, int j)
{
int t = v[i];
v[i] = v[j];
v[j] = t;
}
/* Trivial action to pass to permutations--print out each one. */
__device__ void
print_perm(int *perm, int n, char *msge)
{
for (int j = 0; j < n; j++) {
printf("%2d ", perm[j]);
}
printf(" - %s\n", msge);
}
__host__ void
smallest_in_list(int *list, int *num_short, int n, int *shortest_length, int *num_as_short)
{
int min_path = INT_MAX;
int num = 0;
for (int j = 0; j < n; j++) {
int tmp = list[j];
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num += num_short[j];
}
}
*shortest_length = min_path;
*num_as_short = num;
}
/* Create an instance of a symmetric TSP. */
__host__ int *
create_tsp(int n, int random_seed)
{
int *tsp = (int *) malloc(n * n * sizeof(int));
srandom(random_seed);
for (int i = 0; i < n; i++) {
for (int j = 0; j <= i; j++) {
int val = (int)(random() / (RAND_MAX / 100));
TSP_ELT(tsp, n, i, j) = val;
TSP_ELT(tsp, n, j, i) = val;
}
}
return tsp;
}
/* Print a TSP distance matrix. */
__host__ __device__ void
print_tsp(int *tsp, int n)
{
// printf("TSP (%d cities - seed %d)\n ", n, random_seed);
for (int j = 0; j < n; j++) {
printf("%3d|", j);
}
printf("\n");
for (int i = 0; i < n; i++) {
printf("%2d|", i);
for (int j = 0; j < n; j++) {
printf("%4d", TSP_ELT(tsp, n, i, j));
}
printf("\n");
}
printf("\n");
}
/* Evaluate a single instance of the TSP. */
__device__ int
eval_tsp(int *perm, int n, int* distances)
{
/* Calculate the length of the tour for the current permutation. */
int total = 0;
for (int i = 0; i < n; i++) {
int j = (i + 1) % n;
int from = perm[i];
int to = perm[j];
int val = TSP_ELT(distances, n, from, to);
total += val;
}
return total;
}
/**** List ADT ****************/
typedef struct {
int *values; /* Values stored in list */
int max_size; /* Maximum size allocated */
int cur_size; /* Size currently in use */
} list_t;
/* Dump list, including sizes */
__device__ void
list_dump(list_t *list)
{
printf("%2d/%2d", list->cur_size, list->max_size);
for (int i = 0; i < list->cur_size; i++) {
printf(" %d", list->values[i]);
}
printf("\n");
}
/* Allocate list that can store up to 'max_size' elements */
__device__ list_t *
list_alloc(int max_size)
{
list_t *list = (list_t *)malloc(sizeof(list_t));
list->values = (int *)malloc(max_size * sizeof(int));
list->max_size = max_size;
list->cur_size = 0;
return list;
}
/* Free a list; call this to avoid leaking memory! */
__device__ void
list_free(list_t *list)
{
free(list->values);
free(list);
}
/* Add a value to the end of the list */
__device__ void
list_add(list_t *list, int value)
{
if (list->cur_size >= list->max_size) {
printf("List full");
list_dump(list);
// exit(1);
}
list->values[list->cur_size++] = value;
}
/* Return the current size of the list */
__device__ int
list_size(list_t *list)
{
return list->cur_size;
}
/* Validate index */
__device__ void
_list_check_index(list_t *list, int index)
{
if (index < 0 || index > list->cur_size - 1) {
printf("Invalid index %d\n", index);
list_dump(list);
// exit(1);
}
}
/* Get the value at given index */
__device__ int
list_get(list_t *list, int index)
{
_list_check_index(list, index);
return list->values[index];
}
/* Remove the value at the given index */
__device__ void
list_remove_at(list_t *list, int index)
{
_list_check_index(list, index);
for (int i = index; i < list->cur_size - 1; i++) {
list->values[i] = list->values[i + 1];
}
list->cur_size--;
}
/* Retrieve a copy of the values as a simple array of integers. The returned
array is allocated dynamically; the caller must free the space when no
longer needed.
*/
__device__ int *
list_as_array(list_t *list)
{
int *rtn = (int *)malloc(list->max_size * sizeof(int));
for (int i = 0; i < list->max_size; i++) {
rtn[i] = list_get(list, i);
}
return rtn;
}
/**** Permutation ****************/
/* Permutation algorithms based on code found at:
http://www.mathblog.dk/project-euler-24-millionth-lexicographic-permutation/
which references:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
/* Calculate n! iteratively */
__device__ __host__ long
factorial(int n)
{
if (n < 1) {
return 0;
}
long rtn = 1;
for (int i = 1; i <= n; i++) {
rtn *= i;
}
return rtn;
}
/* Return the kth lexographically ordered permuation of an array of k integers
in the range [0 .. size - 1]. The integers are allocated dynamically and
should be free'd by the caller when no longer needed.
*/
__device__ int *
kth_perm(int k, int size)
{
long remain = k - 1;
list_t *numbers = list_alloc(size);
for (int i = 0; i < size; i++) {
list_add(numbers, i);
}
list_t *perm = list_alloc(size);
for (int i = 1; i < size; i++) {
long f = factorial(size - i);
long j = remain / f;
remain = remain % f;
list_add(perm, list_get(numbers, j));
list_remove_at(numbers, j);
if (remain == 0) {
break;
}
}
/* Append remaining digits */
for (int i = 0; i < list_size(numbers); i++) {
list_add(perm, list_get(numbers, i));
}
int *rtn = list_as_array(perm);
list_free(perm);
return rtn;
}
/* Given an array of size elements at perm, update the array in place to
contain the lexographically next permutation. It is originally due to
Dijkstra. The present version is discussed at:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
__device__ void
next_perm(int *perm, int size)
{
int i = size - 1;
while (perm[i - 1] >= perm[i]) {
i = i - 1;
}
int j = size;
while (perm[j - 1] <= perm[i - 1]) {
j = j - 1;
}
swap(perm, i - 1, j - 1);
i++;
j = size;
while (i < j) {
swap(perm, i - 1, j - 1);
i++;
j--;
}
}
__global__
void tsp_go(int* perm, int num_cities, int num_threads, int* cperm, int* output, int* num_as_short){
long one_index = threadIdx.x + 1;
long cur_idx = (factorial(num_cities)/num_threads) * (threadIdx.x)+1;
long end_idx = (factorial(num_cities)/num_threads) * (one_index);
int min_path = INT_MAX;
int num = 0;
__syncthreads();
perm = kth_perm(cur_idx, num_cities);
while( cur_idx <= end_idx){
// printf("Hello from %d, end_idx: %ld, cur_idx: %ld, perms: %ld\n", threadIdx.x, end_idx, cur_idx, factorial(num_cities));
int tmp = eval_tsp(perm, num_cities, cperm);
// printf("Hello from %d, cost: %d\n", threadIdx.x, tmp);
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num++;
}
cur_idx++;
// MAKING SURE NOT OUT OF RANGE
if( cur_idx <= end_idx){
next_perm(perm, num_cities);
}
// __syncthreads();
}
__syncthreads();
output[threadIdx.x] = min_path;
num_as_short[threadIdx.x] = num;
}
void
usage(char *prog_name)
{
fprintf(stderr, "usage: %s [flags]\n", prog_name);
fprintf(stderr, " -h\n");
fprintf(stderr, " -c <number of cities>\n");
fprintf(stderr, " -s <random seed>\n");
exit(1);
}
int
main(int argc, char **argv)
{
int num_cities = 5;
int shortest_length;
int num_as_short = -1;
long num_trials = 0;
int num_threads = 1;
int random_seed = 42;
/* Use "random" random seed by default. */
random_seed = time(NULL);
int ch;
while ((ch = getopt(argc, argv, "c:hn:s:")) != -1) {
switch (ch) {
case 'c':
num_cities = atoi(optarg);
break;
case 'n':
num_threads = atoi(optarg);
if(num_threads < 1){
usage(argv[0]);
}
break;
case 's':
random_seed = atoi(optarg);
break;
case 'h':
default:
usage(argv[0]);
}
}
num_trials = factorial(num_cities);
if(num_trials < num_threads){
num_threads = num_trials;
}
double start_time = now();
// cost array
int* h_cperm = create_tsp(num_cities, random_seed);
// print_tsp(h_cperm, num_cities);
int* d_cperm;
// output Array
int h_output[num_threads];
int* d_output;
// perm array
int *d_perm;
// num_as_short array
int h_num_short[num_threads];
int *d_num_short;
hipMalloc((void **)&d_perm, sizeof(int)*num_cities);
hipMalloc((void **)&d_cperm, sizeof(int)*num_cities*num_cities);
hipMalloc((void **)&d_output, sizeof(int)*num_threads);
hipMalloc((void **)&d_num_short, sizeof(int)*num_threads);
hipMemcpy(d_cperm, h_cperm, sizeof(int)*num_cities*num_cities, hipMemcpyHostToDevice);
/* "Travel, salesman!" */
tsp_go<<<1, num_threads>>>(d_perm, num_cities, num_threads, d_cperm, d_output, d_num_short);
hipDeviceSynchronize();
// collect results
hipMemcpy(h_output, d_output, num_threads * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(h_num_short, d_num_short, num_threads * sizeof(int), hipMemcpyDeviceToHost);
smallest_in_list(h_output, h_num_short, num_threads, &shortest_length, &num_as_short);
double time_took = now() - start_time;
FILE *f = fopen("time.txt", "a");
fprintf(f, "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n", num_threads, time_took, num_cities, random_seed, shortest_length);
fclose(f);
/* Report. */
printf("\n");
printf("Trials %ld\n", num_trials);
float percent_as_short = (float)num_as_short / (float)num_trials * 100.0;
printf("Shortest %d - %d tours - %.6f%%\n",
shortest_length, num_as_short, percent_as_short);
printf("\n");
free(h_cperm);
// free(h_output);
hipFree(d_perm);
hipFree(d_cperm);
hipFree(d_output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <getopt.h>
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
/* Original permuation code due to D. Jimenez, UT Austin
* http://faculty.cse.tamu.edu/djimenez/ut/utsa/cs3343/
*/
/* Requires C99 compiler (gcc: -std=c99) */
#define ONE_BILLION (double)1000000000.0
#define debug_printf(fmt, ...) do { if (DEBUG) fprintf(stderr, fmt, __VA_ARGS__); } while (0)
/* Action function for each permuation. */
typedef void (*perm_action_t)(int *v, int n);
/* Reference an element in the TSP distance array. */
#define TSP_ELT(tsp, n, i, j) *(tsp + (i * n) + j)
__host__ double
now(void)
{
struct timespec current_time;
clock_gettime(CLOCK_REALTIME, ¤t_time);
return current_time.tv_sec + (current_time.tv_nsec / ONE_BILLION);
}
/* Swap array elements. */
__device__ __host__ void
swap(int *v, int i, int j)
{
int t = v[i];
v[i] = v[j];
v[j] = t;
}
/* Trivial action to pass to permutations--print out each one. */
__device__ void
print_perm(int *perm, int n, char *msge)
{
for (int j = 0; j < n; j++) {
printf("%2d ", perm[j]);
}
printf(" - %s\n", msge);
}
__host__ void
smallest_in_list(int *list, int *num_short, int n, int *shortest_length, int *num_as_short)
{
int min_path = INT_MAX;
int num = 0;
for (int j = 0; j < n; j++) {
int tmp = list[j];
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num += num_short[j];
}
}
*shortest_length = min_path;
*num_as_short = num;
}
/* Create an instance of a symmetric TSP. */
__host__ int *
create_tsp(int n, int random_seed)
{
int *tsp = (int *) malloc(n * n * sizeof(int));
srandom(random_seed);
for (int i = 0; i < n; i++) {
for (int j = 0; j <= i; j++) {
int val = (int)(random() / (RAND_MAX / 100));
TSP_ELT(tsp, n, i, j) = val;
TSP_ELT(tsp, n, j, i) = val;
}
}
return tsp;
}
/* Print a TSP distance matrix. */
__host__ __device__ void
print_tsp(int *tsp, int n)
{
// printf("TSP (%d cities - seed %d)\n ", n, random_seed);
for (int j = 0; j < n; j++) {
printf("%3d|", j);
}
printf("\n");
for (int i = 0; i < n; i++) {
printf("%2d|", i);
for (int j = 0; j < n; j++) {
printf("%4d", TSP_ELT(tsp, n, i, j));
}
printf("\n");
}
printf("\n");
}
/* Evaluate a single instance of the TSP. */
__device__ int
eval_tsp(int *perm, int n, int* distances)
{
/* Calculate the length of the tour for the current permutation. */
int total = 0;
for (int i = 0; i < n; i++) {
int j = (i + 1) % n;
int from = perm[i];
int to = perm[j];
int val = TSP_ELT(distances, n, from, to);
total += val;
}
return total;
}
/**** List ADT ****************/
typedef struct {
int *values; /* Values stored in list */
int max_size; /* Maximum size allocated */
int cur_size; /* Size currently in use */
} list_t;
/* Dump list, including sizes */
__device__ void
list_dump(list_t *list)
{
printf("%2d/%2d", list->cur_size, list->max_size);
for (int i = 0; i < list->cur_size; i++) {
printf(" %d", list->values[i]);
}
printf("\n");
}
/* Allocate list that can store up to 'max_size' elements */
__device__ list_t *
list_alloc(int max_size)
{
list_t *list = (list_t *)malloc(sizeof(list_t));
list->values = (int *)malloc(max_size * sizeof(int));
list->max_size = max_size;
list->cur_size = 0;
return list;
}
/* Free a list; call this to avoid leaking memory! */
__device__ void
list_free(list_t *list)
{
free(list->values);
free(list);
}
/* Add a value to the end of the list */
__device__ void
list_add(list_t *list, int value)
{
if (list->cur_size >= list->max_size) {
printf("List full");
list_dump(list);
// exit(1);
}
list->values[list->cur_size++] = value;
}
/* Return the current size of the list */
__device__ int
list_size(list_t *list)
{
return list->cur_size;
}
/* Validate index */
__device__ void
_list_check_index(list_t *list, int index)
{
if (index < 0 || index > list->cur_size - 1) {
printf("Invalid index %d\n", index);
list_dump(list);
// exit(1);
}
}
/* Get the value at given index */
__device__ int
list_get(list_t *list, int index)
{
_list_check_index(list, index);
return list->values[index];
}
/* Remove the value at the given index */
__device__ void
list_remove_at(list_t *list, int index)
{
_list_check_index(list, index);
for (int i = index; i < list->cur_size - 1; i++) {
list->values[i] = list->values[i + 1];
}
list->cur_size--;
}
/* Retrieve a copy of the values as a simple array of integers. The returned
array is allocated dynamically; the caller must free the space when no
longer needed.
*/
__device__ int *
list_as_array(list_t *list)
{
int *rtn = (int *)malloc(list->max_size * sizeof(int));
for (int i = 0; i < list->max_size; i++) {
rtn[i] = list_get(list, i);
}
return rtn;
}
/**** Permutation ****************/
/* Permutation algorithms based on code found at:
http://www.mathblog.dk/project-euler-24-millionth-lexicographic-permutation/
which references:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
/* Calculate n! iteratively */
__device__ __host__ long
factorial(int n)
{
if (n < 1) {
return 0;
}
long rtn = 1;
for (int i = 1; i <= n; i++) {
rtn *= i;
}
return rtn;
}
/* Return the kth lexographically ordered permuation of an array of k integers
in the range [0 .. size - 1]. The integers are allocated dynamically and
should be free'd by the caller when no longer needed.
*/
__device__ int *
kth_perm(int k, int size)
{
long remain = k - 1;
list_t *numbers = list_alloc(size);
for (int i = 0; i < size; i++) {
list_add(numbers, i);
}
list_t *perm = list_alloc(size);
for (int i = 1; i < size; i++) {
long f = factorial(size - i);
long j = remain / f;
remain = remain % f;
list_add(perm, list_get(numbers, j));
list_remove_at(numbers, j);
if (remain == 0) {
break;
}
}
/* Append remaining digits */
for (int i = 0; i < list_size(numbers); i++) {
list_add(perm, list_get(numbers, i));
}
int *rtn = list_as_array(perm);
list_free(perm);
return rtn;
}
/* Given an array of size elements at perm, update the array in place to
contain the lexographically next permutation. It is originally due to
Dijkstra. The present version is discussed at:
http://www.cut-the-knot.org/do_you_know/AllPerm.shtml
*/
__device__ void
next_perm(int *perm, int size)
{
int i = size - 1;
while (perm[i - 1] >= perm[i]) {
i = i - 1;
}
int j = size;
while (perm[j - 1] <= perm[i - 1]) {
j = j - 1;
}
swap(perm, i - 1, j - 1);
i++;
j = size;
while (i < j) {
swap(perm, i - 1, j - 1);
i++;
j--;
}
}
__global__
void tsp_go(int* perm, int num_cities, int num_threads, int* cperm, int* output, int* num_as_short){
long one_index = threadIdx.x + 1;
long cur_idx = (factorial(num_cities)/num_threads) * (threadIdx.x)+1;
long end_idx = (factorial(num_cities)/num_threads) * (one_index);
int min_path = INT_MAX;
int num = 0;
__syncthreads();
perm = kth_perm(cur_idx, num_cities);
while( cur_idx <= end_idx){
// printf("Hello from %d, end_idx: %ld, cur_idx: %ld, perms: %ld\n", threadIdx.x, end_idx, cur_idx, factorial(num_cities));
int tmp = eval_tsp(perm, num_cities, cperm);
// printf("Hello from %d, cost: %d\n", threadIdx.x, tmp);
if(tmp < min_path){
min_path = tmp;
num = 0;
}
if(tmp == min_path){
num++;
}
cur_idx++;
// MAKING SURE NOT OUT OF RANGE
if( cur_idx <= end_idx){
next_perm(perm, num_cities);
}
// __syncthreads();
}
__syncthreads();
output[threadIdx.x] = min_path;
num_as_short[threadIdx.x] = num;
}
void
usage(char *prog_name)
{
fprintf(stderr, "usage: %s [flags]\n", prog_name);
fprintf(stderr, " -h\n");
fprintf(stderr, " -c <number of cities>\n");
fprintf(stderr, " -s <random seed>\n");
exit(1);
}
int
main(int argc, char **argv)
{
int num_cities = 5;
int shortest_length;
int num_as_short = -1;
long num_trials = 0;
int num_threads = 1;
int random_seed = 42;
/* Use "random" random seed by default. */
random_seed = time(NULL);
int ch;
while ((ch = getopt(argc, argv, "c:hn:s:")) != -1) {
switch (ch) {
case 'c':
num_cities = atoi(optarg);
break;
case 'n':
num_threads = atoi(optarg);
if(num_threads < 1){
usage(argv[0]);
}
break;
case 's':
random_seed = atoi(optarg);
break;
case 'h':
default:
usage(argv[0]);
}
}
num_trials = factorial(num_cities);
if(num_trials < num_threads){
num_threads = num_trials;
}
double start_time = now();
// cost array
int* h_cperm = create_tsp(num_cities, random_seed);
// print_tsp(h_cperm, num_cities);
int* d_cperm;
// output Array
int h_output[num_threads];
int* d_output;
// perm array
int *d_perm;
// num_as_short array
int h_num_short[num_threads];
int *d_num_short;
hipMalloc((void **)&d_perm, sizeof(int)*num_cities);
hipMalloc((void **)&d_cperm, sizeof(int)*num_cities*num_cities);
hipMalloc((void **)&d_output, sizeof(int)*num_threads);
hipMalloc((void **)&d_num_short, sizeof(int)*num_threads);
hipMemcpy(d_cperm, h_cperm, sizeof(int)*num_cities*num_cities, hipMemcpyHostToDevice);
/* "Travel, salesman!" */
tsp_go<<<1, num_threads>>>(d_perm, num_cities, num_threads, d_cperm, d_output, d_num_short);
hipDeviceSynchronize();
// collect results
hipMemcpy(h_output, d_output, num_threads * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(h_num_short, d_num_short, num_threads * sizeof(int), hipMemcpyDeviceToHost);
smallest_in_list(h_output, h_num_short, num_threads, &shortest_length, &num_as_short);
double time_took = now() - start_time;
FILE *f = fopen("time.txt", "a");
fprintf(f, "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n", num_threads, time_took, num_cities, random_seed, shortest_length);
fclose(f);
/* Report. */
printf("\n");
printf("Trials %ld\n", num_trials);
float percent_as_short = (float)num_as_short / (float)num_trials * 100.0;
printf("Shortest %d - %d tours - %.6f%%\n",
shortest_length, num_as_short, percent_as_short);
printf("\n");
free(h_cperm);
// free(h_output);
hipFree(d_perm);
hipFree(d_cperm);
hipFree(d_output);
} | .text
.file "parallel-tsp.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3nowv
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z3nowv
.p2align 4, 0x90
.type _Z3nowv,@function
_Z3nowv: # @_Z3nowv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z3nowv, .Lfunc_end0-_Z3nowv
.cfi_endproc
# -- End function
.globl _Z4swapPiii # -- Begin function _Z4swapPiii
.p2align 4, 0x90
.type _Z4swapPiii,@function
_Z4swapPiii: # @_Z4swapPiii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
movl (%rdi,%rax,4), %ecx
movslq %edx, %rdx
movl (%rdi,%rdx,4), %esi
movl %esi, (%rdi,%rax,4)
movl %ecx, (%rdi,%rdx,4)
retq
.Lfunc_end1:
.size _Z4swapPiii, .Lfunc_end1-_Z4swapPiii
.cfi_endproc
# -- End function
.globl _Z16smallest_in_listPiS_iS_S_ # -- Begin function _Z16smallest_in_listPiS_iS_S_
.p2align 4, 0x90
.type _Z16smallest_in_listPiS_iS_S_,@function
_Z16smallest_in_listPiS_iS_S_: # @_Z16smallest_in_listPiS_iS_S_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %r9d
xorl %r10d, %r10d
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %r11d, %r11d
xorl %edx, %edx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
incq %r11
cmpq %r11, %r9
je .LBB2_7
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%r11,4), %ebx
cmpl %eax, %ebx
cmovll %r10d, %edx
cmovll %ebx, %eax
jg .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
addl (%rsi,%r11,4), %edx
jmp .LBB2_6
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
jmp .LBB2_2
.LBB2_1:
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %edx, %edx
.LBB2_2: # %._crit_edge
movl %eax, (%rcx)
movl %edx, (%r8)
retq
.Lfunc_end2:
.size _Z16smallest_in_listPiS_iS_S_, .Lfunc_end2-_Z16smallest_in_listPiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z10create_tspii # -- Begin function _Z10create_tspii
.p2align 4, 0x90
.type _Z10create_tspii,@function
_Z10create_tspii: # @_Z10create_tspii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl %r14d, %edi
callq srandom
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.preheader.preheader
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
movl $1, %r12d
xorl %ecx, %ecx
movabsq $-4035224944001410015, %rbp # imm = 0xC800004B00001C21
movq 8(%rsp), %r14 # 8-byte Reload
movq %r14, %rbx
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movq %rcx, 32(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq random
movq %rax, %rcx
imulq %rbp
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $24, %rdx
addl %eax, %edx
movl %edx, (%rbx,%r13,4)
movl %edx, (%r14)
incq %r13
addq %r15, %r14
cmpq %r13, %r12
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
movq 32(%rsp), %rcx # 8-byte Reload
incq %rcx
incq %r12
movq 24(%rsp), %r14 # 8-byte Reload
addq $4, %r14
addq %r15, %rbx
cmpq 16(%rsp), %rcx # 8-byte Folded Reload
jne .LBB3_2
.LBB3_5: # %._crit_edge
movq 8(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10create_tspii, .Lfunc_end3-_Z10create_tspii
.cfi_endproc
# -- End function
.globl _Z9print_tspPii # -- Begin function _Z9print_tspPii
.p2align 4, 0x90
.type _Z9print_tspPii,@function
_Z9print_tspPii: # @_Z9print_tspPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
testl %esi, %esi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incl %r14d
cmpl %r14d, %ebp
jne .LBB4_2
.LBB4_3: # %._crit_edge
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB4_8
# %bb.4: # %.lr.ph26
movl %ebp, %r15d
leaq (,%r15,4), %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph22
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r15
jne .LBB4_6
# %bb.7: # %._crit_edge23
# in Loop: Header=BB4_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq %r12, %rbx
cmpq %r15, %r14
jne .LBB4_5
.LBB4_8: # %._crit_edge27
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z9print_tspPii, .Lfunc_end4-_Z9print_tspPii
.cfi_endproc
# -- End function
.globl _Z9factoriali # -- Begin function _Z9factoriali
.p2align 4, 0x90
.type _Z9factoriali,@function
_Z9factoriali: # @_Z9factoriali
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB5_1
# %bb.2: # %.preheader.preheader
incl %edi
movl $1, %ecx
movl $1, %eax
.p2align 4, 0x90
.LBB5_3: # %.preheader
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rax
incq %rcx
cmpq %rcx, %rdi
jne .LBB5_3
# %bb.4: # %.loopexit
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z9factoriali, .Lfunc_end5-_Z9factoriali
.cfi_endproc
# -- End function
.globl _Z21__device_stub__tsp_goPiiiS_S_S_ # -- Begin function _Z21__device_stub__tsp_goPiiiS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__tsp_goPiiiS_S_S_,@function
_Z21__device_stub__tsp_goPiiiS_S_S_: # @_Z21__device_stub__tsp_goPiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6tsp_goPiiiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z21__device_stub__tsp_goPiiiS_S_S_, .Lfunc_end6-_Z21__device_stub__tsp_goPiiiS_S_S_
.cfi_endproc
# -- End function
.globl _Z5usagePc # -- Begin function _Z5usagePc
.p2align 4, 0x90
.type _Z5usagePc,@function
_Z5usagePc: # @_Z5usagePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rdx
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end7:
.size _Z5usagePc, .Lfunc_end7-_Z5usagePc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI8_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI8_1:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $264, %rsp # imm = 0x108
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %r15
movl %edi, %r12d
xorl %edi, %edi
callq time
movq %rax, %r13
movl $5, %ebx
movl $1, %r14d
jmp .LBB8_1
.p2align 4, 0x90
.LBB8_6: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB8_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.8, %edx
movl %r12d, %edi
movq %r15, %rsi
callq getopt
cmpl $99, %eax
je .LBB8_6
# %bb.2: # in Loop: Header=BB8_1 Depth=1
cmpl $-1, %eax
je .LBB8_9
# %bb.3: # in Loop: Header=BB8_1 Depth=1
cmpl $110, %eax
je .LBB8_7
# %bb.4: # in Loop: Header=BB8_1 Depth=1
cmpl $115, %eax
jne .LBB8_8
# %bb.5: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
jmp .LBB8_1
.LBB8_7: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jg .LBB8_1
.LBB8_8:
movq (%r15), %rdx
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB8_9:
testl %ebx, %ebx
jle .LBB8_10
# %bb.11: # %.preheader.preheader.i
leal 1(%rbx), %eax
movl $1, %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB8_12: # %.preheader.i
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rdx
incq %rcx
cmpq %rcx, %rax
jne .LBB8_12
jmp .LBB8_13
.LBB8_10:
xorl %edx, %edx
.LBB8_13: # %_Z9factoriali.exit
movl %r14d, %eax
cmpq %rax, %rdx
movq %rdx, -200(%rbp) # 8-byte Spill
movl %edx, %eax
cmovgel %r14d, %eax
movl %eax, -92(%rbp) # 4-byte Spill
leaq -176(%rbp), %rsi
xorl %edi, %edi
callq clock_gettime
movq -176(%rbp), %rax
movq %rax, -192(%rbp) # 8-byte Spill
movq -168(%rbp), %rax
movq %rax, -184(%rbp) # 8-byte Spill
movl %ebx, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, -64(%rbp) # 8-byte Spill
movq %r13, -208(%rbp) # 8-byte Spill
movl %r13d, %edi
callq srandom
movq %rbx, -56(%rbp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB8_18
# %bb.14: # %.preheader.preheader.i53
movl -56(%rbp), %eax # 4-byte Reload
movq %rax, -216(%rbp) # 8-byte Spill
leaq (,%rax,4), %rdx
movl $1, %r15d
xorl %ecx, %ecx
movabsq $-4035224944001410015, %r14 # imm = 0xC800004B00001C21
movq -64(%rbp), %r13 # 8-byte Reload
movq %r13, %r12
movq %rdx, -48(%rbp) # 8-byte Spill
.p2align 4, 0x90
.LBB8_15: # %.preheader.i54
# =>This Loop Header: Depth=1
# Child Loop BB8_16 Depth 2
movq %rcx, -72(%rbp) # 8-byte Spill
movq %r13, -224(%rbp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_16: # Parent Loop BB8_15 Depth=1
# => This Inner Loop Header: Depth=2
callq random
movq %rax, %rcx
imulq %r14
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $24, %rdx
addl %eax, %edx
movl %edx, (%r12,%rbx,4)
movl %edx, (%r13)
movq -48(%rbp), %rdx # 8-byte Reload
incq %rbx
addq %rdx, %r13
cmpq %rbx, %r15
jne .LBB8_16
# %bb.17: # in Loop: Header=BB8_15 Depth=1
movq -72(%rbp), %rcx # 8-byte Reload
incq %rcx
incq %r15
movq -224(%rbp), %r13 # 8-byte Reload
addq $4, %r13
addq %rdx, %r12
cmpq -216(%rbp), %rcx # 8-byte Folded Reload
jne .LBB8_15
.LBB8_18: # %_Z10create_tspii.exit
movq %rsp, -72(%rbp) # 8-byte Spill
movl -92(%rbp), %r13d # 4-byte Reload
movl %r13d, %ebx
movq %rsp, %r12
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %r12
movq %r12, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movslq -56(%rbp), %r15 # 4-byte Folded Reload
leaq (,%r15,4), %r14
leaq -120(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
imulq %r15, %r14
movl %r13d, %r15d
leaq -88(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %r13d, %r13
shlq $2, %r13
leaq -80(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -112(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -88(%rbp), %rdi
movq -64(%rbp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rbx,%rdi), %rdx
orq $1, %rdi
xorl %r14d, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_20
# %bb.19:
movq -120(%rbp), %rax
movq -88(%rbp), %rcx
movq -80(%rbp), %rdx
movq -112(%rbp), %rsi
movq %rax, -304(%rbp)
movq -56(%rbp), %rax # 8-byte Reload
movl %eax, -100(%rbp)
movl %r15d, -96(%rbp)
movq %rcx, -296(%rbp)
movq %rdx, -288(%rbp)
movq %rsi, -280(%rbp)
leaq -304(%rbp), %rax
movq %rax, -176(%rbp)
leaq -100(%rbp), %rax
movq %rax, -168(%rbp)
leaq -96(%rbp), %rax
movq %rax, -160(%rbp)
leaq -296(%rbp), %rax
movq %rax, -152(%rbp)
leaq -288(%rbp), %rax
movq %rax, -144(%rbp)
leaq -280(%rbp), %rax
movq %rax, -136(%rbp)
leaq -272(%rbp), %rdi
leaq -256(%rbp), %rsi
leaq -240(%rbp), %rdx
leaq -232(%rbp), %rcx
callq __hipPopCallConfiguration
movq -272(%rbp), %rsi
movl -264(%rbp), %edx
movq -256(%rbp), %rcx
movl -248(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z6tsp_goPiiiS_S_S_, %edi
pushq -232(%rbp)
pushq -240(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_20:
callq hipDeviceSynchronize
movq -80(%rbp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -112(%rbp), %rsi
movq -48(%rbp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r15d, %edx
testl %r15d, %r15d
jle .LBB8_21
# %bb.22: # %.lr.ph.i.preheader
xorl %eax, %eax
movl $2147483647, %r13d # imm = 0x7FFFFFFF
xorl %ecx, %ecx
xorl %r14d, %r14d
movq -48(%rbp), %rsi # 8-byte Reload
movl %edx, %r15d
jmp .LBB8_23
.p2align 4, 0x90
.LBB8_25: # in Loop: Header=BB8_23 Depth=1
incq %rcx
cmpq %rcx, %rbx
je .LBB8_26
.LBB8_23: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
cmpl %r13d, %edx
cmovll %eax, %r14d
cmovll %edx, %r13d
jg .LBB8_25
# %bb.24: # in Loop: Header=BB8_23 Depth=1
addl (%rsi,%rcx,4), %r14d
jmp .LBB8_25
.LBB8_21:
movl $2147483647, %r13d # imm = 0x7FFFFFFF
movl %edx, %r15d
.LBB8_26: # %_Z16smallest_in_listPiS_iS_S_.exit
cvtsi2sdq -184(%rbp), %xmm0 # 8-byte Folded Reload
divsd .LCPI8_0(%rip), %xmm0
cvtsi2sdq -192(%rbp), %xmm1 # 8-byte Folded Reload
addsd %xmm0, %xmm1
movsd %xmm1, -48(%rbp) # 8-byte Spill
leaq -176(%rbp), %rsi
xorl %edi, %edi
callq clock_gettime
xorps %xmm0, %xmm0
cvtsi2sdq -176(%rbp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq -168(%rbp), %xmm1
divsd .LCPI8_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd -48(%rbp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, -48(%rbp) # 8-byte Spill
movl $.L.str.9, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r12
movl $.L.str.11, %esi
movq %rax, %rdi
movl %r15d, %edx
movsd -48(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movq -56(%rbp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq -208(%rbp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
movl %r13d, %r9d
movb $1, %al
callq fprintf
movq %r12, %rdi
callq fclose
movl $10, %edi
callq putchar@PLT
movl $.L.str.12, %edi
movq -200(%rbp), %rbx # 8-byte Reload
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
divss %xmm1, %xmm0
mulss .LCPI8_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movl %r13d, %esi
movl %r14d, %edx
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq -64(%rbp), %rdi # 8-byte Reload
callq free
movq -120(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6tsp_goPiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%3d|"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%2d|"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4d"
.size .L.str.3, 4
.type _Z6tsp_goPiiiS_S_S_,@object # @_Z6tsp_goPiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z6tsp_goPiiiS_S_S_
.p2align 3, 0x0
_Z6tsp_goPiiiS_S_S_:
.quad _Z21__device_stub__tsp_goPiiiS_S_S_
.size _Z6tsp_goPiiiS_S_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "usage: %s [flags]\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " -h\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -c <number of cities>\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " -s <random seed>\n"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "c:hn:s:"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "time.txt"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "a"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n"
.size .L.str.11, 89
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Trials %ld\n"
.size .L.str.12, 12
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Shortest %d - %d tours - %.6f%%\n"
.size .L.str.13, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6tsp_goPiiiS_S_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__tsp_goPiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6tsp_goPiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013b443_00000000-6_parallel-tsp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3nowv
.type _Z3nowv, @function
_Z3nowv:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z3nowv, .-_Z3nowv
.globl _Z4swapPiii
.type _Z4swapPiii, @function
_Z4swapPiii:
.LFB2071:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl (%rcx), %esi
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %rax
movl (%rax), %edx
movl %edx, (%rcx)
movl %esi, (%rax)
ret
.cfi_endproc
.LFE2071:
.size _Z4swapPiii, .-_Z4swapPiii
.globl _Z10print_permPiiPc
.type _Z10print_permPiiPc, @function
_Z10print_permPiiPc:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z10print_permPiiPc, .-_Z10print_permPiiPc
.globl _Z16smallest_in_listPiS_iS_S_
.type _Z16smallest_in_listPiS_iS_S_, @function
_Z16smallest_in_listPiS_iS_S_:
.LFB2073:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L15
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movq %rsi, %r11
movslq %edx, %rdx
leaq 0(,%rdx,4), %rdi
movl $0, %eax
movl $0, %r9d
movl $2147483647, %esi
movl $0, %ebx
jmp .L14
.L24:
je .L22
.L13:
addq $4, %rax
cmpq %rdi, %rax
je .L23
.L14:
movl (%r10,%rax), %edx
cmpl %esi, %edx
jge .L24
movl %ebx, %r9d
.L12:
addl (%r11,%rax), %r9d
movl %edx, %esi
jmp .L13
.L22:
movl %esi, %edx
jmp .L12
.L15:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r9d
movl $2147483647, %esi
movl %esi, (%rcx)
movl %r9d, (%r8)
ret
.L23:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, (%rcx)
movl %r9d, (%r8)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z16smallest_in_listPiS_iS_S_, .-_Z16smallest_in_listPiS_iS_S_
.globl _Z10create_tspii
.type _Z10create_tspii, @function
_Z10create_tspii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r14d
movl %edi, 20(%rsp)
movl %esi, %ebx
imull %edi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl %ebx, %edi
call srandom@PLT
testl %r14d, %r14d
jle .L25
movslq %r14d, %rax
movq %rax, 24(%rsp)
leaq 0(,%rax,4), %r15
movl $0, 16(%rsp)
movq $0, (%rsp)
movabsq $-4035224944001410015, %r14
.L27:
movq (%rsp), %rax
movl %eax, %r12d
testl %eax, %eax
js .L34
movq 8(%rsp), %rsi
movq (%rsp), %rax
leaq (%rsi,%rax,4), %rbp
movslq 16(%rsp), %rax
leaq (%rsi,%rax,4), %r13
movl $0, %ebx
.L28:
call random@PLT
movq %rax, %rcx
imulq %r14
addq %rcx, %rdx
sarq $24, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movl %edx, 0(%r13,%rbx,4)
movl %edx, 0(%rbp)
addq $1, %rbx
addq %r15, %rbp
cmpl %ebx, %r12d
jge .L28
addq $1, (%rsp)
movq (%rsp), %rax
movl 20(%rsp), %esi
addl %esi, 16(%rsp)
movq 24(%rsp), %rdi
cmpq %rdi, %rax
jne .L27
.L25:
movq 8(%rsp), %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addq $1, (%rsp)
movl 20(%rsp), %edi
addl %edi, 16(%rsp)
jmp .L27
.cfi_endproc
.LFE2074:
.size _Z10create_tspii, .-_Z10create_tspii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%3d|"
.LC2:
.string "\n"
.LC3:
.string "%2d|"
.LC4:
.string "%4d"
.text
.globl _Z9print_tspPii
.type _Z9print_tspPii, @function
_Z9print_tspPii:
.LFB2075:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
testl %esi, %esi
jle .L36
movl %esi, %ebx
movl $0, %r13d
leaq .LC1(%rip), %rbp
.L37:
movl %r13d, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 12(%rsp)
addl $1, %r13d
cmpl %r13d, %ebx
jne .L37
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %r13
leaq 0(,%r13,4), %rax
movq %rax, 24(%rsp)
movq 16(%rsp), %rcx
leaq (%rcx,%rax), %rbp
movl $0, %r15d
movl $0, %r14d
leaq .LC4(%rip), %r12
jmp .L39
.L41:
movl %eax, %r14d
.L39:
movl %r14d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
leaq (%rax,%r15,4), %rbx
.L38:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L38
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %eax
addq %r13, %r15
movq 24(%rsp), %rcx
addq %rcx, %rbp
cmpl %r14d, 12(%rsp)
jne .L41
.L40:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.cfi_endproc
.LFE2075:
.size _Z9print_tspPii, .-_Z9print_tspPii
.globl _Z8eval_tspPiiS_
.type _Z8eval_tspPiiS_, @function
_Z8eval_tspPiiS_:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z8eval_tspPiiS_, .-_Z8eval_tspPiiS_
.globl _Z9list_dumpP6list_t
.type _Z9list_dumpP6list_t, @function
_Z9list_dumpP6list_t:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Z9list_dumpP6list_t, .-_Z9list_dumpP6list_t
.globl _Z10list_alloci
.type _Z10list_alloci, @function
_Z10list_alloci:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Z10list_alloci, .-_Z10list_alloci
.globl _Z9list_freeP6list_t
.type _Z9list_freeP6list_t, @function
_Z9list_freeP6list_t:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z9list_freeP6list_t, .-_Z9list_freeP6list_t
.globl _Z8list_addP6list_ti
.type _Z8list_addP6list_ti, @function
_Z8list_addP6list_ti:
.LFB2080:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z8list_addP6list_ti, .-_Z8list_addP6list_ti
.globl _Z9list_sizeP6list_t
.type _Z9list_sizeP6list_t, @function
_Z9list_sizeP6list_t:
.LFB2081:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2081:
.size _Z9list_sizeP6list_t, .-_Z9list_sizeP6list_t
.globl _Z17_list_check_indexP6list_ti
.type _Z17_list_check_indexP6list_ti, @function
_Z17_list_check_indexP6list_ti:
.LFB2082:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2082:
.size _Z17_list_check_indexP6list_ti, .-_Z17_list_check_indexP6list_ti
.globl _Z8list_getP6list_ti
.type _Z8list_getP6list_ti, @function
_Z8list_getP6list_ti:
.LFB2083:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size _Z8list_getP6list_ti, .-_Z8list_getP6list_ti
.globl _Z14list_remove_atP6list_ti
.type _Z14list_remove_atP6list_ti, @function
_Z14list_remove_atP6list_ti:
.LFB2084:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2084:
.size _Z14list_remove_atP6list_ti, .-_Z14list_remove_atP6list_ti
.globl _Z13list_as_arrayP6list_t
.type _Z13list_as_arrayP6list_t, @function
_Z13list_as_arrayP6list_t:
.LFB2085:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2085:
.size _Z13list_as_arrayP6list_t, .-_Z13list_as_arrayP6list_t
.globl _Z9factoriali
.type _Z9factoriali, @function
_Z9factoriali:
.LFB2086:
.cfi_startproc
endbr64
movl $0, %edx
testl %edi, %edi
jle .L66
leal 1(%rdi), %ecx
movl $1, %eax
movl $1, %edx
.L68:
imulq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rax
jne .L68
.L66:
movq %rdx, %rax
ret
.cfi_endproc
.LFE2086:
.size _Z9factoriali, .-_Z9factoriali
.globl _Z8kth_permii
.type _Z8kth_permii, @function
_Z8kth_permii:
.LFB2087:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2087:
.size _Z8kth_permii, .-_Z8kth_permii
.globl _Z9next_permPii
.type _Z9next_permPii, @function
_Z9next_permPii:
.LFB2088:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2088:
.size _Z9next_permPii, .-_Z9next_permPii
.section .rodata.str1.1
.LC5:
.string "usage: %s [flags]\n"
.LC6:
.string " -h\n"
.LC7:
.string " -c <number of cities>\n"
.LC8:
.string " -s <random seed>\n"
.text
.globl _Z5usagePc
.type _Z5usagePc, @function
_Z5usagePc:
.LFB2089:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2089:
.size _Z5usagePc, .-_Z5usagePc
.globl _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.type _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_, @function
_Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_:
.LFB2115:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6tsp_goPiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2115:
.size _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_, .-_Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.globl _Z6tsp_goPiiiS_S_S_
.type _Z6tsp_goPiiiS_S_S_, @function
_Z6tsp_goPiiiS_S_S_:
.LFB2116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2116:
.size _Z6tsp_goPiiiS_S_S_, .-_Z6tsp_goPiiiS_S_S_
.section .rodata.str1.1
.LC9:
.string "c:hn:s:"
.LC10:
.string "a"
.LC11:
.string "time.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC12:
.string "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n"
.section .rodata.str1.1
.LC13:
.string "Trials %ld\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Shortest %d - %d tours - %.6f%%\n"
.text
.globl main
.type main, @function
main:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, %r13d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $-1, -116(%rbp)
movl $0, %edi
call time@PLT
movl %eax, -132(%rbp)
movl $1, %r15d
movl $5, %ebx
leaq .LC9(%rip), %r14
jmp .L86
.L87:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
testl %eax, %eax
jg .L86
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
movq (%r12), %rdi
call _Z5usagePc
.L104:
call __stack_chk_fail@PLT
.L88:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, -132(%rbp)
.L86:
movq %r14, %rdx
movq %r12, %rsi
movl %r13d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L105
cmpl $110, %eax
je .L87
cmpl $115, %eax
je .L88
cmpl $99, %eax
jne .L89
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L86
.L89:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L106
movq (%r12), %rdi
call _Z5usagePc
.L106:
call __stack_chk_fail@PLT
.L105:
movl %ebx, %edi
call _Z9factoriali
movq %rax, %r14
movslq %r15d, %rax
cmpq %r14, %rax
cmovg %r14d, %r15d
call _Z3nowv
movsd %xmm0, -152(%rbp)
movl -132(%rbp), %esi
movl %ebx, %edi
call _Z10create_tspii
movq %rax, -144(%rbp)
movslq %r15d, %r12
salq $2, %r12
leaq 15(%r12), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L95:
cmpq %rdx, %rsp
je .L96
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L95
.L96:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L97
orq $0, -8(%rsp,%rax)
.L97:
movq %rsp, %r13
leaq 15(%r12), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L98:
cmpq %rdx, %rsp
je .L99
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L98
.L99:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L100
orq $0, -8(%rsp,%rax)
.L100:
movq %rsp, -160(%rbp)
movslq %ebx, %rax
movq %rax, -168(%rbp)
leaq 0(,%rax,4), %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
movq -168(%rbp), %rax
imulq %rax, %rax
salq $2, %rax
leaq -112(%rbp), %rdi
movq %rax, -168(%rbp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq -168(%rbp), %rdx
movq -144(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl %r15d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L101
movq -88(%rbp), %r9
movq -104(%rbp), %r8
movq -112(%rbp), %rcx
movl %r15d, %edx
movl %ebx, %esi
movq -96(%rbp), %rdi
call _Z33__device_stub__Z6tsp_goPiiiS_S_S_PiiiS_S_S_
.L101:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq -104(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq -88(%rbp), %rsi
movq -160(%rbp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
leaq -68(%rbp), %rcx
leaq -116(%rbp), %r8
movl %r15d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z16smallest_in_listPiS_iS_S_
call _Z3nowv
subsd -152(%rbp), %xmm0
movsd %xmm0, -152(%rbp)
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl -68(%rbp), %r13d
subq $8, %rsp
pushq %r13
movl -132(%rbp), %r9d
movl %ebx, %r8d
movsd -152(%rbp), %xmm0
movl %r15d, %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $16, %rsp
movq %r12, %rdi
call fclose@PLT
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -116(%rbp), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r14, %xmm1
divss %xmm1, %xmm0
mulss .LC14(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r13d, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -144(%rbp), %rdi
call free@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L107
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L107:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6tsp_goPiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2118:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6tsp_goPiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2118:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC14:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel-tsp.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3nowv
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z3nowv
.p2align 4, 0x90
.type _Z3nowv,@function
_Z3nowv: # @_Z3nowv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z3nowv, .Lfunc_end0-_Z3nowv
.cfi_endproc
# -- End function
.globl _Z4swapPiii # -- Begin function _Z4swapPiii
.p2align 4, 0x90
.type _Z4swapPiii,@function
_Z4swapPiii: # @_Z4swapPiii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
movl (%rdi,%rax,4), %ecx
movslq %edx, %rdx
movl (%rdi,%rdx,4), %esi
movl %esi, (%rdi,%rax,4)
movl %ecx, (%rdi,%rdx,4)
retq
.Lfunc_end1:
.size _Z4swapPiii, .Lfunc_end1-_Z4swapPiii
.cfi_endproc
# -- End function
.globl _Z16smallest_in_listPiS_iS_S_ # -- Begin function _Z16smallest_in_listPiS_iS_S_
.p2align 4, 0x90
.type _Z16smallest_in_listPiS_iS_S_,@function
_Z16smallest_in_listPiS_iS_S_: # @_Z16smallest_in_listPiS_iS_S_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %r9d
xorl %r10d, %r10d
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %r11d, %r11d
xorl %edx, %edx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
incq %r11
cmpq %r11, %r9
je .LBB2_7
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%r11,4), %ebx
cmpl %eax, %ebx
cmovll %r10d, %edx
cmovll %ebx, %eax
jg .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
addl (%rsi,%r11,4), %edx
jmp .LBB2_6
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
jmp .LBB2_2
.LBB2_1:
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %edx, %edx
.LBB2_2: # %._crit_edge
movl %eax, (%rcx)
movl %edx, (%r8)
retq
.Lfunc_end2:
.size _Z16smallest_in_listPiS_iS_S_, .Lfunc_end2-_Z16smallest_in_listPiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z10create_tspii # -- Begin function _Z10create_tspii
.p2align 4, 0x90
.type _Z10create_tspii,@function
_Z10create_tspii: # @_Z10create_tspii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl %r14d, %edi
callq srandom
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.preheader.preheader
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
movl $1, %r12d
xorl %ecx, %ecx
movabsq $-4035224944001410015, %rbp # imm = 0xC800004B00001C21
movq 8(%rsp), %r14 # 8-byte Reload
movq %r14, %rbx
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movq %rcx, 32(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq random
movq %rax, %rcx
imulq %rbp
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $24, %rdx
addl %eax, %edx
movl %edx, (%rbx,%r13,4)
movl %edx, (%r14)
incq %r13
addq %r15, %r14
cmpq %r13, %r12
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
movq 32(%rsp), %rcx # 8-byte Reload
incq %rcx
incq %r12
movq 24(%rsp), %r14 # 8-byte Reload
addq $4, %r14
addq %r15, %rbx
cmpq 16(%rsp), %rcx # 8-byte Folded Reload
jne .LBB3_2
.LBB3_5: # %._crit_edge
movq 8(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10create_tspii, .Lfunc_end3-_Z10create_tspii
.cfi_endproc
# -- End function
.globl _Z9print_tspPii # -- Begin function _Z9print_tspPii
.p2align 4, 0x90
.type _Z9print_tspPii,@function
_Z9print_tspPii: # @_Z9print_tspPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
testl %esi, %esi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incl %r14d
cmpl %r14d, %ebp
jne .LBB4_2
.LBB4_3: # %._crit_edge
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB4_8
# %bb.4: # %.lr.ph26
movl %ebp, %r15d
leaq (,%r15,4), %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph22
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r15
jne .LBB4_6
# %bb.7: # %._crit_edge23
# in Loop: Header=BB4_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq %r12, %rbx
cmpq %r15, %r14
jne .LBB4_5
.LBB4_8: # %._crit_edge27
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z9print_tspPii, .Lfunc_end4-_Z9print_tspPii
.cfi_endproc
# -- End function
.globl _Z9factoriali # -- Begin function _Z9factoriali
.p2align 4, 0x90
.type _Z9factoriali,@function
_Z9factoriali: # @_Z9factoriali
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB5_1
# %bb.2: # %.preheader.preheader
incl %edi
movl $1, %ecx
movl $1, %eax
.p2align 4, 0x90
.LBB5_3: # %.preheader
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rax
incq %rcx
cmpq %rcx, %rdi
jne .LBB5_3
# %bb.4: # %.loopexit
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z9factoriali, .Lfunc_end5-_Z9factoriali
.cfi_endproc
# -- End function
.globl _Z21__device_stub__tsp_goPiiiS_S_S_ # -- Begin function _Z21__device_stub__tsp_goPiiiS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__tsp_goPiiiS_S_S_,@function
_Z21__device_stub__tsp_goPiiiS_S_S_: # @_Z21__device_stub__tsp_goPiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6tsp_goPiiiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z21__device_stub__tsp_goPiiiS_S_S_, .Lfunc_end6-_Z21__device_stub__tsp_goPiiiS_S_S_
.cfi_endproc
# -- End function
.globl _Z5usagePc # -- Begin function _Z5usagePc
.p2align 4, 0x90
.type _Z5usagePc,@function
_Z5usagePc: # @_Z5usagePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rdx
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end7:
.size _Z5usagePc, .Lfunc_end7-_Z5usagePc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI8_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI8_1:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $264, %rsp # imm = 0x108
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %r15
movl %edi, %r12d
xorl %edi, %edi
callq time
movq %rax, %r13
movl $5, %ebx
movl $1, %r14d
jmp .LBB8_1
.p2align 4, 0x90
.LBB8_6: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB8_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.8, %edx
movl %r12d, %edi
movq %r15, %rsi
callq getopt
cmpl $99, %eax
je .LBB8_6
# %bb.2: # in Loop: Header=BB8_1 Depth=1
cmpl $-1, %eax
je .LBB8_9
# %bb.3: # in Loop: Header=BB8_1 Depth=1
cmpl $110, %eax
je .LBB8_7
# %bb.4: # in Loop: Header=BB8_1 Depth=1
cmpl $115, %eax
jne .LBB8_8
# %bb.5: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
jmp .LBB8_1
.LBB8_7: # in Loop: Header=BB8_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jg .LBB8_1
.LBB8_8:
movq (%r15), %rdx
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB8_9:
testl %ebx, %ebx
jle .LBB8_10
# %bb.11: # %.preheader.preheader.i
leal 1(%rbx), %eax
movl $1, %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB8_12: # %.preheader.i
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rdx
incq %rcx
cmpq %rcx, %rax
jne .LBB8_12
jmp .LBB8_13
.LBB8_10:
xorl %edx, %edx
.LBB8_13: # %_Z9factoriali.exit
movl %r14d, %eax
cmpq %rax, %rdx
movq %rdx, -200(%rbp) # 8-byte Spill
movl %edx, %eax
cmovgel %r14d, %eax
movl %eax, -92(%rbp) # 4-byte Spill
leaq -176(%rbp), %rsi
xorl %edi, %edi
callq clock_gettime
movq -176(%rbp), %rax
movq %rax, -192(%rbp) # 8-byte Spill
movq -168(%rbp), %rax
movq %rax, -184(%rbp) # 8-byte Spill
movl %ebx, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, -64(%rbp) # 8-byte Spill
movq %r13, -208(%rbp) # 8-byte Spill
movl %r13d, %edi
callq srandom
movq %rbx, -56(%rbp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB8_18
# %bb.14: # %.preheader.preheader.i53
movl -56(%rbp), %eax # 4-byte Reload
movq %rax, -216(%rbp) # 8-byte Spill
leaq (,%rax,4), %rdx
movl $1, %r15d
xorl %ecx, %ecx
movabsq $-4035224944001410015, %r14 # imm = 0xC800004B00001C21
movq -64(%rbp), %r13 # 8-byte Reload
movq %r13, %r12
movq %rdx, -48(%rbp) # 8-byte Spill
.p2align 4, 0x90
.LBB8_15: # %.preheader.i54
# =>This Loop Header: Depth=1
# Child Loop BB8_16 Depth 2
movq %rcx, -72(%rbp) # 8-byte Spill
movq %r13, -224(%rbp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_16: # Parent Loop BB8_15 Depth=1
# => This Inner Loop Header: Depth=2
callq random
movq %rax, %rcx
imulq %r14
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
shrq $24, %rdx
addl %eax, %edx
movl %edx, (%r12,%rbx,4)
movl %edx, (%r13)
movq -48(%rbp), %rdx # 8-byte Reload
incq %rbx
addq %rdx, %r13
cmpq %rbx, %r15
jne .LBB8_16
# %bb.17: # in Loop: Header=BB8_15 Depth=1
movq -72(%rbp), %rcx # 8-byte Reload
incq %rcx
incq %r15
movq -224(%rbp), %r13 # 8-byte Reload
addq $4, %r13
addq %rdx, %r12
cmpq -216(%rbp), %rcx # 8-byte Folded Reload
jne .LBB8_15
.LBB8_18: # %_Z10create_tspii.exit
movq %rsp, -72(%rbp) # 8-byte Spill
movl -92(%rbp), %r13d # 4-byte Reload
movl %r13d, %ebx
movq %rsp, %r12
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %r12
movq %r12, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movslq -56(%rbp), %r15 # 4-byte Folded Reload
leaq (,%r15,4), %r14
leaq -120(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
imulq %r15, %r14
movl %r13d, %r15d
leaq -88(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %r13d, %r13
shlq $2, %r13
leaq -80(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -112(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -88(%rbp), %rdi
movq -64(%rbp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rbx,%rdi), %rdx
orq $1, %rdi
xorl %r14d, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_20
# %bb.19:
movq -120(%rbp), %rax
movq -88(%rbp), %rcx
movq -80(%rbp), %rdx
movq -112(%rbp), %rsi
movq %rax, -304(%rbp)
movq -56(%rbp), %rax # 8-byte Reload
movl %eax, -100(%rbp)
movl %r15d, -96(%rbp)
movq %rcx, -296(%rbp)
movq %rdx, -288(%rbp)
movq %rsi, -280(%rbp)
leaq -304(%rbp), %rax
movq %rax, -176(%rbp)
leaq -100(%rbp), %rax
movq %rax, -168(%rbp)
leaq -96(%rbp), %rax
movq %rax, -160(%rbp)
leaq -296(%rbp), %rax
movq %rax, -152(%rbp)
leaq -288(%rbp), %rax
movq %rax, -144(%rbp)
leaq -280(%rbp), %rax
movq %rax, -136(%rbp)
leaq -272(%rbp), %rdi
leaq -256(%rbp), %rsi
leaq -240(%rbp), %rdx
leaq -232(%rbp), %rcx
callq __hipPopCallConfiguration
movq -272(%rbp), %rsi
movl -264(%rbp), %edx
movq -256(%rbp), %rcx
movl -248(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z6tsp_goPiiiS_S_S_, %edi
pushq -232(%rbp)
pushq -240(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_20:
callq hipDeviceSynchronize
movq -80(%rbp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -112(%rbp), %rsi
movq -48(%rbp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r15d, %edx
testl %r15d, %r15d
jle .LBB8_21
# %bb.22: # %.lr.ph.i.preheader
xorl %eax, %eax
movl $2147483647, %r13d # imm = 0x7FFFFFFF
xorl %ecx, %ecx
xorl %r14d, %r14d
movq -48(%rbp), %rsi # 8-byte Reload
movl %edx, %r15d
jmp .LBB8_23
.p2align 4, 0x90
.LBB8_25: # in Loop: Header=BB8_23 Depth=1
incq %rcx
cmpq %rcx, %rbx
je .LBB8_26
.LBB8_23: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
cmpl %r13d, %edx
cmovll %eax, %r14d
cmovll %edx, %r13d
jg .LBB8_25
# %bb.24: # in Loop: Header=BB8_23 Depth=1
addl (%rsi,%rcx,4), %r14d
jmp .LBB8_25
.LBB8_21:
movl $2147483647, %r13d # imm = 0x7FFFFFFF
movl %edx, %r15d
.LBB8_26: # %_Z16smallest_in_listPiS_iS_S_.exit
cvtsi2sdq -184(%rbp), %xmm0 # 8-byte Folded Reload
divsd .LCPI8_0(%rip), %xmm0
cvtsi2sdq -192(%rbp), %xmm1 # 8-byte Folded Reload
addsd %xmm0, %xmm1
movsd %xmm1, -48(%rbp) # 8-byte Spill
leaq -176(%rbp), %rsi
xorl %edi, %edi
callq clock_gettime
xorps %xmm0, %xmm0
cvtsi2sdq -176(%rbp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq -168(%rbp), %xmm1
divsd .LCPI8_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd -48(%rbp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, -48(%rbp) # 8-byte Spill
movl $.L.str.9, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r12
movl $.L.str.11, %esi
movq %rax, %rdi
movl %r15d, %edx
movsd -48(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movq -56(%rbp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq -208(%rbp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
movl %r13d, %r9d
movb $1, %al
callq fprintf
movq %r12, %rdi
callq fclose
movl $10, %edi
callq putchar@PLT
movl $.L.str.12, %edi
movq -200(%rbp), %rbx # 8-byte Reload
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
divss %xmm1, %xmm0
mulss .LCPI8_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movl %r13d, %esi
movl %r14d, %edx
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq -64(%rbp), %rdi # 8-byte Reload
callq free
movq -120(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6tsp_goPiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%3d|"
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%2d|"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4d"
.size .L.str.3, 4
.type _Z6tsp_goPiiiS_S_S_,@object # @_Z6tsp_goPiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z6tsp_goPiiiS_S_S_
.p2align 3, 0x0
_Z6tsp_goPiiiS_S_S_:
.quad _Z21__device_stub__tsp_goPiiiS_S_S_
.size _Z6tsp_goPiiiS_S_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "usage: %s [flags]\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " -h\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -c <number of cities>\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " -s <random seed>\n"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "c:hn:s:"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "time.txt"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "a"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d Threads took %5.3f to compute %d cities with random_seed: %d. shortest_length= %d\n\n"
.size .L.str.11, 89
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Trials %ld\n"
.size .L.str.12, 12
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Shortest %d - %d tours - %.6f%%\n"
.size .L.str.13, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6tsp_goPiiiS_S_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__tsp_goPiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6tsp_goPiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} | code for sm_80
Function : _Z5morphPfS_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020d */
/*00a0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020d */
/*00b0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ F2F.F64.F32 R8, c[0x0][0x178] ; /* 0x00005e0000087b10 */
/* 0x000e240000201800 */
/*00e0*/ DADD R8, -R8, 1 ; /* 0x3ff0000008087429 */
/* 0x001e220000000100 */
/*00f0*/ FMUL R15, R10, c[0x0][0x178] ; /* 0x00005e000a0f7a20 */
/* 0x004fca0000400000 */
/*0100*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x008ff00000201800 */
/*0110*/ F2F.F64.F32 R10, R15 ; /* 0x0000000f000a7310 */
/* 0x000e240000201800 */
/*0120*/ DFMA R6, R6, R8, R10 ; /* 0x000000080606722b */
/* 0x001e14000000000a */
/*0130*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e220000301000 */
/*0140*/ IMAD.WIDE R8, R0, R13, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e020d */
/*0150*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x001fe8000c101904 */
/*0160*/ LDG.E R2, [R2.64+0x4] ; /* 0x0000040402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R4, [R4.64+0x4] ; /* 0x0000040404047981 */
/* 0x000ee2000c1e1900 */
/*0180*/ F2F.F64.F32 R12, c[0x0][0x17c] ; /* 0x00005f00000c7b10 */
/* 0x000e240000201800 */
/*0190*/ DADD R12, -R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e220000000100 */
/*01a0*/ FMUL R14, R2, c[0x0][0x17c] ; /* 0x00005f00020e7a20 */
/* 0x004fca0000400000 */
/*01b0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x008ff00000201800 */
/*01c0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000e240000201800 */
/*01d0*/ DFMA R10, R10, R12, R14 ; /* 0x0000000c0a0a722b */
/* 0x001e14000000000e */
/*01e0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*01f0*/ STG.E [R8.64+0x4], R11 ; /* 0x0000040b08007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} | .file "tmpxft_000eef69_00000000-6_morph.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
.type _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi, @function
_Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5morphPfS_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi, .-_Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
.globl _Z5morphPfS_S_ffi
.type _Z5morphPfS_S_ffi, @function
_Z5morphPfS_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5morphPfS_S_ffi, .-_Z5morphPfS_S_ffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5morphPfS_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5morphPfS_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5morphPfS_S_ffi
.globl _Z5morphPfS_S_ffi
.p2align 8
.type _Z5morphPfS_S_ffi,@function
_Z5morphPfS_S_ffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_cvt_f64_f32_e32 v[3:4], s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], -v[3:4], 1.0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s6, v7
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], v[5:6], v[7:8]
v_cvt_f32_f64_e32 v9, v[3:4]
v_or_b32_e32 v3, 1, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[0:1], v9, off
global_load_b32 v2, v[5:6], off
global_load_b32 v5, v[7:8], off
v_cvt_f64_f32_e32 v[0:1], s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], -v[0:1], 1.0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s7, v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], v[5:6], v[7:8]
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5morphPfS_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5morphPfS_S_ffi, .Lfunc_end0-_Z5morphPfS_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5morphPfS_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5morphPfS_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void morph(float* output, float* input1, float* input2, float ampCoeff, float freqCoeff, int length) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = i<<1;
if (j < length) {
output[j] = input1[j]*(1.0-ampCoeff) + input2[j]*(ampCoeff);
output[j+1] = input1[j+1]*(1.0-freqCoeff) + input2[j+1]*(freqCoeff);
}
} | .text
.file "morph.hip"
.globl _Z20__device_stub__morphPfS_S_ffi # -- Begin function _Z20__device_stub__morphPfS_S_ffi
.p2align 4, 0x90
.type _Z20__device_stub__morphPfS_S_ffi,@function
_Z20__device_stub__morphPfS_S_ffi: # @_Z20__device_stub__morphPfS_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5morphPfS_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__morphPfS_S_ffi, .Lfunc_end0-_Z20__device_stub__morphPfS_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5morphPfS_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5morphPfS_S_ffi,@object # @_Z5morphPfS_S_ffi
.section .rodata,"a",@progbits
.globl _Z5morphPfS_S_ffi
.p2align 3, 0x0
_Z5morphPfS_S_ffi:
.quad _Z20__device_stub__morphPfS_S_ffi
.size _Z5morphPfS_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5morphPfS_S_ffi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__morphPfS_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5morphPfS_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5morphPfS_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020d */
/*00a0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020d */
/*00b0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ F2F.F64.F32 R8, c[0x0][0x178] ; /* 0x00005e0000087b10 */
/* 0x000e240000201800 */
/*00e0*/ DADD R8, -R8, 1 ; /* 0x3ff0000008087429 */
/* 0x001e220000000100 */
/*00f0*/ FMUL R15, R10, c[0x0][0x178] ; /* 0x00005e000a0f7a20 */
/* 0x004fca0000400000 */
/*0100*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x008ff00000201800 */
/*0110*/ F2F.F64.F32 R10, R15 ; /* 0x0000000f000a7310 */
/* 0x000e240000201800 */
/*0120*/ DFMA R6, R6, R8, R10 ; /* 0x000000080606722b */
/* 0x001e14000000000a */
/*0130*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e220000301000 */
/*0140*/ IMAD.WIDE R8, R0, R13, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e020d */
/*0150*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x001fe8000c101904 */
/*0160*/ LDG.E R2, [R2.64+0x4] ; /* 0x0000040402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R4, [R4.64+0x4] ; /* 0x0000040404047981 */
/* 0x000ee2000c1e1900 */
/*0180*/ F2F.F64.F32 R12, c[0x0][0x17c] ; /* 0x00005f00000c7b10 */
/* 0x000e240000201800 */
/*0190*/ DADD R12, -R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e220000000100 */
/*01a0*/ FMUL R14, R2, c[0x0][0x17c] ; /* 0x00005f00020e7a20 */
/* 0x004fca0000400000 */
/*01b0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x008ff00000201800 */
/*01c0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000e240000201800 */
/*01d0*/ DFMA R10, R10, R12, R14 ; /* 0x0000000c0a0a722b */
/* 0x001e14000000000e */
/*01e0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*01f0*/ STG.E [R8.64+0x4], R11 ; /* 0x0000040b08007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5morphPfS_S_ffi
.globl _Z5morphPfS_S_ffi
.p2align 8
.type _Z5morphPfS_S_ffi,@function
_Z5morphPfS_S_ffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_cvt_f64_f32_e32 v[3:4], s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], -v[3:4], 1.0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s6, v7
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], v[5:6], v[7:8]
v_cvt_f32_f64_e32 v9, v[3:4]
v_or_b32_e32 v3, 1, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[0:1], v9, off
global_load_b32 v2, v[5:6], off
global_load_b32 v5, v[7:8], off
v_cvt_f64_f32_e32 v[0:1], s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], -v[0:1], 1.0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s7, v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], v[5:6], v[7:8]
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5morphPfS_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5morphPfS_S_ffi, .Lfunc_end0-_Z5morphPfS_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5morphPfS_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5morphPfS_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eef69_00000000-6_morph.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
.type _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi, @function
_Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5morphPfS_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi, .-_Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
.globl _Z5morphPfS_S_ffi
.type _Z5morphPfS_S_ffi, @function
_Z5morphPfS_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5morphPfS_S_ffiPfS_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5morphPfS_S_ffi, .-_Z5morphPfS_S_ffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5morphPfS_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5morphPfS_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "morph.hip"
.globl _Z20__device_stub__morphPfS_S_ffi # -- Begin function _Z20__device_stub__morphPfS_S_ffi
.p2align 4, 0x90
.type _Z20__device_stub__morphPfS_S_ffi,@function
_Z20__device_stub__morphPfS_S_ffi: # @_Z20__device_stub__morphPfS_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5morphPfS_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__morphPfS_S_ffi, .Lfunc_end0-_Z20__device_stub__morphPfS_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5morphPfS_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5morphPfS_S_ffi,@object # @_Z5morphPfS_S_ffi
.section .rodata,"a",@progbits
.globl _Z5morphPfS_S_ffi
.p2align 3, 0x0
_Z5morphPfS_S_ffi:
.quad _Z20__device_stub__morphPfS_S_ffi
.size _Z5morphPfS_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5morphPfS_S_ffi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__morphPfS_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5morphPfS_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} | code for sm_80
Function : _Z15host_api_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02c0*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */
/* 0x004fca0000000000 */
/*02d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x270 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0330*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0206 */
/*0340*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0360*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0370*/ FADD R17, R2, R2 ; /* 0x0000000202117221 */
/* 0x004fca0000000000 */
/*0380*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0208 */
/*03c0*/ FADD R19, R2, R2 ; /* 0x0000000202137221 */
/* 0x004fca0000000000 */
/*03d0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0400*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020c */
/*0410*/ FADD R21, R2, R2 ; /* 0x0000000202157221 */
/* 0x004fca0000000000 */
/*0420*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0.reuse, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x041fe200078e0204 */
/*0450*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0460*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0470*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0480*/ FADD R9, R14, R14 ; /* 0x0000000e0e097221 */
/* 0x004fca0000000000 */
/*0490*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04a0*/ @!P0 BRA 0x320 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} | .file "tmpxft_000fbd83_00000000-6_host_api_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
.type _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i, @function
_Z38__device_stub__Z15host_api_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15host_api_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i, .-_Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
.globl _Z15host_api_kernelPfS_i
.type _Z15host_api_kernelPfS_i, @function
_Z15host_api_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15host_api_kernelPfS_i, .-_Z15host_api_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15host_api_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15host_api_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15host_api_kernelPfS_i
.globl _Z15host_api_kernelPfS_i
.p2align 8
.type _Z15host_api_kernelPfS_i,@function
_Z15host_api_kernelPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v0
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15host_api_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15host_api_kernelPfS_i, .Lfunc_end0-_Z15host_api_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15host_api_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15host_api_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void host_api_kernel(float *randomValues, float *out, int N)
{
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int nthreads = gridDim.x * blockDim.x;
for (i = tid; i < N; i += nthreads)
{
float rand = randomValues[i];
rand = rand * 2;
out[i] = rand;
}
} | .text
.file "host_api_kernel.hip"
.globl _Z30__device_stub__host_api_kernelPfS_i # -- Begin function _Z30__device_stub__host_api_kernelPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__host_api_kernelPfS_i,@function
_Z30__device_stub__host_api_kernelPfS_i: # @_Z30__device_stub__host_api_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15host_api_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__host_api_kernelPfS_i, .Lfunc_end0-_Z30__device_stub__host_api_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15host_api_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15host_api_kernelPfS_i,@object # @_Z15host_api_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z15host_api_kernelPfS_i
.p2align 3, 0x0
_Z15host_api_kernelPfS_i:
.quad _Z30__device_stub__host_api_kernelPfS_i
.size _Z15host_api_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15host_api_kernelPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__host_api_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15host_api_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15host_api_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02c0*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */
/* 0x004fca0000000000 */
/*02d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x270 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0330*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0206 */
/*0340*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0360*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0370*/ FADD R17, R2, R2 ; /* 0x0000000202117221 */
/* 0x004fca0000000000 */
/*0380*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0208 */
/*03c0*/ FADD R19, R2, R2 ; /* 0x0000000202137221 */
/* 0x004fca0000000000 */
/*03d0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0400*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020c */
/*0410*/ FADD R21, R2, R2 ; /* 0x0000000202157221 */
/* 0x004fca0000000000 */
/*0420*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0.reuse, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x041fe200078e0204 */
/*0450*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0460*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0470*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0480*/ FADD R9, R14, R14 ; /* 0x0000000e0e097221 */
/* 0x004fca0000000000 */
/*0490*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04a0*/ @!P0 BRA 0x320 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15host_api_kernelPfS_i
.globl _Z15host_api_kernelPfS_i
.p2align 8
.type _Z15host_api_kernelPfS_i,@function
_Z15host_api_kernelPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v0
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15host_api_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15host_api_kernelPfS_i, .Lfunc_end0-_Z15host_api_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15host_api_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15host_api_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fbd83_00000000-6_host_api_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
.type _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i, @function
_Z38__device_stub__Z15host_api_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15host_api_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i, .-_Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
.globl _Z15host_api_kernelPfS_i
.type _Z15host_api_kernelPfS_i, @function
_Z15host_api_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15host_api_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15host_api_kernelPfS_i, .-_Z15host_api_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15host_api_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15host_api_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "host_api_kernel.hip"
.globl _Z30__device_stub__host_api_kernelPfS_i # -- Begin function _Z30__device_stub__host_api_kernelPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__host_api_kernelPfS_i,@function
_Z30__device_stub__host_api_kernelPfS_i: # @_Z30__device_stub__host_api_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15host_api_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__host_api_kernelPfS_i, .Lfunc_end0-_Z30__device_stub__host_api_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15host_api_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15host_api_kernelPfS_i,@object # @_Z15host_api_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z15host_api_kernelPfS_i
.p2align 3, 0x0
_Z15host_api_kernelPfS_i:
.quad _Z30__device_stub__host_api_kernelPfS_i
.size _Z15host_api_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15host_api_kernelPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__host_api_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15host_api_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} | code for sm_80
Function : _Z18transposeCoalescedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R5, R4, 0x4 ; /* 0x0000000405007211 */
/* 0x001fc400078e20ff */
/*0080*/ LEA R3, R9, R6, 0x4 ; /* 0x0000000609037211 */
/* 0x002fca00078e20ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R11, R6, R4.reuse, 0x4 ; /* 0x00000004060b7211 */
/* 0x080fe200078e20ff */
/*00d0*/ IMAD R7, R4, 0x10, R6 ; /* 0x0000001004077824 */
/* 0x000fe200078e0206 */
/*00e0*/ LEA R0, R9, R4, 0x4 ; /* 0x0000000409007211 */
/* 0x000fe400078e20ff */
/*00f0*/ LEA R5, R5, R6, 0x4 ; /* 0x0000000605057211 */
/* 0x000fca00078e20ff */
/*0100*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} | .file "tmpxft_0016e661_00000000-6_transposeCoalesced.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeCoalescedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
.globl _Z18transposeCoalescedPfS_ii
.type _Z18transposeCoalescedPfS_ii, @function
_Z18transposeCoalescedPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeCoalescedPfS_ii, .-_Z18transposeCoalescedPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeCoalescedPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeCoalescedPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeCoalescedPfS_ii
.globl _Z18transposeCoalescedPfS_ii
.p2align 8
.type _Z18transposeCoalescedPfS_ii,@function
_Z18transposeCoalescedPfS_ii:
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 4
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, s6, v2
v_lshlrev_b32_e32 v5, 2, v2
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v1, s4
s_lshl_b32 s4, s14, 4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s4, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_add_nc_u32_e32 v0, s4, v2
v_lshl_add_u32 v2, v2, 6, v4
v_lshl_add_u32 v4, v3, 6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s5
v_add3_u32 v0, s6, v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeCoalescedPfS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeCoalescedPfS_ii, .Lfunc_end0-_Z18transposeCoalescedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeCoalescedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeCoalescedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeCoalesced(float *odata, float *idata, int width, int height)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex)*width;
xIndex = blockIdx.y * TILE_DIM + threadIdx.x;
yIndex = blockIdx.x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex)*height;
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
tile[threadIdx.y+i][threadIdx.x] = idata[index_in+i*width];
}
__syncthreads();
for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS)
{
odata[index_out+i*height] = tile[threadIdx.x][threadIdx.y+i];
}
} | .text
.file "transposeCoalesced.hip"
.globl _Z33__device_stub__transposeCoalescedPfS_ii # -- Begin function _Z33__device_stub__transposeCoalescedPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeCoalescedPfS_ii,@function
_Z33__device_stub__transposeCoalescedPfS_ii: # @_Z33__device_stub__transposeCoalescedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeCoalescedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeCoalescedPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeCoalescedPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeCoalescedPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeCoalescedPfS_ii,@object # @_Z18transposeCoalescedPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeCoalescedPfS_ii
.p2align 3, 0x0
_Z18transposeCoalescedPfS_ii:
.quad _Z33__device_stub__transposeCoalescedPfS_ii
.size _Z18transposeCoalescedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeCoalescedPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeCoalescedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeCoalescedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18transposeCoalescedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R5, R4, 0x4 ; /* 0x0000000405007211 */
/* 0x001fc400078e20ff */
/*0080*/ LEA R3, R9, R6, 0x4 ; /* 0x0000000609037211 */
/* 0x002fca00078e20ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R11, R6, R4.reuse, 0x4 ; /* 0x00000004060b7211 */
/* 0x080fe200078e20ff */
/*00d0*/ IMAD R7, R4, 0x10, R6 ; /* 0x0000001004077824 */
/* 0x000fe200078e0206 */
/*00e0*/ LEA R0, R9, R4, 0x4 ; /* 0x0000000409007211 */
/* 0x000fe400078e20ff */
/*00f0*/ LEA R5, R5, R6, 0x4 ; /* 0x0000000605057211 */
/* 0x000fca00078e20ff */
/*0100*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeCoalescedPfS_ii
.globl _Z18transposeCoalescedPfS_ii
.p2align 8
.type _Z18transposeCoalescedPfS_ii,@function
_Z18transposeCoalescedPfS_ii:
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 4
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, s6, v2
v_lshlrev_b32_e32 v5, 2, v2
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v1, s4
s_lshl_b32 s4, s14, 4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s4, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_add_nc_u32_e32 v0, s4, v2
v_lshl_add_u32 v2, v2, 6, v4
v_lshl_add_u32 v4, v3, 6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s5
v_add3_u32 v0, s6, v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeCoalescedPfS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeCoalescedPfS_ii, .Lfunc_end0-_Z18transposeCoalescedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeCoalescedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeCoalescedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016e661_00000000-6_transposeCoalesced.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeCoalescedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
.globl _Z18transposeCoalescedPfS_ii
.type _Z18transposeCoalescedPfS_ii, @function
_Z18transposeCoalescedPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeCoalescedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeCoalescedPfS_ii, .-_Z18transposeCoalescedPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeCoalescedPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeCoalescedPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transposeCoalesced.hip"
.globl _Z33__device_stub__transposeCoalescedPfS_ii # -- Begin function _Z33__device_stub__transposeCoalescedPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeCoalescedPfS_ii,@function
_Z33__device_stub__transposeCoalescedPfS_ii: # @_Z33__device_stub__transposeCoalescedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeCoalescedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeCoalescedPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeCoalescedPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeCoalescedPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeCoalescedPfS_ii,@object # @_Z18transposeCoalescedPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeCoalescedPfS_ii
.p2align 3, 0x0
_Z18transposeCoalescedPfS_ii:
.quad _Z33__device_stub__transposeCoalescedPfS_ii
.size _Z18transposeCoalescedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeCoalescedPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeCoalescedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeCoalescedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z6matmulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0070*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0120*/ IADD3 R2, R8, R9, RZ ; /* 0x0000000908027210 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0140*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc40000000f00 */
/*0150*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0160*/ @!P0 BRA 0xcb0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R10, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040a7a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R14, R8, R5, c[0x0][0x168] ; /* 0x00005a00080e7625 */
/* 0x000fe200078e0205 */
/*01b0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD R19, R12, R16, R13 ; /* 0x000000100c137224 */
/* 0x004fe400078e020d */
/*0270*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*0310*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c04060c7981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0360*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R14, [R6.64+0x14] ; /* 0x00001404060e7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*0400*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0450*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R14, [R6.64+0x20] ; /* 0x00002004060e7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*04f0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R12, [R6.64+0x24] ; /* 0x00002404060c7981 */
/* 0x000e24000c1e1900 */
/*0530*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0540*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R14, [R6.64+0x2c] ; /* 0x00002c04060e7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*05e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0630*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R21, R18, R16, R25 ; /* 0x0000001012157224 */
/* 0x001fc400078e0219 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x002fc400078e0215 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R14, [R6.64+0x3c] ; /* 0x00003c04060e7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD R13, R12, R14, R23 ; /* 0x0000000e0c0d7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD R19, R12, R16, R13 ; /* 0x000000100c137224 */
/* 0x008fe400078e020d */
/*0820*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x004fc600078e020e */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*08c0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c04060c7981 */
/* 0x000e24000c1e1900 */
/*0900*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0910*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R14, [R6.64+0x14] ; /* 0x00001404060e7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*09b0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x001fc600078e020e */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R13, [R6.64+0x1c] ; /* 0x00001c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ IMAD R13, R12, R13, R25 ; /* 0x0000000d0c0d7224 */
/* 0x004fca00078e0219 */
/*0ab0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD R21, R12, R16, R13 ; /* 0x000000100c157224 */
/* 0x00efe400078e020d */
/*0b40*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R23, R16, R17, R21 ; /* 0x0000001110177224 */
/* 0x004fc400078e0215 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ IMAD R13, R12, R14, R25 ; /* 0x0000000e0c0d7224 */
/* 0x004fe400078e0219 */
/*0c80*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ IADD3 R6, R9, R11, RZ ; /* 0x0000000b09067210 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a24 */
/* 0x000fc800078e0208 */
/*0cf0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0205 */
/*0d10*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d20*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d40*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d50*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d60*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d80*/ IMAD R13, R10, R5, R13 ; /* 0x000000050a0d7224 */
/* 0x00efca00078e020d */
/*0d90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0da0*/ @P0 BRA 0xd10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000187e7_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6matmulPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
.globl _Z6matmulPiS_S_i
.type _Z6matmulPiS_S_i, @function
_Z6matmulPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matmulPiS_S_i, .-_Z6matmulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Elements of matA\n"
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.LC3:
.string "Elements of matB\n"
.LC4:
.string "Elements of MatC\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $3136, %rsp
.cfi_def_cfa_offset 3184
movq %fs:40, %rax
movq %rax, 3128(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 112(%rsp), %r12
movl $0, %ebp
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
.L12:
leaq -64(%r12), %rbx
.L13:
movl %ebp, (%rbx)
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
addq $64, %r12
cmpl $16, %ebp
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %rbp
leaq 2096(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L15:
movl $0, %ebx
.L16:
movl %ebx, %edx
movl %ebx, 0(%rbp,%rbx,4)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L16
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L18:
leaq 2096(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2160(%rsp), %rbp
leaq 3184(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L19:
leaq -64(%rbp), %rbx
.L20:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L19
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 3128(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $3136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $16, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6matmulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPiS_S_i
.globl _Z6matmulPiS_S_i
.p2align 8
.type _Z6matmulPiS_S_i,@function
_Z6matmulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v1, v1, s2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v8, vcc_lo
s_mov_b32 s0, s2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[2:3], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[4:5], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPiS_S_i, .Lfunc_end0-_Z6matmulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define BLOCK_DIM 1
#define N 16
__global__ void matmul(int *a, int *b, int *c, int width)
{
int k, sum=0;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(col<width && row<width){
for(k=0;k<width;k++){
sum+=a[row*width+k]*b[k*width+col];
c[row*width+col]=sum;
}
}
}
int main(void)
{
int a[N][N],b[N][N],c[N][N];
int *d_a,*d_b,*d_c;
int size = sizeof(int) * N * N;
printf("Elements of matA\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
a[i][j]=i;
printf("%d\t",a[i][j]);
}
printf("\n");
}
printf("Elements of matB\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
b[i][j]=j;
printf("%d\t",b[i][j]);
}
printf("\n");
}
printf("\n");
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM,BLOCK_DIM);
dim3 dimGrid((int)(N/dimBlock.x),(int)(N/dimBlock.y));
matmul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,N);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
printf("Elements of MatC\n");
for(int i=0;i<N;i++)
{
for(int j=0;j<N;j++)
{
printf("%d\t",c[i][j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "matrixMultiplication.hip"
.globl _Z21__device_stub__matmulPiS_S_i # -- Begin function _Z21__device_stub__matmulPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPiS_S_i,@function
_Z21__device_stub__matmulPiS_S_i: # @_Z21__device_stub__matmulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPiS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $3184, %rsp # imm = 0xC70
.cfi_def_cfa_offset 3216
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 2160(%rsp), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.preheader50
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%r15,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $64, %r14
cmpq $16, %rbx
jne .LBB1_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 1136(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_5
# %bb.8:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 24(%rsp), %rdi
leaq 2160(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 1136(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matmulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $64, %rbx
cmpq $16, %r14
jne .LBB1_11
# %bb.14:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $3184, %rsp # imm = 0xC70
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPiS_S_i,@object # @_Z6matmulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPiS_S_i
.p2align 3, 0x0
_Z6matmulPiS_S_i:
.quad _Z21__device_stub__matmulPiS_S_i
.size _Z6matmulPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Elements of matA"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Elements of matB"
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Elements of MatC"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0070*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0120*/ IADD3 R2, R8, R9, RZ ; /* 0x0000000908027210 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0140*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc40000000f00 */
/*0150*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0160*/ @!P0 BRA 0xcb0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R10, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040a7a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R14, R8, R5, c[0x0][0x168] ; /* 0x00005a00080e7625 */
/* 0x000fe200078e0205 */
/*01b0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD R19, R12, R16, R13 ; /* 0x000000100c137224 */
/* 0x004fe400078e020d */
/*0270*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*0310*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c04060c7981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0360*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R14, [R6.64+0x14] ; /* 0x00001404060e7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*0400*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0450*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R14, [R6.64+0x20] ; /* 0x00002004060e7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*04f0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R12, [R6.64+0x24] ; /* 0x00002404060c7981 */
/* 0x000e24000c1e1900 */
/*0530*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0540*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R14, [R6.64+0x2c] ; /* 0x00002c04060e7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*05e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0630*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R21, R18, R16, R25 ; /* 0x0000001012157224 */
/* 0x001fc400078e0219 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x002fc400078e0215 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R14, [R6.64+0x3c] ; /* 0x00003c04060e7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD R13, R12, R14, R23 ; /* 0x0000000e0c0d7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD R19, R12, R16, R13 ; /* 0x000000100c137224 */
/* 0x008fe400078e020d */
/*0820*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x004fc600078e020e */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*08c0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c04060c7981 */
/* 0x000e24000c1e1900 */
/*0900*/ IMAD R19, R18, R12, R23 ; /* 0x0000000c12137224 */
/* 0x001fc400078e0217 */
/*0910*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R14, [R6.64+0x14] ; /* 0x00001404060e7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ IMAD R23, R18, R14, R21 ; /* 0x0000000e12177224 */
/* 0x004fc400078e0215 */
/*09b0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x001fc600078e020e */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R13, [R6.64+0x1c] ; /* 0x00001c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ IMAD R13, R12, R13, R25 ; /* 0x0000000d0c0d7224 */
/* 0x004fca00078e0219 */
/*0ab0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD R21, R12, R16, R13 ; /* 0x000000100c157224 */
/* 0x00efe400078e020d */
/*0b40*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R23, R16, R17, R21 ; /* 0x0000001110177224 */
/* 0x004fc400078e0215 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ IMAD R13, R12, R14, R25 ; /* 0x0000000e0c0d7224 */
/* 0x004fe400078e0219 */
/*0c80*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ IADD3 R6, R9, R11, RZ ; /* 0x0000000b09067210 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a24 */
/* 0x000fc800078e0208 */
/*0cf0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0205 */
/*0d10*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d20*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d40*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d50*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d60*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d80*/ IMAD R13, R10, R5, R13 ; /* 0x000000050a0d7224 */
/* 0x00efca00078e020d */
/*0d90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0da0*/ @P0 BRA 0xd10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPiS_S_i
.globl _Z6matmulPiS_S_i
.p2align 8
.type _Z6matmulPiS_S_i,@function
_Z6matmulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v1, v1, s2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v8, vcc_lo
s_mov_b32 s0, s2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[2:3], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[4:5], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPiS_S_i, .Lfunc_end0-_Z6matmulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000187e7_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6matmulPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
.globl _Z6matmulPiS_S_i
.type _Z6matmulPiS_S_i, @function
_Z6matmulPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matmulPiS_S_i, .-_Z6matmulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Elements of matA\n"
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.LC3:
.string "Elements of matB\n"
.LC4:
.string "Elements of MatC\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $3136, %rsp
.cfi_def_cfa_offset 3184
movq %fs:40, %rax
movq %rax, 3128(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 112(%rsp), %r12
movl $0, %ebp
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
.L12:
leaq -64(%r12), %rbx
.L13:
movl %ebp, (%rbx)
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
addq $64, %r12
cmpl $16, %ebp
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %rbp
leaq 2096(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L15:
movl $0, %ebx
.L16:
movl %ebx, %edx
movl %ebx, 0(%rbp,%rbx,4)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L16
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L18:
leaq 2096(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2160(%rsp), %rbp
leaq 3184(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L19:
leaq -64(%rbp), %rbx
.L20:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L19
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 3128(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $3136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $16, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z6matmulPiS_S_iPiS_S_i
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6matmulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiplication.hip"
.globl _Z21__device_stub__matmulPiS_S_i # -- Begin function _Z21__device_stub__matmulPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPiS_S_i,@function
_Z21__device_stub__matmulPiS_S_i: # @_Z21__device_stub__matmulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPiS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $3184, %rsp # imm = 0xC70
.cfi_def_cfa_offset 3216
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 2160(%rsp), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.preheader50
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%r15,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $64, %r14
cmpq $16, %rbx
jne .LBB1_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 1136(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_5
# %bb.8:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 24(%rsp), %rdi
leaq 2160(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 1136(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matmulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $64, %rbx
cmpq $16, %r14
jne .LBB1_11
# %bb.14:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $3184, %rsp # imm = 0xC70
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPiS_S_i,@object # @_Z6matmulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPiS_S_i
.p2align 3, 0x0
_Z6matmulPiS_S_i:
.quad _Z21__device_stub__matmulPiS_S_i
.size _Z6matmulPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Elements of matA"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Elements of matB"
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Elements of MatC"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
cudaMalloc((void**)&d_a, N*sizeof(float));
cudaMalloc((void**)&d_b, N*sizeof(float));
cudaMalloc((void**)&d_partsum, num_blocks*sizeof(float));
cudaMemcpy(d_a, &h_a, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, N*sizeof(float), cudaMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
cudaDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
cudaMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} | code for sm_80
Function : _Z13blockwise_dotIfEvPT_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x3ff, PT ; /* 0x000003ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
cudaMalloc((void**)&d_a, N*sizeof(float));
cudaMalloc((void**)&d_b, N*sizeof(float));
cudaMalloc((void**)&d_partsum, num_blocks*sizeof(float));
cudaMemcpy(d_a, &h_a, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, N*sizeof(float), cudaMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
cudaDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
cudaMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} | .file "tmpxft_00175a20_00000000-6_12_dot_product.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z13blockwise_dotIfEvPT_S1_S1_
.type _Z13blockwise_dotIfEvPT_S1_S1_, @function
_Z13blockwise_dotIfEvPT_S1_S1_:
.LFB3999:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13blockwise_dotIfEvPT_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3999:
.size _Z13blockwise_dotIfEvPT_S1_S1_, .-_Z13blockwise_dotIfEvPT_S1_S1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "#blocks %d #threads/block %d\n"
.LC3:
.string "result = "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8200
orq $0, (%rsp)
subq $104, %rsp
.cfi_def_cfa_offset 8304
movq %fs:40, %rax
movq %rax, 8280(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm1
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 80(%rsp,%rax,4)
movss %xmm1, 4176(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L10
movl $512, %ecx
movl $2, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
call cudaDeviceSynchronize@PLT
leaq 72(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
addss 72(%rsp), %xmm0
addss 76(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8280(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $8296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z13blockwise_dotIfEvPT_S1_S1_
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z13blockwise_dotIfEvPT_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13blockwise_dotIfEvPT_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
cudaMalloc((void**)&d_a, N*sizeof(float));
cudaMalloc((void**)&d_b, N*sizeof(float));
cudaMalloc((void**)&d_partsum, num_blocks*sizeof(float));
cudaMemcpy(d_a, &h_a, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, N*sizeof(float), cudaMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
cudaDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
cudaMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
hipMalloc((void**)&d_a, N*sizeof(float));
hipMalloc((void**)&d_b, N*sizeof(float));
hipMalloc((void**)&d_partsum, num_blocks*sizeof(float));
hipMemcpy(d_a, &h_a, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, N*sizeof(float), hipMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
hipDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
hipMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), hipMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
hipMalloc((void**)&d_a, N*sizeof(float));
hipMalloc((void**)&d_b, N*sizeof(float));
hipMalloc((void**)&d_partsum, num_blocks*sizeof(float));
hipMemcpy(d_a, &h_a, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, N*sizeof(float), hipMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
hipDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
hipMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), hipMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.protected _Z13blockwise_dotIfEvPT_S1_S1_
.globl _Z13blockwise_dotIfEvPT_S1_S1_
.p2align 8
.type _Z13blockwise_dotIfEvPT_S1_S1_,@function
_Z13blockwise_dotIfEvPT_S1_S1_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x3ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13blockwise_dotIfEvPT_S1_S1_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.Lfunc_end0:
.size _Z13blockwise_dotIfEvPT_S1_S1_, .Lfunc_end0-_Z13blockwise_dotIfEvPT_S1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13blockwise_dotIfEvPT_S1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13blockwise_dotIfEvPT_S1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
#define N 1024
#define threads_per_block 512
template<typename T>
__global__ void blockwise_dot(T *d_a, T *d_b, T *block_sum)
{
__shared__ T partial_sum [threads_per_block];
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = threadIdx.x;
T sum=0;
while(tid < N)
{
sum += d_a[tid]*d_b[tid];
tid += blockDim.x * gridDim.x;
}
//store partial sum of threads of current block
//in quickly accessible shared memory
partial_sum[idx] = sum;
//sync all threads
__syncthreads();
int i = blockDim.x /2;
while(i != 0)
{
if(idx < i)
partial_sum[idx] += partial_sum[idx+i];
__syncthreads();
i /= 2;
}
if(idx == 0)
block_sum[blockIdx.x] = partial_sum[0];
}
int main()
{
int num_blocks = std::ceil(float(N)/threads_per_block);
float h_a[N], h_b[N], *d_a, *d_b, *d_partsum;
for(int i=0; i<N; i++)
{
h_a[i] = i; h_b[i] = 1;
}
printf("#blocks %d #threads/block %d\n", num_blocks, threads_per_block);
hipMalloc((void**)&d_a, N*sizeof(float));
hipMalloc((void**)&d_b, N*sizeof(float));
hipMalloc((void**)&d_partsum, num_blocks*sizeof(float));
hipMemcpy(d_a, &h_a, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, N*sizeof(float), hipMemcpyHostToDevice);
blockwise_dot<float> <<<num_blocks,threads_per_block>>> (d_a, d_b, d_partsum);
hipDeviceSynchronize();
float h_partsum[num_blocks], total_sum=0;
hipMemcpy(&h_partsum, d_partsum, num_blocks*sizeof(float), hipMemcpyDeviceToHost);
for(int i=0; i<num_blocks; i++)
{
// printf("%.3f ", h_partsum[i]);
total_sum += h_partsum[i];
}
std:: cout << "result = " << total_sum << "\n";
} | .text
.file "12_dot_product.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r14
pushq %rbx
subq $8320, %rsp # imm = 0x2080
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -8336(%rbp,%rax,4)
movl $1065353216, -4240(%rbp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
movl $2, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
leaq -48(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -40(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -32(%rbp), %rdi
movl $8, %esi
callq hipMalloc
movq -48(%rbp), %rdi
leaq -8336(%rbp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq -40(%rbp), %rdi
leaq -4240(%rbp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq -48(%rbp), %rax
movq -40(%rbp), %rcx
movq -32(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
leaq -120(%rbp), %rax
movq %rax, -144(%rbp)
leaq -112(%rbp), %rax
movq %rax, -136(%rbp)
leaq -104(%rbp), %rax
movq %rax, -128(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -144(%rbp), %r9
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB0_4:
callq hipDeviceSynchronize
movq %rsp, %r14
movq %rsp, %rbx
addq $-16, %rbx
movq %rbx, %rsp
movq -32(%rbp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $1, %rax
je .LBB0_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
movss %xmm0, -20(%rbp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -20(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rsp
xorl %eax, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r14
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_ # -- Begin function _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.p2align 4, 0x90
.type _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,@function
_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_: # @_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_, .Lfunc_end1-_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "#blocks %d #threads/block %d\n"
.size .L.str, 30
.type _Z13blockwise_dotIfEvPT_S1_S1_,@object # @_Z13blockwise_dotIfEvPT_S1_S1_
.section .rodata._Z13blockwise_dotIfEvPT_S1_S1_,"aG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z13blockwise_dotIfEvPT_S1_S1_
.p2align 3, 0x0
_Z13blockwise_dotIfEvPT_S1_S1_:
.quad _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.size _Z13blockwise_dotIfEvPT_S1_S1_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "result = "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13blockwise_dotIfEvPT_S1_S1_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13blockwise_dotIfEvPT_S1_S1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13blockwise_dotIfEvPT_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x3ff, PT ; /* 0x000003ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.protected _Z13blockwise_dotIfEvPT_S1_S1_
.globl _Z13blockwise_dotIfEvPT_S1_S1_
.p2align 8
.type _Z13blockwise_dotIfEvPT_S1_S1_,@function
_Z13blockwise_dotIfEvPT_S1_S1_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x3ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13blockwise_dotIfEvPT_S1_S1_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.Lfunc_end0:
.size _Z13blockwise_dotIfEvPT_S1_S1_, .Lfunc_end0-_Z13blockwise_dotIfEvPT_S1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13blockwise_dotIfEvPT_S1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13blockwise_dotIfEvPT_S1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00175a20_00000000-6_12_dot_product.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z13blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z13blockwise_dotIfEvPT_S1_S1_
.type _Z13blockwise_dotIfEvPT_S1_S1_, @function
_Z13blockwise_dotIfEvPT_S1_S1_:
.LFB3999:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13blockwise_dotIfEvPT_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3999:
.size _Z13blockwise_dotIfEvPT_S1_S1_, .-_Z13blockwise_dotIfEvPT_S1_S1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "#blocks %d #threads/block %d\n"
.LC3:
.string "result = "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8200
orq $0, (%rsp)
subq $104, %rsp
.cfi_def_cfa_offset 8304
movq %fs:40, %rax
movq %rax, 8280(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm1
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 80(%rsp,%rax,4)
movss %xmm1, 4176(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L10
movl $512, %ecx
movl $2, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
call cudaDeviceSynchronize@PLT
leaq 72(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
addss 72(%rsp), %xmm0
addss 76(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8280(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $8296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z13blockwise_dotIfEvPT_S1_S1_
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z13blockwise_dotIfEvPT_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13blockwise_dotIfEvPT_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "12_dot_product.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r14
pushq %rbx
subq $8320, %rsp # imm = 0x2080
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -8336(%rbp,%rax,4)
movl $1065353216, -4240(%rbp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
movl $2, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
leaq -48(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -40(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -32(%rbp), %rdi
movl $8, %esi
callq hipMalloc
movq -48(%rbp), %rdi
leaq -8336(%rbp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq -40(%rbp), %rdi
leaq -4240(%rbp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq -48(%rbp), %rax
movq -40(%rbp), %rcx
movq -32(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
leaq -120(%rbp), %rax
movq %rax, -144(%rbp)
leaq -112(%rbp), %rax
movq %rax, -136(%rbp)
leaq -104(%rbp), %rax
movq %rax, -128(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -144(%rbp), %r9
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB0_4:
callq hipDeviceSynchronize
movq %rsp, %r14
movq %rsp, %rbx
addq $-16, %rbx
movq %rbx, %rsp
movq -32(%rbp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $1, %rax
je .LBB0_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
movss %xmm0, -20(%rbp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -20(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rsp
xorl %eax, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r14
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,"axG",@progbits,_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_ # -- Begin function _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.p2align 4, 0x90
.type _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_,@function
_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_: # @_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_, .Lfunc_end1-_Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13blockwise_dotIfEvPT_S1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "#blocks %d #threads/block %d\n"
.size .L.str, 30
.type _Z13blockwise_dotIfEvPT_S1_S1_,@object # @_Z13blockwise_dotIfEvPT_S1_S1_
.section .rodata._Z13blockwise_dotIfEvPT_S1_S1_,"aG",@progbits,_Z13blockwise_dotIfEvPT_S1_S1_,comdat
.weak _Z13blockwise_dotIfEvPT_S1_S1_
.p2align 3, 0x0
_Z13blockwise_dotIfEvPT_S1_S1_:
.quad _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.size _Z13blockwise_dotIfEvPT_S1_S1_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "result = "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13blockwise_dotIfEvPT_S1_S1_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__blockwise_dotIfEvPT_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13blockwise_dotIfEvPT_S1_S1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
cudaMemGetInfo(&m_free, &m_total);
cudaMalloc((void **)&array, 20*1024*1024*sizeof(double));
cudaMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
cudaMemGetInfo(&m_free, &m_total);
cudaMalloc((void **)&array, 20*1024*1024*sizeof(double));
cudaMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} | .file "tmpxft_000b8027_00000000-6_mem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Livre: %ld, Total %ld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rbp
movq %rsp, %rbx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemGetInfo@PLT
leaq 16(%rsp), %rdi
movl $167772160, %esi
call cudaMalloc@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemGetInfo@PLT
movq 8(%rsp), %rcx
movq (%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
cudaMemGetInfo(&m_free, &m_total);
cudaMalloc((void **)&array, 20*1024*1024*sizeof(double));
cudaMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
hipMemGetInfo(&m_free, &m_total);
hipMalloc((void **)&array, 20*1024*1024*sizeof(double));
hipMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
hipMemGetInfo(&m_free, &m_total);
hipMalloc((void **)&array, 20*1024*1024*sizeof(double));
hipMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main()
{
size_t m_free, m_total;
double* array;
hipMemGetInfo(&m_free, &m_total);
hipMalloc((void **)&array, 20*1024*1024*sizeof(double));
hipMemGetInfo(&m_free, &m_total);
printf("Livre: %ld, Total %ld\n", m_free, m_total);
return 0;
} | .text
.file "mem.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rbx
movq %rsp, %r14
movq %rbx, %rdi
movq %r14, %rsi
callq hipMemGetInfo
leaq 16(%rsp), %rdi
movl $167772160, %esi # imm = 0xA000000
callq hipMalloc
movq %rbx, %rdi
movq %r14, %rsi
callq hipMemGetInfo
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Livre: %ld, Total %ld\n"
.size .L.str, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b8027_00000000-6_mem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Livre: %ld, Total %ld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rbp
movq %rsp, %rbx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemGetInfo@PLT
leaq 16(%rsp), %rdi
movl $167772160, %esi
call cudaMalloc@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemGetInfo@PLT
movq 8(%rsp), %rcx
movq (%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mem.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rbx
movq %rsp, %r14
movq %rbx, %rdi
movq %r14, %rsi
callq hipMemGetInfo
leaq 16(%rsp), %rdi
movl $167772160, %esi # imm = 0xA000000
callq hipMalloc
movq %rbx, %rdi
movq %r14, %rsi
callq hipMemGetInfo
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Livre: %ld, Total %ld\n"
.size .L.str, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} | code for sm_80
Function : _Z3incPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ LEA R2, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004027a11 */
/* 0x001fc800078010ff */
/*00c0*/ LEA.HI.X R3, R4, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f1407 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R9, R6, c[0x0][0xc], RZ ; /* 0x0000030006097a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R4, P0, R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fca0007f1e0ff */
/*0100*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fc80003f06070 */
/*0120*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe40003f06100 */
/*0130*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*0150*/ @!P0 BRA 0xb0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} | .file "tmpxft_001bdcb3_00000000-6_inc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3incPimPim
.type _Z23__device_stub__Z3incPimPim, @function
_Z23__device_stub__Z3incPimPim:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3incPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3incPimPim, .-_Z23__device_stub__Z3incPimPim
.globl _Z3incPim
.type _Z3incPim, @function
_Z3incPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3incPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3incPim, .-_Z3incPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3incPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3incPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3incPim
.globl _Z3incPim
.p2align 8
.type _Z3incPim,@function
_Z3incPim:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s1, s5
.LBB0_2:
global_load_b32 v0, v[3:4], off
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
global_store_b32 v[3:4], v0, off
v_add_co_u32 v3, s0, v3, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3incPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3incPim, .Lfunc_end0-_Z3incPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3incPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3incPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inc(int *array, size_t n){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
while (idx < n){
array[idx]++;
idx += blockDim.x*gridDim.x; // grid-stride loop
}
} | .text
.file "inc.hip"
.globl _Z18__device_stub__incPim # -- Begin function _Z18__device_stub__incPim
.p2align 4, 0x90
.type _Z18__device_stub__incPim,@function
_Z18__device_stub__incPim: # @_Z18__device_stub__incPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3incPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__incPim, .Lfunc_end0-_Z18__device_stub__incPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3incPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3incPim,@object # @_Z3incPim
.section .rodata,"a",@progbits
.globl _Z3incPim
.p2align 3, 0x0
_Z3incPim:
.quad _Z18__device_stub__incPim
.size _Z3incPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3incPim"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__incPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3incPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3incPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ LEA R2, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004027a11 */
/* 0x001fc800078010ff */
/*00c0*/ LEA.HI.X R3, R4, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f1407 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R9, R6, c[0x0][0xc], RZ ; /* 0x0000030006097a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R4, P0, R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fca0007f1e0ff */
/*0100*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fc80003f06070 */
/*0120*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe40003f06100 */
/*0130*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*0150*/ @!P0 BRA 0xb0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3incPim
.globl _Z3incPim
.p2align 8
.type _Z3incPim,@function
_Z3incPim:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s1, s5
.LBB0_2:
global_load_b32 v0, v[3:4], off
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
global_store_b32 v[3:4], v0, off
v_add_co_u32 v3, s0, v3, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3incPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3incPim, .Lfunc_end0-_Z3incPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3incPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3incPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bdcb3_00000000-6_inc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3incPimPim
.type _Z23__device_stub__Z3incPimPim, @function
_Z23__device_stub__Z3incPimPim:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3incPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3incPimPim, .-_Z23__device_stub__Z3incPimPim
.globl _Z3incPim
.type _Z3incPim, @function
_Z3incPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3incPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3incPim, .-_Z3incPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3incPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3incPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "inc.hip"
.globl _Z18__device_stub__incPim # -- Begin function _Z18__device_stub__incPim
.p2align 4, 0x90
.type _Z18__device_stub__incPim,@function
_Z18__device_stub__incPim: # @_Z18__device_stub__incPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3incPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__incPim, .Lfunc_end0-_Z18__device_stub__incPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3incPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3incPim,@object # @_Z3incPim
.section .rodata,"a",@progbits
.globl _Z3incPim
.p2align 3, 0x0
_Z3incPim:
.quad _Z18__device_stub__incPim
.size _Z3incPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3incPim"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__incPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3incPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} | code for sm_80
Function : _Z9max_flopsIiEvPjS0_PT_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ MOV R5, 0xa ; /* 0x0000000a00057802 */
/* 0x000fd20000000f00 */
/*0090*/ IMAD.WIDE R2, R8, R9, c[0x0][0x170] ; /* 0x00005c0008027625 */
/* 0x000fca00078e0209 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00b0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00d0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0100*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0110*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0120*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0130*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0140*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0150*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0160*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0180*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ CS2R.32 R13, SR_CLOCKLO ; /* 0x00000000000d7805 */
/* 0x000fe40000005000 */
/*01c0*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fe200078e0209 */
/*01d0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fc40000000f00 */
/*01e0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe200078e0209 */
/*0200*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*0220*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fca00078e0209 */
/*0240*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} | .file "tmpxft_000bc012_00000000-6_atomic_add_bw.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.type _Z9max_flopsIiEvPjS0_PT_S2_, @function
_Z9max_flopsIiEvPjS0_PT_S2_:
.LFB4256:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4256:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .-_Z9max_flopsIiEvPjS0_PT_S2_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3923:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L15
ret
.L15:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L16
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3923:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_bw/atomic_add_bw.cu"
.align 8
.LC3:
.string "int32 bendwidth = %f (byte/clk)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB3926:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $655360, %edi
call malloc@PLT
movq %rax, %rbp
movl $655360, %edi
call malloc@PLT
movq %rax, %r12
movl $655360, %edi
call malloc@PLT
movq %rax, %rbx
movl $655360, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L18:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $163840, %rax
jne .L18
movq %rsp, %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $74, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $76, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $655360, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $78, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $160, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 655356(%r12), %rdx
leaq 4(%r12), %rax
.L21:
movl (%rax), %ecx
cmpl %ecx, (%r12)
cmovb %rax, %r12
addq $4, %rax
cmpq %rax, %rdx
jne .L21
movl (%r12), %ebx
leaq 655356(%rbp), %rdx
leaq 4(%rbp), %rax
.L23:
movl 0(%rbp), %esi
cmpl %esi, (%rax)
cmovb %rax, %rbp
addq $4, %rax
cmpq %rax, %rdx
jne .L23
subl 0(%rbp), %ebx
movl %ebx, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss .LC2(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9max_flopsIiEvPjS0_PT_S2_
jmp .L19
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3926:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9max_flopsIiEvPjS0_PT_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1260388352
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.protected _Z9max_flopsIiEvPjS0_PT_S2_
.globl _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 8
.type _Z9max_flopsIiEvPjS0_PT_S2_,@function
_Z9max_flopsIiEvPjS0_PT_S2_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
bar.sync 0
s_mov_b32 s5, 16
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 10
mov.u32 s4, %clock
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_1:
global_atomic_add_u32 v[3:4], v0, off
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[1:2]
bar.sync 0
mov.u32 s5, %clock
v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v2, v8, s[2:3]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_flopsIiEvPjS0_PT_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.Lfunc_end0:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .Lfunc_end0-_Z9max_flopsIiEvPjS0_PT_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_flopsIiEvPjS0_PT_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9max_flopsIiEvPjS0_PT_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#define THREADS_PER_BLOCK 1024
#define THREADS_PER_SM 2048
#define BLOCKS_NUM 160
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 16
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
atomicAdd(&data1[gid], 10);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (int32_t)i;
//data2[i] = (int32_t)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float bw;
uint32_t total_time = *std::max_element(&stopClk[0],&stopClk[TOTAL_THREADS-1])-*std::min_element(&startClk[0],&startClk[TOTAL_THREADS-1]);
bw = ((float)(REPEAT_TIMES*TOTAL_THREADS*4)/(float)(total_time));
printf("int32 bendwidth = %f (byte/clk)\n", bw);
printf("Total Clk number = %u \n", total_time);
return 0;
} | .text
.file "atomic_add_bw.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x4b200000 # float 10485760
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %rbx
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r14
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r12
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r12,%rax,4)
incq %rax
cmpq $163840, %rax # imm = 0x28000
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit18
leaq 8(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq %rsp, %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit22
movq 8(%rsp), %rdi
movl $655360, %edx # imm = 0xA0000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit24
movabsq $4294967456, %rdi # imm = 0x1000000A0
leaq 864(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit26
movq 24(%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit28
movq 16(%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit30
movq (%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_31
# %bb.22: # %.lr.ph.i.i.preheader
movl $4, %eax
movq %r14, %rcx
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_25: # %.lr.ph.i.i
# in Loop: Header=BB0_23 Depth=1
addq $4, %rax
cmpq $655356, %rax # imm = 0x9FFFC
je .LBB0_26
.LBB0_23: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movl (%rcx), %edx
cmpl (%r14,%rax), %edx
jae .LBB0_25
# %bb.24: # in Loop: Header=BB0_23 Depth=1
leaq (%r14,%rax), %rcx
jmp .LBB0_25
.LBB0_26: # %_ZSt11max_elementIPjET_S1_S1_.exit
movl (%rcx), %r14d
movl $4, %eax
movq %rbx, %rcx
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_29: # %.lr.ph.i.i33
# in Loop: Header=BB0_27 Depth=1
addq $4, %rax
cmpq $655356, %rax # imm = 0x9FFFC
je .LBB0_30
.LBB0_27: # %.lr.ph.i.i33
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rax), %edx
cmpl (%rcx), %edx
jae .LBB0_29
# %bb.28: # in Loop: Header=BB0_27 Depth=1
leaq (%rbx,%rax), %rcx
jmp .LBB0_29
.LBB0_30: # %_ZSt11min_elementIPjET_S1_S1_.exit
subl (%rcx), %r14d
cvtsi2ss %r14, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %r8d
jmp .LBB0_4
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB0_4
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB0_4
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB0_4
.LBB0_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_ # -- Begin function _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,@function
_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_: # @_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_, .Lfunc_end1-_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_bw/atomic_add_bw.hip"
.size .L.str, 194
.type _Z9max_flopsIiEvPjS0_PT_S2_,@object # @_Z9max_flopsIiEvPjS0_PT_S2_
.section .rodata._Z9max_flopsIiEvPjS0_PT_S2_,"aG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 3, 0x0
_Z9max_flopsIiEvPjS0_PT_S2_:
.quad _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.size _Z9max_flopsIiEvPjS0_PT_S2_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "int32 bendwidth = %f (byte/clk)\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsIiEvPjS0_PT_S2_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9max_flopsIiEvPjS0_PT_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ MOV R5, 0xa ; /* 0x0000000a00057802 */
/* 0x000fd20000000f00 */
/*0090*/ IMAD.WIDE R2, R8, R9, c[0x0][0x170] ; /* 0x00005c0008027625 */
/* 0x000fca00078e0209 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00b0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00d0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*00f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0100*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0110*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0120*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0130*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0140*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0150*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0160*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0180*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e8000c10e184 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ CS2R.32 R13, SR_CLOCKLO ; /* 0x00000000000d7805 */
/* 0x000fe40000005000 */
/*01c0*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fe200078e0209 */
/*01d0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fc40000000f00 */
/*01e0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe200078e0209 */
/*0200*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*0220*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fca00078e0209 */
/*0240*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.protected _Z9max_flopsIiEvPjS0_PT_S2_
.globl _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 8
.type _Z9max_flopsIiEvPjS0_PT_S2_,@function
_Z9max_flopsIiEvPjS0_PT_S2_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
bar.sync 0
s_mov_b32 s5, 16
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 10
mov.u32 s4, %clock
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_1:
global_atomic_add_u32 v[3:4], v0, off
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[1:2]
bar.sync 0
mov.u32 s5, %clock
v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v2, v8, s[2:3]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_flopsIiEvPjS0_PT_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.Lfunc_end0:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .Lfunc_end0-_Z9max_flopsIiEvPjS0_PT_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_flopsIiEvPjS0_PT_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9max_flopsIiEvPjS0_PT_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bc012_00000000-6_atomic_add_bw.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.type _Z9max_flopsIiEvPjS0_PT_S2_, @function
_Z9max_flopsIiEvPjS0_PT_S2_:
.LFB4256:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4256:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .-_Z9max_flopsIiEvPjS0_PT_S2_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3923:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L15
ret
.L15:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L16
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3923:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_bw/atomic_add_bw.cu"
.align 8
.LC3:
.string "int32 bendwidth = %f (byte/clk)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB3926:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $655360, %edi
call malloc@PLT
movq %rax, %rbp
movl $655360, %edi
call malloc@PLT
movq %rax, %r12
movl $655360, %edi
call malloc@PLT
movq %rax, %rbx
movl $655360, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L18:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $163840, %rax
jne .L18
movq %rsp, %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $74, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $655360, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $76, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $655360, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $78, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $160, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $655360, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 655356(%r12), %rdx
leaq 4(%r12), %rax
.L21:
movl (%rax), %ecx
cmpl %ecx, (%r12)
cmovb %rax, %r12
addq $4, %rax
cmpq %rax, %rdx
jne .L21
movl (%r12), %ebx
leaq 655356(%rbp), %rdx
leaq 4(%rbp), %rax
.L23:
movl 0(%rbp), %esi
cmpl %esi, (%rax)
cmovb %rax, %rbp
addq $4, %rax
cmpq %rax, %rdx
jne .L23
subl 0(%rbp), %ebx
movl %ebx, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss .LC2(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9max_flopsIiEvPjS0_PT_S2_
jmp .L19
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3926:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9max_flopsIiEvPjS0_PT_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1260388352
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomic_add_bw.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x4b200000 # float 10485760
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %rbx
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r14
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r12
movl $655360, %edi # imm = 0xA0000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r12,%rax,4)
incq %rax
cmpq $163840, %rax # imm = 0x28000
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit18
leaq 8(%rsp), %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq %rsp, %rdi
movl $655360, %esi # imm = 0xA0000
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit22
movq 8(%rsp), %rdi
movl $655360, %edx # imm = 0xA0000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit24
movabsq $4294967456, %rdi # imm = 0x1000000A0
leaq 864(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit26
movq 24(%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit28
movq 16(%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit30
movq (%rsp), %rsi
movl $655360, %edx # imm = 0xA0000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_31
# %bb.22: # %.lr.ph.i.i.preheader
movl $4, %eax
movq %r14, %rcx
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_25: # %.lr.ph.i.i
# in Loop: Header=BB0_23 Depth=1
addq $4, %rax
cmpq $655356, %rax # imm = 0x9FFFC
je .LBB0_26
.LBB0_23: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movl (%rcx), %edx
cmpl (%r14,%rax), %edx
jae .LBB0_25
# %bb.24: # in Loop: Header=BB0_23 Depth=1
leaq (%r14,%rax), %rcx
jmp .LBB0_25
.LBB0_26: # %_ZSt11max_elementIPjET_S1_S1_.exit
movl (%rcx), %r14d
movl $4, %eax
movq %rbx, %rcx
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_29: # %.lr.ph.i.i33
# in Loop: Header=BB0_27 Depth=1
addq $4, %rax
cmpq $655356, %rax # imm = 0x9FFFC
je .LBB0_30
.LBB0_27: # %.lr.ph.i.i33
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rax), %edx
cmpl (%rcx), %edx
jae .LBB0_29
# %bb.28: # in Loop: Header=BB0_27 Depth=1
leaq (%rbx,%rax), %rcx
jmp .LBB0_29
.LBB0_30: # %_ZSt11min_elementIPjET_S1_S1_.exit
subl (%rcx), %r14d
cvtsi2ss %r14, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %r8d
jmp .LBB0_4
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB0_4
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB0_4
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB0_4
.LBB0_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_ # -- Begin function _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,@function
_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_: # @_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_, .Lfunc_end1-_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_bw/atomic_add_bw.hip"
.size .L.str, 194
.type _Z9max_flopsIiEvPjS0_PT_S2_,@object # @_Z9max_flopsIiEvPjS0_PT_S2_
.section .rodata._Z9max_flopsIiEvPjS0_PT_S2_,"aG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 3, 0x0
_Z9max_flopsIiEvPjS0_PT_S2_:
.quad _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.size _Z9max_flopsIiEvPjS0_PT_S2_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "int32 bendwidth = %f (byte/clk)\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsIiEvPjS0_PT_S2_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <stdio.h>
int main()
{
int n = 10;
thrust::host_vector<int> hv(n);
thrust::generate(hv.begin(), hv.end(), rand);
for (int i = 0; i < n; i++)
printf("%d\n", hv[i]);
thrust::device_vector<int> dv = hv;
thrust::sort(dv.begin(), dv.end());
hv = dv;
printf("\n");
for (int i = 0; i < n; i++)
printf("%d\n", hv[i]);
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <stdio.h>
int main()
{
int n = 10;
thrust::host_vector<int> hv(n);
thrust::generate(hv.begin(), hv.end(), rand);
for (int i = 0; i < n; i++)
printf("%d\n", hv[i]);
thrust::device_vector<int> dv = hv;
thrust::sort(dv.begin(), dv.end());
hv = dv;
printf("\n");
for (int i = 0; i < n; i++)
printf("%d\n", hv[i]);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(cudaMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMemcpy(
a, a_h, N * sizeof(float), cudaMemcpyHostToDevice));
CUDA_SAFE_CALL(cudaMemcpy(
b, b_h, N * sizeof(float), cudaMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} | code for sm_80
Function : _Z13many_elementsPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x5, RZ ; /* 0x0000000500007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0007 */
/*0080*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe200078e0007 */
/*0090*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*00c0*/ FMUL R9, R8, R9 ; /* 0x0000000908097220 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*00e0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x0003e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x0005e8000c101904 */
/*0160*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000ee4000c1e1900 */
/*0180*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x008fca0000400000 */
/*0190*/ STG.E [R6.64+0xc], R15 ; /* 0x00000c0f06007986 */
/* 0x0007e8000c101904 */
/*01a0*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f24000c1e1900 */
/*01c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*01d0*/ STG.E [R6.64+0x10], R9 ; /* 0x0000100906007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000f28000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x002f24000c1e1900 */
/*0200*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0210*/ STG.E [R6.64+0x14], R11 ; /* 0x0000140b06007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R13, [R2.64+0x18] ; /* 0x00001804020d7981 */
/* 0x004f24000c1e1900 */
/*0240*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0250*/ STG.E [R6.64+0x18], R13 ; /* 0x0000180d06007986 */
/* 0x0005e8000c101904 */
/*0260*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x008f24000c1e1900 */
/*0280*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0290*/ STG.E [R6.64+0x1c], R15 ; /* 0x00001c0f06007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x001f24000c1e1900 */
/*02c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*02d0*/ STG.E [R6.64+0x20], R9 ; /* 0x0000200906007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R11, [R2.64+0x24] ; /* 0x00002404020b7981 */
/* 0x002f24000c1e1900 */
/*0300*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0310*/ STG.E [R6.64+0x24], R11 ; /* 0x0000240b06007986 */
/* 0x0003e8000c101904 */
/*0320*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x004f24000c1e1900 */
/*0340*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0350*/ STG.E [R6.64+0x28], R13 ; /* 0x0000280d06007986 */
/* 0x0005e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+0x2c] ; /* 0x00002c04020f7981 */
/* 0x008f24000c1e1900 */
/*0380*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0390*/ STG.E [R6.64+0x2c], R15 ; /* 0x00002c0f06007986 */
/* 0x0007e8000c101904 */
/*03a0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x001f24000c1e1900 */
/*03c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*03d0*/ STG.E [R6.64+0x30], R9 ; /* 0x0000300906007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x002f24000c1e1900 */
/*0400*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0410*/ STG.E [R6.64+0x34], R11 ; /* 0x0000340b06007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x004f24000c1e1900 */
/*0440*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0450*/ STG.E [R6.64+0x38], R13 ; /* 0x0000380d06007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x008f24000c1e1900 */
/*0480*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0490*/ STG.E [R6.64+0x3c], R15 ; /* 0x00003c0f06007986 */
/* 0x0007e8000c101904 */
/*04a0*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000f28000c1e1900 */
/*04b0*/ LDG.E R9, [R2.64+0x40] ; /* 0x0000400402097981 */
/* 0x001f24000c1e1900 */
/*04c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*04d0*/ STG.E [R6.64+0x40], R9 ; /* 0x0000400906007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R11, [R2.64+0x44] ; /* 0x00004404020b7981 */
/* 0x002f24000c1e1900 */
/*0500*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0510*/ STG.E [R6.64+0x44], R11 ; /* 0x0000440b06007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R13, [R2.64+0x48] ; /* 0x00004804020d7981 */
/* 0x004f24000c1e1900 */
/*0540*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0550*/ STG.E [R6.64+0x48], R13 ; /* 0x0000480d06007986 */
/* 0x0005e8000c101904 */
/*0560*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R15, [R2.64+0x4c] ; /* 0x00004c04020f7981 */
/* 0x008f24000c1e1900 */
/*0580*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0590*/ STG.E [R6.64+0x4c], R15 ; /* 0x00004c0f06007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000f28000c1e1900 */
/*05b0*/ LDG.E R9, [R2.64+0x50] ; /* 0x0000500402097981 */
/* 0x001f24000c1e1900 */
/*05c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*05d0*/ STG.E [R6.64+0x50], R9 ; /* 0x0000500906007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R11, [R2.64+0x54] ; /* 0x00005404020b7981 */
/* 0x002f24000c1e1900 */
/*0600*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0610*/ STG.E [R6.64+0x54], R11 ; /* 0x0000540b06007986 */
/* 0x0003e8000c101904 */
/*0620*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R13, [R2.64+0x58] ; /* 0x00005804020d7981 */
/* 0x004f24000c1e1900 */
/*0640*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0650*/ STG.E [R6.64+0x58], R13 ; /* 0x0000580d06007986 */
/* 0x0005e8000c101904 */
/*0660*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x5c] ; /* 0x00005c04020f7981 */
/* 0x008f24000c1e1900 */
/*0680*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0690*/ STG.E [R6.64+0x5c], R15 ; /* 0x00005c0f06007986 */
/* 0x0007e8000c101904 */
/*06a0*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000f28000c1e1900 */
/*06b0*/ LDG.E R9, [R2.64+0x60] ; /* 0x0000600402097981 */
/* 0x001f24000c1e1900 */
/*06c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*06d0*/ STG.E [R6.64+0x60], R9 ; /* 0x0000600906007986 */
/* 0x0001e8000c101904 */
/*06e0*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000f28000c1e1900 */
/*06f0*/ LDG.E R11, [R2.64+0x64] ; /* 0x00006404020b7981 */
/* 0x002f24000c1e1900 */
/*0700*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0710*/ STG.E [R6.64+0x64], R11 ; /* 0x0000640b06007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000f28000c1e1900 */
/*0730*/ LDG.E R13, [R2.64+0x68] ; /* 0x00006804020d7981 */
/* 0x004f24000c1e1900 */
/*0740*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0750*/ STG.E [R6.64+0x68], R13 ; /* 0x0000680d06007986 */
/* 0x0005e8000c101904 */
/*0760*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000f28000c1e1900 */
/*0770*/ LDG.E R15, [R2.64+0x6c] ; /* 0x00006c04020f7981 */
/* 0x008f24000c1e1900 */
/*0780*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0790*/ STG.E [R6.64+0x6c], R15 ; /* 0x00006c0f06007986 */
/* 0x0007e8000c101904 */
/*07a0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R9, [R2.64+0x70] ; /* 0x0000700402097981 */
/* 0x001f24000c1e1900 */
/*07c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*07d0*/ STG.E [R6.64+0x70], R9 ; /* 0x0000700906007986 */
/* 0x000fe8000c101904 */
/*07e0*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R11, [R2.64+0x74] ; /* 0x00007404020b7981 */
/* 0x002f24000c1e1900 */
/*0800*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0810*/ STG.E [R6.64+0x74], R11 ; /* 0x0000740b06007986 */
/* 0x000fe8000c101904 */
/*0820*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R13, [R2.64+0x78] ; /* 0x00007804020d7981 */
/* 0x004f24000c1e1900 */
/*0840*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0850*/ STG.E [R6.64+0x78], R13 ; /* 0x0000780d06007986 */
/* 0x000fe8000c101904 */
/*0860*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R15, [R2.64+0x7c] ; /* 0x00007c04020f7981 */
/* 0x008ea4000c1e1900 */
/*0880*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x004fca0000400000 */
/*0890*/ STG.E [R6.64+0x7c], R15 ; /* 0x00007c0f06007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7blockedPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FMUL R9, R2, R5 ; /* 0x0000000502097220 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(cudaMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMemcpy(
a, a_h, N * sizeof(float), cudaMemcpyHostToDevice));
CUDA_SAFE_CALL(cudaMemcpy(
b, b_h, N * sizeof(float), cudaMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} | .file "tmpxft_00049ac7_00000000-6_many_elements.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7blockedPfS_S_PfS_S_
.type _Z30__device_stub__Z7blockedPfS_S_PfS_S_, @function
_Z30__device_stub__Z7blockedPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7blockedPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7blockedPfS_S_PfS_S_, .-_Z30__device_stub__Z7blockedPfS_S_PfS_S_
.globl _Z7blockedPfS_S_
.type _Z7blockedPfS_S_, @function
_Z7blockedPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7blockedPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7blockedPfS_S_, .-_Z7blockedPfS_S_
.globl _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
.type _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_, @function
_Z37__device_stub__Z13many_elementsPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13many_elementsPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_, .-_Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
.globl _Z13many_elementsPfS_S_
.type _Z13many_elementsPfS_S_, @function
_Z13many_elementsPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13many_elementsPfS_S_, .-_Z13many_elementsPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ordovicia/huffman-coding-cuda/master/ManyElements/many_elements.cu"
.align 8
.LC2:
.string "[Error] %s (error code: %d) at %s line %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %r12
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $134217728, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $536870912, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $536870912, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $4096, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L26:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $37
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $38
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $39
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $40
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $42
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L35:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
jmp .L26
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13many_elementsPfS_S_"
.LC6:
.string "_Z7blockedPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13many_elementsPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7blockedPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(cudaMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(cudaMemcpy(
a, a_h, N * sizeof(float), cudaMemcpyHostToDevice));
CUDA_SAFE_CALL(cudaMemcpy(
b, b_h, N * sizeof(float), cudaMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(hipMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(hipMemcpy(
a, a_h, N * sizeof(float), hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(
b, b_h, N * sizeof(float), hipMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(hipMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(hipMemcpy(
a, a_h, N * sizeof(float), hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(
b, b_h, N * sizeof(float), hipMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7blockedPfS_S_
.globl _Z7blockedPfS_S_
.p2align 8
.type _Z7blockedPfS_S_,@function
_Z7blockedPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7blockedPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7blockedPfS_S_, .Lfunc_end0-_Z7blockedPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13many_elementsPfS_S_
.globl _Z13many_elementsPfS_S_
.p2align 8
.type _Z13many_elementsPfS_S_,@function
_Z13many_elementsPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v0, s15, v0, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB1_1:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v6, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[0:1], 0x80
s_waitcnt vmcnt(0)
v_mul_f32_e32 v8, v10, v8
global_store_b32 v[6:7], v8, off
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13many_elementsPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13many_elementsPfS_S_, .Lfunc_end1-_Z13many_elementsPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7blockedPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7blockedPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13many_elementsPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13many_elementsPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define GRID_DIM (1u << 12)
#define BLOCK_DIM (1u << 10)
#define BLOCK_NUM 32
#define ONE_BLOCK (GRID_DIM * BLOCK_DIM)
#define N (BLOCK_NUM * ONE_BLOCK)
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
__global__ void blocked(float* a, float* b, float* c);
__global__ void many_elements(float* a, float* b, float* c);
int main(void)
{
float* a_h = (float*)malloc(N * sizeof(float));
float* b_h = (float*)malloc(N * sizeof(float));
for (size_t i = 0; i < N; i++) {
a_h[i] = (float)rand() / (float)RAND_MAX;
b_h[i] = (float)rand() / (float)RAND_MAX;
}
float *a, *b, *c;
CUDA_SAFE_CALL(hipMalloc((void**)&a, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&b, N * sizeof(float)));
CUDA_SAFE_CALL(hipMalloc((void**)&c, N * sizeof(float)));
CUDA_SAFE_CALL(hipMemcpy(
a, a_h, N * sizeof(float), hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(
b, b_h, N * sizeof(float), hipMemcpyHostToDevice));
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
#if 0
for (size_t i = 0; i < BLOCK_NUM; i++)
blocked<<<GRID_DIM, BLOCK_DIM>>>(
a + i * ONE_BLOCK, b + i * ONE_BLOCK, c + i * ONE_BLOCK);
#else
many_elements<<<GRID_DIM, BLOCK_DIM>>>(a, b, c);
#endif
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("%lf\n", sec);
/*
float* out_h = (float*)malloc(N * sizeof(float));
CUDA_SAFE_CALL(cudaMemcpy(
out_h, c, N * sizeof(float), cudaMemcpyDeviceToHost));
for (size_t i = 0; i < N; i++) {
printf("%lf\n", out_h[i]);
}
*/
return 0;
}
__global__ void blocked(float* a, float* b, float* c)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
c[idx] = a[idx] * b[idx];
}
__global__ void many_elements(float* a, float* b, float* c)
{
size_t idx = BLOCK_NUM * (blockDim.x * blockIdx.x + threadIdx.x);
for (size_t i = 0; i < BLOCK_NUM; i++)
c[idx + i] = a[idx + i] * b[idx + i];
} | .text
.file "many_elements.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $134217728, %r15 # imm = 0x8000000
jne .LBB0_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movq %rsp, %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7:
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movq 8(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq (%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13:
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13many_elementsPfS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 128(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $37, %r9d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $38, %r9d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $39, %r9d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $41, %r9d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $43, %r9d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__many_elementsPfS_S_ # -- Begin function _Z28__device_stub__many_elementsPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__many_elementsPfS_S_,@function
_Z28__device_stub__many_elementsPfS_S_: # @_Z28__device_stub__many_elementsPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13many_elementsPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__many_elementsPfS_S_, .Lfunc_end1-_Z28__device_stub__many_elementsPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__blockedPfS_S_ # -- Begin function _Z22__device_stub__blockedPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__blockedPfS_S_,@function
_Z22__device_stub__blockedPfS_S_: # @_Z22__device_stub__blockedPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7blockedPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__blockedPfS_S_, .Lfunc_end2-_Z22__device_stub__blockedPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7blockedPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13many_elementsPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Error] %s (error code: %d) at %s line %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ordovicia/huffman-coding-cuda/master/ManyElements/many_elements.hip"
.size .L.str.1, 125
.type _Z13many_elementsPfS_S_,@object # @_Z13many_elementsPfS_S_
.section .rodata,"a",@progbits
.globl _Z13many_elementsPfS_S_
.p2align 3, 0x0
_Z13many_elementsPfS_S_:
.quad _Z28__device_stub__many_elementsPfS_S_
.size _Z13many_elementsPfS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%lf\n"
.size .L.str.2, 5
.type _Z7blockedPfS_S_,@object # @_Z7blockedPfS_S_
.section .rodata,"a",@progbits
.globl _Z7blockedPfS_S_
.p2align 3, 0x0
_Z7blockedPfS_S_:
.quad _Z22__device_stub__blockedPfS_S_
.size _Z7blockedPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7blockedPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13many_elementsPfS_S_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__many_elementsPfS_S_
.addrsig_sym _Z22__device_stub__blockedPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13many_elementsPfS_S_
.addrsig_sym _Z7blockedPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13many_elementsPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x5, RZ ; /* 0x0000000500007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0007 */
/*0080*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe200078e0007 */
/*0090*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*00c0*/ FMUL R9, R8, R9 ; /* 0x0000000908097220 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*00e0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x0003e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x0005e8000c101904 */
/*0160*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000ee4000c1e1900 */
/*0180*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x008fca0000400000 */
/*0190*/ STG.E [R6.64+0xc], R15 ; /* 0x00000c0f06007986 */
/* 0x0007e8000c101904 */
/*01a0*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f24000c1e1900 */
/*01c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*01d0*/ STG.E [R6.64+0x10], R9 ; /* 0x0000100906007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000f28000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x002f24000c1e1900 */
/*0200*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0210*/ STG.E [R6.64+0x14], R11 ; /* 0x0000140b06007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R13, [R2.64+0x18] ; /* 0x00001804020d7981 */
/* 0x004f24000c1e1900 */
/*0240*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0250*/ STG.E [R6.64+0x18], R13 ; /* 0x0000180d06007986 */
/* 0x0005e8000c101904 */
/*0260*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x008f24000c1e1900 */
/*0280*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0290*/ STG.E [R6.64+0x1c], R15 ; /* 0x00001c0f06007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x001f24000c1e1900 */
/*02c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*02d0*/ STG.E [R6.64+0x20], R9 ; /* 0x0000200906007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R11, [R2.64+0x24] ; /* 0x00002404020b7981 */
/* 0x002f24000c1e1900 */
/*0300*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0310*/ STG.E [R6.64+0x24], R11 ; /* 0x0000240b06007986 */
/* 0x0003e8000c101904 */
/*0320*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x004f24000c1e1900 */
/*0340*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0350*/ STG.E [R6.64+0x28], R13 ; /* 0x0000280d06007986 */
/* 0x0005e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+0x2c] ; /* 0x00002c04020f7981 */
/* 0x008f24000c1e1900 */
/*0380*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0390*/ STG.E [R6.64+0x2c], R15 ; /* 0x00002c0f06007986 */
/* 0x0007e8000c101904 */
/*03a0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x001f24000c1e1900 */
/*03c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*03d0*/ STG.E [R6.64+0x30], R9 ; /* 0x0000300906007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x002f24000c1e1900 */
/*0400*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0410*/ STG.E [R6.64+0x34], R11 ; /* 0x0000340b06007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x004f24000c1e1900 */
/*0440*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0450*/ STG.E [R6.64+0x38], R13 ; /* 0x0000380d06007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x008f24000c1e1900 */
/*0480*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0490*/ STG.E [R6.64+0x3c], R15 ; /* 0x00003c0f06007986 */
/* 0x0007e8000c101904 */
/*04a0*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000f28000c1e1900 */
/*04b0*/ LDG.E R9, [R2.64+0x40] ; /* 0x0000400402097981 */
/* 0x001f24000c1e1900 */
/*04c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*04d0*/ STG.E [R6.64+0x40], R9 ; /* 0x0000400906007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R11, [R2.64+0x44] ; /* 0x00004404020b7981 */
/* 0x002f24000c1e1900 */
/*0500*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0510*/ STG.E [R6.64+0x44], R11 ; /* 0x0000440b06007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R13, [R2.64+0x48] ; /* 0x00004804020d7981 */
/* 0x004f24000c1e1900 */
/*0540*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0550*/ STG.E [R6.64+0x48], R13 ; /* 0x0000480d06007986 */
/* 0x0005e8000c101904 */
/*0560*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R15, [R2.64+0x4c] ; /* 0x00004c04020f7981 */
/* 0x008f24000c1e1900 */
/*0580*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0590*/ STG.E [R6.64+0x4c], R15 ; /* 0x00004c0f06007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000f28000c1e1900 */
/*05b0*/ LDG.E R9, [R2.64+0x50] ; /* 0x0000500402097981 */
/* 0x001f24000c1e1900 */
/*05c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*05d0*/ STG.E [R6.64+0x50], R9 ; /* 0x0000500906007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R11, [R2.64+0x54] ; /* 0x00005404020b7981 */
/* 0x002f24000c1e1900 */
/*0600*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0610*/ STG.E [R6.64+0x54], R11 ; /* 0x0000540b06007986 */
/* 0x0003e8000c101904 */
/*0620*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R13, [R2.64+0x58] ; /* 0x00005804020d7981 */
/* 0x004f24000c1e1900 */
/*0640*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0650*/ STG.E [R6.64+0x58], R13 ; /* 0x0000580d06007986 */
/* 0x0005e8000c101904 */
/*0660*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x5c] ; /* 0x00005c04020f7981 */
/* 0x008f24000c1e1900 */
/*0680*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0690*/ STG.E [R6.64+0x5c], R15 ; /* 0x00005c0f06007986 */
/* 0x0007e8000c101904 */
/*06a0*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000f28000c1e1900 */
/*06b0*/ LDG.E R9, [R2.64+0x60] ; /* 0x0000600402097981 */
/* 0x001f24000c1e1900 */
/*06c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*06d0*/ STG.E [R6.64+0x60], R9 ; /* 0x0000600906007986 */
/* 0x0001e8000c101904 */
/*06e0*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000f28000c1e1900 */
/*06f0*/ LDG.E R11, [R2.64+0x64] ; /* 0x00006404020b7981 */
/* 0x002f24000c1e1900 */
/*0700*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0710*/ STG.E [R6.64+0x64], R11 ; /* 0x0000640b06007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000f28000c1e1900 */
/*0730*/ LDG.E R13, [R2.64+0x68] ; /* 0x00006804020d7981 */
/* 0x004f24000c1e1900 */
/*0740*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0750*/ STG.E [R6.64+0x68], R13 ; /* 0x0000680d06007986 */
/* 0x0005e8000c101904 */
/*0760*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000f28000c1e1900 */
/*0770*/ LDG.E R15, [R2.64+0x6c] ; /* 0x00006c04020f7981 */
/* 0x008f24000c1e1900 */
/*0780*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x010fca0000400000 */
/*0790*/ STG.E [R6.64+0x6c], R15 ; /* 0x00006c0f06007986 */
/* 0x0007e8000c101904 */
/*07a0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R9, [R2.64+0x70] ; /* 0x0000700402097981 */
/* 0x001f24000c1e1900 */
/*07c0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x010fca0000400000 */
/*07d0*/ STG.E [R6.64+0x70], R9 ; /* 0x0000700906007986 */
/* 0x000fe8000c101904 */
/*07e0*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R11, [R2.64+0x74] ; /* 0x00007404020b7981 */
/* 0x002f24000c1e1900 */
/*0800*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x010fca0000400000 */
/*0810*/ STG.E [R6.64+0x74], R11 ; /* 0x0000740b06007986 */
/* 0x000fe8000c101904 */
/*0820*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R13, [R2.64+0x78] ; /* 0x00007804020d7981 */
/* 0x004f24000c1e1900 */
/*0840*/ FMUL R13, R0, R13 ; /* 0x0000000d000d7220 */
/* 0x010fca0000400000 */
/*0850*/ STG.E [R6.64+0x78], R13 ; /* 0x0000780d06007986 */
/* 0x000fe8000c101904 */
/*0860*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R15, [R2.64+0x7c] ; /* 0x00007c04020f7981 */
/* 0x008ea4000c1e1900 */
/*0880*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x004fca0000400000 */
/*0890*/ STG.E [R6.64+0x7c], R15 ; /* 0x00007c0f06007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7blockedPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FMUL R9, R2, R5 ; /* 0x0000000502097220 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7blockedPfS_S_
.globl _Z7blockedPfS_S_
.p2align 8
.type _Z7blockedPfS_S_,@function
_Z7blockedPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7blockedPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7blockedPfS_S_, .Lfunc_end0-_Z7blockedPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13many_elementsPfS_S_
.globl _Z13many_elementsPfS_S_
.p2align 8
.type _Z13many_elementsPfS_S_,@function
_Z13many_elementsPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v0, s15, v0, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB1_1:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v6, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[0:1], 0x80
s_waitcnt vmcnt(0)
v_mul_f32_e32 v8, v10, v8
global_store_b32 v[6:7], v8, off
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13many_elementsPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13many_elementsPfS_S_, .Lfunc_end1-_Z13many_elementsPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7blockedPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7blockedPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13many_elementsPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13many_elementsPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00049ac7_00000000-6_many_elements.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7blockedPfS_S_PfS_S_
.type _Z30__device_stub__Z7blockedPfS_S_PfS_S_, @function
_Z30__device_stub__Z7blockedPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7blockedPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7blockedPfS_S_PfS_S_, .-_Z30__device_stub__Z7blockedPfS_S_PfS_S_
.globl _Z7blockedPfS_S_
.type _Z7blockedPfS_S_, @function
_Z7blockedPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7blockedPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7blockedPfS_S_, .-_Z7blockedPfS_S_
.globl _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
.type _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_, @function
_Z37__device_stub__Z13many_elementsPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13many_elementsPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_, .-_Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
.globl _Z13many_elementsPfS_S_
.type _Z13many_elementsPfS_S_, @function
_Z13many_elementsPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13many_elementsPfS_S_, .-_Z13many_elementsPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ordovicia/huffman-coding-cuda/master/ManyElements/many_elements.cu"
.align 8
.LC2:
.string "[Error] %s (error code: %d) at %s line %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %r12
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $134217728, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $536870912, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $536870912, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $4096, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L26:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $37
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $38
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $39
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $40
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $42
.cfi_def_cfa_offset 144
leaq .LC1(%rip), %r9
movl %ebx, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L35:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z13many_elementsPfS_S_PfS_S_
jmp .L26
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13many_elementsPfS_S_"
.LC6:
.string "_Z7blockedPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13many_elementsPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7blockedPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "many_elements.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $134217728, %r15 # imm = 0x8000000
jne .LBB0_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movq %rsp, %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7:
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movq 8(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq (%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13:
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13many_elementsPfS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 128(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $37, %r9d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $38, %r9d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $39, %r9d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $41, %r9d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $43, %r9d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__many_elementsPfS_S_ # -- Begin function _Z28__device_stub__many_elementsPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__many_elementsPfS_S_,@function
_Z28__device_stub__many_elementsPfS_S_: # @_Z28__device_stub__many_elementsPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13many_elementsPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__many_elementsPfS_S_, .Lfunc_end1-_Z28__device_stub__many_elementsPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__blockedPfS_S_ # -- Begin function _Z22__device_stub__blockedPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__blockedPfS_S_,@function
_Z22__device_stub__blockedPfS_S_: # @_Z22__device_stub__blockedPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7blockedPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__blockedPfS_S_, .Lfunc_end2-_Z22__device_stub__blockedPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7blockedPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13many_elementsPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Error] %s (error code: %d) at %s line %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ordovicia/huffman-coding-cuda/master/ManyElements/many_elements.hip"
.size .L.str.1, 125
.type _Z13many_elementsPfS_S_,@object # @_Z13many_elementsPfS_S_
.section .rodata,"a",@progbits
.globl _Z13many_elementsPfS_S_
.p2align 3, 0x0
_Z13many_elementsPfS_S_:
.quad _Z28__device_stub__many_elementsPfS_S_
.size _Z13many_elementsPfS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%lf\n"
.size .L.str.2, 5
.type _Z7blockedPfS_S_,@object # @_Z7blockedPfS_S_
.section .rodata,"a",@progbits
.globl _Z7blockedPfS_S_
.p2align 3, 0x0
_Z7blockedPfS_S_:
.quad _Z22__device_stub__blockedPfS_S_
.size _Z7blockedPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7blockedPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13many_elementsPfS_S_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__many_elementsPfS_S_
.addrsig_sym _Z22__device_stub__blockedPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13many_elementsPfS_S_
.addrsig_sym _Z7blockedPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} | code for sm_80
Function : _Z15set_permutationPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} | .file "tmpxft_00014411_00000000-6_set_permutation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15set_permutationPiiPii
.type _Z36__device_stub__Z15set_permutationPiiPii, @function
_Z36__device_stub__Z15set_permutationPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15set_permutationPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z15set_permutationPiiPii, .-_Z36__device_stub__Z15set_permutationPiiPii
.globl _Z15set_permutationPii
.type _Z15set_permutationPii, @function
_Z15set_permutationPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15set_permutationPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15set_permutationPii, .-_Z15set_permutationPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15set_permutationPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15set_permutationPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15set_permutationPii
.globl _Z15set_permutationPii
.p2align 8
.type _Z15set_permutationPii,@function
_Z15set_permutationPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15set_permutationPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15set_permutationPii, .Lfunc_end0-_Z15set_permutationPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15set_permutationPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15set_permutationPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_permutation(int *d_permutation, int M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= M) {
return;
}
d_permutation[i] = i;
} | .text
.file "set_permutation.hip"
.globl _Z30__device_stub__set_permutationPii # -- Begin function _Z30__device_stub__set_permutationPii
.p2align 4, 0x90
.type _Z30__device_stub__set_permutationPii,@function
_Z30__device_stub__set_permutationPii: # @_Z30__device_stub__set_permutationPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15set_permutationPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__set_permutationPii, .Lfunc_end0-_Z30__device_stub__set_permutationPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15set_permutationPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15set_permutationPii,@object # @_Z15set_permutationPii
.section .rodata,"a",@progbits
.globl _Z15set_permutationPii
.p2align 3, 0x0
_Z15set_permutationPii:
.quad _Z30__device_stub__set_permutationPii
.size _Z15set_permutationPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15set_permutationPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__set_permutationPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15set_permutationPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15set_permutationPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15set_permutationPii
.globl _Z15set_permutationPii
.p2align 8
.type _Z15set_permutationPii,@function
_Z15set_permutationPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15set_permutationPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15set_permutationPii, .Lfunc_end0-_Z15set_permutationPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15set_permutationPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15set_permutationPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014411_00000000-6_set_permutation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15set_permutationPiiPii
.type _Z36__device_stub__Z15set_permutationPiiPii, @function
_Z36__device_stub__Z15set_permutationPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15set_permutationPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z15set_permutationPiiPii, .-_Z36__device_stub__Z15set_permutationPiiPii
.globl _Z15set_permutationPii
.type _Z15set_permutationPii, @function
_Z15set_permutationPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15set_permutationPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15set_permutationPii, .-_Z15set_permutationPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15set_permutationPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15set_permutationPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "set_permutation.hip"
.globl _Z30__device_stub__set_permutationPii # -- Begin function _Z30__device_stub__set_permutationPii
.p2align 4, 0x90
.type _Z30__device_stub__set_permutationPii,@function
_Z30__device_stub__set_permutationPii: # @_Z30__device_stub__set_permutationPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15set_permutationPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__set_permutationPii, .Lfunc_end0-_Z30__device_stub__set_permutationPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15set_permutationPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15set_permutationPii,@object # @_Z15set_permutationPii
.section .rodata,"a",@progbits
.globl _Z15set_permutationPii
.p2align 3, 0x0
_Z15set_permutationPii:
.quad _Z30__device_stub__set_permutationPii
.size _Z15set_permutationPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15set_permutationPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__set_permutationPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15set_permutationPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Edge Version: Input Edge Stream
// 3 Kernels: Process only active edges in every iteration
#include<string.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<fstream>
#include<sys/time.h>
#include<cuda.h>
//#include"common.h"
#define INF INT_MAX;
#define MAX_THREADS_PER_BLOCK 1024
#define PRINTFLAG true
using namespace std;
dim3 gridDimension;
dim3 blockDimension;
void printEarliestTimes(int earliestTime[], int vCount, double runningTime, bool print)
{
if(print == true)
{//cout<<"Memory copied"<<endl;
for(int i=0;i<=vCount-1;i++)
{
cout<<i<<" "<<earliestTime[i]<<endl;
//fprintf(fp1,"Earliest time for %d is %d\n",i,earliest[i]);
}
}
cout<<"Time is "<<runningTime<<endl;
}
void createHostMemoryBool(bool *&X, int n)
{
X = new bool[n];
}
bool readInput(char *fileName, int &vCount, int &cCount, int *&from, int *&to, int *&departure, int *&duration)
{
ifstream fin;
fin.open(fileName);
fin>>vCount>>cCount;
from = new int[cCount];
to = new int[cCount];
departure = new int[cCount];
duration = new int[cCount];
for(int i=0; i<=cCount-1; i++)
fin>>from[i]>>to[i]>>departure[i]>>duration[i];
//cout<<"reading the input is over"<<endl;
return true;
}
bool printInput(int vCount, int cCount, int *vertex, int *edge, int *departure, int *duration)
{
ofstream fout;
fout.open("csr2.txt");
for(int i=0; i<=vCount; i++)
fout<<vertex[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<edge[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<departure[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<duration[i]<<" ";
fout<<endl;
return true;
}
void initConfiguration(dim3 &grid, dim3 &block, int n)
{
int num_of_blocks = 1;
int num_of_threads_per_block = n;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(n>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(n/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
grid.x = num_of_blocks; grid.y=1; grid.z=1;
block.x = num_of_threads_per_block; block.y=1; block.z=1;
}
void initEarlistTime(int *earliestTime, int vCount, int source, int departureTime)
{
for(int i=0; i<=vCount-1; i++)
{
earliestTime[i] = INF;
}
earliestTime[source]=departureTime;
}
void initActiveVertices(bool *active, int vCount, int source)
{
for(int i=0; i<=vCount-1; i++)
{
active[i] = false;
}
active[source]=true;
}
void cudaCopyToDevice(int *X, int *&cX, int n)
{
cudaMalloc((void**)&cX, n*sizeof(int));
cudaMemcpy( cX, X, n*sizeof(int), cudaMemcpyHostToDevice);
}
void cudaCopyToDeviceBool(bool *X, bool *&cX, int n)
{
cudaMalloc((void**)&cX, n*sizeof(bool));
cudaMemcpy(cX, X, n*sizeof(bool), cudaMemcpyHostToDevice);
}
__global__
void processEdges2(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges1(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
active[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, int *active, int *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
//if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void passiveToActive(int n, int *active, int *nextActive)
{
int v,i;
//****LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
v = i;
if( i< n && nextActive[v]==true)
{
nextActive[v] = false;
active[v] = true;
}
}
__global__
void activeToPassive(int n, int *active)
{
int u,i;
//***LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
u = i;
if( i< n && active[u]==true)
{
active[u] = false;
}
}
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
//computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
void computeEarliestTime(int vCount, int cCount, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *active, bool *nextActive)
{
int iterations=0;
bool hContinue;
bool *dContinue;
cudaMalloc( (void**) &dContinue, sizeof(bool));
//Call the Kernel untill all the elements of Frontier are not false
do
{
//if no thread changes this value then the loop stops
hContinue=false;
cudaMemcpy(dContinue, &hContinue, sizeof(bool), cudaMemcpyHostToDevice) ;
processEdges1<<< ceil(cCount/1024.0), 1024>>>(cCount ,from, to, departure, duration, earliestTime,dContinue,active,nextActive);
// updateActiveVertices<<<ceil(vCount/1024.0), 1024>>>(vCount,active,nextActive);
//activeToPassive<<<ceil(vCount/1024.0), 1024>>>(vCount,active);
//passiveToActive<<<ceil(vCount/1024.0), 1024>>>(vCount,active, nextActive);
cudaMemcpy( &hContinue, dContinue, sizeof(bool), cudaMemcpyDeviceToHost) ;
cudaDeviceSynchronize();
iterations++;
}
while(hContinue);
}
//computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,active, nextActive, runTime);
void computeEarliestTimesSetUP(int vCount, int cCount,int from[],int to[],int departure[], int duration[], int source[], int departureTime[], int earliestTime[],int qCount)
{
int *cFrom, *cTo, *cDeparture, *cDuration, *cEarliestTime;
bool *cActive, *cNextActive;
struct timeval start,stop;
bool *active, *nextActive;
double time;
initConfiguration(gridDimension,blockDimension, cCount);
createHostMemoryBool(active,vCount);
createHostMemoryBool(nextActive,vCount);
cudaCopyToDevice(from,cFrom,cCount);
cudaCopyToDevice(to,cTo,cCount);
cudaCopyToDevice(departure,cDeparture,cCount);
cudaCopyToDevice(duration,cDuration,cCount);
//cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
//cudaCopyToDevice(active,cActive,vCount);
//cudaCopyToDevice(nextActive,cNextActive,vCount);
for(int i=0; i<=qCount-1; i++)
{
initEarlistTime(earliestTime,vCount,source[i],departureTime[i]);
initActiveVertices(active,vCount,source[i]);
cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
cudaCopyToDeviceBool(active,cActive,vCount);
gettimeofday(&start,0);
computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
gettimeofday(&stop,0);
time = (1000000.0*(stop.tv_sec-start.tv_sec) + stop.tv_usec-start.tv_usec)/1000.0;
cudaMemcpy(earliestTime, cEarliestTime, vCount * sizeof(int), cudaMemcpyDeviceToHost);
printEarliestTimes(earliestTime,vCount,time,PRINTFLAG);
}
cudaFree(cEarliestTime);
cudaFree(cFrom);
cudaFree(cTo);
cudaFree(cDeparture);
cudaFree(cDuration);
cudaFree(cActive);
cudaFree(cNextActive);
}
void createHostMemory(int *&X, int n)
{
X = new int[n];
}
void readQuery(char *fileName, int *&source, int *&departureTime, int &qCount)
{
ifstream fin;
fin.open(fileName);
fin>>qCount;
source = new int[qCount];
departureTime = new int[qCount];
for(int i=0; i<=qCount-1; i++)
fin>>source[i]>>departureTime[i];
}
int main(int argc, char *argv[])
{
int vCount, cCount, qCount;
int *from, *to, *departure, *duration, *earliestTime, *source, *departureTime;
char queryFile[100];
char fileName[100];
strcpy(fileName, argv[1]);
strcpy(queryFile,"query.txt");
readInput(fileName,vCount, cCount, from, to, departure, duration);
readQuery(queryFile, source, departureTime, qCount);
createHostMemory(earliestTime,vCount);
//departureTime = 180; //Change this ****************************************
computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,qCount);
return 0;
} | code for sm_80
Function : _Z15activeToPassiveiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15passiveToActiveiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ LEA R4, P0, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x040fe200078010ff */
/*00f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*0100*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12processEdgesiPiS_S_S_S_PbS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e020b */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fca00078e020b */
/*00b0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R2, R11, c[0x0][0x188] ; /* 0x0000620002067625 */
/* 0x004fcc00078e020b */
/*00d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ ISETP.GT.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x008fda0003f04270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0120*/ SHF.L.U64.HI R3, R0, 0x2, R3 ; /* 0x0000000200037819 */
/* 0x000fe40000010203 */
/*0130*/ IADD3 R6, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R7, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003077a10 */
/* 0x000fcc00007fe4ff */
/*0150*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R4, P0, R4, c[0x0][0x180], RZ ; /* 0x0000600004047a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R5, R3, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610003057a10 */
/* 0x000fca00007fe4ff */
/*0180*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IMAD.WIDE R2, R7, R11, c[0x0][0x188] ; /* 0x0000620007027625 */
/* 0x004fca00078e020b */
/*01a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109097824 */
/* 0x008fca00078e0204 */
/*01c0*/ ISETP.GE.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x004fda0003f06270 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R7 ; /* 0x0000001fff007819 */
/* 0x000fe20000011407 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0200*/ LEA R6, P0, R7.reuse, c[0x0][0x1a0], 0x2 ; /* 0x0000680007067a11 */
/* 0x040fe200078010ff */
/*0210*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0220*/ RED.E.MIN.S32.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c90e384 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff057624 */
/* 0x000fe200078e00ff */
/*0240*/ LEA.HI.X R7, R7, c[0x0][0x1a4], R0.reuse, 0x2, P0 ; /* 0x0000690007077a11 */
/* 0x100fe400000f1400 */
/*0250*/ PRMT R0, R4, 0x7610, R0 ; /* 0x0000761004007816 */
/* 0x000fe20000000000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe400078e00ff */
/*0270*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E.U8 [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101104 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13processEdges1iPiS_S_S_S_PbS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x004fe40000011407 */
/*00b0*/ IADD3 R4, P0, R7, c[0x0][0x198], RZ ; /* 0x0000660007047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R8, c[0x0][0x19c], RZ, P0, !PT ; /* 0x0000670008057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f25270 */
/*0110*/ IMAD.SHL.U32 R9, R0, 0x4, RZ ; /* 0x0000000400097824 */
/* 0x000fe200078e00ff */
/*0120*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0130*/ SHF.L.U64.HI R10, R0, 0x2, R3 ; /* 0x00000002000a7819 */
/* 0x000fe40000010203 */
/*0140*/ IADD3 R2, P0, R9, c[0x0][0x178], RZ ; /* 0x00005e0009027a10 */
/* 0x000fca0007f1e0ff */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000ff00003800000 */
/*0160*/ LEA R6, P1, R7.reuse, c[0x0][0x188], 0x2 ; /* 0x0000620007067a11 */
/* 0x040fe400078210ff */
/*0170*/ IADD3.X R3, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a037a10 */
/* 0x000fe400007fe4ff */
/*0180*/ LEA.HI.X R7, R7, c[0x0][0x18c], R8, 0x2, P1 ; /* 0x0000630007077a11 */
/* 0x000fc600008f1408 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R4, P1, R9, c[0x0][0x170], RZ ; /* 0x00005c0009047a10 */
/* 0x000fc80007f3e0ff */
/*01c0*/ IADD3.X R5, R10, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000a057a10 */
/* 0x000fe40000ffe4ff */
/*01d0*/ ISETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fda0003f04270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, P0, R9, c[0x0][0x180], RZ ; /* 0x0000600009067a10 */
/* 0x000fc80007f1e0ff */
/*0210*/ IADD3.X R7, R10, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000a077a10 */
/* 0x000fcc00007fe4ff */
/*0220*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0230*/ SHF.R.S32.HI R11, RZ, 0x1f, R4 ; /* 0x0000001fff0b7819 */
/* 0x004fe40000011404 */
/*0240*/ LEA R2, P0, R4, c[0x0][0x188], 0x2 ; /* 0x0000620004027a11 */
/* 0x000fc800078010ff */
/*0250*/ LEA.HI.X R3, R4, c[0x0][0x18c], R11, 0x2, P0 ; /* 0x0000630004037a11 */
/* 0x000fca00000f140b */
/*0260*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.IADD R9, R0, 0x1, R7 ; /* 0x0000000100097824 */
/* 0x008fca00078e0207 */
/*0280*/ ISETP.GE.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x004fda0003f06270 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*02b0*/ IADD3 R6, P0, R4, c[0x0][0x198], RZ ; /* 0x0000660004067a10 */
/* 0x000fe20007f1e0ff */
/*02c0*/ RED.E.MIN.S32.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001e2000c90e384 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe400078e00ff */
/*02e0*/ IADD3.X R7, R11, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000b077a10 */
/* 0x000fe200007fe4ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff057624 */
/* 0x000fe200078e00ff */
/*0300*/ PRMT R3, R0, 0x7610, R3 ; /* 0x0000761000037816 */
/* 0x001fca0000000003 */
/*0310*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*0320*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101104 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13processEdges2iPiS_S_S_S_PbS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x004fe40000011407 */
/*00b0*/ IADD3 R4, P0, R7, c[0x0][0x198], RZ ; /* 0x0000660007047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R8, c[0x0][0x19c], RZ, P0, !PT ; /* 0x0000670008057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f25270 */
/*0110*/ IMAD.SHL.U32 R9, R0, 0x4, RZ ; /* 0x0000000400097824 */
/* 0x000fe200078e00ff */
/*0120*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0130*/ SHF.L.U64.HI R10, R0, 0x2, R3 ; /* 0x00000002000a7819 */
/* 0x000fe40000010203 */
/*0140*/ IADD3 R2, P0, R9, c[0x0][0x178], RZ ; /* 0x00005e0009027a10 */
/* 0x000fca0007f1e0ff */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000ff00003800000 */
/*0160*/ LEA R6, P1, R7.reuse, c[0x0][0x188], 0x2 ; /* 0x0000620007067a11 */
/* 0x040fe400078210ff */
/*0170*/ IADD3.X R3, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a037a10 */
/* 0x000fe400007fe4ff */
/*0180*/ LEA.HI.X R7, R7, c[0x0][0x18c], R8, 0x2, P1 ; /* 0x0000630007077a11 */
/* 0x000fc600008f1408 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R4, P1, R9, c[0x0][0x170], RZ ; /* 0x00005c0009047a10 */
/* 0x000fc80007f3e0ff */
/*01c0*/ IADD3.X R5, R10, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000a057a10 */
/* 0x000fe40000ffe4ff */
/*01d0*/ ISETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fda0003f04270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, P0, R9, c[0x0][0x180], RZ ; /* 0x0000600009067a10 */
/* 0x000fc80007f1e0ff */
/*0210*/ IADD3.X R7, R10, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000a077a10 */
/* 0x000fcc00007fe4ff */
/*0220*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0230*/ SHF.R.S32.HI R11, RZ, 0x1f, R4 ; /* 0x0000001fff0b7819 */
/* 0x004fe40000011404 */
/*0240*/ LEA R2, P0, R4, c[0x0][0x188], 0x2 ; /* 0x0000620004027a11 */
/* 0x000fc800078010ff */
/*0250*/ LEA.HI.X R3, R4, c[0x0][0x18c], R11, 0x2, P0 ; /* 0x0000630004037a11 */
/* 0x000fca00000f140b */
/*0260*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.IADD R9, R0, 0x1, R7 ; /* 0x0000000100097824 */
/* 0x008fca00078e0207 */
/*0280*/ ISETP.GE.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x004fda0003f06270 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*02b0*/ IADD3 R6, P0, R4, c[0x0][0x1a0], RZ ; /* 0x0000680004067a10 */
/* 0x000fe20007f1e0ff */
/*02c0*/ RED.E.MIN.S32.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001e2000c90e384 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe400078e00ff */
/*02e0*/ IADD3.X R7, R11, c[0x0][0x1a4], RZ, P0, !PT ; /* 0x000069000b077a10 */
/* 0x000fe200007fe4ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff057624 */
/* 0x000fe200078e00ff */
/*0300*/ PRMT R3, R0, 0x7610, R3 ; /* 0x0000761000037816 */
/* 0x001fca0000000003 */
/*0310*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*0320*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101104 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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