system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Edge Version: Input Edge Stream
// 3 Kernels: Process only active edges in every iteration
#include<string.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<fstream>
#include<sys/time.h>
#include<cuda.h>
//#include"common.h"
#define INF INT_MAX;
#define MAX_THREADS_PER_BLOCK 1024
#define PRINTFLAG true
using namespace std;
dim3 gridDimension;
dim3 blockDimension;
void printEarliestTimes(int earliestTime[], int vCount, double runningTime, bool print)
{
if(print == true)
{//cout<<"Memory copied"<<endl;
for(int i=0;i<=vCount-1;i++)
{
cout<<i<<" "<<earliestTime[i]<<endl;
//fprintf(fp1,"Earliest time for %d is %d\n",i,earliest[i]);
}
}
cout<<"Time is "<<runningTime<<endl;
}
void createHostMemoryBool(bool *&X, int n)
{
X = new bool[n];
}
bool readInput(char *fileName, int &vCount, int &cCount, int *&from, int *&to, int *&departure, int *&duration)
{
ifstream fin;
fin.open(fileName);
fin>>vCount>>cCount;
from = new int[cCount];
to = new int[cCount];
departure = new int[cCount];
duration = new int[cCount];
for(int i=0; i<=cCount-1; i++)
fin>>from[i]>>to[i]>>departure[i]>>duration[i];
//cout<<"reading the input is over"<<endl;
return true;
}
bool printInput(int vCount, int cCount, int *vertex, int *edge, int *departure, int *duration)
{
ofstream fout;
fout.open("csr2.txt");
for(int i=0; i<=vCount; i++)
fout<<vertex[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<edge[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<departure[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<duration[i]<<" ";
fout<<endl;
return true;
}
void initConfiguration(dim3 &grid, dim3 &block, int n)
{
int num_of_blocks = 1;
int num_of_threads_per_block = n;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(n>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(n/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
grid.x = num_of_blocks; grid.y=1; grid.z=1;
block.x = num_of_threads_per_block; block.y=1; block.z=1;
}
void initEarlistTime(int *earliestTime, int vCount, int source, int departureTime)
{
for(int i=0; i<=vCount-1; i++)
{
earliestTime[i] = INF;
}
earliestTime[source]=departureTime;
}
void initActiveVertices(bool *active, int vCount, int source)
{
for(int i=0; i<=vCount-1; i++)
{
active[i] = false;
}
active[source]=true;
}
void cudaCopyToDevice(int *X, int *&cX, int n)
{
cudaMalloc((void**)&cX, n*sizeof(int));
cudaMemcpy( cX, X, n*sizeof(int), cudaMemcpyHostToDevice);
}
void cudaCopyToDeviceBool(bool *X, bool *&cX, int n)
{
cudaMalloc((void**)&cX, n*sizeof(bool));
cudaMemcpy(cX, X, n*sizeof(bool), cudaMemcpyHostToDevice);
}
__global__
void processEdges2(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges1(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
active[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, int *active, int *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
//if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void passiveToActive(int n, int *active, int *nextActive)
{
int v,i;
//****LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
v = i;
if( i< n && nextActive[v]==true)
{
nextActive[v] = false;
active[v] = true;
}
}
__global__
void activeToPassive(int n, int *active)
{
int u,i;
//***LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
u = i;
if( i< n && active[u]==true)
{
active[u] = false;
}
}
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
//computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
void computeEarliestTime(int vCount, int cCount, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *active, bool *nextActive)
{
int iterations=0;
bool hContinue;
bool *dContinue;
cudaMalloc( (void**) &dContinue, sizeof(bool));
//Call the Kernel untill all the elements of Frontier are not false
do
{
//if no thread changes this value then the loop stops
hContinue=false;
cudaMemcpy(dContinue, &hContinue, sizeof(bool), cudaMemcpyHostToDevice) ;
processEdges1<<< ceil(cCount/1024.0), 1024>>>(cCount ,from, to, departure, duration, earliestTime,dContinue,active,nextActive);
// updateActiveVertices<<<ceil(vCount/1024.0), 1024>>>(vCount,active,nextActive);
//activeToPassive<<<ceil(vCount/1024.0), 1024>>>(vCount,active);
//passiveToActive<<<ceil(vCount/1024.0), 1024>>>(vCount,active, nextActive);
cudaMemcpy( &hContinue, dContinue, sizeof(bool), cudaMemcpyDeviceToHost) ;
cudaDeviceSynchronize();
iterations++;
}
while(hContinue);
}
//computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,active, nextActive, runTime);
void computeEarliestTimesSetUP(int vCount, int cCount,int from[],int to[],int departure[], int duration[], int source[], int departureTime[], int earliestTime[],int qCount)
{
int *cFrom, *cTo, *cDeparture, *cDuration, *cEarliestTime;
bool *cActive, *cNextActive;
struct timeval start,stop;
bool *active, *nextActive;
double time;
initConfiguration(gridDimension,blockDimension, cCount);
createHostMemoryBool(active,vCount);
createHostMemoryBool(nextActive,vCount);
cudaCopyToDevice(from,cFrom,cCount);
cudaCopyToDevice(to,cTo,cCount);
cudaCopyToDevice(departure,cDeparture,cCount);
cudaCopyToDevice(duration,cDuration,cCount);
//cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
//cudaCopyToDevice(active,cActive,vCount);
//cudaCopyToDevice(nextActive,cNextActive,vCount);
for(int i=0; i<=qCount-1; i++)
{
initEarlistTime(earliestTime,vCount,source[i],departureTime[i]);
initActiveVertices(active,vCount,source[i]);
cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
cudaCopyToDeviceBool(active,cActive,vCount);
gettimeofday(&start,0);
computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
gettimeofday(&stop,0);
time = (1000000.0*(stop.tv_sec-start.tv_sec) + stop.tv_usec-start.tv_usec)/1000.0;
cudaMemcpy(earliestTime, cEarliestTime, vCount * sizeof(int), cudaMemcpyDeviceToHost);
printEarliestTimes(earliestTime,vCount,time,PRINTFLAG);
}
cudaFree(cEarliestTime);
cudaFree(cFrom);
cudaFree(cTo);
cudaFree(cDeparture);
cudaFree(cDuration);
cudaFree(cActive);
cudaFree(cNextActive);
}
void createHostMemory(int *&X, int n)
{
X = new int[n];
}
void readQuery(char *fileName, int *&source, int *&departureTime, int &qCount)
{
ifstream fin;
fin.open(fileName);
fin>>qCount;
source = new int[qCount];
departureTime = new int[qCount];
for(int i=0; i<=qCount-1; i++)
fin>>source[i]>>departureTime[i];
}
int main(int argc, char *argv[])
{
int vCount, cCount, qCount;
int *from, *to, *departure, *duration, *earliestTime, *source, *departureTime;
char queryFile[100];
char fileName[100];
strcpy(fileName, argv[1]);
strcpy(queryFile,"query.txt");
readInput(fileName,vCount, cCount, from, to, departure, duration);
readQuery(queryFile, source, departureTime, qCount);
createHostMemory(earliestTime,vCount);
//departureTime = 180; //Change this ****************************************
computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,qCount);
return 0;
} | // Edge Version: Input Edge Stream
// 3 Kernels: Process only active edges in every iteration
#include<string.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<fstream>
#include<sys/time.h>
#include<hip/hip_runtime.h>
//#include"common.h"
#define INF INT_MAX;
#define MAX_THREADS_PER_BLOCK 1024
#define PRINTFLAG true
using namespace std;
dim3 gridDimension;
dim3 blockDimension;
void printEarliestTimes(int earliestTime[], int vCount, double runningTime, bool print)
{
if(print == true)
{//cout<<"Memory copied"<<endl;
for(int i=0;i<=vCount-1;i++)
{
cout<<i<<" "<<earliestTime[i]<<endl;
//fprintf(fp1,"Earliest time for %d is %d\n",i,earliest[i]);
}
}
cout<<"Time is "<<runningTime<<endl;
}
void createHostMemoryBool(bool *&X, int n)
{
X = new bool[n];
}
bool readInput(char *fileName, int &vCount, int &cCount, int *&from, int *&to, int *&departure, int *&duration)
{
ifstream fin;
fin.open(fileName);
fin>>vCount>>cCount;
from = new int[cCount];
to = new int[cCount];
departure = new int[cCount];
duration = new int[cCount];
for(int i=0; i<=cCount-1; i++)
fin>>from[i]>>to[i]>>departure[i]>>duration[i];
//cout<<"reading the input is over"<<endl;
return true;
}
bool printInput(int vCount, int cCount, int *vertex, int *edge, int *departure, int *duration)
{
ofstream fout;
fout.open("csr2.txt");
for(int i=0; i<=vCount; i++)
fout<<vertex[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<edge[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<departure[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<duration[i]<<" ";
fout<<endl;
return true;
}
void initConfiguration(dim3 &grid, dim3 &block, int n)
{
int num_of_blocks = 1;
int num_of_threads_per_block = n;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(n>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(n/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
grid.x = num_of_blocks; grid.y=1; grid.z=1;
block.x = num_of_threads_per_block; block.y=1; block.z=1;
}
void initEarlistTime(int *earliestTime, int vCount, int source, int departureTime)
{
for(int i=0; i<=vCount-1; i++)
{
earliestTime[i] = INF;
}
earliestTime[source]=departureTime;
}
void initActiveVertices(bool *active, int vCount, int source)
{
for(int i=0; i<=vCount-1; i++)
{
active[i] = false;
}
active[source]=true;
}
void cudaCopyToDevice(int *X, int *&cX, int n)
{
hipMalloc((void**)&cX, n*sizeof(int));
hipMemcpy( cX, X, n*sizeof(int), hipMemcpyHostToDevice);
}
void cudaCopyToDeviceBool(bool *X, bool *&cX, int n)
{
hipMalloc((void**)&cX, n*sizeof(bool));
hipMemcpy(cX, X, n*sizeof(bool), hipMemcpyHostToDevice);
}
__global__
void processEdges2(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges1(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
active[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, int *active, int *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
//if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void passiveToActive(int n, int *active, int *nextActive)
{
int v,i;
//****LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
v = i;
if( i< n && nextActive[v]==true)
{
nextActive[v] = false;
active[v] = true;
}
}
__global__
void activeToPassive(int n, int *active)
{
int u,i;
//***LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
u = i;
if( i< n && active[u]==true)
{
active[u] = false;
}
}
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
//computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
void computeEarliestTime(int vCount, int cCount, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *active, bool *nextActive)
{
int iterations=0;
bool hContinue;
bool *dContinue;
hipMalloc( (void**) &dContinue, sizeof(bool));
//Call the Kernel untill all the elements of Frontier are not false
do
{
//if no thread changes this value then the loop stops
hContinue=false;
hipMemcpy(dContinue, &hContinue, sizeof(bool), hipMemcpyHostToDevice) ;
processEdges1<<< ceil(cCount/1024.0), 1024>>>(cCount ,from, to, departure, duration, earliestTime,dContinue,active,nextActive);
// updateActiveVertices<<<ceil(vCount/1024.0), 1024>>>(vCount,active,nextActive);
//activeToPassive<<<ceil(vCount/1024.0), 1024>>>(vCount,active);
//passiveToActive<<<ceil(vCount/1024.0), 1024>>>(vCount,active, nextActive);
hipMemcpy( &hContinue, dContinue, sizeof(bool), hipMemcpyDeviceToHost) ;
hipDeviceSynchronize();
iterations++;
}
while(hContinue);
}
//computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,active, nextActive, runTime);
void computeEarliestTimesSetUP(int vCount, int cCount,int from[],int to[],int departure[], int duration[], int source[], int departureTime[], int earliestTime[],int qCount)
{
int *cFrom, *cTo, *cDeparture, *cDuration, *cEarliestTime;
bool *cActive, *cNextActive;
struct timeval start,stop;
bool *active, *nextActive;
double time;
initConfiguration(gridDimension,blockDimension, cCount);
createHostMemoryBool(active,vCount);
createHostMemoryBool(nextActive,vCount);
cudaCopyToDevice(from,cFrom,cCount);
cudaCopyToDevice(to,cTo,cCount);
cudaCopyToDevice(departure,cDeparture,cCount);
cudaCopyToDevice(duration,cDuration,cCount);
//cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
//cudaCopyToDevice(active,cActive,vCount);
//cudaCopyToDevice(nextActive,cNextActive,vCount);
for(int i=0; i<=qCount-1; i++)
{
initEarlistTime(earliestTime,vCount,source[i],departureTime[i]);
initActiveVertices(active,vCount,source[i]);
cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
cudaCopyToDeviceBool(active,cActive,vCount);
gettimeofday(&start,0);
computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
gettimeofday(&stop,0);
time = (1000000.0*(stop.tv_sec-start.tv_sec) + stop.tv_usec-start.tv_usec)/1000.0;
hipMemcpy(earliestTime, cEarliestTime, vCount * sizeof(int), hipMemcpyDeviceToHost);
printEarliestTimes(earliestTime,vCount,time,PRINTFLAG);
}
hipFree(cEarliestTime);
hipFree(cFrom);
hipFree(cTo);
hipFree(cDeparture);
hipFree(cDuration);
hipFree(cActive);
hipFree(cNextActive);
}
void createHostMemory(int *&X, int n)
{
X = new int[n];
}
void readQuery(char *fileName, int *&source, int *&departureTime, int &qCount)
{
ifstream fin;
fin.open(fileName);
fin>>qCount;
source = new int[qCount];
departureTime = new int[qCount];
for(int i=0; i<=qCount-1; i++)
fin>>source[i]>>departureTime[i];
}
int main(int argc, char *argv[])
{
int vCount, cCount, qCount;
int *from, *to, *departure, *duration, *earliestTime, *source, *departureTime;
char queryFile[100];
char fileName[100];
strcpy(fileName, argv[1]);
strcpy(queryFile,"query.txt");
readInput(fileName,vCount, cCount, from, to, departure, duration);
readQuery(queryFile, source, departureTime, qCount);
createHostMemory(earliestTime,vCount);
//departureTime = 180; //Change this ****************************************
computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,qCount);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Edge Version: Input Edge Stream
// 3 Kernels: Process only active edges in every iteration
#include<string.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<fstream>
#include<sys/time.h>
#include<hip/hip_runtime.h>
//#include"common.h"
#define INF INT_MAX;
#define MAX_THREADS_PER_BLOCK 1024
#define PRINTFLAG true
using namespace std;
dim3 gridDimension;
dim3 blockDimension;
void printEarliestTimes(int earliestTime[], int vCount, double runningTime, bool print)
{
if(print == true)
{//cout<<"Memory copied"<<endl;
for(int i=0;i<=vCount-1;i++)
{
cout<<i<<" "<<earliestTime[i]<<endl;
//fprintf(fp1,"Earliest time for %d is %d\n",i,earliest[i]);
}
}
cout<<"Time is "<<runningTime<<endl;
}
void createHostMemoryBool(bool *&X, int n)
{
X = new bool[n];
}
bool readInput(char *fileName, int &vCount, int &cCount, int *&from, int *&to, int *&departure, int *&duration)
{
ifstream fin;
fin.open(fileName);
fin>>vCount>>cCount;
from = new int[cCount];
to = new int[cCount];
departure = new int[cCount];
duration = new int[cCount];
for(int i=0; i<=cCount-1; i++)
fin>>from[i]>>to[i]>>departure[i]>>duration[i];
//cout<<"reading the input is over"<<endl;
return true;
}
bool printInput(int vCount, int cCount, int *vertex, int *edge, int *departure, int *duration)
{
ofstream fout;
fout.open("csr2.txt");
for(int i=0; i<=vCount; i++)
fout<<vertex[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<edge[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<departure[i]<<" ";
fout<<endl;
for(int i=0; i<=cCount-1; i++)
fout<<duration[i]<<" ";
fout<<endl;
return true;
}
void initConfiguration(dim3 &grid, dim3 &block, int n)
{
int num_of_blocks = 1;
int num_of_threads_per_block = n;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(n>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(n/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
grid.x = num_of_blocks; grid.y=1; grid.z=1;
block.x = num_of_threads_per_block; block.y=1; block.z=1;
}
void initEarlistTime(int *earliestTime, int vCount, int source, int departureTime)
{
for(int i=0; i<=vCount-1; i++)
{
earliestTime[i] = INF;
}
earliestTime[source]=departureTime;
}
void initActiveVertices(bool *active, int vCount, int source)
{
for(int i=0; i<=vCount-1; i++)
{
active[i] = false;
}
active[source]=true;
}
void cudaCopyToDevice(int *X, int *&cX, int n)
{
hipMalloc((void**)&cX, n*sizeof(int));
hipMemcpy( cX, X, n*sizeof(int), hipMemcpyHostToDevice);
}
void cudaCopyToDeviceBool(bool *X, bool *&cX, int n)
{
hipMalloc((void**)&cX, n*sizeof(bool));
hipMemcpy(cX, X, n*sizeof(bool), hipMemcpyHostToDevice);
}
__global__
void processEdges2(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges1(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, bool *active, bool *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n || active[from[i]] == false) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
//nextActive[v] = true;
active[v] = true;
*dContinue=true;
}
}
}
__global__
void processEdges(int n, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *dContinue, int *active, int *nextActive)
{
int i,u,v,t,lambda;
i = blockIdx.x * blockDim.x + threadIdx.x;
if(i>= n) return;
//**** LOOP
//** n
u = from[i];
v = to[i];
t = departure[i];
lambda = duration[i];
//if((active[u]==true))
{
if((earliestTime[u]<=t) && (t+lambda < earliestTime[v]))
{
//if(i==0){printf("first thread updating:after \n"); }
//earliestTime[v]= t + lambda;
atomicMin(&earliestTime[v], t+lambda);
nextActive[v] = true;
*dContinue=true;
}
}
}
__global__
void passiveToActive(int n, int *active, int *nextActive)
{
int v,i;
//****LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
v = i;
if( i< n && nextActive[v]==true)
{
nextActive[v] = false;
active[v] = true;
}
}
__global__
void activeToPassive(int n, int *active)
{
int u,i;
//***LOOP
i = blockIdx.x * blockDim.x + threadIdx.x;
u = i;
if( i< n && active[u]==true)
{
active[u] = false;
}
}
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
// computeEarliestTimes(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
//computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
void computeEarliestTime(int vCount, int cCount, int *from, int *to, int *departure, int *duration, int *earliestTime, bool *active, bool *nextActive)
{
int iterations=0;
bool hContinue;
bool *dContinue;
hipMalloc( (void**) &dContinue, sizeof(bool));
//Call the Kernel untill all the elements of Frontier are not false
do
{
//if no thread changes this value then the loop stops
hContinue=false;
hipMemcpy(dContinue, &hContinue, sizeof(bool), hipMemcpyHostToDevice) ;
processEdges1<<< ceil(cCount/1024.0), 1024>>>(cCount ,from, to, departure, duration, earliestTime,dContinue,active,nextActive);
// updateActiveVertices<<<ceil(vCount/1024.0), 1024>>>(vCount,active,nextActive);
//activeToPassive<<<ceil(vCount/1024.0), 1024>>>(vCount,active);
//passiveToActive<<<ceil(vCount/1024.0), 1024>>>(vCount,active, nextActive);
hipMemcpy( &hContinue, dContinue, sizeof(bool), hipMemcpyDeviceToHost) ;
hipDeviceSynchronize();
iterations++;
}
while(hContinue);
}
//computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,active, nextActive, runTime);
void computeEarliestTimesSetUP(int vCount, int cCount,int from[],int to[],int departure[], int duration[], int source[], int departureTime[], int earliestTime[],int qCount)
{
int *cFrom, *cTo, *cDeparture, *cDuration, *cEarliestTime;
bool *cActive, *cNextActive;
struct timeval start,stop;
bool *active, *nextActive;
double time;
initConfiguration(gridDimension,blockDimension, cCount);
createHostMemoryBool(active,vCount);
createHostMemoryBool(nextActive,vCount);
cudaCopyToDevice(from,cFrom,cCount);
cudaCopyToDevice(to,cTo,cCount);
cudaCopyToDevice(departure,cDeparture,cCount);
cudaCopyToDevice(duration,cDuration,cCount);
//cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
//cudaCopyToDevice(active,cActive,vCount);
//cudaCopyToDevice(nextActive,cNextActive,vCount);
for(int i=0; i<=qCount-1; i++)
{
initEarlistTime(earliestTime,vCount,source[i],departureTime[i]);
initActiveVertices(active,vCount,source[i]);
cudaCopyToDevice(earliestTime,cEarliestTime,vCount);
cudaCopyToDeviceBool(active,cActive,vCount);
gettimeofday(&start,0);
computeEarliestTime(vCount,cCount,cFrom,cTo,cDeparture,cDuration,cEarliestTime,cActive, cNextActive);
gettimeofday(&stop,0);
time = (1000000.0*(stop.tv_sec-start.tv_sec) + stop.tv_usec-start.tv_usec)/1000.0;
hipMemcpy(earliestTime, cEarliestTime, vCount * sizeof(int), hipMemcpyDeviceToHost);
printEarliestTimes(earliestTime,vCount,time,PRINTFLAG);
}
hipFree(cEarliestTime);
hipFree(cFrom);
hipFree(cTo);
hipFree(cDeparture);
hipFree(cDuration);
hipFree(cActive);
hipFree(cNextActive);
}
void createHostMemory(int *&X, int n)
{
X = new int[n];
}
void readQuery(char *fileName, int *&source, int *&departureTime, int &qCount)
{
ifstream fin;
fin.open(fileName);
fin>>qCount;
source = new int[qCount];
departureTime = new int[qCount];
for(int i=0; i<=qCount-1; i++)
fin>>source[i]>>departureTime[i];
}
int main(int argc, char *argv[])
{
int vCount, cCount, qCount;
int *from, *to, *departure, *duration, *earliestTime, *source, *departureTime;
char queryFile[100];
char fileName[100];
strcpy(fileName, argv[1]);
strcpy(queryFile,"query.txt");
readInput(fileName,vCount, cCount, from, to, departure, duration);
readQuery(queryFile, source, departureTime, qCount);
createHostMemory(earliestTime,vCount);
//departureTime = 180; //Change this ****************************************
computeEarliestTimesSetUP(vCount,cCount,from,to,departure,duration,source, departureTime,earliestTime,qCount);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13processEdges2iPiS_S_S_S_PbS0_S0_
.globl _Z13processEdges2iPiS_S_S_S_PbS0_S0_
.p2align 8
.type _Z13processEdges2iPiS_S_S_S_PbS0_S0_,@function
_Z13processEdges2iPiS_S_S_S_PbS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
global_load_u8 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x28
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v4, v[3:4], off
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_atomic_min_i32 v[2:3], v4, off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x40
s_load_b64 s[0:1], s[0:1], 0x30
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[0:1], v2, off
global_store_b8 v3, v2, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13processEdges2iPiS_S_S_S_PbS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13processEdges2iPiS_S_S_S_PbS0_S0_, .Lfunc_end0-_Z13processEdges2iPiS_S_S_S_PbS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13processEdges1iPiS_S_S_S_PbS0_S0_
.globl _Z13processEdges1iPiS_S_S_S_PbS0_S0_
.p2align 8
.type _Z13processEdges1iPiS_S_S_S_PbS0_S0_,@function
_Z13processEdges1iPiS_S_S_S_PbS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v7, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
global_load_u8 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x28
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v4, v[3:4], off
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
global_atomic_min_i32 v[2:3], v4, off
s_load_b64 s[0:1], s[0:1], 0x30
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
global_store_b8 v[0:1], v2, off
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v2, s[0:1]
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13processEdges1iPiS_S_S_S_PbS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13processEdges1iPiS_S_S_S_PbS0_S0_, .Lfunc_end1-_Z13processEdges1iPiS_S_S_S_PbS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12processEdgesiPiS_S_S_S_PbS_S_
.globl _Z12processEdgesiPiS_S_S_S_PbS_S_
.p2align 8
.type _Z12processEdgesiPiS_S_S_S_PbS_S_,@function
_Z12processEdgesiPiS_S_S_S_PbS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_4
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v7, v[0:1], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
global_atomic_min_i32 v[0:1], v4, off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x40
s_load_b64 s[0:1], s[0:1], 0x30
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
global_store_b8 v2, v4, s[0:1]
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12processEdgesiPiS_S_S_S_PbS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12processEdgesiPiS_S_S_S_PbS_S_, .Lfunc_end2-_Z12processEdgesiPiS_S_S_S_PbS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15passiveToActiveiPiS_
.globl _Z15passiveToActiveiPiS_
.p2align 8
.type _Z15passiveToActiveiPiS_,@function
_Z15passiveToActiveiPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_3
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15passiveToActiveiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z15passiveToActiveiPiS_, .Lfunc_end3-_Z15passiveToActiveiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15activeToPassiveiPi
.globl _Z15activeToPassiveiPi
.p2align 8
.type _Z15activeToPassiveiPi,@function
_Z15activeToPassiveiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB4_3
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_3
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15activeToPassiveiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z15activeToPassiveiPi, .Lfunc_end4-_Z15activeToPassiveiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13processEdges2iPiS_S_S_S_PbS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13processEdges2iPiS_S_S_S_PbS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13processEdges1iPiS_S_S_S_PbS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13processEdges1iPiS_S_S_S_PbS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12processEdgesiPiS_S_S_S_PbS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12processEdgesiPiS_S_S_S_PbS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15passiveToActiveiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15passiveToActiveiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15activeToPassiveiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15activeToPassiveiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} | code for sm_80
Function : _Z10stencil_ldPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fc800078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x0000a8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x0000e8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402068981 */
/* 0x000124000c1e1900 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fc40000011400 */
/*00c0*/ STS [R13.X4], R4 ; /* 0x000000040d007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4+-0xc], R5 ; /* 0xfffff4050d008388 */
/* 0x008fe80000004800 */
/*00e0*/ @!P0 STS [R13.X4+0x4], R6 ; /* 0x000004060d008388 */
/* 0x010fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0120*/ LDS R7, [R13.X4+-0x8] ; /* 0xfffff8000d077984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R8, [R13.X4+-0xc] ; /* 0xfffff4000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+-0x4] ; /* 0xfffffc000d097984 */
/* 0x000e280000004800 */
/*0150*/ LDS R10, [R13.X4] ; /* 0x000000000d0a7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R13.X4+0x4] ; /* 0x000004000d0b7984 */
/* 0x000e680000004800 */
/*0170*/ LDS R12, [R13.X4+0x8] ; /* 0x000008000d0c7984 */
/* 0x000ea20000004800 */
/*0180*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*0190*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fca0007ffe007 */
/*01a0*/ IMAD.IADD R7, R7, 0x1, R12 ; /* 0x0000000107077824 */
/* 0x004fca00078e020c */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} | .file "tmpxft_0019a5df_00000000-6_stencil_ld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10stencil_ldPjS_PjS_
.type _Z32__device_stub__Z10stencil_ldPjS_PjS_, @function
_Z32__device_stub__Z10stencil_ldPjS_PjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_ldPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10stencil_ldPjS_PjS_, .-_Z32__device_stub__Z10stencil_ldPjS_PjS_
.globl _Z10stencil_ldPjS_
.type _Z10stencil_ldPjS_, @function
_Z10stencil_ldPjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_ldPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10stencil_ldPjS_, .-_Z10stencil_ldPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10stencil_ldPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_ldPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_ldPjS_
.globl _Z10stencil_ldPjS_
.p2align 8
.type _Z10stencil_ldPjS_,@function
_Z10stencil_ldPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-12
global_load_b32 v3, v[3:4], off offset:-4
v_add_nc_u32_e32 v4, -12, v5
s_waitcnt vmcnt(1)
ds_store_b32 v4, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, -12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 12
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_ldPjS_
.amdhsa_group_segment_fixed_size 28
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_ldPjS_, .Lfunc_end0-_Z10stencil_ldPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 28
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_ldPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_ldPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil_ld(unsigned *in, unsigned *out){
__shared__ int temp[BLOCK_SIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x;
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS){
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex - BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for(int offset = -RADIUS; offset < RADIUS; offset++){
result += temp[lindex + offset];
}
out[gindex] = result;
} | .text
.file "stencil_ld.hip"
.globl _Z25__device_stub__stencil_ldPjS_ # -- Begin function _Z25__device_stub__stencil_ldPjS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_ldPjS_,@function
_Z25__device_stub__stencil_ldPjS_: # @_Z25__device_stub__stencil_ldPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_ldPjS_, .Lfunc_end0-_Z25__device_stub__stencil_ldPjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_ldPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_ldPjS_,@object # @_Z10stencil_ldPjS_
.section .rodata,"a",@progbits
.globl _Z10stencil_ldPjS_
.p2align 3, 0x0
_Z10stencil_ldPjS_:
.quad _Z25__device_stub__stencil_ldPjS_
.size _Z10stencil_ldPjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10stencil_ldPjS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_ldPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_ldPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10stencil_ldPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fc800078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x0000a8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x0000e8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402068981 */
/* 0x000124000c1e1900 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fc40000011400 */
/*00c0*/ STS [R13.X4], R4 ; /* 0x000000040d007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4+-0xc], R5 ; /* 0xfffff4050d008388 */
/* 0x008fe80000004800 */
/*00e0*/ @!P0 STS [R13.X4+0x4], R6 ; /* 0x000004060d008388 */
/* 0x010fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0120*/ LDS R7, [R13.X4+-0x8] ; /* 0xfffff8000d077984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R8, [R13.X4+-0xc] ; /* 0xfffff4000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+-0x4] ; /* 0xfffffc000d097984 */
/* 0x000e280000004800 */
/*0150*/ LDS R10, [R13.X4] ; /* 0x000000000d0a7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R13.X4+0x4] ; /* 0x000004000d0b7984 */
/* 0x000e680000004800 */
/*0170*/ LDS R12, [R13.X4+0x8] ; /* 0x000008000d0c7984 */
/* 0x000ea20000004800 */
/*0180*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*0190*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fca0007ffe007 */
/*01a0*/ IMAD.IADD R7, R7, 0x1, R12 ; /* 0x0000000107077824 */
/* 0x004fca00078e020c */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_ldPjS_
.globl _Z10stencil_ldPjS_
.p2align 8
.type _Z10stencil_ldPjS_,@function
_Z10stencil_ldPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-12
global_load_b32 v3, v[3:4], off offset:-4
v_add_nc_u32_e32 v4, -12, v5
s_waitcnt vmcnt(1)
ds_store_b32 v4, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, -12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 12
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_ldPjS_
.amdhsa_group_segment_fixed_size 28
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_ldPjS_, .Lfunc_end0-_Z10stencil_ldPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 28
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_ldPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_ldPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019a5df_00000000-6_stencil_ld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10stencil_ldPjS_PjS_
.type _Z32__device_stub__Z10stencil_ldPjS_PjS_, @function
_Z32__device_stub__Z10stencil_ldPjS_PjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_ldPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10stencil_ldPjS_PjS_, .-_Z32__device_stub__Z10stencil_ldPjS_PjS_
.globl _Z10stencil_ldPjS_
.type _Z10stencil_ldPjS_, @function
_Z10stencil_ldPjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_ldPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10stencil_ldPjS_, .-_Z10stencil_ldPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10stencil_ldPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_ldPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencil_ld.hip"
.globl _Z25__device_stub__stencil_ldPjS_ # -- Begin function _Z25__device_stub__stencil_ldPjS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_ldPjS_,@function
_Z25__device_stub__stencil_ldPjS_: # @_Z25__device_stub__stencil_ldPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_ldPjS_, .Lfunc_end0-_Z25__device_stub__stencil_ldPjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_ldPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_ldPjS_,@object # @_Z10stencil_ldPjS_
.section .rodata,"a",@progbits
.globl _Z10stencil_ldPjS_
.p2align 3, 0x0
_Z10stencil_ldPjS_:
.quad _Z25__device_stub__stencil_ldPjS_
.size _Z10stencil_ldPjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10stencil_ldPjS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_ldPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_ldPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} | code for sm_80
Function : _Z13NaiveMMKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} | .file "tmpxft_00064171_00000000-6_NaiveMMKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13NaiveMMKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
.globl _Z13NaiveMMKernelPfS_S_i
.type _Z13NaiveMMKernelPfS_S_i, @function
_Z13NaiveMMKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13NaiveMMKernelPfS_S_i, .-_Z13NaiveMMKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13NaiveMMKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13NaiveMMKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} | #include <hip/hip_runtime.h>
#include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13NaiveMMKernelPfS_S_i
.globl _Z13NaiveMMKernelPfS_S_i
.p2align 8
.type _Z13NaiveMMKernelPfS_S_i,@function
_Z13NaiveMMKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13NaiveMMKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13NaiveMMKernelPfS_S_i, .Lfunc_end0-_Z13NaiveMMKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13NaiveMMKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13NaiveMMKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/// Tile size used by the OptimizedMMKernel
#define TILE_SIZE 32
/// Naive matrix multiplication CUDA Kernel
/// Tiled 1D Shared Memory No Unrolling
/// Tiled 2D Shared Memory No Unrolling
/// Tiled 2D Shared Memory With Unrolling (4x4 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (8x8 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (16x16 Tile Size)
/// Tiled 2D Shared Memory With Unrolling (32x32 Tile Size)
/// Prints a matrix out to the stderr stream
__global__ void NaiveMMKernel(float *a, float *b, float *c, int size)
{
int xOut = blockDim.x * blockIdx.x + threadIdx.x;
int yOut = blockDim.y * blockIdx.y + threadIdx.y;
float outValue = 0;
for (int i = 0; i < size; i++)
{
// Row of a mulitplied by the column of b
float prod = a[yOut * size + i] * b[i * size + xOut];
outValue += prod;
}
// Store sum of dot products in C matrix
c[yOut * size + xOut] = outValue;
} | .text
.file "NaiveMMKernel.hip"
.globl _Z28__device_stub__NaiveMMKernelPfS_S_i # -- Begin function _Z28__device_stub__NaiveMMKernelPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__NaiveMMKernelPfS_S_i,@function
_Z28__device_stub__NaiveMMKernelPfS_S_i: # @_Z28__device_stub__NaiveMMKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13NaiveMMKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__NaiveMMKernelPfS_S_i, .Lfunc_end0-_Z28__device_stub__NaiveMMKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13NaiveMMKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13NaiveMMKernelPfS_S_i,@object # @_Z13NaiveMMKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z13NaiveMMKernelPfS_S_i
.p2align 3, 0x0
_Z13NaiveMMKernelPfS_S_i:
.quad _Z28__device_stub__NaiveMMKernelPfS_S_i
.size _Z13NaiveMMKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13NaiveMMKernelPfS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__NaiveMMKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13NaiveMMKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13NaiveMMKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13NaiveMMKernelPfS_S_i
.globl _Z13NaiveMMKernelPfS_S_i
.p2align 8
.type _Z13NaiveMMKernelPfS_S_i,@function
_Z13NaiveMMKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13NaiveMMKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13NaiveMMKernelPfS_S_i, .Lfunc_end0-_Z13NaiveMMKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13NaiveMMKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13NaiveMMKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064171_00000000-6_NaiveMMKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13NaiveMMKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
.globl _Z13NaiveMMKernelPfS_S_i
.type _Z13NaiveMMKernelPfS_S_i, @function
_Z13NaiveMMKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13NaiveMMKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13NaiveMMKernelPfS_S_i, .-_Z13NaiveMMKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13NaiveMMKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13NaiveMMKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NaiveMMKernel.hip"
.globl _Z28__device_stub__NaiveMMKernelPfS_S_i # -- Begin function _Z28__device_stub__NaiveMMKernelPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__NaiveMMKernelPfS_S_i,@function
_Z28__device_stub__NaiveMMKernelPfS_S_i: # @_Z28__device_stub__NaiveMMKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13NaiveMMKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__NaiveMMKernelPfS_S_i, .Lfunc_end0-_Z28__device_stub__NaiveMMKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13NaiveMMKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13NaiveMMKernelPfS_S_i,@object # @_Z13NaiveMMKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z13NaiveMMKernelPfS_S_i
.p2align 3, 0x0
_Z13NaiveMMKernelPfS_S_i:
.quad _Z28__device_stub__NaiveMMKernelPfS_S_i
.size _Z13NaiveMMKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13NaiveMMKernelPfS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__NaiveMMKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13NaiveMMKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
cudaHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
cudaHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} | .file "tmpxft_00005681_00000000-6_memcpy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "host->device elapsed time: "
.LC1:
.string " ms"
.LC2:
.string "device->host elapsed time: "
.text
.globl _Z6memcpyv
.type _Z6memcpyv, @function
_Z6memcpyv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $41943040, %edi
call _Znam@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $41943040, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 41943040(%r12), %rbp
.L4:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $41943040, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $27, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L16
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %eax
.L8:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $41943040, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $27, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L17
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %eax
.L12:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
call _ZSt16__throw_bad_castv@PLT
.L19:
call __stack_chk_fail@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L8
.L17:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
call _ZSt16__throw_bad_castv@PLT
.L20:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z6memcpyv, .-_Z6memcpyv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "page-locked host->device elapsed time: "
.align 8
.LC4:
.string "page-locked device->host elapsed time: "
.text
.globl _Z17memcpy_PageLockedv
.type _Z17memcpy_PageLockedv, @function
_Z17memcpy_PageLockedv:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $41943040, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $41943040, %esi
call cudaHostAlloc@PLT
movl $0, %ebx
.L22:
movq %rbx, %rbp
addq 16(%rsp), %rbp
call rand@PLT
movl %eax, 0(%rbp)
addq $4, %rbx
cmpq $41943040, %rbx
jne .L22
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $41943040, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L34
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %eax
.L26:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $41943040, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L35
cmpb $0, 56(%rbp)
je .L29
movzbl 67(%rbp), %eax
.L30:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
call _ZSt16__throw_bad_castv@PLT
.L37:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L26
.L35:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L29:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z17memcpy_PageLockedv, .-_Z17memcpy_PageLockedv
.section .rodata.str1.8
.align 8
.LC5:
.string "Device does not support overlapping"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 400(%rsp)
je .L44
call _Z6memcpyv
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _Z17memcpy_PageLockedv
movl $0, %eax
.L39:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L45
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %eax
jmp .L39
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
cudaMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
cudaHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
cudaEventRecord(start, 0);
cudaMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
hipHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
hipHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 10)
using namespace std;
void memcpy()
{
int *dev;
int *host = new int[FULL_DATA_SIZE];
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "device->host elapsed time: " << elapsedTime << " ms" << endl;
}
void memcpy_PageLocked()
{
int *dev;
int *host;
hipMalloc((void**)&dev, FULL_DATA_SIZE * sizeof(int));
hipHostAlloc((void**)&host, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < FULL_DATA_SIZE; i++)
host[i] = rand();
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(dev, host, FULL_DATA_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked host->device elapsed time: " << elapsedTime << " ms" << endl;
hipEventRecord(start, 0);
hipMemcpy(host, dev, FULL_DATA_SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "page-locked device->host elapsed time: " << elapsedTime << " ms" << endl;
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 1;
}
memcpy();
cout << endl;
memcpy_PageLocked();
return 0;
} | .text
.file "memcpy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6memcpyv # -- Begin function _Z6memcpyv
.p2align 4, 0x90
.type _Z6memcpyv,@function
_Z6memcpyv: # @_Z6memcpyv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $41943040, %edi # imm = 0x2800000
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $41943040, %esi # imm = 0x2800000
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10485760, %r14 # imm = 0xA00000
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $41943040, %edx # imm = 0x2800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB0_6
.LBB0_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%r14)
je .LBB0_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB0_10
.LBB0_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z6memcpyv, .Lfunc_end0-_Z6memcpyv
.cfi_endproc
# -- End function
.globl _Z17memcpy_PageLockedv # -- Begin function _Z17memcpy_PageLockedv
.p2align 4, 0x90
.type _Z17memcpy_PageLockedv,@function
_Z17memcpy_PageLockedv: # @_Z17memcpy_PageLockedv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rdi
movl $41943040, %esi # imm = 0x2800000
callq hipMalloc
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $41943040, %esi # imm = 0x2800000
xorl %edx, %edx
callq hipHostAlloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $10485760, %rbx # imm = 0xA00000
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq 32(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB1_10
.LBB1_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z17memcpy_PageLockedv, .Lfunc_end1-_Z17memcpy_PageLockedv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 400(%rsp)
je .LBB2_1
# %bb.6:
callq _Z6memcpyv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_1:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_12
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB2_5
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _Z17memcpy_PageLockedv
xorl %eax, %eax
jmp .LBB2_11
.LBB2_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
.LBB2_11:
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "host->device elapsed time: "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "device->host elapsed time: "
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "page-locked host->device elapsed time: "
.size .L.str.3, 40
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "page-locked device->host elapsed time: "
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device does not support overlapping"
.size .L.str.5, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005681_00000000-6_memcpy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "host->device elapsed time: "
.LC1:
.string " ms"
.LC2:
.string "device->host elapsed time: "
.text
.globl _Z6memcpyv
.type _Z6memcpyv, @function
_Z6memcpyv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $41943040, %edi
call _Znam@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $41943040, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 41943040(%r12), %rbp
.L4:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $41943040, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $27, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L16
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %eax
.L8:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $41943040, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $27, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L17
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %eax
.L12:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
call _ZSt16__throw_bad_castv@PLT
.L19:
call __stack_chk_fail@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L8
.L17:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
call _ZSt16__throw_bad_castv@PLT
.L20:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z6memcpyv, .-_Z6memcpyv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "page-locked host->device elapsed time: "
.align 8
.LC4:
.string "page-locked device->host elapsed time: "
.text
.globl _Z17memcpy_PageLockedv
.type _Z17memcpy_PageLockedv, @function
_Z17memcpy_PageLockedv:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $41943040, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $41943040, %esi
call cudaHostAlloc@PLT
movl $0, %ebx
.L22:
movq %rbx, %rbp
addq 16(%rsp), %rbp
call rand@PLT
movl %eax, 0(%rbp)
addq $4, %rbx
cmpq $41943040, %rbx
jne .L22
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $41943040, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L34
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %eax
.L26:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $41943040, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $39, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L35
cmpb $0, 56(%rbp)
je .L29
movzbl 67(%rbp), %eax
.L30:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
call _ZSt16__throw_bad_castv@PLT
.L37:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L26
.L35:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L29:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z17memcpy_PageLockedv, .-_Z17memcpy_PageLockedv
.section .rodata.str1.8
.align 8
.LC5:
.string "Device does not support overlapping"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 400(%rsp)
je .L44
call _Z6memcpyv
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _Z17memcpy_PageLockedv
movl $0, %eax
.L39:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L45
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %eax
jmp .L39
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcpy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6memcpyv # -- Begin function _Z6memcpyv
.p2align 4, 0x90
.type _Z6memcpyv,@function
_Z6memcpyv: # @_Z6memcpyv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $41943040, %edi # imm = 0x2800000
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $41943040, %esi # imm = 0x2800000
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10485760, %r14 # imm = 0xA00000
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $41943040, %edx # imm = 0x2800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB0_6
.LBB0_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%r14)
je .LBB0_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB0_10
.LBB0_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z6memcpyv, .Lfunc_end0-_Z6memcpyv
.cfi_endproc
# -- End function
.globl _Z17memcpy_PageLockedv # -- Begin function _Z17memcpy_PageLockedv
.p2align 4, 0x90
.type _Z17memcpy_PageLockedv,@function
_Z17memcpy_PageLockedv: # @_Z17memcpy_PageLockedv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rdi
movl $41943040, %esi # imm = 0x2800000
callq hipMalloc
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $41943040, %esi # imm = 0x2800000
xorl %edx, %edx
callq hipHostAlloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $10485760, %rbx # imm = 0xA00000
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq 32(%rsp), %rsi
movl $41943040, %edx # imm = 0x2800000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB1_10
.LBB1_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z17memcpy_PageLockedv, .Lfunc_end1-_Z17memcpy_PageLockedv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 400(%rsp)
je .LBB2_1
# %bb.6:
callq _Z6memcpyv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_1:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_12
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB2_5
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _Z17memcpy_PageLockedv
xorl %eax, %eax
jmp .LBB2_11
.LBB2_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
.LBB2_11:
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "host->device elapsed time: "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "device->host elapsed time: "
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "page-locked host->device elapsed time: "
.size .L.str.3, 40
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "page-locked device->host elapsed time: "
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device does not support overlapping"
.size .L.str.5, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
cudaMalloc((void**) &gpu_A, sizeof(double) * M * N);
cudaMalloc((void**) &gpu_B, sizeof(double) * N * O);
cudaMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
cudaMemcpy(gpu_A, A, sizeof(double) * M * N, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_B, b, sizeof(double) * N * O, cudaMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
cudaMemcpy(c, gpu_C, sizeof(double) * M * O, cudaMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
cudaFree(gpu_A);
cudaFree(gpu_B);
cudaFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} | code for sm_80
Function : _Z7mat_mulPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002200 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R2, R8, c[0x0][0x4], R9 ; /* 0x0000010008027a24 */
/* 0x001fc800078e0209 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e000b */
/*0090*/ IMAD R4, R6, c[0x0][0x10], R7 ; /* 0x0000040006047a24 */
/* 0x002fe400078e0207 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e000b */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IMAD R8, R8, c[0x0][0x10], R7 ; /* 0x0000040008087a24 */
/* 0x000fe200078e0207 */
/*00e0*/ LOP3.LUT P0, RZ, R6, R9, RZ, 0xfc, !PT ; /* 0x0000000906ff7212 */
/* 0x000fc6000780fcff */
/*00f0*/ IMAD R0, R8, c[0x0][0x4], RZ ; /* 0x0000010008007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0209 */
/*0110*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*0120*/ STS.64 [R9.X8], R6 ; /* 0x0000000609007388 */
/* 0x0011e80000008a00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0150*/ IMAD.WIDE.U32 R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fe200078e000b */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc4000001ff00 */
/*0180*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0190*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101b06 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R15.reuse, 0x3, PT ; /* 0x000000030f00780c */
/* 0x040fe40003f06070 */
/*01b0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ LOP3.LUT R15, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f0f7812 */
/* 0x000fce00078ec0ff */
/*01d0*/ @!P0 BRA 0x740 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R16, -R15, c[0x0][0x4], RZ ; /* 0x000001000f107a10 */
/* 0x001fe20007ffe1ff */
/*01f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0200*/ LEA R14, R0, 0x10, 0x3 ; /* 0x00000010000e7811 */
/* 0x000fe200078e18ff */
/*0210*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.GT.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fda0003f04270 */
/*0230*/ @!P0 BRA 0x670 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R6, R16, 0x1, RZ ; /* 0x0000000110067810 */
/* 0x000fe40007ffe0ff */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0260*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fda0003f24270 */
/*0270*/ @!P1 BRA 0x4e0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0290*/ LDS.64 R8, [R14+-0x10] ; /* 0xfffff0000e087984 */
/* 0x001e220000000a00 */
/*02a0*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*02c0*/ LDS.64 R22, [R14+-0x8] ; /* 0xfffff8000e167984 */
/* 0x002e620000000a00 */
/*02d0*/ ISETP.GT.AND P1, PT, R16, 0xb, PT ; /* 0x0000000b1000780c */
/* 0x000fc60003f24270 */
/*02e0*/ LDS.64 R6, [R14] ; /* 0x000000000e067984 */
/* 0x000ea80000000a00 */
/*02f0*/ LDS.64 R20, [R14+0x8] ; /* 0x000008000e147984 */
/* 0x000ee80000000a00 */
/*0300*/ LDS.64 R18, [R14+0x10] ; /* 0x000010000e127984 */
/* 0x000f280000000a00 */
/*0310*/ LDS.64 R12, [R14+0x18] ; /* 0x000018000e0c7984 */
/* 0x000f680000000a00 */
/*0320*/ LDS.64 R10, [R14+0x20] ; /* 0x000020000e0a7984 */
/* 0x000f220000000a00 */
/*0330*/ DADD R4, R8, R4 ; /* 0x0000000008047229 */
/* 0x0010460000000004 */
/*0340*/ LDS.64 R8, [R14+0x28] ; /* 0x000028000e087984 */
/* 0x001e260000000a00 */
/*0350*/ DADD R22, R4, R22 ; /* 0x0000000004167229 */
/* 0x0022880000000016 */
/*0360*/ LDS.64 R4, [R14+0x30] ; /* 0x000030000e047984 */
/* 0x002e640000000a00 */
/*0370*/ DADD R22, R22, R6 ; /* 0x0000000016167229 */
/* 0x0044e40000000006 */
/*0380*/ LDS.64 R6, [R14+0x38] ; /* 0x000038000e067984 */
/* 0x004ea80000000a00 */
/*0390*/ DADD R22, R22, R20 ; /* 0x0000000016167229 */
/* 0x0087240000000014 */
/*03a0*/ LDS.64 R20, [R14+0x40] ; /* 0x000040000e147984 */
/* 0x008ee80000000a00 */
/*03b0*/ DADD R22, R22, R18 ; /* 0x0000000016167229 */
/* 0x0109440000000012 */
/*03c0*/ LDS.64 R18, [R14+0x48] ; /* 0x000048000e127984 */
/* 0x010f280000000a00 */
/*03d0*/ DADD R22, R22, R12 ; /* 0x0000000016167229 */
/* 0x020b64000000000c */
/*03e0*/ LDS.64 R12, [R14+0x50] ; /* 0x000050000e0c7984 */
/* 0x020f680000000a00 */
/*03f0*/ DADD R22, R22, R10 ; /* 0x0000000016167229 */
/* 0x000004000000000a */
/*0400*/ LDS.64 R10, [R14+0x58] ; /* 0x000058000e0a7984 */
/* 0x001e280000000a00 */
/*0410*/ DADD R22, R22, R8 ; /* 0x0000000016167229 */
/* 0x0002640000000008 */
/*0420*/ LDS.64 R8, [R14+0x60] ; /* 0x000060000e087984 */
/* 0x002e680000000a00 */
/*0430*/ DADD R22, R22, R4 ; /* 0x0000000016167229 */
/* 0x0004840000000004 */
/*0440*/ LDS.64 R4, [R14+0x68] ; /* 0x000068000e047984 */
/* 0x0044680000000a00 */
/*0450*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x000ee20000000006 */
/*0460*/ IADD3 R14, R14, 0x80, RZ ; /* 0x000000800e0e7810 */
/* 0x004fca0007ffe0ff */
/*0470*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x008f0c0000000014 */
/*0480*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x010f4c0000000012 */
/*0490*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*04a0*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e4c000000000a */
/*04b0*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002e0c0000000008 */
/*04c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0010620000000004 */
/*04d0*/ @P1 BRA 0x290 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*04e0*/ IADD3 R6, R16, 0x1, RZ ; /* 0x0000000110067810 */
/* 0x001fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0500*/ @!P1 BRA 0x650 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0510*/ LDS.64 R22, [R14+-0x10] ; /* 0xfffff0000e167984 */
/* 0x000e220000000a00 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0530*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0540*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe20007ffe0ff */
/*0550*/ LDS.64 R6, [R14+-0x8] ; /* 0xfffff8000e067984 */
/* 0x000ea80000000a00 */
/*0560*/ LDS.64 R20, [R14] ; /* 0x000000000e147984 */
/* 0x000ee80000000a00 */
/*0570*/ LDS.64 R18, [R14+0x8] ; /* 0x000008000e127984 */
/* 0x000f280000000a00 */
/*0580*/ LDS.64 R12, [R14+0x10] ; /* 0x000010000e0c7984 */
/* 0x000f680000000a00 */
/*0590*/ LDS.64 R10, [R14+0x18] ; /* 0x000018000e0a7984 */
/* 0x000e680000000a00 */
/*05a0*/ LDS.64 R8, [R14+0x20] ; /* 0x000020000e087984 */
/* 0x000e640000000a00 */
/*05b0*/ DADD R22, R4, R22 ; /* 0x0000000004167229 */
/* 0x0030840000000016 */
/*05c0*/ LDS.64 R4, [R14+0x28] ; /* 0x000028000e047984 */
/* 0x0010680000000a00 */
/*05d0*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x004ee20000000006 */
/*05e0*/ IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x001fca0007ffe0ff */
/*05f0*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x008f0c0000000014 */
/*0600*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x010f4c0000000012 */
/*0610*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*0620*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e0c000000000a */
/*0630*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e4c0000000008 */
/*0640*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0020480000000004 */
/*0650*/ ISETP.NE.OR P0, PT, R16, -0x1, P0 ; /* 0xffffffff1000780c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x740 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0670*/ LDS.64 R6, [R14+-0x10] ; /* 0xfffff0000e067984 */
/* 0x001e220000000a00 */
/*0680*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe20007ffe0ff */
/*0690*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*06a0*/ LDS.64 R8, [R14+-0x8] ; /* 0xfffff8000e087984 */
/* 0x000ea20000000a00 */
/*06b0*/ ISETP.NE.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fc60003f05270 */
/*06c0*/ LDS.64 R10, [R14] ; /* 0x000000000e0a7984 */
/* 0x000ee80000000a00 */
/*06d0*/ LDS.64 R12, [R14+0x8] ; /* 0x000008000e0c7984 */
/* 0x0009640000000a00 */
/*06e0*/ IADD3 R14, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x010fe20007ffe0ff */
/*06f0*/ DADD R6, R6, R4 ; /* 0x0000000006067229 */
/* 0x003e8c0000000004 */
/*0700*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004ecc0000000008 */
/*0710*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x008f4c000000000a */
/*0720*/ DADD R4, R6, R12 ; /* 0x0000000006047229 */
/* 0x020064000000000c */
/*0730*/ @P0 BRA 0x670 ; /* 0xffffff3000000947 */
/* 0x003fea000383ffff */
/*0740*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x001fda0003f05270 */
/*0750*/ @!P0 BRA 0x7e0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0760*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fca000fffe0ff */
/*0770*/ IMAD.SHL.U32 R0, R0, 0x8, RZ ; /* 0x0000000800007824 */
/* 0x000fca00078e00ff */
/*0780*/ LDS.64 R6, [R0] ; /* 0x0000000000067984 */
/* 0x0010a20000000a00 */
/*0790*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fc80007ffe0ff */
/*07a0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*07b0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x001fe20007ffe0ff */
/*07c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0060540000000004 */
/*07d0*/ @P0 BRA 0x780 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b06 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
cudaMalloc((void**) &gpu_A, sizeof(double) * M * N);
cudaMalloc((void**) &gpu_B, sizeof(double) * N * O);
cudaMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
cudaMemcpy(gpu_A, A, sizeof(double) * M * N, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_B, b, sizeof(double) * N * O, cudaMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
cudaMemcpy(c, gpu_C, sizeof(double) * M * O, cudaMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
cudaFree(gpu_A);
cudaFree(gpu_B);
cudaFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} | .file "tmpxft_000a3c60_00000000-6_lab5_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[\n"
.LC1:
.string "["
.LC2:
.string "%.2f, "
.LC3:
.string "%.2f],\n"
.LC4:
.string "%.2f]]"
.text
.globl _Z7mat2strPcPviii
.type _Z7mat2strPcPviii, @function
_Z7mat2strPcPviii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movq %rsi, %r14
movq %rsi, 24(%rsp)
movl %edx, %ebx
movl %ecx, %r15d
movl %ecx, 12(%rsp)
movl %r8d, %r12d
movslq %r8d, %rsi
leaq .LC0(%rip), %rdx
movl $0, %eax
call snprintf@PLT
movl %eax, %ebp
leal -1(%rbx), %eax
movl %eax, 60(%rsp)
testl %eax, %eax
jle .L4
movl %r15d, %eax
movslq %r15d, %rdx
salq $3, %rdx
leaq (%r14,%rdx), %rcx
movq %rcx, 16(%rsp)
leal -1(%rbx), %ecx
movl %ecx, 36(%rsp)
movl $0, 32(%rsp)
movl $0, 8(%rsp)
subl $2, %eax
movl %eax, 56(%rsp)
leaq 8(%r14), %rax
movq %rax, 48(%rsp)
leaq .LC2(%rip), %r15
movl %ebp, %ebx
movq %rdx, 40(%rsp)
.L7:
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
leaq .LC1(%rip), %rdx
movl $0, %eax
call snprintf@PLT
addl %eax, %ebx
cmpl $1, 12(%rsp)
jle .L5
movslq 32(%rsp), %rdx
movq 24(%rsp), %rax
leaq (%rax,%rdx,8), %rbp
movl 56(%rsp), %eax
addq %rdx, %rax
movq 48(%rsp), %rcx
leaq (%rcx,%rax,8), %r14
.L6:
movsd 0(%rbp), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
movq %r15, %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
addq $8, %rbp
cmpq %r14, %rbp
jne .L6
.L5:
movq 16(%rsp), %r14
movsd -8(%r14), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
leaq .LC3(%rip), %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
addl $1, 8(%rsp)
movl 8(%rsp), %eax
movq 40(%rsp), %rcx
addq %rcx, %r14
movq %r14, 16(%rsp)
movl 12(%rsp), %edx
addl %edx, 32(%rsp)
movl 36(%rsp), %ecx
cmpl %ecx, %eax
jne .L7
movl %ebx, %ebp
.L4:
movl %r12d, %esi
subl %ebp, %esi
movslq %esi, %rsi
movslq %ebp, %rdi
addq %r13, %rdi
leaq .LC1(%rip), %rdx
movl $0, %eax
call snprintf@PLT
leal (%rax,%rbp), %ebx
movl 12(%rsp), %edx
cmpl $1, %edx
jle .L8
movl %edx, %eax
movl 60(%rsp), %ecx
imull %ecx, %eax
cltq
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %rbp
leal -2(%rdx), %edx
addq %rdx, %rax
leaq (%rcx,%rax,8), %r15
leaq .LC2(%rip), %r14
.L9:
movsd 0(%rbp), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
movq %r14, %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
movq %rbp, %rax
addq $8, %rbp
cmpq %r15, %rax
jne .L9
.L8:
movl 60(%rsp), %eax
movl 12(%rsp), %ecx
imull %ecx, %eax
movslq %eax, %rdx
movslq %ecx, %rax
addq %rdx, %rax
movq 24(%rsp), %rdx
movsd -8(%rdx,%rax,8), %xmm0
subl %ebx, %r12d
movslq %r12d, %rsi
movslq %ebx, %rbx
leaq 0(%r13,%rbx), %rdi
leaq .LC4(%rip), %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7mat2strPcPviii, .-_Z7mat2strPcPviii
.globl _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
.type _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_, @function
_Z30__device_stub__Z7mat_mulPdS_S_PdS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_mulPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_, .-_Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
.globl _Z7mat_mulPdS_S_
.type _Z7mat_mulPdS_S_, @function
_Z7mat_mulPdS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7mat_mulPdS_S_, .-_Z7mat_mulPdS_S_
.section .rodata.str1.1
.LC23:
.string "A: %s\n"
.LC24:
.string "b: %s\n"
.LC25:
.string "c: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1112, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movsd .LC5(%rip), %xmm0
movsd %xmm0, 144(%rsp)
movsd .LC6(%rip), %xmm1
movsd %xmm1, 152(%rsp)
movsd .LC7(%rip), %xmm2
movsd %xmm2, 160(%rsp)
movq $0x000000000, 168(%rsp)
movsd %xmm2, 176(%rsp)
movsd .LC9(%rip), %xmm2
movsd %xmm2, 184(%rsp)
movsd %xmm1, 192(%rsp)
movsd .LC10(%rip), %xmm3
movsd %xmm3, 200(%rsp)
movq $0x000000000, 208(%rsp)
movsd %xmm0, 216(%rsp)
movsd %xmm0, 224(%rsp)
movsd %xmm3, 232(%rsp)
movsd %xmm0, 240(%rsp)
movsd %xmm1, 248(%rsp)
movsd %xmm2, 256(%rsp)
movsd %xmm2, 264(%rsp)
movsd %xmm2, 272(%rsp)
movsd %xmm1, 280(%rsp)
movsd %xmm1, 288(%rsp)
movsd %xmm0, 296(%rsp)
movq .LC11(%rip), %rax
movq %rax, 304(%rsp)
movq .LC12(%rip), %rax
movq %rax, 312(%rsp)
movq .LC13(%rip), %rax
movq %rax, 320(%rsp)
movq .LC14(%rip), %rax
movq %rax, 328(%rsp)
movq .LC15(%rip), %rax
movq %rax, 336(%rsp)
movq .LC16(%rip), %rax
movq %rax, 344(%rsp)
movq .LC17(%rip), %rax
movq %rax, 352(%rsp)
movq .LC18(%rip), %rax
movq %rax, 360(%rsp)
movq .LC19(%rip), %rax
movq %rax, 48(%rsp)
movq .LC20(%rip), %rax
movq %rax, 56(%rsp)
movq .LC21(%rip), %rax
movq %rax, 64(%rsp)
movq .LC22(%rip), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rbp
leaq 448(%rsp), %r13
movl $320, %r8d
movl $4, %ecx
movl $7, %edx
movq %rbp, %rsi
movq %r13, %rdi
call _Z7mat2strPcPviii
leaq 48(%rsp), %rbx
leaq 768(%rsp), %r12
movl $320, %r8d
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z7mat2strPcPviii
movq %r13, %rdx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $224, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $56, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $224, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $7, 24(%rsp)
movl $1, 28(%rsp)
movl $7, 36(%rsp)
movl $4, 40(%rsp)
movl $0, %r9d
movl $224, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
leaq 80(%rsp), %rbp
movl $2, %ecx
movl $56, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 368(%rsp), %rbx
movl $80, %r8d
movl $1, %ecx
movl $7, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z7mat2strPcPviii
movq %rbx, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
jmp .L23
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC26:
.string "_Z7mat_mulPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_mulPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1074266112
.align 8
.LC6:
.long 0
.long 1075052544
.align 8
.LC7:
.long 0
.long 1073741824
.align 8
.LC9:
.long 0
.long 1074790400
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC11:
.long 0
.long 1076101120
.align 8
.LC12:
.long 0
.long 1076494336
.align 8
.LC13:
.long 0
.long 1077215232
.align 8
.LC14:
.long 0
.long 1076887552
.align 8
.LC15:
.long 0
.long 1075970048
.align 8
.LC16:
.long 0
.long 1076232192
.align 8
.LC17:
.long 0
.long 1076756480
.align 8
.LC18:
.long 0
.long 1075838976
.align 8
.LC19:
.long -1546188227
.long 1077804400
.align 8
.LC20:
.long 1202590843
.long 1076755169
.align 8
.LC21:
.long 1202590843
.long 1076099809
.align 8
.LC22:
.long -1546188227
.long 1077476720
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
cudaMalloc((void**) &gpu_A, sizeof(double) * M * N);
cudaMalloc((void**) &gpu_B, sizeof(double) * N * O);
cudaMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
cudaMemcpy(gpu_A, A, sizeof(double) * M * N, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_B, b, sizeof(double) * N * O, cudaMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
cudaMemcpy(c, gpu_C, sizeof(double) * M * O, cudaMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
cudaFree(gpu_A);
cudaFree(gpu_B);
cudaFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
hipMalloc((void**) &gpu_A, sizeof(double) * M * N);
hipMalloc((void**) &gpu_B, sizeof(double) * N * O);
hipMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
hipMemcpy(gpu_A, A, sizeof(double) * M * N, hipMemcpyHostToDevice);
hipMemcpy(gpu_B, b, sizeof(double) * N * O, hipMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
hipMemcpy(c, gpu_C, sizeof(double) * M * O, hipMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
hipFree(gpu_A);
hipFree(gpu_B);
hipFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
hipMalloc((void**) &gpu_A, sizeof(double) * M * N);
hipMalloc((void**) &gpu_B, sizeof(double) * N * O);
hipMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
hipMemcpy(gpu_A, A, sizeof(double) * M * N, hipMemcpyHostToDevice);
hipMemcpy(gpu_B, b, sizeof(double) * N * O, hipMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
hipMemcpy(c, gpu_C, sizeof(double) * M * O, hipMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
hipFree(gpu_A);
hipFree(gpu_B);
hipFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_mulPdS_S_
.globl _Z7mat_mulPdS_S_
.p2align 8
.type _Z7mat_mulPdS_S_,@function
_Z7mat_mulPdS_S_:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[4:5], null, s5, v0, s[2:3]
s_mul_i32 s3, s5, s14
v_or_b32_e32 v0, v0, v1
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_add_i32 s2, s3, s15
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_mad_u64_u32 v[4:5], null, s2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v4, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[6:7], s[2:3], 3
s_mul_i32 s2, s2, s4
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_lshl_b32 s3, s2, 3
s_add_i32 s2, s4, 1
s_add_i32 s3, s3, 0
global_store_b64 v4, v[2:3], s[0:1]
.LBB0_2:
v_mov_b32_e32 v2, s3
s_add_i32 s2, s2, -1
s_add_i32 s3, s3, 8
s_cmp_lg_u32 s2, 0
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_cbranch_scc1 .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_mulPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_mulPdS_S_, .Lfunc_end0-_Z7mat_mulPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_mulPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_mulPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Command to compile on Windows:
nvcc .\lab5_3.cu -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\VC\Tools\MSVC\14.29.30133\bin\Hostx64\x64"
Output should be:
A: [
[3.00, 5.00, 2.00, 0.00],
[2.00, 4.00, 5.00, 1.00],
[0.00, 3.00, 3.00, 1.00],
[3.00, 5.00, 4.00, 4.00],
[4.00, 5.00, 5.00, 3.00],
[10.00, 13.00, 21.00, 16.00],
[9.00, 11.00, 15.00, 8.00]]
b: [
[29.99],
[14.99],
[9.99],
[24.99]]
c: [
[184.90],
[194.88],
[99.93],
[304.84],
[319.83],
[1104.40],
[784.57]]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mat_mul(double *C, double *A, double *B) {
extern __shared__ double tmp[];
tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + threadIdx.y] = A[blockIdx.x * blockDim.y + threadIdx.y] * B[threadIdx.x * gridDim.y + blockIdx.y];
__syncthreads();
if (threadIdx.x == 0 && threadIdx.y == 0) {
C[blockIdx.x * gridDim.y + blockIdx.y] = 0;
for (int i = 0; i <= blockDim.y; i++) {
C[blockIdx.x * gridDim.y + blockIdx.y] += tmp[blockDim.y * (blockIdx.x * gridDim.y + blockIdx.y) + i];
}
}
}
void mat2str(char *str, void *mat, int m, int n, int str_size) {
double *mat_p = (double *) mat;
int written = 0;
written += snprintf(str + written, str_size - written, "[\n");
for (int idx = 0; idx < m - 1; idx++) {
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + idx * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f],\n", *(mat_p + idx * n + n - 1));
}
written += snprintf(str + written, str_size - written, "[");
for (int jdx = 0; jdx < n - 1; jdx++) {
written += snprintf(str + written, str_size - written, "%.2f, ", *(mat_p + (m - 1) * n + jdx));
}
written += snprintf(str + written, str_size - written, "%.2f]]", *(mat_p + (m - 1) * n + n - 1));
}
int main(void) {
/* Intiialize inputs (CPU) */
const int M = 7;
const int N = 4;
const int O = 1;
double A[M][N] {
{3, 5, 2, 0},
{2, 4, 5, 1},
{0, 3, 3, 1},
{3, 5, 4, 4},
{4, 5, 5, 3},
{10, 13, 21, 16},
{9, 11, 15, 8}
};
double b[N][O] {
{29.99},
{14.99},
{9.99},
{24.99}
};
double c[M][O];
char str_A[320];
char str_b[320];
mat2str(str_A, A, M, N, 320);
mat2str(str_b, b, N, O, 320);
printf("A: %s\n", str_A);
printf("b: %s\n", str_b);
/* Allocate memory for calculation on GPU */
double *gpu_A;
double *gpu_B;
double *gpu_C;
hipMalloc((void**) &gpu_A, sizeof(double) * M * N);
hipMalloc((void**) &gpu_B, sizeof(double) * N * O);
hipMalloc((void**) &gpu_C, sizeof(double) * M * O);
/* Copy inputs to GPU */
hipMemcpy(gpu_A, A, sizeof(double) * M * N, hipMemcpyHostToDevice);
hipMemcpy(gpu_B, b, sizeof(double) * N * O, hipMemcpyHostToDevice);
/* Do the thing */
dim3 out_dim(M, O);
dim3 block_dim(M, N);
mat_mul<<<out_dim, block_dim, sizeof(double) * M * N * O>>>(gpu_C, gpu_A, gpu_B);
hipMemcpy(c, gpu_C, sizeof(double) * M * O, hipMemcpyDeviceToHost);
/* Remember to clean up after ourselves */
hipFree(gpu_A);
hipFree(gpu_B);
hipFree(gpu_C);
/* Print result */
char str_c[80];
mat2str(str_c, c, M, O, 80);
printf("c: %s\n", str_c);
return 0;
} | .text
.file "lab5_3.hip"
.globl _Z22__device_stub__mat_mulPdS_S_ # -- Begin function _Z22__device_stub__mat_mulPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_mulPdS_S_,@function
_Z22__device_stub__mat_mulPdS_S_: # @_Z22__device_stub__mat_mulPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_mulPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__mat_mulPdS_S_, .Lfunc_end0-_Z22__device_stub__mat_mulPdS_S_
.cfi_endproc
# -- End function
.globl _Z7mat2strPcPviii # -- Begin function _Z7mat2strPcPviii
.p2align 4, 0x90
.type _Z7mat2strPcPviii,@function
_Z7mat2strPcPviii: # @_Z7mat2strPcPviii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %r13
movq %rdi, %rbx
movslq %r8d, %rsi
movl $.L.str, %edx
xorl %eax, %eax
callq snprintf
leal -1(%r12), %ecx
movq %r15, 16(%rsp) # 8-byte Spill
movslq %r15d, %rdx
cmpl $2, %r12d
movq %r13, 24(%rsp) # 8-byte Spill
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rdx, 32(%rsp) # 8-byte Spill
jl .LBB1_6
# %bb.1: # %.lr.ph69
leal -1(%rdx), %r12d
leaq -8(,%rdx,8), %rsi
addq %r13, %rsi
movq %rsi, 56(%rsp) # 8-byte Spill
movl %ecx, %ecx
movq %rcx, 48(%rsp) # 8-byte Spill
leaq (,%rdx,8), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movslq %eax, %r15
leaq (%rbx,%r15), %rdi
movl %ebp, %eax
subl %r15d, %eax
movslq %eax, %rsi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rax
imulq 32(%rsp), %rax # 8-byte Folded Reload
movq 56(%rsp), %rcx # 8-byte Reload
movsd (%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edx
movb $1, %al
callq snprintf
addl %r15d, %eax
incq %r14
addq 40(%rsp), %r13 # 8-byte Folded Reload
cmpq 48(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %r14, 64(%rsp) # 8-byte Spill
movslq %eax, %r15
leaq (%rbx,%r15), %rdi
movl %ebp, %eax
subl %r15d, %eax
movslq %eax, %rsi
movl $.L.str.1, %edx
xorl %eax, %eax
callq snprintf
addl %r15d, %eax
cmpl $2, 16(%rsp) # 4-byte Folded Reload
jl .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq %eax, %r14
leaq (%rbx,%r14), %rdi
movl %ebp, %eax
subl %r14d, %eax
movslq %eax, %rsi
movsd (%r13,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edx
movb $1, %al
callq snprintf
addl %r14d, %eax
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge70
movslq %eax, %r14
leaq (%rbx,%r14), %rdi
movl %ebp, %eax
subl %r14d, %eax
movslq %eax, %rsi
movl $.L.str.1, %edx
xorl %eax, %eax
callq snprintf
addl %r14d, %eax
movq 16(%rsp), %rdx # 8-byte Reload
cmpl $2, %edx
jl .LBB1_9
# %bb.7: # %.lr.ph78
leal -1(%rdx), %r14d
movl 12(%rsp), %ecx # 4-byte Reload
imull %edx, %ecx
movslq %ecx, %rcx
movq 24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rcx,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movslq %eax, %r13
leaq (%rbx,%r13), %rdi
movl %ebp, %eax
subl %r13d, %eax
movslq %eax, %rsi
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edx
movb $1, %al
callq snprintf
addl %r13d, %eax
incq %r12
cmpq %r12, %r14
jne .LBB1_8
.LBB1_9: # %._crit_edge79
cltq
addq %rax, %rbx
subl %eax, %ebp
movslq %ebp, %rsi
movl 12(%rsp), %eax # 4-byte Reload
imull 16(%rsp), %eax # 4-byte Folded Reload
cltq
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rax
movq 32(%rsp), %rcx # 8-byte Reload
movsd -8(%rax,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edx
movq %rbx, %rdi
movb $1, %al
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp snprintf # TAILCALL
.Lfunc_end1:
.size _Z7mat2strPcPviii, .Lfunc_end1-_Z7mat2strPcPviii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1128, %rsp # imm = 0x468
.cfi_def_cfa_offset 1168
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 256(%rsp), %rbx
movl $.L__const.main.A, %esi
movl $224, %edx
movq %rbx, %rdi
callq memcpy@PLT
movabsq $4629134652233681469, %rax # imm = 0x403DFD70A3D70A3D
movq %rax, 80(%rsp)
movabsq $4624628237856543867, %rax # imm = 0x402DFAE147AE147B
movq %rax, 88(%rsp)
movabsq $4621813488089437307, %rax # imm = 0x4023FAE147AE147B
movq %rax, 96(%rsp)
movabsq $4627727277350128189, %rax # imm = 0x4038FD70A3D70A3D
movq %rax, 104(%rsp)
leaq 800(%rsp), %r15
movq %r15, %rdi
movq %rbx, %rsi
movl $7, %edx
movl $4, %ecx
movl $320, %r8d # imm = 0x140
callq _Z7mat2strPcPviii
leaq 480(%rsp), %r12
leaq 80(%rsp), %r14
movq %r12, %rdi
movq %r14, %rsi
movl $4, %edx
movl $1, %ecx
movl $320, %r8d # imm = 0x140
callq _Z7mat2strPcPviii
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $224, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $56, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $224, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967303, %rdi # imm = 0x100000007
movabsq $17179869191, %rdx # imm = 0x400000007
movl $224, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7mat_mulPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 112(%rsp), %rbx
movl $56, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
leaq 176(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rsi
movl $7, %edx
movl $1, %ecx
movl $80, %r8d
callq _Z7mat2strPcPviii
movl $.L.str.7, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1128, %rsp # imm = 0x468
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_mulPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mat_mulPdS_S_,@object # @_Z7mat_mulPdS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_mulPdS_S_
.p2align 3, 0x0
_Z7mat_mulPdS_S_:
.quad _Z22__device_stub__mat_mulPdS_S_
.size _Z7mat_mulPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[\n"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.2f, "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%.2f],\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.2f]]"
.size .L.str.4, 7
.type .L__const.main.A,@object # @__const.main.A
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.A:
.quad 0x4008000000000000 # double 3
.quad 0x4014000000000000 # double 5
.quad 0x4000000000000000 # double 2
.quad 0x0000000000000000 # double 0
.quad 0x4000000000000000 # double 2
.quad 0x4010000000000000 # double 4
.quad 0x4014000000000000 # double 5
.quad 0x3ff0000000000000 # double 1
.quad 0x0000000000000000 # double 0
.quad 0x4008000000000000 # double 3
.quad 0x4008000000000000 # double 3
.quad 0x3ff0000000000000 # double 1
.quad 0x4008000000000000 # double 3
.quad 0x4014000000000000 # double 5
.quad 0x4010000000000000 # double 4
.quad 0x4010000000000000 # double 4
.quad 0x4010000000000000 # double 4
.quad 0x4014000000000000 # double 5
.quad 0x4014000000000000 # double 5
.quad 0x4008000000000000 # double 3
.quad 0x4024000000000000 # double 10
.quad 0x402a000000000000 # double 13
.quad 0x4035000000000000 # double 21
.quad 0x4030000000000000 # double 16
.quad 0x4022000000000000 # double 9
.quad 0x4026000000000000 # double 11
.quad 0x402e000000000000 # double 15
.quad 0x4020000000000000 # double 8
.size .L__const.main.A, 224
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "A: %s\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "b: %s\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "c: %s\n"
.size .L.str.7, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_mulPdS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_mulPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mat_mulPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mat_mulPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002200 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R2, R8, c[0x0][0x4], R9 ; /* 0x0000010008027a24 */
/* 0x001fc800078e0209 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e000b */
/*0090*/ IMAD R4, R6, c[0x0][0x10], R7 ; /* 0x0000040006047a24 */
/* 0x002fe400078e0207 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e000b */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IMAD R8, R8, c[0x0][0x10], R7 ; /* 0x0000040008087a24 */
/* 0x000fe200078e0207 */
/*00e0*/ LOP3.LUT P0, RZ, R6, R9, RZ, 0xfc, !PT ; /* 0x0000000906ff7212 */
/* 0x000fc6000780fcff */
/*00f0*/ IMAD R0, R8, c[0x0][0x4], RZ ; /* 0x0000010008007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0209 */
/*0110*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*0120*/ STS.64 [R9.X8], R6 ; /* 0x0000000609007388 */
/* 0x0011e80000008a00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0150*/ IMAD.WIDE.U32 R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fe200078e000b */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc4000001ff00 */
/*0180*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0190*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101b06 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R15.reuse, 0x3, PT ; /* 0x000000030f00780c */
/* 0x040fe40003f06070 */
/*01b0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ LOP3.LUT R15, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f0f7812 */
/* 0x000fce00078ec0ff */
/*01d0*/ @!P0 BRA 0x740 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R16, -R15, c[0x0][0x4], RZ ; /* 0x000001000f107a10 */
/* 0x001fe20007ffe1ff */
/*01f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0200*/ LEA R14, R0, 0x10, 0x3 ; /* 0x00000010000e7811 */
/* 0x000fe200078e18ff */
/*0210*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.GT.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fda0003f04270 */
/*0230*/ @!P0 BRA 0x670 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R6, R16, 0x1, RZ ; /* 0x0000000110067810 */
/* 0x000fe40007ffe0ff */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0260*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fda0003f24270 */
/*0270*/ @!P1 BRA 0x4e0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0290*/ LDS.64 R8, [R14+-0x10] ; /* 0xfffff0000e087984 */
/* 0x001e220000000a00 */
/*02a0*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*02c0*/ LDS.64 R22, [R14+-0x8] ; /* 0xfffff8000e167984 */
/* 0x002e620000000a00 */
/*02d0*/ ISETP.GT.AND P1, PT, R16, 0xb, PT ; /* 0x0000000b1000780c */
/* 0x000fc60003f24270 */
/*02e0*/ LDS.64 R6, [R14] ; /* 0x000000000e067984 */
/* 0x000ea80000000a00 */
/*02f0*/ LDS.64 R20, [R14+0x8] ; /* 0x000008000e147984 */
/* 0x000ee80000000a00 */
/*0300*/ LDS.64 R18, [R14+0x10] ; /* 0x000010000e127984 */
/* 0x000f280000000a00 */
/*0310*/ LDS.64 R12, [R14+0x18] ; /* 0x000018000e0c7984 */
/* 0x000f680000000a00 */
/*0320*/ LDS.64 R10, [R14+0x20] ; /* 0x000020000e0a7984 */
/* 0x000f220000000a00 */
/*0330*/ DADD R4, R8, R4 ; /* 0x0000000008047229 */
/* 0x0010460000000004 */
/*0340*/ LDS.64 R8, [R14+0x28] ; /* 0x000028000e087984 */
/* 0x001e260000000a00 */
/*0350*/ DADD R22, R4, R22 ; /* 0x0000000004167229 */
/* 0x0022880000000016 */
/*0360*/ LDS.64 R4, [R14+0x30] ; /* 0x000030000e047984 */
/* 0x002e640000000a00 */
/*0370*/ DADD R22, R22, R6 ; /* 0x0000000016167229 */
/* 0x0044e40000000006 */
/*0380*/ LDS.64 R6, [R14+0x38] ; /* 0x000038000e067984 */
/* 0x004ea80000000a00 */
/*0390*/ DADD R22, R22, R20 ; /* 0x0000000016167229 */
/* 0x0087240000000014 */
/*03a0*/ LDS.64 R20, [R14+0x40] ; /* 0x000040000e147984 */
/* 0x008ee80000000a00 */
/*03b0*/ DADD R22, R22, R18 ; /* 0x0000000016167229 */
/* 0x0109440000000012 */
/*03c0*/ LDS.64 R18, [R14+0x48] ; /* 0x000048000e127984 */
/* 0x010f280000000a00 */
/*03d0*/ DADD R22, R22, R12 ; /* 0x0000000016167229 */
/* 0x020b64000000000c */
/*03e0*/ LDS.64 R12, [R14+0x50] ; /* 0x000050000e0c7984 */
/* 0x020f680000000a00 */
/*03f0*/ DADD R22, R22, R10 ; /* 0x0000000016167229 */
/* 0x000004000000000a */
/*0400*/ LDS.64 R10, [R14+0x58] ; /* 0x000058000e0a7984 */
/* 0x001e280000000a00 */
/*0410*/ DADD R22, R22, R8 ; /* 0x0000000016167229 */
/* 0x0002640000000008 */
/*0420*/ LDS.64 R8, [R14+0x60] ; /* 0x000060000e087984 */
/* 0x002e680000000a00 */
/*0430*/ DADD R22, R22, R4 ; /* 0x0000000016167229 */
/* 0x0004840000000004 */
/*0440*/ LDS.64 R4, [R14+0x68] ; /* 0x000068000e047984 */
/* 0x0044680000000a00 */
/*0450*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x000ee20000000006 */
/*0460*/ IADD3 R14, R14, 0x80, RZ ; /* 0x000000800e0e7810 */
/* 0x004fca0007ffe0ff */
/*0470*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x008f0c0000000014 */
/*0480*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x010f4c0000000012 */
/*0490*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*04a0*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e4c000000000a */
/*04b0*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002e0c0000000008 */
/*04c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0010620000000004 */
/*04d0*/ @P1 BRA 0x290 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*04e0*/ IADD3 R6, R16, 0x1, RZ ; /* 0x0000000110067810 */
/* 0x001fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0500*/ @!P1 BRA 0x650 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0510*/ LDS.64 R22, [R14+-0x10] ; /* 0xfffff0000e167984 */
/* 0x000e220000000a00 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0530*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0540*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe20007ffe0ff */
/*0550*/ LDS.64 R6, [R14+-0x8] ; /* 0xfffff8000e067984 */
/* 0x000ea80000000a00 */
/*0560*/ LDS.64 R20, [R14] ; /* 0x000000000e147984 */
/* 0x000ee80000000a00 */
/*0570*/ LDS.64 R18, [R14+0x8] ; /* 0x000008000e127984 */
/* 0x000f280000000a00 */
/*0580*/ LDS.64 R12, [R14+0x10] ; /* 0x000010000e0c7984 */
/* 0x000f680000000a00 */
/*0590*/ LDS.64 R10, [R14+0x18] ; /* 0x000018000e0a7984 */
/* 0x000e680000000a00 */
/*05a0*/ LDS.64 R8, [R14+0x20] ; /* 0x000020000e087984 */
/* 0x000e640000000a00 */
/*05b0*/ DADD R22, R4, R22 ; /* 0x0000000004167229 */
/* 0x0030840000000016 */
/*05c0*/ LDS.64 R4, [R14+0x28] ; /* 0x000028000e047984 */
/* 0x0010680000000a00 */
/*05d0*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x004ee20000000006 */
/*05e0*/ IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x001fca0007ffe0ff */
/*05f0*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x008f0c0000000014 */
/*0600*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x010f4c0000000012 */
/*0610*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*0620*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e0c000000000a */
/*0630*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e4c0000000008 */
/*0640*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0020480000000004 */
/*0650*/ ISETP.NE.OR P0, PT, R16, -0x1, P0 ; /* 0xffffffff1000780c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x740 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0670*/ LDS.64 R6, [R14+-0x10] ; /* 0xfffff0000e067984 */
/* 0x001e220000000a00 */
/*0680*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe20007ffe0ff */
/*0690*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*06a0*/ LDS.64 R8, [R14+-0x8] ; /* 0xfffff8000e087984 */
/* 0x000ea20000000a00 */
/*06b0*/ ISETP.NE.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fc60003f05270 */
/*06c0*/ LDS.64 R10, [R14] ; /* 0x000000000e0a7984 */
/* 0x000ee80000000a00 */
/*06d0*/ LDS.64 R12, [R14+0x8] ; /* 0x000008000e0c7984 */
/* 0x0009640000000a00 */
/*06e0*/ IADD3 R14, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x010fe20007ffe0ff */
/*06f0*/ DADD R6, R6, R4 ; /* 0x0000000006067229 */
/* 0x003e8c0000000004 */
/*0700*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004ecc0000000008 */
/*0710*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x008f4c000000000a */
/*0720*/ DADD R4, R6, R12 ; /* 0x0000000006047229 */
/* 0x020064000000000c */
/*0730*/ @P0 BRA 0x670 ; /* 0xffffff3000000947 */
/* 0x003fea000383ffff */
/*0740*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x001fda0003f05270 */
/*0750*/ @!P0 BRA 0x7e0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0760*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fca000fffe0ff */
/*0770*/ IMAD.SHL.U32 R0, R0, 0x8, RZ ; /* 0x0000000800007824 */
/* 0x000fca00078e00ff */
/*0780*/ LDS.64 R6, [R0] ; /* 0x0000000000067984 */
/* 0x0010a20000000a00 */
/*0790*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fc80007ffe0ff */
/*07a0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*07b0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x001fe20007ffe0ff */
/*07c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0060540000000004 */
/*07d0*/ @P0 BRA 0x780 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b06 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_mulPdS_S_
.globl _Z7mat_mulPdS_S_
.p2align 8
.type _Z7mat_mulPdS_S_,@function
_Z7mat_mulPdS_S_:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[4:5], null, s5, v0, s[2:3]
s_mul_i32 s3, s5, s14
v_or_b32_e32 v0, v0, v1
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_add_i32 s2, s3, s15
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_mad_u64_u32 v[4:5], null, s2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v4, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[6:7], s[2:3], 3
s_mul_i32 s2, s2, s4
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_lshl_b32 s3, s2, 3
s_add_i32 s2, s4, 1
s_add_i32 s3, s3, 0
global_store_b64 v4, v[2:3], s[0:1]
.LBB0_2:
v_mov_b32_e32 v2, s3
s_add_i32 s2, s2, -1
s_add_i32 s3, s3, 8
s_cmp_lg_u32 s2, 0
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_cbranch_scc1 .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_mulPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_mulPdS_S_, .Lfunc_end0-_Z7mat_mulPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_mulPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_mulPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a3c60_00000000-6_lab5_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[\n"
.LC1:
.string "["
.LC2:
.string "%.2f, "
.LC3:
.string "%.2f],\n"
.LC4:
.string "%.2f]]"
.text
.globl _Z7mat2strPcPviii
.type _Z7mat2strPcPviii, @function
_Z7mat2strPcPviii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movq %rsi, %r14
movq %rsi, 24(%rsp)
movl %edx, %ebx
movl %ecx, %r15d
movl %ecx, 12(%rsp)
movl %r8d, %r12d
movslq %r8d, %rsi
leaq .LC0(%rip), %rdx
movl $0, %eax
call snprintf@PLT
movl %eax, %ebp
leal -1(%rbx), %eax
movl %eax, 60(%rsp)
testl %eax, %eax
jle .L4
movl %r15d, %eax
movslq %r15d, %rdx
salq $3, %rdx
leaq (%r14,%rdx), %rcx
movq %rcx, 16(%rsp)
leal -1(%rbx), %ecx
movl %ecx, 36(%rsp)
movl $0, 32(%rsp)
movl $0, 8(%rsp)
subl $2, %eax
movl %eax, 56(%rsp)
leaq 8(%r14), %rax
movq %rax, 48(%rsp)
leaq .LC2(%rip), %r15
movl %ebp, %ebx
movq %rdx, 40(%rsp)
.L7:
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
leaq .LC1(%rip), %rdx
movl $0, %eax
call snprintf@PLT
addl %eax, %ebx
cmpl $1, 12(%rsp)
jle .L5
movslq 32(%rsp), %rdx
movq 24(%rsp), %rax
leaq (%rax,%rdx,8), %rbp
movl 56(%rsp), %eax
addq %rdx, %rax
movq 48(%rsp), %rcx
leaq (%rcx,%rax,8), %r14
.L6:
movsd 0(%rbp), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
movq %r15, %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
addq $8, %rbp
cmpq %r14, %rbp
jne .L6
.L5:
movq 16(%rsp), %r14
movsd -8(%r14), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
leaq .LC3(%rip), %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
addl $1, 8(%rsp)
movl 8(%rsp), %eax
movq 40(%rsp), %rcx
addq %rcx, %r14
movq %r14, 16(%rsp)
movl 12(%rsp), %edx
addl %edx, 32(%rsp)
movl 36(%rsp), %ecx
cmpl %ecx, %eax
jne .L7
movl %ebx, %ebp
.L4:
movl %r12d, %esi
subl %ebp, %esi
movslq %esi, %rsi
movslq %ebp, %rdi
addq %r13, %rdi
leaq .LC1(%rip), %rdx
movl $0, %eax
call snprintf@PLT
leal (%rax,%rbp), %ebx
movl 12(%rsp), %edx
cmpl $1, %edx
jle .L8
movl %edx, %eax
movl 60(%rsp), %ecx
imull %ecx, %eax
cltq
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %rbp
leal -2(%rdx), %edx
addq %rdx, %rax
leaq (%rcx,%rax,8), %r15
leaq .LC2(%rip), %r14
.L9:
movsd 0(%rbp), %xmm0
movl %r12d, %esi
subl %ebx, %esi
movslq %esi, %rsi
movslq %ebx, %rdi
addq %r13, %rdi
movq %r14, %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addl %eax, %ebx
movq %rbp, %rax
addq $8, %rbp
cmpq %r15, %rax
jne .L9
.L8:
movl 60(%rsp), %eax
movl 12(%rsp), %ecx
imull %ecx, %eax
movslq %eax, %rdx
movslq %ecx, %rax
addq %rdx, %rax
movq 24(%rsp), %rdx
movsd -8(%rdx,%rax,8), %xmm0
subl %ebx, %r12d
movslq %r12d, %rsi
movslq %ebx, %rbx
leaq 0(%r13,%rbx), %rdi
leaq .LC4(%rip), %r8
movq $-1, %rcx
movl $2, %edx
movl $1, %eax
call __snprintf_chk@PLT
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7mat2strPcPviii, .-_Z7mat2strPcPviii
.globl _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
.type _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_, @function
_Z30__device_stub__Z7mat_mulPdS_S_PdS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_mulPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_, .-_Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
.globl _Z7mat_mulPdS_S_
.type _Z7mat_mulPdS_S_, @function
_Z7mat_mulPdS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7mat_mulPdS_S_, .-_Z7mat_mulPdS_S_
.section .rodata.str1.1
.LC23:
.string "A: %s\n"
.LC24:
.string "b: %s\n"
.LC25:
.string "c: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1112, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movsd .LC5(%rip), %xmm0
movsd %xmm0, 144(%rsp)
movsd .LC6(%rip), %xmm1
movsd %xmm1, 152(%rsp)
movsd .LC7(%rip), %xmm2
movsd %xmm2, 160(%rsp)
movq $0x000000000, 168(%rsp)
movsd %xmm2, 176(%rsp)
movsd .LC9(%rip), %xmm2
movsd %xmm2, 184(%rsp)
movsd %xmm1, 192(%rsp)
movsd .LC10(%rip), %xmm3
movsd %xmm3, 200(%rsp)
movq $0x000000000, 208(%rsp)
movsd %xmm0, 216(%rsp)
movsd %xmm0, 224(%rsp)
movsd %xmm3, 232(%rsp)
movsd %xmm0, 240(%rsp)
movsd %xmm1, 248(%rsp)
movsd %xmm2, 256(%rsp)
movsd %xmm2, 264(%rsp)
movsd %xmm2, 272(%rsp)
movsd %xmm1, 280(%rsp)
movsd %xmm1, 288(%rsp)
movsd %xmm0, 296(%rsp)
movq .LC11(%rip), %rax
movq %rax, 304(%rsp)
movq .LC12(%rip), %rax
movq %rax, 312(%rsp)
movq .LC13(%rip), %rax
movq %rax, 320(%rsp)
movq .LC14(%rip), %rax
movq %rax, 328(%rsp)
movq .LC15(%rip), %rax
movq %rax, 336(%rsp)
movq .LC16(%rip), %rax
movq %rax, 344(%rsp)
movq .LC17(%rip), %rax
movq %rax, 352(%rsp)
movq .LC18(%rip), %rax
movq %rax, 360(%rsp)
movq .LC19(%rip), %rax
movq %rax, 48(%rsp)
movq .LC20(%rip), %rax
movq %rax, 56(%rsp)
movq .LC21(%rip), %rax
movq %rax, 64(%rsp)
movq .LC22(%rip), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rbp
leaq 448(%rsp), %r13
movl $320, %r8d
movl $4, %ecx
movl $7, %edx
movq %rbp, %rsi
movq %r13, %rdi
call _Z7mat2strPcPviii
leaq 48(%rsp), %rbx
leaq 768(%rsp), %r12
movl $320, %r8d
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z7mat2strPcPviii
movq %r13, %rdx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $224, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $56, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $224, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $7, 24(%rsp)
movl $1, 28(%rsp)
movl $7, 36(%rsp)
movl $4, 40(%rsp)
movl $0, %r9d
movl $224, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
leaq 80(%rsp), %rbp
movl $2, %ecx
movl $56, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 368(%rsp), %rbx
movl $80, %r8d
movl $1, %ecx
movl $7, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z7mat2strPcPviii
movq %rbx, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z7mat_mulPdS_S_PdS_S_
jmp .L23
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC26:
.string "_Z7mat_mulPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_mulPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1074266112
.align 8
.LC6:
.long 0
.long 1075052544
.align 8
.LC7:
.long 0
.long 1073741824
.align 8
.LC9:
.long 0
.long 1074790400
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC11:
.long 0
.long 1076101120
.align 8
.LC12:
.long 0
.long 1076494336
.align 8
.LC13:
.long 0
.long 1077215232
.align 8
.LC14:
.long 0
.long 1076887552
.align 8
.LC15:
.long 0
.long 1075970048
.align 8
.LC16:
.long 0
.long 1076232192
.align 8
.LC17:
.long 0
.long 1076756480
.align 8
.LC18:
.long 0
.long 1075838976
.align 8
.LC19:
.long -1546188227
.long 1077804400
.align 8
.LC20:
.long 1202590843
.long 1076755169
.align 8
.LC21:
.long 1202590843
.long 1076099809
.align 8
.LC22:
.long -1546188227
.long 1077476720
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab5_3.hip"
.globl _Z22__device_stub__mat_mulPdS_S_ # -- Begin function _Z22__device_stub__mat_mulPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_mulPdS_S_,@function
_Z22__device_stub__mat_mulPdS_S_: # @_Z22__device_stub__mat_mulPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_mulPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__mat_mulPdS_S_, .Lfunc_end0-_Z22__device_stub__mat_mulPdS_S_
.cfi_endproc
# -- End function
.globl _Z7mat2strPcPviii # -- Begin function _Z7mat2strPcPviii
.p2align 4, 0x90
.type _Z7mat2strPcPviii,@function
_Z7mat2strPcPviii: # @_Z7mat2strPcPviii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %r13
movq %rdi, %rbx
movslq %r8d, %rsi
movl $.L.str, %edx
xorl %eax, %eax
callq snprintf
leal -1(%r12), %ecx
movq %r15, 16(%rsp) # 8-byte Spill
movslq %r15d, %rdx
cmpl $2, %r12d
movq %r13, 24(%rsp) # 8-byte Spill
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rdx, 32(%rsp) # 8-byte Spill
jl .LBB1_6
# %bb.1: # %.lr.ph69
leal -1(%rdx), %r12d
leaq -8(,%rdx,8), %rsi
addq %r13, %rsi
movq %rsi, 56(%rsp) # 8-byte Spill
movl %ecx, %ecx
movq %rcx, 48(%rsp) # 8-byte Spill
leaq (,%rdx,8), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movslq %eax, %r15
leaq (%rbx,%r15), %rdi
movl %ebp, %eax
subl %r15d, %eax
movslq %eax, %rsi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rax
imulq 32(%rsp), %rax # 8-byte Folded Reload
movq 56(%rsp), %rcx # 8-byte Reload
movsd (%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edx
movb $1, %al
callq snprintf
addl %r15d, %eax
incq %r14
addq 40(%rsp), %r13 # 8-byte Folded Reload
cmpq 48(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %r14, 64(%rsp) # 8-byte Spill
movslq %eax, %r15
leaq (%rbx,%r15), %rdi
movl %ebp, %eax
subl %r15d, %eax
movslq %eax, %rsi
movl $.L.str.1, %edx
xorl %eax, %eax
callq snprintf
addl %r15d, %eax
cmpl $2, 16(%rsp) # 4-byte Folded Reload
jl .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq %eax, %r14
leaq (%rbx,%r14), %rdi
movl %ebp, %eax
subl %r14d, %eax
movslq %eax, %rsi
movsd (%r13,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edx
movb $1, %al
callq snprintf
addl %r14d, %eax
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge70
movslq %eax, %r14
leaq (%rbx,%r14), %rdi
movl %ebp, %eax
subl %r14d, %eax
movslq %eax, %rsi
movl $.L.str.1, %edx
xorl %eax, %eax
callq snprintf
addl %r14d, %eax
movq 16(%rsp), %rdx # 8-byte Reload
cmpl $2, %edx
jl .LBB1_9
# %bb.7: # %.lr.ph78
leal -1(%rdx), %r14d
movl 12(%rsp), %ecx # 4-byte Reload
imull %edx, %ecx
movslq %ecx, %rcx
movq 24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rcx,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movslq %eax, %r13
leaq (%rbx,%r13), %rdi
movl %ebp, %eax
subl %r13d, %eax
movslq %eax, %rsi
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edx
movb $1, %al
callq snprintf
addl %r13d, %eax
incq %r12
cmpq %r12, %r14
jne .LBB1_8
.LBB1_9: # %._crit_edge79
cltq
addq %rax, %rbx
subl %eax, %ebp
movslq %ebp, %rsi
movl 12(%rsp), %eax # 4-byte Reload
imull 16(%rsp), %eax # 4-byte Folded Reload
cltq
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rax
movq 32(%rsp), %rcx # 8-byte Reload
movsd -8(%rax,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edx
movq %rbx, %rdi
movb $1, %al
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp snprintf # TAILCALL
.Lfunc_end1:
.size _Z7mat2strPcPviii, .Lfunc_end1-_Z7mat2strPcPviii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1128, %rsp # imm = 0x468
.cfi_def_cfa_offset 1168
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 256(%rsp), %rbx
movl $.L__const.main.A, %esi
movl $224, %edx
movq %rbx, %rdi
callq memcpy@PLT
movabsq $4629134652233681469, %rax # imm = 0x403DFD70A3D70A3D
movq %rax, 80(%rsp)
movabsq $4624628237856543867, %rax # imm = 0x402DFAE147AE147B
movq %rax, 88(%rsp)
movabsq $4621813488089437307, %rax # imm = 0x4023FAE147AE147B
movq %rax, 96(%rsp)
movabsq $4627727277350128189, %rax # imm = 0x4038FD70A3D70A3D
movq %rax, 104(%rsp)
leaq 800(%rsp), %r15
movq %r15, %rdi
movq %rbx, %rsi
movl $7, %edx
movl $4, %ecx
movl $320, %r8d # imm = 0x140
callq _Z7mat2strPcPviii
leaq 480(%rsp), %r12
leaq 80(%rsp), %r14
movq %r12, %rdi
movq %r14, %rsi
movl $4, %edx
movl $1, %ecx
movl $320, %r8d # imm = 0x140
callq _Z7mat2strPcPviii
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $224, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $56, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $224, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967303, %rdi # imm = 0x100000007
movabsq $17179869191, %rdx # imm = 0x400000007
movl $224, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7mat_mulPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 112(%rsp), %rbx
movl $56, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
leaq 176(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rsi
movl $7, %edx
movl $1, %ecx
movl $80, %r8d
callq _Z7mat2strPcPviii
movl $.L.str.7, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1128, %rsp # imm = 0x468
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_mulPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mat_mulPdS_S_,@object # @_Z7mat_mulPdS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_mulPdS_S_
.p2align 3, 0x0
_Z7mat_mulPdS_S_:
.quad _Z22__device_stub__mat_mulPdS_S_
.size _Z7mat_mulPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[\n"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.2f, "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%.2f],\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.2f]]"
.size .L.str.4, 7
.type .L__const.main.A,@object # @__const.main.A
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.A:
.quad 0x4008000000000000 # double 3
.quad 0x4014000000000000 # double 5
.quad 0x4000000000000000 # double 2
.quad 0x0000000000000000 # double 0
.quad 0x4000000000000000 # double 2
.quad 0x4010000000000000 # double 4
.quad 0x4014000000000000 # double 5
.quad 0x3ff0000000000000 # double 1
.quad 0x0000000000000000 # double 0
.quad 0x4008000000000000 # double 3
.quad 0x4008000000000000 # double 3
.quad 0x3ff0000000000000 # double 1
.quad 0x4008000000000000 # double 3
.quad 0x4014000000000000 # double 5
.quad 0x4010000000000000 # double 4
.quad 0x4010000000000000 # double 4
.quad 0x4010000000000000 # double 4
.quad 0x4014000000000000 # double 5
.quad 0x4014000000000000 # double 5
.quad 0x4008000000000000 # double 3
.quad 0x4024000000000000 # double 10
.quad 0x402a000000000000 # double 13
.quad 0x4035000000000000 # double 21
.quad 0x4030000000000000 # double 16
.quad 0x4022000000000000 # double 9
.quad 0x4026000000000000 # double 11
.quad 0x402e000000000000 # double 15
.quad 0x4020000000000000 # double 8
.size .L__const.main.A, 224
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "A: %s\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "b: %s\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "c: %s\n"
.size .L.str.7, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_mulPdS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_mulPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mat_mulPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} | .file "tmpxft_00162489_00000000-6_newPrime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15appending_primePyS_yyy
.type _Z15appending_primePyS_yyy, @function
_Z15appending_primePyS_yyy:
.LFB2058:
.cfi_startproc
endbr64
movq %r8, %rax
cmpq %rcx, %rdx
jb .L6
.L4:
ret
.L5:
addq $1, %rdx
cmpq %rdx, %rcx
je .L4
.L6:
cmpq $0, (%rdi,%rdx,8)
jne .L5
movq %rdx, (%rsi,%rax,8)
addq $1, %rax
jmp .L5
.cfi_endproc
.LFE2058:
.size _Z15appending_primePyS_yyy, .-_Z15appending_primePyS_yyy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n"
.align 8
.LC1:
.string "-------- END CALCULATING PRIME NUMBERS--------\n"
.text
.globl _Z14calculatePrimePyS_yyy
.type _Z14calculatePrimePyS_yyy, @function
_Z14calculatePrimePyS_yyy:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
movq %rdx, %rbx
movq %rcx, %r12
movq %r8, %r14
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq %r12, %rbx
jnb .L9
leaq 0(%r13,%r14,8), %rsi
jmp .L10
.L11:
addq $8, %rcx
cmpq %rsi, %rcx
je .L13
.L12:
movq %rbx, %rax
movl $0, %edx
divq (%rcx)
testq %rdx, %rdx
jne .L11
movq $1, 0(%rbp,%rbx,8)
jmp .L11
.L13:
addq $1, %rbx
cmpq %rbx, %r12
je .L9
.L10:
movq %r13, %rcx
testq %r14, %r14
jne .L12
jmp .L13
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14calculatePrimePyS_yyy, .-_Z14calculatePrimePyS_yyy
.globl _Z25memsetting_range_of_inputPyy
.type _Z25memsetting_range_of_inputPyy, @function
_Z25memsetting_range_of_inputPyy:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 0(,%rsi,8), %rdx
movl $0, %esi
call memset@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z25memsetting_range_of_inputPyy, .-_Z25memsetting_range_of_inputPyy
.globl _Z22initializing_inputlistPy
.type _Z22initializing_inputlistPy, @function
_Z22initializing_inputlistPy:
.LFB2061:
.cfi_startproc
endbr64
leaq 800000008(%rdi), %rax
.L21:
movq $2, (%rdi)
addq $8, %rdi
cmpq %rax, %rdi
jne .L21
ret
.cfi_endproc
.LFE2061:
.size _Z22initializing_inputlistPy, .-_Z22initializing_inputlistPy
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d\t--->\t%llu\n"
.text
.globl _Z15print_inputlistPy
.type _Z15print_inputlistPy, @function
_Z15print_inputlistPy:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L24:
movq 0(%rbp,%rbx,8), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000000, %rbx
jne .L24
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z15print_inputlistPy, .-_Z15print_inputlistPy
.section .rodata.str1.1
.LC3:
.string "%llu\n"
.text
.globl _Z15print_primelistPyy
.type _Z15print_primelistPyy, @function
_Z15print_primelistPyy:
.LFB2063:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L32
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r13
.L29:
movq (%r12,%rbx,8), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L29
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2063:
.size _Z15print_primelistPyy, .-_Z15print_primelistPyy
.globl _Z16copy_seed_primesPyPii
.type _Z16copy_seed_primesPyPii, @function
_Z16copy_seed_primesPyPii:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L35
movslq %edx, %rdx
movl $0, %eax
.L37:
movslq (%rsi,%rax,4), %rcx
movq %rcx, (%rdi,%rax,8)
addq $1, %rax
cmpq %rax, %rdx
jne .L37
.L35:
ret
.cfi_endproc
.LFE2064:
.size _Z16copy_seed_primesPyPii, .-_Z16copy_seed_primesPyPii
.globl _Z20generate_seed_primesPiS_y
.type _Z20generate_seed_primesPiS_y, @function
_Z20generate_seed_primesPiS_y:
.LFB2065:
.cfi_startproc
endbr64
movq %rsi, %r9
cmpq $3, %rdx
jbe .L40
movl $4, %r8d
movl $2, %esi
jmp .L43
.L41:
leal 1(%rcx), %eax
addq $1, %rsi
addl $2, %r8d
imull %eax, %eax
cltq
cmpq %rax, %rdx
jb .L44
.L43:
movl %esi, %ecx
cmpl $0, (%rdi,%rsi,4)
jne .L41
movslq %r8d, %rax
cmpq %rax, %rdx
jb .L41
.L42:
movl $1, (%rdi,%rax,4)
addq %rsi, %rax
cmpq %rax, %rdx
jnb .L42
jmp .L41
.L40:
cmpq $1, %rdx
ja .L44
movl $0, %esi
.L39:
movl %esi, %eax
ret
.L44:
movl $2, %eax
movl $0, %esi
jmp .L47
.L46:
leaq 1(%rax), %rcx
cmpq %rdx, %rax
je .L39
movq %rcx, %rax
.L47:
cmpl $0, (%rdi,%rax,4)
jne .L46
movslq %esi, %rcx
movl %eax, (%r9,%rcx,4)
addl $1, %esi
jmp .L46
.cfi_endproc
.LFE2065:
.size _Z20generate_seed_primesPiS_y, .-_Z20generate_seed_primesPiS_y
.section .rodata.str1.1
.LC4:
.string "TOTAL INPUT SIZE IS: %llu\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "THE PRIMES WILL BE GENERATED FROM 0 - %llu\n"
.align 8
.LC6:
.string "-------------------------------------------------------------------------\n\n\n"
.align 8
.LC7:
.string "THE NUMBER OF PRIMES GENERATED: %llu \n"
.align 8
.LC9:
.string "MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n"
.align 8
.LC10:
.string "CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n"
.section .rodata.str1.1
.LC11:
.string "\n\n\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n"
.align 8
.LC13:
.string "TOTAL NUMBER OF PRIMES GENERATED: %llu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edx
movq %rax, %rsi
movq %rbp, %rdi
call _Z20generate_seed_primesPiS_y
movl %eax, %r12d
movl $100000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rbp
movl $800000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rdi
call _Z22initializing_inputlistPy
movl $80000000, %edi
call malloc@PLT
movq %rax, %r14
movl %r12d, %edx
movq %rbx, %rsi
movq %rax, %rdi
call _Z16copy_seed_primesPyPii
movl $10, %ebx
leaq .LC7(%rip), %r15
jmp .L58
.L53:
movq %rbx, %rax
shrq %rax
movq %rbx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L54
.L55:
subsd .LC8(%rip), %xmm0
cvttsd2siq %xmm0, %rbx
movabsq $-9223372036854775808, %rax
xorq %rax, %rbx
jmp .L56
.L62:
movq %rbx, %rcx
movq %r12, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %r13, %rdi
call _Z25memsetting_range_of_inputPyy
movq %rbp, %r8
movq %rbx, %rcx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z14calculatePrimePyS_yyy
movq %rbp, %r8
movq %rbx, %rcx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z15appending_primePyS_yyy
movq %rax, %rbp
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $9999999, %rbx
ja .L59
.L58:
movq %rbp, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbx, %rbx
js .L53
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L54:
movq %rbx, %r12
mulsd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
jnb .L55
cvttsd2siq %xmm0, %rbx
.L56:
movq %rbx, %rcx
movq %r12, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $10000000, %rbx
jbe .L62
movl $10000000, %ecx
movq %r12, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10000000, %esi
movq %r13, %rdi
call _Z25memsetting_range_of_inputPyy
movq %rbp, %r8
movl $10000000, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z14calculatePrimePyS_yyy
movq %rbp, %r8
movl $10000000, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z15appending_primePyS_yyy
movq %rax, %rbp
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L59:
movq %rbp, %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq %r14, %rdi
call _Z15print_primelistPyy
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<string.h>
#define INPUT_SIZE 100000000
#define PRIME_RANGE 10000000
typedef unsigned long long int uint64_c;
int generate_seed_primes(int*, int*, uint64_c);
void copy_seed_primes(uint64_c *,int *,int);
void print_primelist(uint64_c *, uint64_c);
void print_inputlist(uint64_c *);
void initializing_inputlist(uint64_c *);
void memsetting_range_of_input(uint64_c *,uint64_c);
void calculatePrime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
uint64_c appending_prime(uint64_c*, uint64_c*, uint64_c, uint64_c, uint64_c);
//KERNAL CODE GOES HERE!!
//KERNAL CODE ENDS HERE!!!
int main()
{
// This code is just to generate the seed prime numbers
int input_size=100;
int *input;
uint64_c n= 10 ;// seed prime list.
int *seed_primelist;
input=(int *)malloc(input_size*sizeof(int));
seed_primelist=(int *)malloc(input_size*sizeof(int));
int num_of_seed = generate_seed_primes(input,seed_primelist,n);
// seed prime list code ends here.
//Starting code for gpu.
//declaring host variables.
// declaring the ranges of the input size and the primes to be generated.
uint64_c total_input_size = INPUT_SIZE;
printf("TOTAL INPUT SIZE IS: %llu\n",total_input_size);
uint64_c prime_range = PRIME_RANGE;
printf("THE PRIMES WILL BE GENERATED FROM 0 - %llu\n",prime_range);
printf("-------------------------------------------------------------------------\n\n\n");
// creating the host array of input-list and primelist.
uint64_c *input_list;
uint64_c *prime_list;
uint64_c number_of_primes= num_of_seed; //initializing the number of primes to the number of seed primes.
input_list=(uint64_c *)malloc(total_input_size * sizeof(uint64_c));
//setting all the values of the input list to -1.
initializing_inputlist(input_list);
prime_list=(uint64_c *)malloc(prime_range * sizeof(uint64_c));
//copying the seed primes in prime_list.
copy_seed_primes(prime_list,seed_primelist,num_of_seed);
while(n<PRIME_RANGE){
uint64_c previous_range=n;
printf("THE NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
//to determine the maximum range a the calculated prime range can determine.
uint64_c max_prime_range = pow(n,2);
printf("MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n", n,max_prime_range);
if(max_prime_range<=PRIME_RANGE){
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n", previous_range,max_prime_range);
memsetting_range_of_input(input_list,max_prime_range);
calculatePrime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, max_prime_range, number_of_primes);
}
else
{
printf("CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n", previous_range,PRIME_RANGE);
memsetting_range_of_input(input_list,PRIME_RANGE);
calculatePrime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
number_of_primes = appending_prime(input_list, prime_list, previous_range, PRIME_RANGE, number_of_primes);
}
printf("\n\n\n");
//print_inputlist(input_list);
n=pow(n,2);
}
printf("TOTAL NUMBER OF PRIMES GENERATED: %llu \n",number_of_primes);
print_primelist(prime_list,number_of_primes);
//ending code for gpu.
return 0;
}
uint64_c appending_prime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
if(input_list[i]==0)
{
prime_list[number_of_primes] = i;
number_of_primes++;
}
}
return number_of_primes;
}
void calculatePrime(uint64_c* input_list, uint64_c* prime_list, uint64_c start_of_range,uint64_c end_of_range, uint64_c number_of_primes)
{
printf("--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n", start_of_range,end_of_range);
// print_primelist(prime_list,number_of_primes);
for(uint64_c i=start_of_range;i<end_of_range;i++)
{
for(uint64_c j=0;j<number_of_primes;j++){
if(i % prime_list[j]==0)
{
input_list[i]=1;
}
}
}
printf("-------- END CALCULATING PRIME NUMBERS--------\n");
}
void memsetting_range_of_input(uint64_c *input_list,uint64_c size)
{
memset(input_list,0,size * sizeof(uint64_c));
}
void initializing_inputlist(uint64_c *input_list){
for(int i=0;i<=INPUT_SIZE;i++)
{
input_list[i]=2;
}
}
void print_inputlist(uint64_c *input_list)
{
for(int i=0;i<INPUT_SIZE;i++)
{
printf("%d\t--->\t%llu\n", i,input_list[i]);
}
}
void print_primelist(uint64_c *prime_list,uint64_c number_of_primes)
{
for(int i=0;i<number_of_primes;i++)
{
printf("%llu\n",prime_list[i]);
}
}
void copy_seed_primes(uint64_c *prime_list,int * seed_primelist,int num_of_seed)
{
for(int i=0;i<num_of_seed;i++)
{
prime_list[i]=seed_primelist[i];
}
}
int generate_seed_primes(int *input,int *primelist, uint64_c n)
{
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
return i;
} | .text
.file "newPrime.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movq %rbx, %rax
addq $16, %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_4: # %.loopexit.i
# in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $4, %rdx
je .LBB0_5
.LBB0_1: # %.lr.ph35.i
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
cmpl $0, (%rbx,%rdx,4)
jne .LBB0_4
# %bb.2: # %.lr.ph.i.preheader
# in Loop: Header=BB0_1 Depth=1
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $11, %r8
jb .LBB0_3
jmp .LBB0_4
.LBB0_5: # %.lr.ph39.i.preheader
xorl %r12d, %r12d
movl $2, %eax
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_6 Depth=1
incq %rax
cmpq $11, %rax
je .LBB0_9
.LBB0_6: # %.lr.ph39.i
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%rax,4)
jne .LBB0_8
# %bb.7: # in Loop: Header=BB0_6 Depth=1
movslq %r12d, %r12
movl %eax, (%r15,%r12,4)
incl %r12d
jmp .LBB0_8
.LBB0_9: # %_Z20generate_seed_primesPiS_y.exit
xorl %ebx, %ebx
movl $.L.str, %edi
movl $100000000, %esi # imm = 0x5F5E100
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $10000000, %esi # imm = 0x989680
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $800000000, %edi # imm = 0x2FAF0800
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB0_10: # =>This Inner Loop Header: Depth=1
movq $2, (%r14,%rbx,8)
incq %rbx
cmpq $100000001, %rbx # imm = 0x5F5E101
jne .LBB0_10
# %bb.11: # %_Z22initializing_inputlistPy.exit
movl $80000000, %edi # imm = 0x4C4B400
callq malloc
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB0_14
# %bb.12: # %.lr.ph.preheader.i
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_13: # %.lr.ph.i53
# =>This Inner Loop Header: Depth=1
movslq (%r15,%rcx,4), %rdx
movq %rdx, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_13
.LBB0_14: # %_Z16copy_seed_primesPyPii.exit.preheader
movslq %r12d, %r15
movl $10, %r12d
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_28: # %_Z15appending_primePyS_yyy.exit.critedge
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
.LBB0_40: # %_Z15appending_primePyS_yyy.exit
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movsd .LCPI0_2(%rip), %xmm0 # xmm0 = mem[0],zero
movapd 16(%rsp), %xmm1 # 16-byte Reload
subsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
andq 8(%rsp), %rax # 8-byte Folded Reload
orq %rax, %rbp
movq %rbp, %r12
cmpq $10000000, %rbp # imm = 0x989680
jae .LBB0_41
.LBB0_15: # %_Z16copy_seed_primesPyPii.exit
# =>This Loop Header: Depth=1
# Child Loop BB0_30 Depth 2
# Child Loop BB0_32 Depth 3
# Child Loop BB0_37 Depth 2
# Child Loop BB0_18 Depth 2
# Child Loop BB0_20 Depth 3
# Child Loop BB0_25 Depth 2
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %r12, %xmm0
punpckldq .LCPI0_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI0_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
mulsd %xmm1, %xmm1
cvttsd2si %xmm1, %rbp
movq %rbp, %rax
sarq $63, %rax
movapd %xmm1, 16(%rsp) # 16-byte Spill
movapd %xmm1, %xmm0
subsd .LCPI0_2(%rip), %xmm0
cvttsd2si %xmm0, %r13
movq %rax, 8(%rsp) # 8-byte Spill
andq %rax, %r13
orq %rbp, %r13
movl $.L.str.4, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
cmpq $10000000, %r13 # imm = 0x989680
ja .LBB0_29
# %bb.16: # in Loop: Header=BB0_15 Depth=1
movl $.L.str.5, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
leaq (,%r13,8), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.9, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
cmpq %r13, %r12
jae .LBB0_28
# %bb.17: # %.preheader.lr.ph.i
# in Loop: Header=BB0_15 Depth=1
movq %r12, %rcx
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_23: # %._crit_edge.i
# in Loop: Header=BB0_18 Depth=2
incq %rcx
cmpq %r13, %rcx
je .LBB0_24
.LBB0_18: # %.preheader.i58
# Parent Loop BB0_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_20 Depth 3
testq %r15, %r15
je .LBB0_23
# %bb.19: # %.lr.ph.i59
# in Loop: Header=BB0_18 Depth=2
xorl %esi, %esi
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_20 Depth=3
incq %rsi
cmpq %rsi, %r15
je .LBB0_23
.LBB0_20: # Parent Loop BB0_15 Depth=1
# Parent Loop BB0_18 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
xorl %edx, %edx
divq (%rbx,%rsi,8)
testq %rdx, %rdx
jne .LBB0_22
# %bb.21: # in Loop: Header=BB0_20 Depth=3
movq $1, (%r14,%rcx,8)
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_29: # %.preheader.lr.ph.i66
# in Loop: Header=BB0_15 Depth=1
movl $.L.str.6, %edi
movq %r12, %rsi
movl $10000000, %edx # imm = 0x989680
xorl %eax, %eax
callq printf
movl $80000000, %edx # imm = 0x4C4B400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.9, %edi
movl $10000000, %edx # imm = 0x989680
movq %r12, %rsi
xorl %eax, %eax
callq printf
movq %r12, %rcx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_35: # %._crit_edge.i73
# in Loop: Header=BB0_30 Depth=2
incq %rcx
cmpq $10000000, %rcx # imm = 0x989680
je .LBB0_36
.LBB0_30: # %.preheader.i68
# Parent Loop BB0_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_32 Depth 3
testq %r15, %r15
je .LBB0_35
# %bb.31: # %.lr.ph.i70
# in Loop: Header=BB0_30 Depth=2
xorl %esi, %esi
jmp .LBB0_32
.p2align 4, 0x90
.LBB0_34: # in Loop: Header=BB0_32 Depth=3
incq %rsi
cmpq %rsi, %r15
je .LBB0_35
.LBB0_32: # Parent Loop BB0_15 Depth=1
# Parent Loop BB0_30 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
xorl %edx, %edx
divq (%rbx,%rsi,8)
testq %rdx, %rdx
jne .LBB0_34
# %bb.33: # in Loop: Header=BB0_32 Depth=3
movq $1, (%r14,%rcx,8)
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_36: # %_Z14calculatePrimePyS_yyy.exit75
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB0_37
.p2align 4, 0x90
.LBB0_39: # in Loop: Header=BB0_37 Depth=2
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB0_40
.LBB0_37: # %.lr.ph.i78
# Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $0, (%r14,%r12,8)
jne .LBB0_39
# %bb.38: # in Loop: Header=BB0_37 Depth=2
movq %r12, (%rbx,%r15,8)
incq %r15
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_24: # %_Z14calculatePrimePyS_yyy.exit
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
cmpq %r13, %r12
jb .LBB0_25
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_25 Depth=2
incq %r12
cmpq %r12, %r13
je .LBB0_40
.LBB0_25: # %.lr.ph.i62
# Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $0, (%r14,%r12,8)
jne .LBB0_27
# %bb.26: # in Loop: Header=BB0_25 Depth=2
movq %r12, (%rbx,%r15,8)
incq %r15
jmp .LBB0_27
.LBB0_41:
movl $.L.str.8, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
testq %r15, %r15
je .LBB0_44
# %bb.42: # %.lr.ph.i85.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_43: # %.lr.ph.i85
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB0_43
.LBB0_44: # %_Z15print_primelistPyy.exit
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z20generate_seed_primesPiS_y # -- Begin function _Z20generate_seed_primesPiS_y
.p2align 4, 0x90
.type _Z20generate_seed_primesPiS_y,@function
_Z20generate_seed_primesPiS_y: # @_Z20generate_seed_primesPiS_y
.cfi_startproc
# %bb.0:
cmpq $4, %rdx
jae .LBB1_1
.LBB1_7: # %.preheader
xorl %eax, %eax
cmpq $2, %rdx
jae .LBB1_8
.LBB1_12: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.LBB1_1: # %.lr.ph35.preheader
leaq 16(%rdi), %rax
movl $4, %ecx
movl $2, %r8d
movl $8, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %.loopexit
# in Loop: Header=BB1_2 Depth=1
incq %r8
movq %r8, %r10
imulq %r8, %r10
addq $2, %rcx
addq $8, %rax
addq $4, %r9
cmpq %rdx, %r10
ja .LBB1_7
.LBB1_2: # %.lr.ph35
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
cmpl $0, (%rdi,%r8,4)
jne .LBB1_6
# %bb.3: # %.lr.ph35
# in Loop: Header=BB1_2 Depth=1
leaq (%r8,%r8), %r10
cmpq %rdx, %r10
ja .LBB1_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %rax, %r10
movq %rcx, %r11
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%r10)
addq %r8, %r11
addq %r9, %r10
cmpq %rdx, %r11
jbe .LBB1_5
jmp .LBB1_6
.LBB1_8: # %.lr.ph39.preheader
movl $1, %ecx
subq %rdx, %rcx
xorl %eax, %eax
movl $2, %edx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
leaq (%rcx,%rdx), %r8
incq %r8
incq %rdx
cmpq $2, %r8
je .LBB1_12
.LBB1_9: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rdi,%rdx,4)
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
cltq
movl %edx, (%rsi,%rax,4)
incl %eax
jmp .LBB1_11
.Lfunc_end1:
.size _Z20generate_seed_primesPiS_y, .Lfunc_end1-_Z20generate_seed_primesPiS_y
.cfi_endproc
# -- End function
.globl _Z22initializing_inputlistPy # -- Begin function _Z22initializing_inputlistPy
.p2align 4, 0x90
.type _Z22initializing_inputlistPy,@function
_Z22initializing_inputlistPy: # @_Z22initializing_inputlistPy
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq $2, (%rdi,%rax,8)
incq %rax
cmpq $100000001, %rax # imm = 0x5F5E101
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z22initializing_inputlistPy, .Lfunc_end2-_Z22initializing_inputlistPy
.cfi_endproc
# -- End function
.globl _Z16copy_seed_primesPyPii # -- Begin function _Z16copy_seed_primesPyPii
.p2align 4, 0x90
.type _Z16copy_seed_primesPyPii,@function
_Z16copy_seed_primesPyPii: # @_Z16copy_seed_primesPyPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq (%rsi,%rcx,4), %rdx
movq %rdx, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16copy_seed_primesPyPii, .Lfunc_end3-_Z16copy_seed_primesPyPii
.cfi_endproc
# -- End function
.globl _Z25memsetting_range_of_inputPyy # -- Begin function _Z25memsetting_range_of_inputPyy
.p2align 4, 0x90
.type _Z25memsetting_range_of_inputPyy,@function
_Z25memsetting_range_of_inputPyy: # @_Z25memsetting_range_of_inputPyy
.cfi_startproc
# %bb.0:
leaq (,%rsi,8), %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.Lfunc_end4:
.size _Z25memsetting_range_of_inputPyy, .Lfunc_end4-_Z25memsetting_range_of_inputPyy
.cfi_endproc
# -- End function
.globl _Z14calculatePrimePyS_yyy # -- Begin function _Z14calculatePrimePyS_yyy
.p2align 4, 0x90
.type _Z14calculatePrimePyS_yyy,@function
_Z14calculatePrimePyS_yyy: # @_Z14calculatePrimePyS_yyy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str.9, %edi
movq %rdx, %rsi
movq %rcx, %rdx
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jb .LBB5_1
.LBB5_7: # %._crit_edge16
movl $.Lstr.2, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.p2align 4, 0x90
.LBB5_6: # %._crit_edge
# in Loop: Header=BB5_1 Depth=1
.cfi_def_cfa_offset 48
incq %r15
cmpq %r14, %r15
je .LBB5_7
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
testq %rbx, %rbx
je .LBB5_6
# %bb.2: # %.lr.ph
# in Loop: Header=BB5_1 Depth=1
xorl %ecx, %ecx
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=2
incq %rcx
cmpq %rcx, %rbx
je .LBB5_6
.LBB5_3: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rax
xorl %edx, %edx
divq (%r12,%rcx,8)
testq %rdx, %rdx
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=2
movq $1, (%r13,%r15,8)
jmp .LBB5_5
.Lfunc_end5:
.size _Z14calculatePrimePyS_yyy, .Lfunc_end5-_Z14calculatePrimePyS_yyy
.cfi_endproc
# -- End function
.globl _Z15appending_primePyS_yyy # -- Begin function _Z15appending_primePyS_yyy
.p2align 4, 0x90
.type _Z15appending_primePyS_yyy,@function
_Z15appending_primePyS_yyy: # @_Z15appending_primePyS_yyy
.cfi_startproc
# %bb.0:
movq %r8, %rax
cmpq %rcx, %rdx
jb .LBB6_1
.LBB6_4: # %._crit_edge
retq
.p2align 4, 0x90
.LBB6_3: # in Loop: Header=BB6_1 Depth=1
incq %rdx
cmpq %rdx, %rcx
je .LBB6_4
.LBB6_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rdi,%rdx,8)
jne .LBB6_3
# %bb.2: # in Loop: Header=BB6_1 Depth=1
movq %rdx, (%rsi,%rax,8)
incq %rax
jmp .LBB6_3
.Lfunc_end6:
.size _Z15appending_primePyS_yyy, .Lfunc_end6-_Z15appending_primePyS_yyy
.cfi_endproc
# -- End function
.globl _Z15print_primelistPyy # -- Begin function _Z15print_primelistPyy
.p2align 4, 0x90
.type _Z15print_primelistPyy,@function
_Z15print_primelistPyy: # @_Z15print_primelistPyy
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB7_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB7_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_4: # %._crit_edge
retq
.Lfunc_end7:
.size _Z15print_primelistPyy, .Lfunc_end7-_Z15print_primelistPyy
.cfi_endproc
# -- End function
.globl _Z15print_inputlistPy # -- Begin function _Z15print_inputlistPy
.p2align 4, 0x90
.type _Z15print_inputlistPy,@function
_Z15print_inputlistPy: # @_Z15print_inputlistPy
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdx
movl $.L.str.11, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB8_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z15print_inputlistPy, .Lfunc_end8-_Z15print_inputlistPy
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "TOTAL INPUT SIZE IS: %llu\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "THE PRIMES WILL BE GENERATED FROM 0 - %llu\n"
.size .L.str.1, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "THE NUMBER OF PRIMES GENERATED: %llu \n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n"
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n"
.size .L.str.6, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "TOTAL NUMBER OF PRIMES GENERATED: %llu \n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n"
.size .L.str.9, 62
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d\t--->\t%llu\n"
.size .L.str.11, 14
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%llu\n"
.size .L.str.12, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "-------------------------------------------------------------------------\n\n"
.size .Lstr, 76
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "-------- END CALCULATING PRIME NUMBERS--------"
.size .Lstr.2, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00162489_00000000-6_newPrime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15appending_primePyS_yyy
.type _Z15appending_primePyS_yyy, @function
_Z15appending_primePyS_yyy:
.LFB2058:
.cfi_startproc
endbr64
movq %r8, %rax
cmpq %rcx, %rdx
jb .L6
.L4:
ret
.L5:
addq $1, %rdx
cmpq %rdx, %rcx
je .L4
.L6:
cmpq $0, (%rdi,%rdx,8)
jne .L5
movq %rdx, (%rsi,%rax,8)
addq $1, %rax
jmp .L5
.cfi_endproc
.LFE2058:
.size _Z15appending_primePyS_yyy, .-_Z15appending_primePyS_yyy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n"
.align 8
.LC1:
.string "-------- END CALCULATING PRIME NUMBERS--------\n"
.text
.globl _Z14calculatePrimePyS_yyy
.type _Z14calculatePrimePyS_yyy, @function
_Z14calculatePrimePyS_yyy:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
movq %rdx, %rbx
movq %rcx, %r12
movq %r8, %r14
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq %r12, %rbx
jnb .L9
leaq 0(%r13,%r14,8), %rsi
jmp .L10
.L11:
addq $8, %rcx
cmpq %rsi, %rcx
je .L13
.L12:
movq %rbx, %rax
movl $0, %edx
divq (%rcx)
testq %rdx, %rdx
jne .L11
movq $1, 0(%rbp,%rbx,8)
jmp .L11
.L13:
addq $1, %rbx
cmpq %rbx, %r12
je .L9
.L10:
movq %r13, %rcx
testq %r14, %r14
jne .L12
jmp .L13
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14calculatePrimePyS_yyy, .-_Z14calculatePrimePyS_yyy
.globl _Z25memsetting_range_of_inputPyy
.type _Z25memsetting_range_of_inputPyy, @function
_Z25memsetting_range_of_inputPyy:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 0(,%rsi,8), %rdx
movl $0, %esi
call memset@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z25memsetting_range_of_inputPyy, .-_Z25memsetting_range_of_inputPyy
.globl _Z22initializing_inputlistPy
.type _Z22initializing_inputlistPy, @function
_Z22initializing_inputlistPy:
.LFB2061:
.cfi_startproc
endbr64
leaq 800000008(%rdi), %rax
.L21:
movq $2, (%rdi)
addq $8, %rdi
cmpq %rax, %rdi
jne .L21
ret
.cfi_endproc
.LFE2061:
.size _Z22initializing_inputlistPy, .-_Z22initializing_inputlistPy
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d\t--->\t%llu\n"
.text
.globl _Z15print_inputlistPy
.type _Z15print_inputlistPy, @function
_Z15print_inputlistPy:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L24:
movq 0(%rbp,%rbx,8), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000000, %rbx
jne .L24
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z15print_inputlistPy, .-_Z15print_inputlistPy
.section .rodata.str1.1
.LC3:
.string "%llu\n"
.text
.globl _Z15print_primelistPyy
.type _Z15print_primelistPyy, @function
_Z15print_primelistPyy:
.LFB2063:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L32
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r13
.L29:
movq (%r12,%rbx,8), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L29
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2063:
.size _Z15print_primelistPyy, .-_Z15print_primelistPyy
.globl _Z16copy_seed_primesPyPii
.type _Z16copy_seed_primesPyPii, @function
_Z16copy_seed_primesPyPii:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L35
movslq %edx, %rdx
movl $0, %eax
.L37:
movslq (%rsi,%rax,4), %rcx
movq %rcx, (%rdi,%rax,8)
addq $1, %rax
cmpq %rax, %rdx
jne .L37
.L35:
ret
.cfi_endproc
.LFE2064:
.size _Z16copy_seed_primesPyPii, .-_Z16copy_seed_primesPyPii
.globl _Z20generate_seed_primesPiS_y
.type _Z20generate_seed_primesPiS_y, @function
_Z20generate_seed_primesPiS_y:
.LFB2065:
.cfi_startproc
endbr64
movq %rsi, %r9
cmpq $3, %rdx
jbe .L40
movl $4, %r8d
movl $2, %esi
jmp .L43
.L41:
leal 1(%rcx), %eax
addq $1, %rsi
addl $2, %r8d
imull %eax, %eax
cltq
cmpq %rax, %rdx
jb .L44
.L43:
movl %esi, %ecx
cmpl $0, (%rdi,%rsi,4)
jne .L41
movslq %r8d, %rax
cmpq %rax, %rdx
jb .L41
.L42:
movl $1, (%rdi,%rax,4)
addq %rsi, %rax
cmpq %rax, %rdx
jnb .L42
jmp .L41
.L40:
cmpq $1, %rdx
ja .L44
movl $0, %esi
.L39:
movl %esi, %eax
ret
.L44:
movl $2, %eax
movl $0, %esi
jmp .L47
.L46:
leaq 1(%rax), %rcx
cmpq %rdx, %rax
je .L39
movq %rcx, %rax
.L47:
cmpl $0, (%rdi,%rax,4)
jne .L46
movslq %esi, %rcx
movl %eax, (%r9,%rcx,4)
addl $1, %esi
jmp .L46
.cfi_endproc
.LFE2065:
.size _Z20generate_seed_primesPiS_y, .-_Z20generate_seed_primesPiS_y
.section .rodata.str1.1
.LC4:
.string "TOTAL INPUT SIZE IS: %llu\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "THE PRIMES WILL BE GENERATED FROM 0 - %llu\n"
.align 8
.LC6:
.string "-------------------------------------------------------------------------\n\n\n"
.align 8
.LC7:
.string "THE NUMBER OF PRIMES GENERATED: %llu \n"
.align 8
.LC9:
.string "MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n"
.align 8
.LC10:
.string "CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n"
.section .rodata.str1.1
.LC11:
.string "\n\n\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n"
.align 8
.LC13:
.string "TOTAL NUMBER OF PRIMES GENERATED: %llu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edx
movq %rax, %rsi
movq %rbp, %rdi
call _Z20generate_seed_primesPiS_y
movl %eax, %r12d
movl $100000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rbp
movl $800000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rdi
call _Z22initializing_inputlistPy
movl $80000000, %edi
call malloc@PLT
movq %rax, %r14
movl %r12d, %edx
movq %rbx, %rsi
movq %rax, %rdi
call _Z16copy_seed_primesPyPii
movl $10, %ebx
leaq .LC7(%rip), %r15
jmp .L58
.L53:
movq %rbx, %rax
shrq %rax
movq %rbx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L54
.L55:
subsd .LC8(%rip), %xmm0
cvttsd2siq %xmm0, %rbx
movabsq $-9223372036854775808, %rax
xorq %rax, %rbx
jmp .L56
.L62:
movq %rbx, %rcx
movq %r12, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %r13, %rdi
call _Z25memsetting_range_of_inputPyy
movq %rbp, %r8
movq %rbx, %rcx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z14calculatePrimePyS_yyy
movq %rbp, %r8
movq %rbx, %rcx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z15appending_primePyS_yyy
movq %rax, %rbp
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $9999999, %rbx
ja .L59
.L58:
movq %rbp, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbx, %rbx
js .L53
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L54:
movq %rbx, %r12
mulsd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
jnb .L55
cvttsd2siq %xmm0, %rbx
.L56:
movq %rbx, %rcx
movq %r12, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $10000000, %rbx
jbe .L62
movl $10000000, %ecx
movq %r12, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10000000, %esi
movq %r13, %rdi
call _Z25memsetting_range_of_inputPyy
movq %rbp, %r8
movl $10000000, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z14calculatePrimePyS_yyy
movq %rbp, %r8
movl $10000000, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z15appending_primePyS_yyy
movq %rax, %rbp
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L59:
movq %rbp, %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq %r14, %rdi
call _Z15print_primelistPyy
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "newPrime.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movq %rbx, %rax
addq $16, %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_4: # %.loopexit.i
# in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $4, %rdx
je .LBB0_5
.LBB0_1: # %.lr.ph35.i
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
cmpl $0, (%rbx,%rdx,4)
jne .LBB0_4
# %bb.2: # %.lr.ph.i.preheader
# in Loop: Header=BB0_1 Depth=1
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $11, %r8
jb .LBB0_3
jmp .LBB0_4
.LBB0_5: # %.lr.ph39.i.preheader
xorl %r12d, %r12d
movl $2, %eax
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_6 Depth=1
incq %rax
cmpq $11, %rax
je .LBB0_9
.LBB0_6: # %.lr.ph39.i
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%rax,4)
jne .LBB0_8
# %bb.7: # in Loop: Header=BB0_6 Depth=1
movslq %r12d, %r12
movl %eax, (%r15,%r12,4)
incl %r12d
jmp .LBB0_8
.LBB0_9: # %_Z20generate_seed_primesPiS_y.exit
xorl %ebx, %ebx
movl $.L.str, %edi
movl $100000000, %esi # imm = 0x5F5E100
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $10000000, %esi # imm = 0x989680
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $800000000, %edi # imm = 0x2FAF0800
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB0_10: # =>This Inner Loop Header: Depth=1
movq $2, (%r14,%rbx,8)
incq %rbx
cmpq $100000001, %rbx # imm = 0x5F5E101
jne .LBB0_10
# %bb.11: # %_Z22initializing_inputlistPy.exit
movl $80000000, %edi # imm = 0x4C4B400
callq malloc
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB0_14
# %bb.12: # %.lr.ph.preheader.i
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_13: # %.lr.ph.i53
# =>This Inner Loop Header: Depth=1
movslq (%r15,%rcx,4), %rdx
movq %rdx, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_13
.LBB0_14: # %_Z16copy_seed_primesPyPii.exit.preheader
movslq %r12d, %r15
movl $10, %r12d
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_28: # %_Z15appending_primePyS_yyy.exit.critedge
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
.LBB0_40: # %_Z15appending_primePyS_yyy.exit
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movsd .LCPI0_2(%rip), %xmm0 # xmm0 = mem[0],zero
movapd 16(%rsp), %xmm1 # 16-byte Reload
subsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
andq 8(%rsp), %rax # 8-byte Folded Reload
orq %rax, %rbp
movq %rbp, %r12
cmpq $10000000, %rbp # imm = 0x989680
jae .LBB0_41
.LBB0_15: # %_Z16copy_seed_primesPyPii.exit
# =>This Loop Header: Depth=1
# Child Loop BB0_30 Depth 2
# Child Loop BB0_32 Depth 3
# Child Loop BB0_37 Depth 2
# Child Loop BB0_18 Depth 2
# Child Loop BB0_20 Depth 3
# Child Loop BB0_25 Depth 2
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %r12, %xmm0
punpckldq .LCPI0_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI0_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
mulsd %xmm1, %xmm1
cvttsd2si %xmm1, %rbp
movq %rbp, %rax
sarq $63, %rax
movapd %xmm1, 16(%rsp) # 16-byte Spill
movapd %xmm1, %xmm0
subsd .LCPI0_2(%rip), %xmm0
cvttsd2si %xmm0, %r13
movq %rax, 8(%rsp) # 8-byte Spill
andq %rax, %r13
orq %rbp, %r13
movl $.L.str.4, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
cmpq $10000000, %r13 # imm = 0x989680
ja .LBB0_29
# %bb.16: # in Loop: Header=BB0_15 Depth=1
movl $.L.str.5, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
leaq (,%r13,8), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.9, %edi
movq %r12, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq printf
cmpq %r13, %r12
jae .LBB0_28
# %bb.17: # %.preheader.lr.ph.i
# in Loop: Header=BB0_15 Depth=1
movq %r12, %rcx
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_23: # %._crit_edge.i
# in Loop: Header=BB0_18 Depth=2
incq %rcx
cmpq %r13, %rcx
je .LBB0_24
.LBB0_18: # %.preheader.i58
# Parent Loop BB0_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_20 Depth 3
testq %r15, %r15
je .LBB0_23
# %bb.19: # %.lr.ph.i59
# in Loop: Header=BB0_18 Depth=2
xorl %esi, %esi
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_20 Depth=3
incq %rsi
cmpq %rsi, %r15
je .LBB0_23
.LBB0_20: # Parent Loop BB0_15 Depth=1
# Parent Loop BB0_18 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
xorl %edx, %edx
divq (%rbx,%rsi,8)
testq %rdx, %rdx
jne .LBB0_22
# %bb.21: # in Loop: Header=BB0_20 Depth=3
movq $1, (%r14,%rcx,8)
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_29: # %.preheader.lr.ph.i66
# in Loop: Header=BB0_15 Depth=1
movl $.L.str.6, %edi
movq %r12, %rsi
movl $10000000, %edx # imm = 0x989680
xorl %eax, %eax
callq printf
movl $80000000, %edx # imm = 0x4C4B400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.9, %edi
movl $10000000, %edx # imm = 0x989680
movq %r12, %rsi
xorl %eax, %eax
callq printf
movq %r12, %rcx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_35: # %._crit_edge.i73
# in Loop: Header=BB0_30 Depth=2
incq %rcx
cmpq $10000000, %rcx # imm = 0x989680
je .LBB0_36
.LBB0_30: # %.preheader.i68
# Parent Loop BB0_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_32 Depth 3
testq %r15, %r15
je .LBB0_35
# %bb.31: # %.lr.ph.i70
# in Loop: Header=BB0_30 Depth=2
xorl %esi, %esi
jmp .LBB0_32
.p2align 4, 0x90
.LBB0_34: # in Loop: Header=BB0_32 Depth=3
incq %rsi
cmpq %rsi, %r15
je .LBB0_35
.LBB0_32: # Parent Loop BB0_15 Depth=1
# Parent Loop BB0_30 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
xorl %edx, %edx
divq (%rbx,%rsi,8)
testq %rdx, %rdx
jne .LBB0_34
# %bb.33: # in Loop: Header=BB0_32 Depth=3
movq $1, (%r14,%rcx,8)
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_36: # %_Z14calculatePrimePyS_yyy.exit75
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB0_37
.p2align 4, 0x90
.LBB0_39: # in Loop: Header=BB0_37 Depth=2
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB0_40
.LBB0_37: # %.lr.ph.i78
# Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $0, (%r14,%r12,8)
jne .LBB0_39
# %bb.38: # in Loop: Header=BB0_37 Depth=2
movq %r12, (%rbx,%r15,8)
incq %r15
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_24: # %_Z14calculatePrimePyS_yyy.exit
# in Loop: Header=BB0_15 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
cmpq %r13, %r12
jb .LBB0_25
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_25 Depth=2
incq %r12
cmpq %r12, %r13
je .LBB0_40
.LBB0_25: # %.lr.ph.i62
# Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $0, (%r14,%r12,8)
jne .LBB0_27
# %bb.26: # in Loop: Header=BB0_25 Depth=2
movq %r12, (%rbx,%r15,8)
incq %r15
jmp .LBB0_27
.LBB0_41:
movl $.L.str.8, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
testq %r15, %r15
je .LBB0_44
# %bb.42: # %.lr.ph.i85.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_43: # %.lr.ph.i85
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB0_43
.LBB0_44: # %_Z15print_primelistPyy.exit
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z20generate_seed_primesPiS_y # -- Begin function _Z20generate_seed_primesPiS_y
.p2align 4, 0x90
.type _Z20generate_seed_primesPiS_y,@function
_Z20generate_seed_primesPiS_y: # @_Z20generate_seed_primesPiS_y
.cfi_startproc
# %bb.0:
cmpq $4, %rdx
jae .LBB1_1
.LBB1_7: # %.preheader
xorl %eax, %eax
cmpq $2, %rdx
jae .LBB1_8
.LBB1_12: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.LBB1_1: # %.lr.ph35.preheader
leaq 16(%rdi), %rax
movl $4, %ecx
movl $2, %r8d
movl $8, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %.loopexit
# in Loop: Header=BB1_2 Depth=1
incq %r8
movq %r8, %r10
imulq %r8, %r10
addq $2, %rcx
addq $8, %rax
addq $4, %r9
cmpq %rdx, %r10
ja .LBB1_7
.LBB1_2: # %.lr.ph35
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
cmpl $0, (%rdi,%r8,4)
jne .LBB1_6
# %bb.3: # %.lr.ph35
# in Loop: Header=BB1_2 Depth=1
leaq (%r8,%r8), %r10
cmpq %rdx, %r10
ja .LBB1_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %rax, %r10
movq %rcx, %r11
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%r10)
addq %r8, %r11
addq %r9, %r10
cmpq %rdx, %r11
jbe .LBB1_5
jmp .LBB1_6
.LBB1_8: # %.lr.ph39.preheader
movl $1, %ecx
subq %rdx, %rcx
xorl %eax, %eax
movl $2, %edx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
leaq (%rcx,%rdx), %r8
incq %r8
incq %rdx
cmpq $2, %r8
je .LBB1_12
.LBB1_9: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rdi,%rdx,4)
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
cltq
movl %edx, (%rsi,%rax,4)
incl %eax
jmp .LBB1_11
.Lfunc_end1:
.size _Z20generate_seed_primesPiS_y, .Lfunc_end1-_Z20generate_seed_primesPiS_y
.cfi_endproc
# -- End function
.globl _Z22initializing_inputlistPy # -- Begin function _Z22initializing_inputlistPy
.p2align 4, 0x90
.type _Z22initializing_inputlistPy,@function
_Z22initializing_inputlistPy: # @_Z22initializing_inputlistPy
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq $2, (%rdi,%rax,8)
incq %rax
cmpq $100000001, %rax # imm = 0x5F5E101
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z22initializing_inputlistPy, .Lfunc_end2-_Z22initializing_inputlistPy
.cfi_endproc
# -- End function
.globl _Z16copy_seed_primesPyPii # -- Begin function _Z16copy_seed_primesPyPii
.p2align 4, 0x90
.type _Z16copy_seed_primesPyPii,@function
_Z16copy_seed_primesPyPii: # @_Z16copy_seed_primesPyPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq (%rsi,%rcx,4), %rdx
movq %rdx, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16copy_seed_primesPyPii, .Lfunc_end3-_Z16copy_seed_primesPyPii
.cfi_endproc
# -- End function
.globl _Z25memsetting_range_of_inputPyy # -- Begin function _Z25memsetting_range_of_inputPyy
.p2align 4, 0x90
.type _Z25memsetting_range_of_inputPyy,@function
_Z25memsetting_range_of_inputPyy: # @_Z25memsetting_range_of_inputPyy
.cfi_startproc
# %bb.0:
leaq (,%rsi,8), %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.Lfunc_end4:
.size _Z25memsetting_range_of_inputPyy, .Lfunc_end4-_Z25memsetting_range_of_inputPyy
.cfi_endproc
# -- End function
.globl _Z14calculatePrimePyS_yyy # -- Begin function _Z14calculatePrimePyS_yyy
.p2align 4, 0x90
.type _Z14calculatePrimePyS_yyy,@function
_Z14calculatePrimePyS_yyy: # @_Z14calculatePrimePyS_yyy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str.9, %edi
movq %rdx, %rsi
movq %rcx, %rdx
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jb .LBB5_1
.LBB5_7: # %._crit_edge16
movl $.Lstr.2, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.p2align 4, 0x90
.LBB5_6: # %._crit_edge
# in Loop: Header=BB5_1 Depth=1
.cfi_def_cfa_offset 48
incq %r15
cmpq %r14, %r15
je .LBB5_7
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
testq %rbx, %rbx
je .LBB5_6
# %bb.2: # %.lr.ph
# in Loop: Header=BB5_1 Depth=1
xorl %ecx, %ecx
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=2
incq %rcx
cmpq %rcx, %rbx
je .LBB5_6
.LBB5_3: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rax
xorl %edx, %edx
divq (%r12,%rcx,8)
testq %rdx, %rdx
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=2
movq $1, (%r13,%r15,8)
jmp .LBB5_5
.Lfunc_end5:
.size _Z14calculatePrimePyS_yyy, .Lfunc_end5-_Z14calculatePrimePyS_yyy
.cfi_endproc
# -- End function
.globl _Z15appending_primePyS_yyy # -- Begin function _Z15appending_primePyS_yyy
.p2align 4, 0x90
.type _Z15appending_primePyS_yyy,@function
_Z15appending_primePyS_yyy: # @_Z15appending_primePyS_yyy
.cfi_startproc
# %bb.0:
movq %r8, %rax
cmpq %rcx, %rdx
jb .LBB6_1
.LBB6_4: # %._crit_edge
retq
.p2align 4, 0x90
.LBB6_3: # in Loop: Header=BB6_1 Depth=1
incq %rdx
cmpq %rdx, %rcx
je .LBB6_4
.LBB6_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rdi,%rdx,8)
jne .LBB6_3
# %bb.2: # in Loop: Header=BB6_1 Depth=1
movq %rdx, (%rsi,%rax,8)
incq %rax
jmp .LBB6_3
.Lfunc_end6:
.size _Z15appending_primePyS_yyy, .Lfunc_end6-_Z15appending_primePyS_yyy
.cfi_endproc
# -- End function
.globl _Z15print_primelistPyy # -- Begin function _Z15print_primelistPyy
.p2align 4, 0x90
.type _Z15print_primelistPyy,@function
_Z15print_primelistPyy: # @_Z15print_primelistPyy
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB7_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB7_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_4: # %._crit_edge
retq
.Lfunc_end7:
.size _Z15print_primelistPyy, .Lfunc_end7-_Z15print_primelistPyy
.cfi_endproc
# -- End function
.globl _Z15print_inputlistPy # -- Begin function _Z15print_inputlistPy
.p2align 4, 0x90
.type _Z15print_inputlistPy,@function
_Z15print_inputlistPy: # @_Z15print_inputlistPy
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdx
movl $.L.str.11, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB8_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z15print_inputlistPy, .Lfunc_end8-_Z15print_inputlistPy
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "TOTAL INPUT SIZE IS: %llu\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "THE PRIMES WILL BE GENERATED FROM 0 - %llu\n"
.size .L.str.1, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "THE NUMBER OF PRIMES GENERATED: %llu \n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "MAXIMUM RANGE PRIMES BETWEEN 0 - %llu CAN DETERMINE IS %llu \n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CALCULATE PRIME NUMBERS BETWEEN %llu - %llu\n"
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CALCULATE PRIME NUMBERS BETWEEN %llu - %d\n"
.size .L.str.6, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "TOTAL NUMBER OF PRIMES GENERATED: %llu \n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "--------CALCULATING PRIME NUMBERS from %llu to %llu --------\n"
.size .L.str.9, 62
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d\t--->\t%llu\n"
.size .L.str.11, 14
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%llu\n"
.size .L.str.12, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "-------------------------------------------------------------------------\n\n"
.size .Lstr, 76
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "-------- END CALCULATING PRIME NUMBERS--------"
.size .Lstr.2, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/execution_policy.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <iostream>
#include <numeric>
#include <ctime>
struct HashGenerator {
int current_;
HashGenerator (int start) : current_(start) {}
double operator() () { current_++;
return generateReal(current_);}
// generates a int hash from an int value
int hash(int i)
{
uint64_t v = ((uint64_t) i) * 3935559000370003845 + 2691343689449507681;
v = v ^ (v >> 21);
v = v ^ (v << 37);
v = v ^ (v >> 4);
v = v * 4768777513237032717;
v = v ^ (v << 20);
v = v ^ (v >> 41);
v = v ^ (v << 5);
return (int) (v & ((((uint64_t) 1) << 31) - 1));
}
// generates a pseudorandom double precision real from an integer
double generateReal(int i) {
return (double(hash(i)));
}
};
struct IncGenerator {
double current_;
IncGenerator (double start) : current_(start) {}
double operator() () { return current_++; }
};
int main(void)
{
int N = 10000000;
// generate 100M numbers serially
thrust::host_vector<double> h_vec(N);
thrust::host_vector<double> v_vec(N);
thrust::host_vector<double> h_vec_result(N);
thrust::host_vector<double> v_vec_result(N);
HashGenerator HG (0);
IncGenerator IG (0);
clock_t begin_generation = clock();
std::generate(h_vec.begin(), h_vec.end(), HG);
std::generate(v_vec.begin(), v_vec.end(), IG);
clock_t end_generation = clock();
double generation_time = double(end_generation - begin_generation) / CLOCKS_PER_SEC;
std::cout << "Generation Time: " << generation_time << std::endl;
int numRuns = 5;
for(int i = 0; i < numRuns; i++) {
clock_t begin_sort_copy = clock();
// transfer data to the device
thrust::device_vector<double> d_vec = h_vec;
thrust::device_vector<double> dv_vec = v_vec;
clock_t begin_sort = clock();
// sort data on the device
thrust::sort_by_key(thrust::device, d_vec.begin(), d_vec.end(), dv_vec.begin());
cudaThreadSynchronize();
clock_t end_sort = clock();
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec_result.begin());
thrust::copy(dv_vec.begin(), dv_vec.end(), v_vec_result.begin());
cudaThreadSynchronize();
clock_t end_sort_copy = clock();
double sort_copy_time = double(end_sort_copy - begin_sort_copy) / CLOCKS_PER_SEC;
double sort_time = double(end_sort - begin_sort) / CLOCKS_PER_SEC;
std::cout << "Sort + Copy Time: " << sort_copy_time << std::endl;
std::cout << "Sort Only Time: " << sort_time << std::endl;
clock_t begin_check = clock();
for(int j = 1; j < N; j++) {
if(h_vec_result[j] < h_vec_result[j-1]){
std::cout << "Error: " << h_vec_result[j-1] << " is before " << h_vec_result[j] << std::endl;
}
}
clock_t end_check = clock();
double check_time = double(end_check - begin_check) / CLOCKS_PER_SEC;
std::cout << "Check Time: " << check_time << std::endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/execution_policy.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <iostream>
#include <numeric>
#include <ctime>
struct HashGenerator {
int current_;
HashGenerator (int start) : current_(start) {}
double operator() () { current_++;
return generateReal(current_);}
// generates a int hash from an int value
int hash(int i)
{
uint64_t v = ((uint64_t) i) * 3935559000370003845 + 2691343689449507681;
v = v ^ (v >> 21);
v = v ^ (v << 37);
v = v ^ (v >> 4);
v = v * 4768777513237032717;
v = v ^ (v << 20);
v = v ^ (v >> 41);
v = v ^ (v << 5);
return (int) (v & ((((uint64_t) 1) << 31) - 1));
}
// generates a pseudorandom double precision real from an integer
double generateReal(int i) {
return (double(hash(i)));
}
};
struct IncGenerator {
double current_;
IncGenerator (double start) : current_(start) {}
double operator() () { return current_++; }
};
int main(void)
{
int N = 10000000;
// generate 100M numbers serially
thrust::host_vector<double> h_vec(N);
thrust::host_vector<double> v_vec(N);
thrust::host_vector<double> h_vec_result(N);
thrust::host_vector<double> v_vec_result(N);
HashGenerator HG (0);
IncGenerator IG (0);
clock_t begin_generation = clock();
std::generate(h_vec.begin(), h_vec.end(), HG);
std::generate(v_vec.begin(), v_vec.end(), IG);
clock_t end_generation = clock();
double generation_time = double(end_generation - begin_generation) / CLOCKS_PER_SEC;
std::cout << "Generation Time: " << generation_time << std::endl;
int numRuns = 5;
for(int i = 0; i < numRuns; i++) {
clock_t begin_sort_copy = clock();
// transfer data to the device
thrust::device_vector<double> d_vec = h_vec;
thrust::device_vector<double> dv_vec = v_vec;
clock_t begin_sort = clock();
// sort data on the device
thrust::sort_by_key(thrust::device, d_vec.begin(), d_vec.end(), dv_vec.begin());
hipDeviceSynchronize();
clock_t end_sort = clock();
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec_result.begin());
thrust::copy(dv_vec.begin(), dv_vec.end(), v_vec_result.begin());
hipDeviceSynchronize();
clock_t end_sort_copy = clock();
double sort_copy_time = double(end_sort_copy - begin_sort_copy) / CLOCKS_PER_SEC;
double sort_time = double(end_sort - begin_sort) / CLOCKS_PER_SEC;
std::cout << "Sort + Copy Time: " << sort_copy_time << std::endl;
std::cout << "Sort Only Time: " << sort_time << std::endl;
clock_t begin_check = clock();
for(int j = 1; j < N; j++) {
if(h_vec_result[j] < h_vec_result[j-1]){
std::cout << "Error: " << h_vec_result[j-1] << " is before " << h_vec_result[j] << std::endl;
}
}
clock_t end_check = clock();
double check_time = double(end_check - begin_check) / CLOCKS_PER_SEC;
std::cout << "Check Time: " << check_time << std::endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} | .file "tmpxft_00174786_00000000-6_test1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Mayank"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main(){
cout<<"Mayank"<<endl;
return 0;
} | .text
.file "test1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mayank"
.size .L.str, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00174786_00000000-6_test1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Mayank"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mayank"
.size .L.str, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} | code for sm_80
Function : _Z3CosPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*00c0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007f1e1ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0004 */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R8, R0, c[0x0][0x170], R8 ; /* 0x00005c0000087a25 */
/* 0x000fc800078e0008 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R8, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x8d0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R7, R7, c[0x0][0x178] ; /* 0x00005e0007077a20 */
/* 0x004fc80000400000 */
/*0180*/ FMUL R8, R7.reuse, 0.63661974668502807617 ; /* 0x3f22f98307087820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R7|, 105615, PT ; /* 0x47ce47800700780b */
/* 0x000fca0003f06200 */
/*01a0*/ F2I.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e300000203100 */
/*01b0*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x001e240000201400 */
/*01c0*/ FFMA R9, R10, -1.5707962512969970703, R7 ; /* 0xbfc90fda0a097823 */
/* 0x001fc80000000007 */
/*01d0*/ FFMA R9, R10, -7.5497894158615963534e-08, R9 ; /* 0xb3a221680a097823 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R10, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c50a097823 */
/* 0x000fe20000000009 */
/*01f0*/ @!P0 BRA 0x8c0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f0d200 */
/*0210*/ @!P0 BRA 0x8a0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R8, RZ, 0x17, R7 ; /* 0x00000017ff087819 */
/* 0x000fe20000011607 */
/*0230*/ IMAD.SHL.U32 R9, R7, 0x100, RZ ; /* 0x0000010007097824 */
/* 0x000fe200078e00ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0280*/ LOP3.LUT R21, R9, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000009157812 */
/* 0x000fe200078efcff */
/*0290*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*02a0*/ IADD3 R20, R8, -0x80, RZ ; /* 0xffffff8008147810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*02c0*/ SHF.R.U32.HI R12, RZ, 0x5, R20 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011614 */
/*02d0*/ IMAD.U32 R8, RZ, RZ, UR8 ; /* 0x00000008ff087e24 */
/* 0x000fe4000f8e00ff */
/*02e0*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*02f0*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e9900 */
/*0300*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0320*/ ISETP.EQ.AND P0, PT, R22.reuse, RZ, PT ; /* 0x000000ff1600720c */
/* 0x040fe40003f02270 */
/*0330*/ ISETP.EQ.AND P5, PT, R22.reuse, 0x4, PT ; /* 0x000000041600780c */
/* 0x040fe20003fa2270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ ISETP.EQ.AND P4, PT, R22.reuse, 0x8, PT ; /* 0x000000081600780c */
/* 0x040fe40003f82270 */
/*0360*/ ISETP.EQ.AND P3, PT, R22.reuse, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x040fe40003f62270 */
/*0370*/ ISETP.EQ.AND P2, PT, R22, 0x10, PT ; /* 0x000000101600780c */
/* 0x000fc40003f42270 */
/*0380*/ ISETP.EQ.AND P1, PT, R22.reuse, 0x14, PT ; /* 0x000000141600780c */
/* 0x040fe40003f22270 */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R10, R8, R21, RZ ; /* 0x00000015080a7225 */
/* 0x004fca00078e00ff */
/*03b0*/ IADD3 R10, P6, R10, R13, RZ ; /* 0x0000000d0a0a7210 */
/* 0x000fc80007fde0ff */
/*03c0*/ IADD3.X R13, R11, UR4, RZ, P6, !PT ; /* 0x000000040b0d7c10 */
/* 0x000fe2000b7fe4ff */
/*03d0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R10.reuse ; /* 0x000000ffff060224 */
/* 0x100fe200078e000a */
/*03e0*/ ISETP.NE.AND P6, PT, R19, 0x6, PT ; /* 0x000000061300780c */
/* 0x000fe20003fc5270 */
/*03f0*/ @P4 IMAD.MOV.U32 R18, RZ, RZ, R10.reuse ; /* 0x000000ffff124224 */
/* 0x100fe200078e000a */
/*0400*/ @P5 MOV R17, R10 ; /* 0x0000000a00115202 */
/* 0x000fe20000000f00 */
/*0410*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R10.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e000a */
/*0420*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R10.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e000a */
/*0430*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff101224 */
/* 0x000fcc00078e000a */
/*0440*/ @P6 BRA 0x2d0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0450*/ IADD3 R8, -R12, 0x6, RZ ; /* 0x000000060c087810 */
/* 0x000fe20007ffe1ff */
/*0460*/ BSSY B1, 0x790 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.EQ.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f02270 */
/*0490*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x4, PT ; /* 0x000000040800780c */
/* 0x040fe40003f62270 */
/*04a0*/ ISETP.EQ.AND P4, PT, R8.reuse, 0x8, PT ; /* 0x000000080800780c */
/* 0x040fe40003f82270 */
/*04b0*/ ISETP.EQ.AND P2, PT, R8.reuse, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x040fe40003f42270 */
/*04c0*/ ISETP.EQ.AND P1, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fca0003f22270 */
/*04d0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R6.reuse ; /* 0x000000ffff090224 */
/* 0x100fe200078e0006 */
/*04e0*/ ISETP.EQ.AND P0, PT, R8.reuse, 0x14, PT ; /* 0x000000140800780c */
/* 0x040fe20003f02270 */
/*04f0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0006 */
/*0500*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R17.reuse ; /* 0x000000ffff093224 */
/* 0x100fe200078e0011 */
/*0510*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x18, PT ; /* 0x000000180800780c */
/* 0x040fe20003f62270 */
/*0520*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a4224 */
/* 0x000fe200078e0011 */
/*0530*/ @P2 MOV R10, R18 ; /* 0x00000012000a2202 */
/* 0x000fe20000000f00 */
/*0540*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff094224 */
/* 0x000fe200078e0012 */
/*0550*/ ISETP.EQ.AND P4, PT, R8, 0x1c, PT ; /* 0x0000001c0800780c */
/* 0x000fe20003f82270 */
/*0560*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff092224 */
/* 0x000fc400078e000e */
/*0570*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0580*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff091224 */
/* 0x000fe200078e000f */
/*0590*/ LOP3.LUT P1, R19, R20, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f14137812 */
/* 0x000fe2000782c0ff */
/*05a0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R16.reuse ; /* 0x000000ffff090224 */
/* 0x100fe400078e0010 */
/*05b0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff093224 */
/* 0x000fe400078e000d */
/*05c0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e000f */
/*05d0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a3224 */
/* 0x000fc400078e0010 */
/*05e0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e000d */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0009 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, -R12, 0x4, RZ ; /* 0x000000040c097810 */
/* 0x000fe40007ffe1ff */
/*0620*/ SHF.L.U32 R11, R8, R19.reuse, RZ ; /* 0x00000013080b7219 */
/* 0x080fe400000006ff */
/*0630*/ SHF.L.U32 R20, R10, R19, RZ ; /* 0x000000130a147219 */
/* 0x000fe200000006ff */
/*0640*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x000fca00078e00ff */
/*0650*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f02270 */
/*0660*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x4, PT ; /* 0x000000040900780c */
/* 0x040fe40003f22270 */
/*0670*/ ISETP.EQ.AND P2, PT, R9.reuse, 0x8, PT ; /* 0x000000080900780c */
/* 0x040fe40003f42270 */
/*0680*/ ISETP.EQ.AND P3, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fce0003f62270 */
/*0690*/ @P0 MOV R12, R6 ; /* 0x00000006000c0202 */
/* 0x000fe40000000f00 */
/*06a0*/ ISETP.EQ.AND P0, PT, R9.reuse, 0x10, PT ; /* 0x000000100900780c */
/* 0x040fe20003f02270 */
/*06b0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0011 */
/*06c0*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x14, PT ; /* 0x000000140900780c */
/* 0x040fe20003f22270 */
/*06d0*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c2224 */
/* 0x000fe200078e0012 */
/*06e0*/ ISETP.EQ.AND P2, PT, R9, 0x18, PT ; /* 0x000000180900780c */
/* 0x000fe20003f42270 */
/*06f0*/ @P3 IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c3224 */
/* 0x000fe200078e000e */
/*0700*/ IADD3 R9, -R19, 0x20, RZ ; /* 0x0000002013097810 */
/* 0x000fc80007ffe1ff */
/*0710*/ SHF.R.U32.HI R8, RZ, R9, R10 ; /* 0x00000009ff087219 */
/* 0x000fc6000001160a */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e000f */
/*0730*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e0010 */
/*0740*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c2224 */
/* 0x000fe400078e000d */
/*0750*/ IMAD.IADD R8, R8, 0x1, R11 ; /* 0x0000000108087824 */
/* 0x000fc600078e020b */
/*0760*/ SHF.R.U32.HI R9, RZ, R9, R12 ; /* 0x00000009ff097219 */
/* 0x000fca000001160c */
/*0770*/ IMAD.IADD R10, R9, 0x1, R20 ; /* 0x00000001090a7824 */
/* 0x000fe400078e0214 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ SHF.L.U32.HI R13, R10.reuse, 0x2, R8 ; /* 0x000000020a0d7819 */
/* 0x040fe20000010608 */
/*07a0*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT P1, R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fe4000782c0ff */
/*07c0*/ SHF.R.U32.HI R9, RZ, 0x1f, R13 ; /* 0x0000001fff097819 */
/* 0x000fc8000001160d */
/*07d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*07e0*/ LEA.HI R8, R8, R9, RZ, 0x2 ; /* 0x0000000908087211 */
/* 0x000fd600078f10ff */
/*07f0*/ @P0 LOP3.LUT R13, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff0d0212 */
/* 0x000fe400078e33ff */
/*0800*/ @P0 LOP3.LUT R12, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff0c0212 */
/* 0x000fe400078e33ff */
/*0810*/ @P0 LOP3.LUT R7, R7, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000007070812 */
/* 0x000fe400078e3cff */
/*0820*/ I2F.F64.S64 R10, R12 ; /* 0x0000000c000a7312 */
/* 0x000e240000301c00 */
/*0830*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0840*/ IADD3 R7, -R8, RZ, RZ ; /* 0x000000ff08077210 */
/* 0x000fca0007ffe1ff */
/*0850*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0007 */
/*0860*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*0870*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000301000 */
/*0880*/ FSEL R9, R10, -R10, !P0 ; /* 0x8000000a0a097208 */
/* 0x001fe20004000000 */
/*0890*/ BRA 0x8c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FMUL R9, RZ, R7 ; /* 0x00000007ff097220 */
/* 0x000fe40000400000 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R12, R8, 0x1, RZ ; /* 0x00000001080c7810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff087424 */
/* 0x000fe400078e00ff */
/*08f0*/ FMUL R13, R9, R9 ; /* 0x00000009090d7220 */
/* 0x000fe20000400000 */
/*0900*/ LOP3.LUT P1, RZ, R12.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010cff7812 */
/* 0x040fe2000782c0ff */
/*0910*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0b7424 */
/* 0x000fe200078e00ff */
/*0920*/ LOP3.LUT P0, RZ, R12, 0x2, RZ, 0xc0, !PT ; /* 0x000000020cff7812 */
/* 0x000fe2000780c0ff */
/*0930*/ IMAD.MOV.U32 R7, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff077424 */
/* 0x000fe200078e00ff */
/*0940*/ FSEL R8, R8, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb08087808 */
/* 0x000fc40004800000 */
/*0950*/ FSEL R9, R9, 1, !P1 ; /* 0x3f80000009097808 */
/* 0x000fce0004800000 */
/*0960*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff0a1424 */
/* 0x000fc800078e00ff */
/*0970*/ @P1 FFMA R7, R13, R10, -0.0013887860113754868507 ; /* 0xbab607ed0d071423 */
/* 0x000fe2000000000a */
/*0980*/ FSEL R10, -R11, -0.4999999701976776123, !P1 ; /* 0xbeffffff0b0a7808 */
/* 0x000fc60004800100 */
/*0990*/ FFMA R7, R13, R7, R8 ; /* 0x000000070d077223 */
/* 0x000fe40000000008 */
/*09a0*/ FFMA R8, R9, R13, RZ ; /* 0x0000000d09087223 */
/* 0x000fe400000000ff */
/*09b0*/ FFMA R7, R13, R7, R10 ; /* 0x000000070d077223 */
/* 0x000fc8000000000a */
/*09c0*/ FFMA R7, R7, R8, R9 ; /* 0x0000000807077223 */
/* 0x000fe40000000009 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*09e0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fe400000000ff */
/*09f0*/ IMAD R8, R9, c[0x0][0xc], R4 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0204 */
/*0a00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101906 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, R8.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0008 */
/*0a20*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0a30*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0a40*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0a50*/ @!P0 BRA 0xf0 ; /* 0xfffff69000008947 */
/* 0x001fea000383ffff */
/*0a60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a70*/ BRA 0xa70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} | .file "tmpxft_0009cab7_00000000-6_Cos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3CosPfmmfPfmmf
.type _Z25__device_stub__Z3CosPfmmfPfmmf, @function
_Z25__device_stub__Z3CosPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3CosPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3CosPfmmfPfmmf, .-_Z25__device_stub__Z3CosPfmmfPfmmf
.globl _Z3CosPfmmf
.type _Z3CosPfmmf, @function
_Z3CosPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3CosPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3CosPfmmf, .-_Z3CosPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3CosPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3CosPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3CosPfmmf
.globl _Z3CosPfmmf
.p2align 8
.type _Z3CosPfmmf,@function
_Z3CosPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[5:6], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_cmpx_gt_u64_e64 s[2:3], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s6, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s5, s6, s5
s_mul_i32 s0, s0, s2
s_add_i32 s1, s5, s1
s_mov_b32 s10, 0xb94c1982
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s11, 0x37d75334
s_add_u32 s5, s8, s0
s_addc_u32 s6, s9, s1
s_add_i32 s15, s15, s12
s_mov_b32 s8, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_mul_i32 s7, s12, s7
s_mov_b32 s9, 0x7fffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v6, v2, v2 :: v_dual_and_b32 v9, 1, v5
v_cmp_class_f32_e64 s0, v0, 0x1f8
v_lshlrev_b32_e32 v5, 30, v5
v_fmaak_f32 v7, s10, v6, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_dual_fmaak_f32 v8, s11, v6, 0xbab64f3b :: v_dual_mul_f32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
v_fmac_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbf000004
v_fma_f32 v6, v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, -v2, v6, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_xor_b32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
v_add_nc_u32_e32 v1, s7, v1
s_or_b32 s8, vcc_lo, s8
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s5, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s6, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s12, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v2, 0x7fffffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v15, v2, s9, 0x800000
v_lshrrev_b32_e32 v2, 23, v2
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0xffffff88, v2
v_cmp_lt_u32_e32 vcc_lo, 63, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v13, v2
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v2
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
v_add_nc_u32_e32 v2, v14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
v_cmp_lt_u32_e64 s1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v11
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v12
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v13
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v12, v10, vcc_lo
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
v_cndmask_b32_e32 v6, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, v13, v7, s0
v_cndmask_b32_e64 v10, v12, v13, s0
v_cndmask_b32_e64 v7, v7, v11, s0
v_sub_nc_u32_e32 v12, 32, v2
v_cndmask_b32_e64 v11, v11, v6, s0
v_cndmask_b32_e64 v5, v6, v5, s0
v_cndmask_b32_e64 v10, v10, v8, s1
v_cndmask_b32_e64 v8, v8, v7, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v7, v11, s1
v_cndmask_b32_e64 v5, v11, v5, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v10, v8, v12
v_alignbit_b32 v9, v8, v7, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v7, v5, v12
v_cndmask_b32_e32 v2, v13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v9, v8 :: v_dual_cndmask_b32 v7, v11, v7
v_bfe_u32 v8, v2, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v2, v6, 30
v_alignbit_b32 v6, v6, v7, 30
v_alignbit_b32 v5, v7, v5, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, 0, v8
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v6, v6, v10
v_xor_b32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v11, v9
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v5, v6, v5, v7
v_lshrrev_b32_e32 v7, 29, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v6, v9, v5, 9
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v10, v6
v_or_b32_e32 v12, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v10, 32, v10
v_sub_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, 31, v10
v_alignbit_b32 v5, v6, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
v_lshrrev_b32_e32 v5, 9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, 0x3fc90fda, v6
v_sub_nc_u32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v6, 0x3fc90fda, -v10
v_add_nc_u32_e32 v5, 0x33000000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0x33a22168, v6
v_or_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0x3fc90fda, v5
v_lshrrev_b32_e32 v5, 30, v2
v_add_f32_e32 v2, v10, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v5, v8, v5
.LBB0_5:
s_and_not1_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v2, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v2
v_fma_f32 v2, v5, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0xb3a22168, v5
v_fmac_f32_e32 v2, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v5, v5
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3CosPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3CosPfmmf, .Lfunc_end0-_Z3CosPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3CosPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3CosPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Cos( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = cos ( W0*x[(idx-1)*N+i] );
}
return;
} | .text
.file "Cos.hip"
.globl _Z18__device_stub__CosPfmmf # -- Begin function _Z18__device_stub__CosPfmmf
.p2align 4, 0x90
.type _Z18__device_stub__CosPfmmf,@function
_Z18__device_stub__CosPfmmf: # @_Z18__device_stub__CosPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3CosPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__CosPfmmf, .Lfunc_end0-_Z18__device_stub__CosPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3CosPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3CosPfmmf,@object # @_Z3CosPfmmf
.section .rodata,"a",@progbits
.globl _Z3CosPfmmf
.p2align 3, 0x0
_Z3CosPfmmf:
.quad _Z18__device_stub__CosPfmmf
.size _Z3CosPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3CosPfmmf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__CosPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3CosPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3CosPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*00c0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007f1e1ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0004 */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R8, R0, c[0x0][0x170], R8 ; /* 0x00005c0000087a25 */
/* 0x000fc800078e0008 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R8, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x8d0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R7, R7, c[0x0][0x178] ; /* 0x00005e0007077a20 */
/* 0x004fc80000400000 */
/*0180*/ FMUL R8, R7.reuse, 0.63661974668502807617 ; /* 0x3f22f98307087820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R7|, 105615, PT ; /* 0x47ce47800700780b */
/* 0x000fca0003f06200 */
/*01a0*/ F2I.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e300000203100 */
/*01b0*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x001e240000201400 */
/*01c0*/ FFMA R9, R10, -1.5707962512969970703, R7 ; /* 0xbfc90fda0a097823 */
/* 0x001fc80000000007 */
/*01d0*/ FFMA R9, R10, -7.5497894158615963534e-08, R9 ; /* 0xb3a221680a097823 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R10, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c50a097823 */
/* 0x000fe20000000009 */
/*01f0*/ @!P0 BRA 0x8c0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f0d200 */
/*0210*/ @!P0 BRA 0x8a0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R8, RZ, 0x17, R7 ; /* 0x00000017ff087819 */
/* 0x000fe20000011607 */
/*0230*/ IMAD.SHL.U32 R9, R7, 0x100, RZ ; /* 0x0000010007097824 */
/* 0x000fe200078e00ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0280*/ LOP3.LUT R21, R9, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000009157812 */
/* 0x000fe200078efcff */
/*0290*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*02a0*/ IADD3 R20, R8, -0x80, RZ ; /* 0xffffff8008147810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*02c0*/ SHF.R.U32.HI R12, RZ, 0x5, R20 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011614 */
/*02d0*/ IMAD.U32 R8, RZ, RZ, UR8 ; /* 0x00000008ff087e24 */
/* 0x000fe4000f8e00ff */
/*02e0*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*02f0*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e9900 */
/*0300*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0320*/ ISETP.EQ.AND P0, PT, R22.reuse, RZ, PT ; /* 0x000000ff1600720c */
/* 0x040fe40003f02270 */
/*0330*/ ISETP.EQ.AND P5, PT, R22.reuse, 0x4, PT ; /* 0x000000041600780c */
/* 0x040fe20003fa2270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ ISETP.EQ.AND P4, PT, R22.reuse, 0x8, PT ; /* 0x000000081600780c */
/* 0x040fe40003f82270 */
/*0360*/ ISETP.EQ.AND P3, PT, R22.reuse, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x040fe40003f62270 */
/*0370*/ ISETP.EQ.AND P2, PT, R22, 0x10, PT ; /* 0x000000101600780c */
/* 0x000fc40003f42270 */
/*0380*/ ISETP.EQ.AND P1, PT, R22.reuse, 0x14, PT ; /* 0x000000141600780c */
/* 0x040fe40003f22270 */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R10, R8, R21, RZ ; /* 0x00000015080a7225 */
/* 0x004fca00078e00ff */
/*03b0*/ IADD3 R10, P6, R10, R13, RZ ; /* 0x0000000d0a0a7210 */
/* 0x000fc80007fde0ff */
/*03c0*/ IADD3.X R13, R11, UR4, RZ, P6, !PT ; /* 0x000000040b0d7c10 */
/* 0x000fe2000b7fe4ff */
/*03d0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R10.reuse ; /* 0x000000ffff060224 */
/* 0x100fe200078e000a */
/*03e0*/ ISETP.NE.AND P6, PT, R19, 0x6, PT ; /* 0x000000061300780c */
/* 0x000fe20003fc5270 */
/*03f0*/ @P4 IMAD.MOV.U32 R18, RZ, RZ, R10.reuse ; /* 0x000000ffff124224 */
/* 0x100fe200078e000a */
/*0400*/ @P5 MOV R17, R10 ; /* 0x0000000a00115202 */
/* 0x000fe20000000f00 */
/*0410*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R10.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e000a */
/*0420*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R10.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e000a */
/*0430*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff101224 */
/* 0x000fcc00078e000a */
/*0440*/ @P6 BRA 0x2d0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0450*/ IADD3 R8, -R12, 0x6, RZ ; /* 0x000000060c087810 */
/* 0x000fe20007ffe1ff */
/*0460*/ BSSY B1, 0x790 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.EQ.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f02270 */
/*0490*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x4, PT ; /* 0x000000040800780c */
/* 0x040fe40003f62270 */
/*04a0*/ ISETP.EQ.AND P4, PT, R8.reuse, 0x8, PT ; /* 0x000000080800780c */
/* 0x040fe40003f82270 */
/*04b0*/ ISETP.EQ.AND P2, PT, R8.reuse, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x040fe40003f42270 */
/*04c0*/ ISETP.EQ.AND P1, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fca0003f22270 */
/*04d0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R6.reuse ; /* 0x000000ffff090224 */
/* 0x100fe200078e0006 */
/*04e0*/ ISETP.EQ.AND P0, PT, R8.reuse, 0x14, PT ; /* 0x000000140800780c */
/* 0x040fe20003f02270 */
/*04f0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0006 */
/*0500*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R17.reuse ; /* 0x000000ffff093224 */
/* 0x100fe200078e0011 */
/*0510*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x18, PT ; /* 0x000000180800780c */
/* 0x040fe20003f62270 */
/*0520*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a4224 */
/* 0x000fe200078e0011 */
/*0530*/ @P2 MOV R10, R18 ; /* 0x00000012000a2202 */
/* 0x000fe20000000f00 */
/*0540*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff094224 */
/* 0x000fe200078e0012 */
/*0550*/ ISETP.EQ.AND P4, PT, R8, 0x1c, PT ; /* 0x0000001c0800780c */
/* 0x000fe20003f82270 */
/*0560*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff092224 */
/* 0x000fc400078e000e */
/*0570*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0580*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff091224 */
/* 0x000fe200078e000f */
/*0590*/ LOP3.LUT P1, R19, R20, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f14137812 */
/* 0x000fe2000782c0ff */
/*05a0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R16.reuse ; /* 0x000000ffff090224 */
/* 0x100fe400078e0010 */
/*05b0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff093224 */
/* 0x000fe400078e000d */
/*05c0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e000f */
/*05d0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a3224 */
/* 0x000fc400078e0010 */
/*05e0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e000d */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0009 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, -R12, 0x4, RZ ; /* 0x000000040c097810 */
/* 0x000fe40007ffe1ff */
/*0620*/ SHF.L.U32 R11, R8, R19.reuse, RZ ; /* 0x00000013080b7219 */
/* 0x080fe400000006ff */
/*0630*/ SHF.L.U32 R20, R10, R19, RZ ; /* 0x000000130a147219 */
/* 0x000fe200000006ff */
/*0640*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x000fca00078e00ff */
/*0650*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f02270 */
/*0660*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x4, PT ; /* 0x000000040900780c */
/* 0x040fe40003f22270 */
/*0670*/ ISETP.EQ.AND P2, PT, R9.reuse, 0x8, PT ; /* 0x000000080900780c */
/* 0x040fe40003f42270 */
/*0680*/ ISETP.EQ.AND P3, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fce0003f62270 */
/*0690*/ @P0 MOV R12, R6 ; /* 0x00000006000c0202 */
/* 0x000fe40000000f00 */
/*06a0*/ ISETP.EQ.AND P0, PT, R9.reuse, 0x10, PT ; /* 0x000000100900780c */
/* 0x040fe20003f02270 */
/*06b0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0011 */
/*06c0*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x14, PT ; /* 0x000000140900780c */
/* 0x040fe20003f22270 */
/*06d0*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c2224 */
/* 0x000fe200078e0012 */
/*06e0*/ ISETP.EQ.AND P2, PT, R9, 0x18, PT ; /* 0x000000180900780c */
/* 0x000fe20003f42270 */
/*06f0*/ @P3 IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c3224 */
/* 0x000fe200078e000e */
/*0700*/ IADD3 R9, -R19, 0x20, RZ ; /* 0x0000002013097810 */
/* 0x000fc80007ffe1ff */
/*0710*/ SHF.R.U32.HI R8, RZ, R9, R10 ; /* 0x00000009ff087219 */
/* 0x000fc6000001160a */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e000f */
/*0730*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e0010 */
/*0740*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c2224 */
/* 0x000fe400078e000d */
/*0750*/ IMAD.IADD R8, R8, 0x1, R11 ; /* 0x0000000108087824 */
/* 0x000fc600078e020b */
/*0760*/ SHF.R.U32.HI R9, RZ, R9, R12 ; /* 0x00000009ff097219 */
/* 0x000fca000001160c */
/*0770*/ IMAD.IADD R10, R9, 0x1, R20 ; /* 0x00000001090a7824 */
/* 0x000fe400078e0214 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ SHF.L.U32.HI R13, R10.reuse, 0x2, R8 ; /* 0x000000020a0d7819 */
/* 0x040fe20000010608 */
/*07a0*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT P1, R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fe4000782c0ff */
/*07c0*/ SHF.R.U32.HI R9, RZ, 0x1f, R13 ; /* 0x0000001fff097819 */
/* 0x000fc8000001160d */
/*07d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*07e0*/ LEA.HI R8, R8, R9, RZ, 0x2 ; /* 0x0000000908087211 */
/* 0x000fd600078f10ff */
/*07f0*/ @P0 LOP3.LUT R13, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff0d0212 */
/* 0x000fe400078e33ff */
/*0800*/ @P0 LOP3.LUT R12, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff0c0212 */
/* 0x000fe400078e33ff */
/*0810*/ @P0 LOP3.LUT R7, R7, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000007070812 */
/* 0x000fe400078e3cff */
/*0820*/ I2F.F64.S64 R10, R12 ; /* 0x0000000c000a7312 */
/* 0x000e240000301c00 */
/*0830*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0840*/ IADD3 R7, -R8, RZ, RZ ; /* 0x000000ff08077210 */
/* 0x000fca0007ffe1ff */
/*0850*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0007 */
/*0860*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*0870*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000301000 */
/*0880*/ FSEL R9, R10, -R10, !P0 ; /* 0x8000000a0a097208 */
/* 0x001fe20004000000 */
/*0890*/ BRA 0x8c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FMUL R9, RZ, R7 ; /* 0x00000007ff097220 */
/* 0x000fe40000400000 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R12, R8, 0x1, RZ ; /* 0x00000001080c7810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff087424 */
/* 0x000fe400078e00ff */
/*08f0*/ FMUL R13, R9, R9 ; /* 0x00000009090d7220 */
/* 0x000fe20000400000 */
/*0900*/ LOP3.LUT P1, RZ, R12.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010cff7812 */
/* 0x040fe2000782c0ff */
/*0910*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0b7424 */
/* 0x000fe200078e00ff */
/*0920*/ LOP3.LUT P0, RZ, R12, 0x2, RZ, 0xc0, !PT ; /* 0x000000020cff7812 */
/* 0x000fe2000780c0ff */
/*0930*/ IMAD.MOV.U32 R7, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff077424 */
/* 0x000fe200078e00ff */
/*0940*/ FSEL R8, R8, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb08087808 */
/* 0x000fc40004800000 */
/*0950*/ FSEL R9, R9, 1, !P1 ; /* 0x3f80000009097808 */
/* 0x000fce0004800000 */
/*0960*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff0a1424 */
/* 0x000fc800078e00ff */
/*0970*/ @P1 FFMA R7, R13, R10, -0.0013887860113754868507 ; /* 0xbab607ed0d071423 */
/* 0x000fe2000000000a */
/*0980*/ FSEL R10, -R11, -0.4999999701976776123, !P1 ; /* 0xbeffffff0b0a7808 */
/* 0x000fc60004800100 */
/*0990*/ FFMA R7, R13, R7, R8 ; /* 0x000000070d077223 */
/* 0x000fe40000000008 */
/*09a0*/ FFMA R8, R9, R13, RZ ; /* 0x0000000d09087223 */
/* 0x000fe400000000ff */
/*09b0*/ FFMA R7, R13, R7, R10 ; /* 0x000000070d077223 */
/* 0x000fc8000000000a */
/*09c0*/ FFMA R7, R7, R8, R9 ; /* 0x0000000807077223 */
/* 0x000fe40000000009 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*09e0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fe400000000ff */
/*09f0*/ IMAD R8, R9, c[0x0][0xc], R4 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0204 */
/*0a00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101906 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, R8.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0008 */
/*0a20*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0a30*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0a40*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0a50*/ @!P0 BRA 0xf0 ; /* 0xfffff69000008947 */
/* 0x001fea000383ffff */
/*0a60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a70*/ BRA 0xa70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3CosPfmmf
.globl _Z3CosPfmmf
.p2align 8
.type _Z3CosPfmmf,@function
_Z3CosPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[5:6], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_cmpx_gt_u64_e64 s[2:3], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s6, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s5, s6, s5
s_mul_i32 s0, s0, s2
s_add_i32 s1, s5, s1
s_mov_b32 s10, 0xb94c1982
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s11, 0x37d75334
s_add_u32 s5, s8, s0
s_addc_u32 s6, s9, s1
s_add_i32 s15, s15, s12
s_mov_b32 s8, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_mul_i32 s7, s12, s7
s_mov_b32 s9, 0x7fffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v6, v2, v2 :: v_dual_and_b32 v9, 1, v5
v_cmp_class_f32_e64 s0, v0, 0x1f8
v_lshlrev_b32_e32 v5, 30, v5
v_fmaak_f32 v7, s10, v6, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_dual_fmaak_f32 v8, s11, v6, 0xbab64f3b :: v_dual_mul_f32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
v_fmac_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbf000004
v_fma_f32 v6, v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, -v2, v6, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_xor_b32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
v_add_nc_u32_e32 v1, s7, v1
s_or_b32 s8, vcc_lo, s8
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s5, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s6, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s12, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v2, 0x7fffffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v15, v2, s9, 0x800000
v_lshrrev_b32_e32 v2, 23, v2
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0xffffff88, v2
v_cmp_lt_u32_e32 vcc_lo, 63, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v13, v2
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v2
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
v_add_nc_u32_e32 v2, v14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
v_cmp_lt_u32_e64 s1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v11
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v12
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v13
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v12, v10, vcc_lo
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
v_cndmask_b32_e32 v6, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, v13, v7, s0
v_cndmask_b32_e64 v10, v12, v13, s0
v_cndmask_b32_e64 v7, v7, v11, s0
v_sub_nc_u32_e32 v12, 32, v2
v_cndmask_b32_e64 v11, v11, v6, s0
v_cndmask_b32_e64 v5, v6, v5, s0
v_cndmask_b32_e64 v10, v10, v8, s1
v_cndmask_b32_e64 v8, v8, v7, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v7, v11, s1
v_cndmask_b32_e64 v5, v11, v5, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v10, v8, v12
v_alignbit_b32 v9, v8, v7, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v7, v5, v12
v_cndmask_b32_e32 v2, v13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v9, v8 :: v_dual_cndmask_b32 v7, v11, v7
v_bfe_u32 v8, v2, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v2, v6, 30
v_alignbit_b32 v6, v6, v7, 30
v_alignbit_b32 v5, v7, v5, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, 0, v8
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v6, v6, v10
v_xor_b32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v11, v9
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v5, v6, v5, v7
v_lshrrev_b32_e32 v7, 29, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v6, v9, v5, 9
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v10, v6
v_or_b32_e32 v12, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v10, 32, v10
v_sub_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, 31, v10
v_alignbit_b32 v5, v6, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
v_lshrrev_b32_e32 v5, 9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, 0x3fc90fda, v6
v_sub_nc_u32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v6, 0x3fc90fda, -v10
v_add_nc_u32_e32 v5, 0x33000000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0x33a22168, v6
v_or_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0x3fc90fda, v5
v_lshrrev_b32_e32 v5, 30, v2
v_add_f32_e32 v2, v10, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v5, v8, v5
.LBB0_5:
s_and_not1_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v2, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v2
v_fma_f32 v2, v5, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0xb3a22168, v5
v_fmac_f32_e32 v2, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v5, v5
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3CosPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3CosPfmmf, .Lfunc_end0-_Z3CosPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3CosPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3CosPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009cab7_00000000-6_Cos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3CosPfmmfPfmmf
.type _Z25__device_stub__Z3CosPfmmfPfmmf, @function
_Z25__device_stub__Z3CosPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3CosPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3CosPfmmfPfmmf, .-_Z25__device_stub__Z3CosPfmmfPfmmf
.globl _Z3CosPfmmf
.type _Z3CosPfmmf, @function
_Z3CosPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3CosPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3CosPfmmf, .-_Z3CosPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3CosPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3CosPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Cos.hip"
.globl _Z18__device_stub__CosPfmmf # -- Begin function _Z18__device_stub__CosPfmmf
.p2align 4, 0x90
.type _Z18__device_stub__CosPfmmf,@function
_Z18__device_stub__CosPfmmf: # @_Z18__device_stub__CosPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3CosPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__CosPfmmf, .Lfunc_end0-_Z18__device_stub__CosPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3CosPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3CosPfmmf,@object # @_Z3CosPfmmf
.section .rodata,"a",@progbits
.globl _Z3CosPfmmf
.p2align 3, 0x0
_Z3CosPfmmf:
.quad _Z18__device_stub__CosPfmmf
.size _Z3CosPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3CosPfmmf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__CosPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3CosPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //============================================================================
// Name : Unordered Reduction.cpp
// Author :
// Version :
// Copyright :
// Description : Test of the segment add plug-in
//============================================================================
#include <cuda_runtime.h>
#include <iostream>
#include <string>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include <limits>
#include <algorithm>
#include <limits>
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define PER_THREAD_INIT_NUM 1
#define PER_THREAD_SEG_NUM 32
#define ARRAY_SIZE (1024 * 1024 * 32)
#define MAX_NUM 4
#define THREAD_NUM 1024
#define SEGMENT_NUM 512
typedef int operand_type;
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value == false, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
atomicAdd(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicAdd(addr_temp, value_temp);
}
template <typename T>
struct SumOp {
__device__ void operator()(T *addr, T value) {
SumOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value > __uint_as_float(value_assumed) ? value : __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value > __longlong_as_double(value_assumed) ? value : __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, unsigned int>::value || std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int>::value || std::is_same<T, long long int>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
atomicMax(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicMax(addr_temp, value_temp);
}
template <typename T>
struct MaxOp {
__device__ void operator()(T *addr, T value) {
MaxOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value * __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, int>::value || std::is_same<T, unsigned int>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
(value * value_assumed));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value * __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, long long int>::value ||
std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
((unsigned long long int)value * value_assumed));
} while (value_assumed != value_old);
}
template <typename T>
struct MulOp {
__device__ void operator()(T *addr, T value) {
MulOpByType(addr, value);
}
};
template <typename T>
__global__ void InitValue(T *input, int total_size, T value) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < value) {
int split_size = total_size / PER_THREAD_INIT_NUM;
#pragma unroll
for (int i = 0; i < PER_THREAD_INIT_NUM; i++) {
input[i * split_size + index] = value;
}
}
}
template <typename ReductionF, typename T>
__global__ void Segmentation(T *__restrict__ input_data,
int *__restrict__ input_segment_id,
T *__restrict__ output_segment_result,
int segment_result_size,
int total_size,
T initial_value) {
extern __shared__ int segment_result_slm_shared[];
T *segment_result_slm = (T *)segment_result_slm_shared;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int split_size = total_size / PER_THREAD_SEG_NUM;
int local_index = threadIdx.x;
int local_size = blockDim.x;
int loop_slm = (segment_result_size + local_size - 1) / local_size;
if (index < total_size) {
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
segment_result_slm[slm_index] = initial_value;
}
}
__syncthreads();
#pragma unroll
for (int i = 0; i < PER_THREAD_SEG_NUM; i++) {
int split_index = index + split_size * i;
if (split_index < total_size) {
int segment_id = input_segment_id[split_index];
T data_value = input_data[split_index];
ReductionF()(segment_result_slm + segment_id, data_value);
}
}
__syncthreads();
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
if (slm_index < segment_result_size) {
ReductionF()(output_segment_result + slm_index, segment_result_slm[slm_index]);
}
}
}
}
}
int main(int argc, char **argv) {
operand_type *input_data = nullptr;
int *input_segment_id = nullptr;
operand_type *output_segment_result = nullptr;
operand_type *input_data_cpu = nullptr;
int *input_segment_id_cpu = nullptr;
operand_type *output_segment_result_cpu = nullptr;
operand_type *output_segment_result_gold = nullptr;
int array_num = ARRAY_SIZE;
int segment_num = SEGMENT_NUM;
int thread_num = THREAD_NUM;
float time = 0.0f;
int initial_value = 0;
cudaEvent_t event1, event2;
std::srand(std::time(nullptr));
int dev = cudaSetDevice(0);
CUDA_CHECK_RETURN(cudaMalloc((void **)&input_data, array_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(cudaMalloc((void **)&input_segment_id, array_num * sizeof(int)));
CUDA_CHECK_RETURN(cudaMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(cudaEventCreate(&event1));
CUDA_CHECK_RETURN(cudaEventCreate(&event2));
if ((input_data_cpu = new operand_type[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((input_segment_id_cpu = new int[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_cpu = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_gold = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
// Initialize array
for (int i = 0; i < array_num; i++) {
input_data_cpu[i] = (float)rand() / RAND_MAX + 1.0f;
}
CUDA_CHECK_RETURN(cudaMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), cudaMemcpyHostToDevice));
for (int i = 0; i < array_num; i++) {
input_segment_id_cpu[i] = rand() % segment_num;
}
CUDA_CHECK_RETURN(cudaMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
InitValue<operand_type><<<1, segment_num / PER_THREAD_INIT_NUM>>>(output_segment_result, segment_num, initial_value);
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Kernel InitValue Execution time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
int block_num = (array_num + PER_THREAD_SEG_NUM * thread_num - 1) / (PER_THREAD_SEG_NUM * thread_num);
Segmentation<SumOp<operand_type>, operand_type><<<block_num, thread_num, segment_num * sizeof(operand_type)>>>(input_data, input_segment_id, output_segment_result, segment_num, array_num, initial_value);
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Kernel Segmentation Reduction time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
CUDA_CHECK_RETURN(cudaMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), cudaMemcpyDeviceToHost));
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Memory copy time: " << time << " ms" << std::endl;
// compute and compare gold
for (int i = 0; i < segment_num; i++) {
output_segment_result_gold[i] = initial_value;
}
clock_t begin_clock = std::clock();
// sum reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] += input_data_cpu[i];
}
// max reduction
/*
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] = output_segment_result_gold[input_segment_id_cpu[i]] > input_data_cpu[i] ? output_segment_result_gold[input_segment_id_cpu[i]] : input_data_cpu[i];
}
*/
/*
// mul reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] *= input_data_cpu[i];
}
*/
clock_t end_clock = std::clock();
double elapsed_cpu = double(end_clock - begin_clock) / CLOCKS_PER_SEC * 1000.0;
std::cout << "CPU reduction time " << elapsed_cpu << " ms" << std::endl;
for (int i = 0; i < segment_num; i++) {
std::cout << "gpu result: " << output_segment_result_cpu[i] << " gold result: " << output_segment_result_gold[i] << std::endl;
if ((output_segment_result_cpu[i] != output_segment_result_gold[i])) {
std::cout << "Error comparing with Gold! " << "Position " << i << std::endl;
return -1;
}
}
std::cout << "Test passed! " << std::endl;
// clean up
if (input_data_cpu != nullptr) {
delete[] input_data_cpu;
}
if (input_segment_id_cpu != nullptr) {
delete[] input_segment_id_cpu;
}
if (output_segment_result_cpu != nullptr) {
delete[] output_segment_result_cpu;
}
if (output_segment_result_gold != nullptr) {
delete[] output_segment_result_gold;
}
cudaFree(output_segment_result);
cudaFree(input_segment_id);
cudaFree(input_data);
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .file "tmpxft_000e5cd7_00000000-6_Test_Cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z9InitValueIiEvPT_iS0_,"axG",@progbits,_Z9InitValueIiEvPT_iS0_,comdat
.weak _Z9InitValueIiEvPT_iS0_
.type _Z9InitValueIiEvPT_iS0_, @function
_Z9InitValueIiEvPT_iS0_:
.LFB4274:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, (%rsp)
movl %edx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9InitValueIiEvPT_iS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4274:
.size _Z9InitValueIiEvPT_iS0_, .-_Z9InitValueIiEvPT_iS0_
.section .text._Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,"axG",@progbits,_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,comdat
.weak _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.type _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, @function
_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_:
.LFB4276:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl %ecx, 12(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 20(%rsp)
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4276:
.size _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, .-_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3941:
.cfi_startproc
testl %ecx, %ecx
jne .L19
ret
.L19:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3941:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3944:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3944:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "cudaMalloc((void **)&input_data, array_num * sizeof(operand_type))"
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/zh7i/test/master/Test_Cuda/src/Test_Cuda.cu"
.align 8
.LC7:
.string "cudaMalloc((void **)&input_segment_id, array_num * sizeof(int))"
.align 8
.LC8:
.string "cudaMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type))"
.section .rodata.str1.1
.LC9:
.string "cudaEventCreate(&event1)"
.LC10:
.string "cudaEventCreate(&event2)"
.section .rodata.str1.8
.align 8
.LC13:
.string "cudaMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), cudaMemcpyHostToDevice)"
.align 8
.LC14:
.string "cudaMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), cudaMemcpyHostToDevice)"
.section .rodata.str1.1
.LC15:
.string "cudaEventRecord(event1, 0)"
.LC16:
.string "cudaEventRecord(event2, 0)"
.LC17:
.string "cudaEventSynchronize(event2)"
.section .rodata.str1.8
.align 8
.LC18:
.string "cudaEventElapsedTime(&time, event1, event2)"
.align 8
.LC19:
.string "Kernel InitValue Execution time "
.section .rodata.str1.1
.LC20:
.string " ms"
.section .rodata.str1.8
.align 8
.LC21:
.string "Kernel Segmentation Reduction time "
.align 8
.LC22:
.string "cudaMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC23:
.string "Memory copy time: "
.LC26:
.string "CPU reduction time "
.LC27:
.string "gpu result: "
.LC28:
.string " gold result: "
.LC29:
.string "Error comparing with Gold! "
.LC30:
.string "Position "
.LC31:
.string "Test passed! "
.text
.globl main
.type main, @function
main:
.LFB3940:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl $0x00000000, 20(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq 24(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $248, %esi
leaq .LC6(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 32(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $249, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 40(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $250, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $252, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $253, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r12
movl $134217728, %edi
call _Znam@PLT
movq %rax, %rbp
movl $2048, %edi
call _Znam@PLT
movq %rax, (%rsp)
movl $2048, %edi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %r13
leaq 134217728(%r12), %r14
.L23:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC11(%rip), %xmm0
addss .LC12(%rip), %xmm0
cvttss2sil %xmm0, %eax
movl %eax, 0(%r13)
addq $4, %r13
cmpq %r14, %r13
jne .L23
movl $1, %ecx
movl $134217728, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $276, %esi
leaq .LC6(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq %rbp, %r13
leaq 134217728(%rbp), %r14
.L24:
call rand@PLT
cltd
shrl $23, %edx
addl %edx, %eax
andl $511, %eax
subl %edx, %eax
movl %eax, 0(%r13)
addq $4, %r13
cmpq %r14, %r13
jne .L24
movl $1, %ecx
movl $134217728, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC14(%rip), %rdx
movl $281, %esi
leaq .LC6(%rip), %r13
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
leaq .LC15(%rip), %rdx
movl $284, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $512, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L25:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
leaq .LC16(%rip), %rdx
movl $287, %esi
leaq .LC6(%rip), %r13
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $289, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ecx
leaq .LC18(%rip), %rdx
movl $290, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
leaq .LC15(%rip), %rdx
movl $295, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $2048, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L26:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
leaq .LC16(%rip), %r15
movq %r15, %rdx
movl $298, %esi
leaq .LC6(%rip), %r13
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $300, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 20(%rsp), %r14
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl %eax, %ecx
leaq .LC18(%rip), %rdx
movl $301, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
leaq .LC15(%rip), %rdx
movl $305, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $2, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC22(%rip), %rdx
movl $306, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ecx
movq %r15, %rdx
movl $307, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $309, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl %eax, %ecx
leaq .LC18(%rip), %rdx
movl $310, %esi
movq %r13, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rax
leaq 2048(%rbx), %rdx
.L27:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L27
call clock@PLT
movq %rax, %r13
movl $0, %eax
.L28:
movslq 0(%rbp,%rax), %rdx
movl (%r12,%rax), %ecx
addl %ecx, (%rbx,%rdx,4)
addq $4, %rax
cmpq $134217728, %rax
jne .L28
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC24(%rip), %xmm0
mulsd .LC25(%rip), %xmm0
movq %xmm0, %r13
leaq .LC26(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
jmp .L35
.L43:
movl $0, %edx
movl $512, %esi
movq 40(%rsp), %rdi
call _Z9InitValueIiEvPT_iS0_
jmp .L25
.L44:
movl $0, %r9d
movl $33554432, %r8d
movl $512, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
jmp .L26
.L48:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L32:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%rsp), %rax
movl 12(%rsp), %esi
cmpl (%rax,%r13,4), %esi
jne .L46
addq $1, %r13
cmpq $512, %r13
je .L47
.L35:
movl $12, %edx
leaq .LC27(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rsp), %rax
movl (%rax,%r13,4), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movl $14, %edx
leaq .LC28(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%rbx,%r13,4), %eax
movl %eax, 12(%rsp)
movl %eax, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L48
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
jmp .L32
.L46:
leaq .LC29(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC30(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
.L22:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L49
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC31(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L22
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3940:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC32:
.string "_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_"
.section .rodata.str1.1
.LC33:
.string "_Z9InitValueIiEvPT_iS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3971:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _Z9InitValueIiEvPT_iS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3971:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 805306368
.align 4
.LC12:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC24:
.long 0
.long 1093567616
.align 8
.LC25:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //============================================================================
// Name : Unordered Reduction.cpp
// Author :
// Version :
// Copyright :
// Description : Test of the segment add plug-in
//============================================================================
#include <cuda_runtime.h>
#include <iostream>
#include <string>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include <limits>
#include <algorithm>
#include <limits>
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define PER_THREAD_INIT_NUM 1
#define PER_THREAD_SEG_NUM 32
#define ARRAY_SIZE (1024 * 1024 * 32)
#define MAX_NUM 4
#define THREAD_NUM 1024
#define SEGMENT_NUM 512
typedef int operand_type;
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value == false, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
atomicAdd(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicAdd(addr_temp, value_temp);
}
template <typename T>
struct SumOp {
__device__ void operator()(T *addr, T value) {
SumOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value > __uint_as_float(value_assumed) ? value : __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value > __longlong_as_double(value_assumed) ? value : __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, unsigned int>::value || std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int>::value || std::is_same<T, long long int>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
atomicMax(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicMax(addr_temp, value_temp);
}
template <typename T>
struct MaxOp {
__device__ void operator()(T *addr, T value) {
MaxOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value * __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, int>::value || std::is_same<T, unsigned int>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
(value * value_assumed));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value * __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, long long int>::value ||
std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
((unsigned long long int)value * value_assumed));
} while (value_assumed != value_old);
}
template <typename T>
struct MulOp {
__device__ void operator()(T *addr, T value) {
MulOpByType(addr, value);
}
};
template <typename T>
__global__ void InitValue(T *input, int total_size, T value) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < value) {
int split_size = total_size / PER_THREAD_INIT_NUM;
#pragma unroll
for (int i = 0; i < PER_THREAD_INIT_NUM; i++) {
input[i * split_size + index] = value;
}
}
}
template <typename ReductionF, typename T>
__global__ void Segmentation(T *__restrict__ input_data,
int *__restrict__ input_segment_id,
T *__restrict__ output_segment_result,
int segment_result_size,
int total_size,
T initial_value) {
extern __shared__ int segment_result_slm_shared[];
T *segment_result_slm = (T *)segment_result_slm_shared;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int split_size = total_size / PER_THREAD_SEG_NUM;
int local_index = threadIdx.x;
int local_size = blockDim.x;
int loop_slm = (segment_result_size + local_size - 1) / local_size;
if (index < total_size) {
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
segment_result_slm[slm_index] = initial_value;
}
}
__syncthreads();
#pragma unroll
for (int i = 0; i < PER_THREAD_SEG_NUM; i++) {
int split_index = index + split_size * i;
if (split_index < total_size) {
int segment_id = input_segment_id[split_index];
T data_value = input_data[split_index];
ReductionF()(segment_result_slm + segment_id, data_value);
}
}
__syncthreads();
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
if (slm_index < segment_result_size) {
ReductionF()(output_segment_result + slm_index, segment_result_slm[slm_index]);
}
}
}
}
}
int main(int argc, char **argv) {
operand_type *input_data = nullptr;
int *input_segment_id = nullptr;
operand_type *output_segment_result = nullptr;
operand_type *input_data_cpu = nullptr;
int *input_segment_id_cpu = nullptr;
operand_type *output_segment_result_cpu = nullptr;
operand_type *output_segment_result_gold = nullptr;
int array_num = ARRAY_SIZE;
int segment_num = SEGMENT_NUM;
int thread_num = THREAD_NUM;
float time = 0.0f;
int initial_value = 0;
cudaEvent_t event1, event2;
std::srand(std::time(nullptr));
int dev = cudaSetDevice(0);
CUDA_CHECK_RETURN(cudaMalloc((void **)&input_data, array_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(cudaMalloc((void **)&input_segment_id, array_num * sizeof(int)));
CUDA_CHECK_RETURN(cudaMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(cudaEventCreate(&event1));
CUDA_CHECK_RETURN(cudaEventCreate(&event2));
if ((input_data_cpu = new operand_type[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((input_segment_id_cpu = new int[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_cpu = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_gold = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
// Initialize array
for (int i = 0; i < array_num; i++) {
input_data_cpu[i] = (float)rand() / RAND_MAX + 1.0f;
}
CUDA_CHECK_RETURN(cudaMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), cudaMemcpyHostToDevice));
for (int i = 0; i < array_num; i++) {
input_segment_id_cpu[i] = rand() % segment_num;
}
CUDA_CHECK_RETURN(cudaMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
InitValue<operand_type><<<1, segment_num / PER_THREAD_INIT_NUM>>>(output_segment_result, segment_num, initial_value);
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Kernel InitValue Execution time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
int block_num = (array_num + PER_THREAD_SEG_NUM * thread_num - 1) / (PER_THREAD_SEG_NUM * thread_num);
Segmentation<SumOp<operand_type>, operand_type><<<block_num, thread_num, segment_num * sizeof(operand_type)>>>(input_data, input_segment_id, output_segment_result, segment_num, array_num, initial_value);
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Kernel Segmentation Reduction time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(cudaEventRecord(event1, 0));
CUDA_CHECK_RETURN(cudaMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), cudaMemcpyDeviceToHost));
CUDA_CHECK_RETURN(cudaEventRecord(event2, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(event2));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&time, event1, event2));
std::cout << "Memory copy time: " << time << " ms" << std::endl;
// compute and compare gold
for (int i = 0; i < segment_num; i++) {
output_segment_result_gold[i] = initial_value;
}
clock_t begin_clock = std::clock();
// sum reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] += input_data_cpu[i];
}
// max reduction
/*
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] = output_segment_result_gold[input_segment_id_cpu[i]] > input_data_cpu[i] ? output_segment_result_gold[input_segment_id_cpu[i]] : input_data_cpu[i];
}
*/
/*
// mul reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] *= input_data_cpu[i];
}
*/
clock_t end_clock = std::clock();
double elapsed_cpu = double(end_clock - begin_clock) / CLOCKS_PER_SEC * 1000.0;
std::cout << "CPU reduction time " << elapsed_cpu << " ms" << std::endl;
for (int i = 0; i < segment_num; i++) {
std::cout << "gpu result: " << output_segment_result_cpu[i] << " gold result: " << output_segment_result_gold[i] << std::endl;
if ((output_segment_result_cpu[i] != output_segment_result_gold[i])) {
std::cout << "Error comparing with Gold! " << "Position " << i << std::endl;
return -1;
}
}
std::cout << "Test passed! " << std::endl;
// clean up
if (input_data_cpu != nullptr) {
delete[] input_data_cpu;
}
if (input_segment_id_cpu != nullptr) {
delete[] input_segment_id_cpu;
}
if (output_segment_result_cpu != nullptr) {
delete[] output_segment_result_cpu;
}
if (output_segment_result_gold != nullptr) {
delete[] output_segment_result_gold;
}
cudaFree(output_segment_result);
cudaFree(input_segment_id);
cudaFree(input_data);
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | //============================================================================
// Name : Unordered Reduction.cpp
// Author :
// Version :
// Copyright :
// Description : Test of the segment add plug-in
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include <limits>
#include <algorithm>
#include <limits>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define PER_THREAD_INIT_NUM 1
#define PER_THREAD_SEG_NUM 32
#define ARRAY_SIZE (1024 * 1024 * 32)
#define MAX_NUM 4
#define THREAD_NUM 1024
#define SEGMENT_NUM 512
typedef int operand_type;
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value == false, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
atomicAdd(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicAdd(addr_temp, value_temp);
}
template <typename T>
struct SumOp {
__device__ void operator()(T *addr, T value) {
SumOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value > __uint_as_float(value_assumed) ? value : __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value > __longlong_as_double(value_assumed) ? value : __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, unsigned int>::value || std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int>::value || std::is_same<T, long long int>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
atomicMax(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicMax(addr_temp, value_temp);
}
template <typename T>
struct MaxOp {
__device__ void operator()(T *addr, T value) {
MaxOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value * __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, int>::value || std::is_same<T, unsigned int>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
(value * value_assumed));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value * __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, long long int>::value ||
std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
((unsigned long long int)value * value_assumed));
} while (value_assumed != value_old);
}
template <typename T>
struct MulOp {
__device__ void operator()(T *addr, T value) {
MulOpByType(addr, value);
}
};
template <typename T>
__global__ void InitValue(T *input, int total_size, T value) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < value) {
int split_size = total_size / PER_THREAD_INIT_NUM;
#pragma unroll
for (int i = 0; i < PER_THREAD_INIT_NUM; i++) {
input[i * split_size + index] = value;
}
}
}
template <typename ReductionF, typename T>
__global__ void Segmentation(T *__restrict__ input_data,
int *__restrict__ input_segment_id,
T *__restrict__ output_segment_result,
int segment_result_size,
int total_size,
T initial_value) {
extern __shared__ int segment_result_slm_shared[];
T *segment_result_slm = (T *)segment_result_slm_shared;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int split_size = total_size / PER_THREAD_SEG_NUM;
int local_index = threadIdx.x;
int local_size = blockDim.x;
int loop_slm = (segment_result_size + local_size - 1) / local_size;
if (index < total_size) {
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
segment_result_slm[slm_index] = initial_value;
}
}
__syncthreads();
#pragma unroll
for (int i = 0; i < PER_THREAD_SEG_NUM; i++) {
int split_index = index + split_size * i;
if (split_index < total_size) {
int segment_id = input_segment_id[split_index];
T data_value = input_data[split_index];
ReductionF()(segment_result_slm + segment_id, data_value);
}
}
__syncthreads();
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
if (slm_index < segment_result_size) {
ReductionF()(output_segment_result + slm_index, segment_result_slm[slm_index]);
}
}
}
}
}
int main(int argc, char **argv) {
operand_type *input_data = nullptr;
int *input_segment_id = nullptr;
operand_type *output_segment_result = nullptr;
operand_type *input_data_cpu = nullptr;
int *input_segment_id_cpu = nullptr;
operand_type *output_segment_result_cpu = nullptr;
operand_type *output_segment_result_gold = nullptr;
int array_num = ARRAY_SIZE;
int segment_num = SEGMENT_NUM;
int thread_num = THREAD_NUM;
float time = 0.0f;
int initial_value = 0;
hipEvent_t event1, event2;
std::srand(std::time(nullptr));
int dev = hipSetDevice(0);
CUDA_CHECK_RETURN(hipMalloc((void **)&input_data, array_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipMalloc((void **)&input_segment_id, array_num * sizeof(int)));
CUDA_CHECK_RETURN(hipMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipEventCreate(&event1));
CUDA_CHECK_RETURN(hipEventCreate(&event2));
if ((input_data_cpu = new operand_type[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((input_segment_id_cpu = new int[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_cpu = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_gold = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
// Initialize array
for (int i = 0; i < array_num; i++) {
input_data_cpu[i] = (float)rand() / RAND_MAX + 1.0f;
}
CUDA_CHECK_RETURN(hipMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), hipMemcpyHostToDevice));
for (int i = 0; i < array_num; i++) {
input_segment_id_cpu[i] = rand() % segment_num;
}
CUDA_CHECK_RETURN(hipMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
InitValue<operand_type><<<1, segment_num / PER_THREAD_INIT_NUM>>>(output_segment_result, segment_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel InitValue Execution time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
int block_num = (array_num + PER_THREAD_SEG_NUM * thread_num - 1) / (PER_THREAD_SEG_NUM * thread_num);
Segmentation<SumOp<operand_type>, operand_type><<<block_num, thread_num, segment_num * sizeof(operand_type)>>>(input_data, input_segment_id, output_segment_result, segment_num, array_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel Segmentation Reduction time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
CUDA_CHECK_RETURN(hipMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Memory copy time: " << time << " ms" << std::endl;
// compute and compare gold
for (int i = 0; i < segment_num; i++) {
output_segment_result_gold[i] = initial_value;
}
clock_t begin_clock = std::clock();
// sum reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] += input_data_cpu[i];
}
// max reduction
/*
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] = output_segment_result_gold[input_segment_id_cpu[i]] > input_data_cpu[i] ? output_segment_result_gold[input_segment_id_cpu[i]] : input_data_cpu[i];
}
*/
/*
// mul reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] *= input_data_cpu[i];
}
*/
clock_t end_clock = std::clock();
double elapsed_cpu = double(end_clock - begin_clock) / CLOCKS_PER_SEC * 1000.0;
std::cout << "CPU reduction time " << elapsed_cpu << " ms" << std::endl;
for (int i = 0; i < segment_num; i++) {
std::cout << "gpu result: " << output_segment_result_cpu[i] << " gold result: " << output_segment_result_gold[i] << std::endl;
if ((output_segment_result_cpu[i] != output_segment_result_gold[i])) {
std::cout << "Error comparing with Gold! " << "Position " << i << std::endl;
return -1;
}
}
std::cout << "Test passed! " << std::endl;
// clean up
if (input_data_cpu != nullptr) {
delete[] input_data_cpu;
}
if (input_segment_id_cpu != nullptr) {
delete[] input_segment_id_cpu;
}
if (output_segment_result_cpu != nullptr) {
delete[] output_segment_result_cpu;
}
if (output_segment_result_gold != nullptr) {
delete[] output_segment_result_gold;
}
hipFree(output_segment_result);
hipFree(input_segment_id);
hipFree(input_data);
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //============================================================================
// Name : Unordered Reduction.cpp
// Author :
// Version :
// Copyright :
// Description : Test of the segment add plug-in
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include <limits>
#include <algorithm>
#include <limits>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define PER_THREAD_INIT_NUM 1
#define PER_THREAD_SEG_NUM 32
#define ARRAY_SIZE (1024 * 1024 * 32)
#define MAX_NUM 4
#define THREAD_NUM 1024
#define SEGMENT_NUM 512
typedef int operand_type;
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value == false, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
atomicAdd(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicAdd(addr_temp, value_temp);
}
template <typename T>
struct SumOp {
__device__ void operator()(T *addr, T value) {
SumOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value > __uint_as_float(value_assumed) ? value : __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value > __longlong_as_double(value_assumed) ? value : __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, unsigned int>::value || std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int>::value || std::is_same<T, long long int>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
atomicMax(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicMax(addr_temp, value_temp);
}
template <typename T>
struct MaxOp {
__device__ void operator()(T *addr, T value) {
MaxOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value * __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, int>::value || std::is_same<T, unsigned int>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
(value * value_assumed));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value * __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, long long int>::value ||
std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
((unsigned long long int)value * value_assumed));
} while (value_assumed != value_old);
}
template <typename T>
struct MulOp {
__device__ void operator()(T *addr, T value) {
MulOpByType(addr, value);
}
};
template <typename T>
__global__ void InitValue(T *input, int total_size, T value) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < value) {
int split_size = total_size / PER_THREAD_INIT_NUM;
#pragma unroll
for (int i = 0; i < PER_THREAD_INIT_NUM; i++) {
input[i * split_size + index] = value;
}
}
}
template <typename ReductionF, typename T>
__global__ void Segmentation(T *__restrict__ input_data,
int *__restrict__ input_segment_id,
T *__restrict__ output_segment_result,
int segment_result_size,
int total_size,
T initial_value) {
extern __shared__ int segment_result_slm_shared[];
T *segment_result_slm = (T *)segment_result_slm_shared;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int split_size = total_size / PER_THREAD_SEG_NUM;
int local_index = threadIdx.x;
int local_size = blockDim.x;
int loop_slm = (segment_result_size + local_size - 1) / local_size;
if (index < total_size) {
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
segment_result_slm[slm_index] = initial_value;
}
}
__syncthreads();
#pragma unroll
for (int i = 0; i < PER_THREAD_SEG_NUM; i++) {
int split_index = index + split_size * i;
if (split_index < total_size) {
int segment_id = input_segment_id[split_index];
T data_value = input_data[split_index];
ReductionF()(segment_result_slm + segment_id, data_value);
}
}
__syncthreads();
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
if (slm_index < segment_result_size) {
ReductionF()(output_segment_result + slm_index, segment_result_slm[slm_index]);
}
}
}
}
}
int main(int argc, char **argv) {
operand_type *input_data = nullptr;
int *input_segment_id = nullptr;
operand_type *output_segment_result = nullptr;
operand_type *input_data_cpu = nullptr;
int *input_segment_id_cpu = nullptr;
operand_type *output_segment_result_cpu = nullptr;
operand_type *output_segment_result_gold = nullptr;
int array_num = ARRAY_SIZE;
int segment_num = SEGMENT_NUM;
int thread_num = THREAD_NUM;
float time = 0.0f;
int initial_value = 0;
hipEvent_t event1, event2;
std::srand(std::time(nullptr));
int dev = hipSetDevice(0);
CUDA_CHECK_RETURN(hipMalloc((void **)&input_data, array_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipMalloc((void **)&input_segment_id, array_num * sizeof(int)));
CUDA_CHECK_RETURN(hipMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipEventCreate(&event1));
CUDA_CHECK_RETURN(hipEventCreate(&event2));
if ((input_data_cpu = new operand_type[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((input_segment_id_cpu = new int[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_cpu = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_gold = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
// Initialize array
for (int i = 0; i < array_num; i++) {
input_data_cpu[i] = (float)rand() / RAND_MAX + 1.0f;
}
CUDA_CHECK_RETURN(hipMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), hipMemcpyHostToDevice));
for (int i = 0; i < array_num; i++) {
input_segment_id_cpu[i] = rand() % segment_num;
}
CUDA_CHECK_RETURN(hipMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
InitValue<operand_type><<<1, segment_num / PER_THREAD_INIT_NUM>>>(output_segment_result, segment_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel InitValue Execution time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
int block_num = (array_num + PER_THREAD_SEG_NUM * thread_num - 1) / (PER_THREAD_SEG_NUM * thread_num);
Segmentation<SumOp<operand_type>, operand_type><<<block_num, thread_num, segment_num * sizeof(operand_type)>>>(input_data, input_segment_id, output_segment_result, segment_num, array_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel Segmentation Reduction time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
CUDA_CHECK_RETURN(hipMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Memory copy time: " << time << " ms" << std::endl;
// compute and compare gold
for (int i = 0; i < segment_num; i++) {
output_segment_result_gold[i] = initial_value;
}
clock_t begin_clock = std::clock();
// sum reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] += input_data_cpu[i];
}
// max reduction
/*
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] = output_segment_result_gold[input_segment_id_cpu[i]] > input_data_cpu[i] ? output_segment_result_gold[input_segment_id_cpu[i]] : input_data_cpu[i];
}
*/
/*
// mul reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] *= input_data_cpu[i];
}
*/
clock_t end_clock = std::clock();
double elapsed_cpu = double(end_clock - begin_clock) / CLOCKS_PER_SEC * 1000.0;
std::cout << "CPU reduction time " << elapsed_cpu << " ms" << std::endl;
for (int i = 0; i < segment_num; i++) {
std::cout << "gpu result: " << output_segment_result_cpu[i] << " gold result: " << output_segment_result_gold[i] << std::endl;
if ((output_segment_result_cpu[i] != output_segment_result_gold[i])) {
std::cout << "Error comparing with Gold! " << "Position " << i << std::endl;
return -1;
}
}
std::cout << "Test passed! " << std::endl;
// clean up
if (input_data_cpu != nullptr) {
delete[] input_data_cpu;
}
if (input_segment_id_cpu != nullptr) {
delete[] input_segment_id_cpu;
}
if (output_segment_result_cpu != nullptr) {
delete[] output_segment_result_cpu;
}
if (output_segment_result_gold != nullptr) {
delete[] output_segment_result_gold;
}
hipFree(output_segment_result);
hipFree(input_segment_id);
hipFree(input_data);
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9InitValueIiEvPT_iS0_,"axG",@progbits,_Z9InitValueIiEvPT_iS0_,comdat
.protected _Z9InitValueIiEvPT_iS0_
.globl _Z9InitValueIiEvPT_iS0_
.p2align 8
.type _Z9InitValueIiEvPT_iS0_,@function
_Z9InitValueIiEvPT_iS0_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9InitValueIiEvPT_iS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9InitValueIiEvPT_iS0_,"axG",@progbits,_Z9InitValueIiEvPT_iS0_,comdat
.Lfunc_end0:
.size _Z9InitValueIiEvPT_iS0_, .Lfunc_end0-_Z9InitValueIiEvPT_iS0_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,"axG",@progbits,_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,comdat
.protected _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.globl _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.p2align 8
.type _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,@function
_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s9, s[0:1], 0x1c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v3
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB1_75
s_load_b32 s3, s[0:1], 0x18
s_sub_i32 s6, 0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
s_mul_hi_u32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s6
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s3, s2
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s8, s5, 31
s_add_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s5, s8
s_mul_hi_u32 s11, s10, s4
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s12, s11, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s10, s10, s12
s_add_i32 s12, s11, 1
s_sub_i32 s13, s10, s2
s_cmp_ge_u32 s10, s2
s_cselect_b32 s11, s12, s11
s_cselect_b32 s10, s13, s10
s_add_i32 s12, s11, 1
s_cmp_ge_u32 s10, s2
s_cselect_b32 s10, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s10, s8
s_sub_i32 s8, s10, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB1_6
s_load_b32 s10, s[0:1], 0x20
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v3, v0
s_lshl_b32 s11, s2, 2
s_mov_b32 s12, s8
s_branch .LBB1_4
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v2, s11, v2
v_add_nc_u32_e32 v3, s2, v3
s_add_i32 s12, s12, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB1_6
.LBB1_4:
s_mov_b32 s13, exec_lo
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB1_3
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v4, s10
ds_store_b32 v2, v4
s_branch .LBB1_3
.LBB1_6:
s_waitcnt lgkmcnt(0)
s_mov_b32 s10, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB1_8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s10
s_ashr_i32 s10, s9, 31
s_mov_b32 s11, exec_lo
s_lshr_b32 s10, s10, 27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s9, s10
s_ashr_i32 s10, s10, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s10, v1
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s11
v_lshl_add_u32 v2, s10, 1, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_12
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 3, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s11
v_lshl_add_u32 v2, s10, 2, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_16
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 5, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_18:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 6, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 7, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_22
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_22:
s_or_b32 exec_lo, exec_lo, s11
v_lshl_add_u32 v2, s10, 3, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_24
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_24:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 9, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_26
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 10, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_28
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_28:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 11, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_30
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_30:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 12, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_32
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_32:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 13, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_34
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_34:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 14, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_36
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_36:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 15, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_38
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_38:
s_or_b32 exec_lo, exec_lo, s11
v_lshl_add_u32 v2, s10, 4, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_40
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_40:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 17, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_42
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_42:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 18, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_44
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_44:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 19, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_46
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_46:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 20, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_48
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_48:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 21, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_50
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_50:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 22, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_52
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_52:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 23, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_54
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_54:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 24, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_56
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_56:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 25, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_58
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_58:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 26, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_60
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_60:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 27, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_62
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_62:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 28, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_64
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_64:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 29, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_66
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_66:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 30, v[1:2]
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB1_68
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v4, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v3, v2
.LBB1_68:
s_or_b32 exec_lo, exec_lo, s11
v_mad_u64_u32 v[2:3], null, s10, 31, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s9, v2
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_70
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v2, v3, 2, 0
s_waitcnt vmcnt(0)
ds_add_u32 v2, v1
.LBB1_70:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_i32 s8, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_75
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s0, 0
s_lshl_b32 s1, s2, 2
s_branch .LBB1_73
.p2align 6
.LBB1_72:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v1, vcc_lo, v1, s1
v_add_nc_u32_e32 v3, s1, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s0, v2, vcc_lo
v_add_nc_u32_e32 v0, s2, v0
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
s_cbranch_scc0 .LBB1_75
.LBB1_73:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_72
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v[1:2], v4, off
s_branch .LBB1_72
.LBB1_75:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,"axG",@progbits,_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,comdat
.Lfunc_end1:
.size _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, .Lfunc_end1-_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym segment_result_slm_shared
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9InitValueIiEvPT_iS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9InitValueIiEvPT_iS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //============================================================================
// Name : Unordered Reduction.cpp
// Author :
// Version :
// Copyright :
// Description : Test of the segment add plug-in
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include <limits>
#include <algorithm>
#include <limits>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define PER_THREAD_INIT_NUM 1
#define PER_THREAD_SEG_NUM 32
#define ARRAY_SIZE (1024 * 1024 * 32)
#define MAX_NUM 4
#define THREAD_NUM 1024
#define SEGMENT_NUM 512
typedef int operand_type;
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value == false, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
atomicAdd(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void SumOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicAdd(addr_temp, value_temp);
}
template <typename T>
struct SumOp {
__device__ void operator()(T *addr, T value) {
SumOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value > __uint_as_float(value_assumed) ? value : __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value > __longlong_as_double(value_assumed) ? value : __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, unsigned int>::value || std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int>::value || std::is_same<T, long long int>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
atomicMax(addr, value);
}
template<typename T, typename std::enable_if<std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MaxOpByType(T *addr, T value)
{
unsigned long long int *addr_temp = (unsigned long long int *)addr;
unsigned long long int value_temp = (unsigned long long int) value;
atomicMax(addr_temp, value_temp);
}
template <typename T>
struct MaxOp {
__device__ void operator()(T *addr, T value) {
MaxOpByType(addr, value);
}
};
template<typename T, typename std::enable_if<std::is_same<T, float>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__float_as_uint(value * __uint_as_float(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, int>::value || std::is_same<T, unsigned int>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned int *address = (unsigned int *)addr;
unsigned int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
(value * value_assumed));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, double>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
__double_as_longlong(value * __longlong_as_double(value_assumed)));
} while (value_assumed != value_old);
}
template<typename T, typename std::enable_if<std::is_same<T, long long int>::value ||
std::is_same<T, unsigned long long int>::value ||
std::is_same<T, int64_t>::value, void>::type* = nullptr>
__device__ void MulOpByType(T *addr, T value)
{
unsigned long long int *address = (unsigned long long int *)addr;
unsigned long long int value_old = *address, value_assumed;
do {
value_assumed = value_old;
value_old = atomicCAS(address,
value_assumed,
((unsigned long long int)value * value_assumed));
} while (value_assumed != value_old);
}
template <typename T>
struct MulOp {
__device__ void operator()(T *addr, T value) {
MulOpByType(addr, value);
}
};
template <typename T>
__global__ void InitValue(T *input, int total_size, T value) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < value) {
int split_size = total_size / PER_THREAD_INIT_NUM;
#pragma unroll
for (int i = 0; i < PER_THREAD_INIT_NUM; i++) {
input[i * split_size + index] = value;
}
}
}
template <typename ReductionF, typename T>
__global__ void Segmentation(T *__restrict__ input_data,
int *__restrict__ input_segment_id,
T *__restrict__ output_segment_result,
int segment_result_size,
int total_size,
T initial_value) {
extern __shared__ int segment_result_slm_shared[];
T *segment_result_slm = (T *)segment_result_slm_shared;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int split_size = total_size / PER_THREAD_SEG_NUM;
int local_index = threadIdx.x;
int local_size = blockDim.x;
int loop_slm = (segment_result_size + local_size - 1) / local_size;
if (index < total_size) {
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
segment_result_slm[slm_index] = initial_value;
}
}
__syncthreads();
#pragma unroll
for (int i = 0; i < PER_THREAD_SEG_NUM; i++) {
int split_index = index + split_size * i;
if (split_index < total_size) {
int segment_id = input_segment_id[split_index];
T data_value = input_data[split_index];
ReductionF()(segment_result_slm + segment_id, data_value);
}
}
__syncthreads();
for (int i = 0; i < loop_slm; i++) {
int slm_index = i * local_size + local_index;
if (slm_index < segment_result_size) {
if (slm_index < segment_result_size) {
ReductionF()(output_segment_result + slm_index, segment_result_slm[slm_index]);
}
}
}
}
}
int main(int argc, char **argv) {
operand_type *input_data = nullptr;
int *input_segment_id = nullptr;
operand_type *output_segment_result = nullptr;
operand_type *input_data_cpu = nullptr;
int *input_segment_id_cpu = nullptr;
operand_type *output_segment_result_cpu = nullptr;
operand_type *output_segment_result_gold = nullptr;
int array_num = ARRAY_SIZE;
int segment_num = SEGMENT_NUM;
int thread_num = THREAD_NUM;
float time = 0.0f;
int initial_value = 0;
hipEvent_t event1, event2;
std::srand(std::time(nullptr));
int dev = hipSetDevice(0);
CUDA_CHECK_RETURN(hipMalloc((void **)&input_data, array_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipMalloc((void **)&input_segment_id, array_num * sizeof(int)));
CUDA_CHECK_RETURN(hipMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type)));
CUDA_CHECK_RETURN(hipEventCreate(&event1));
CUDA_CHECK_RETURN(hipEventCreate(&event2));
if ((input_data_cpu = new operand_type[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((input_segment_id_cpu = new int[array_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_cpu = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
if ((output_segment_result_gold = new operand_type[segment_num]) == nullptr) {
std::cout << "Allocation memory failure!" << std::endl;
return -1;
}
// Initialize array
for (int i = 0; i < array_num; i++) {
input_data_cpu[i] = (float)rand() / RAND_MAX + 1.0f;
}
CUDA_CHECK_RETURN(hipMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), hipMemcpyHostToDevice));
for (int i = 0; i < array_num; i++) {
input_segment_id_cpu[i] = rand() % segment_num;
}
CUDA_CHECK_RETURN(hipMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
InitValue<operand_type><<<1, segment_num / PER_THREAD_INIT_NUM>>>(output_segment_result, segment_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel InitValue Execution time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
int block_num = (array_num + PER_THREAD_SEG_NUM * thread_num - 1) / (PER_THREAD_SEG_NUM * thread_num);
Segmentation<SumOp<operand_type>, operand_type><<<block_num, thread_num, segment_num * sizeof(operand_type)>>>(input_data, input_segment_id, output_segment_result, segment_num, array_num, initial_value);
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Kernel Segmentation Reduction time " << time << " ms" << std::endl;
CUDA_CHECK_RETURN(hipEventRecord(event1, 0));
CUDA_CHECK_RETURN(hipMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipEventRecord(event2, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(event2));
CUDA_CHECK_RETURN(hipEventElapsedTime(&time, event1, event2));
std::cout << "Memory copy time: " << time << " ms" << std::endl;
// compute and compare gold
for (int i = 0; i < segment_num; i++) {
output_segment_result_gold[i] = initial_value;
}
clock_t begin_clock = std::clock();
// sum reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] += input_data_cpu[i];
}
// max reduction
/*
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] = output_segment_result_gold[input_segment_id_cpu[i]] > input_data_cpu[i] ? output_segment_result_gold[input_segment_id_cpu[i]] : input_data_cpu[i];
}
*/
/*
// mul reduction
for (int i = 0; i < array_num; i++) {
output_segment_result_gold[input_segment_id_cpu[i]] *= input_data_cpu[i];
}
*/
clock_t end_clock = std::clock();
double elapsed_cpu = double(end_clock - begin_clock) / CLOCKS_PER_SEC * 1000.0;
std::cout << "CPU reduction time " << elapsed_cpu << " ms" << std::endl;
for (int i = 0; i < segment_num; i++) {
std::cout << "gpu result: " << output_segment_result_cpu[i] << " gold result: " << output_segment_result_gold[i] << std::endl;
if ((output_segment_result_cpu[i] != output_segment_result_gold[i])) {
std::cout << "Error comparing with Gold! " << "Position " << i << std::endl;
return -1;
}
}
std::cout << "Test passed! " << std::endl;
// clean up
if (input_data_cpu != nullptr) {
delete[] input_data_cpu;
}
if (input_segment_id_cpu != nullptr) {
delete[] input_segment_id_cpu;
}
if (output_segment_result_cpu != nullptr) {
delete[] output_segment_result_cpu;
}
if (output_segment_result_gold != nullptr) {
delete[] output_segment_result_gold;
}
hipFree(output_segment_result);
hipFree(input_segment_id);
hipFree(input_data);
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.file "Test_Cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_3:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 40(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movl $0, 4(%rsp)
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %edi, %edi
callq hipSetDevice
leaq 40(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
movl $.L.str.1, %esi
movl $248, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 32(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
movl $.L.str.2, %esi
movl $249, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $.L.str.3, %esi
movl $250, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.L.str.4, %esi
movl $252, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.L.str.5, %esi
movl $253, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %rbx
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq _Znam
movq %rax, 56(%rsp) # 8-byte Spill
movl $2048, %edi # imm = 0x800
callq _Znam
movq %rax, %r12
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
addss .LCPI0_1(%rip), %xmm0
cvttss2si %xmm0, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $33554432, %r15 # imm = 0x2000000
jne .LBB0_1
# %bb.2:
movq 40(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl $276, %edi # imm = 0x114
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 511(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-512, %ecx # imm = 0xFE00
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $33554432, %r15 # imm = 0x2000000
jne .LBB0_3
# %bb.4:
movq %rbx, 48(%rsp) # 8-byte Spill
movabsq $4294968320, %r15 # imm = 0x100000400
movq 32(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.8, %esi
movl $281, %edi # imm = 0x119
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.9, %esi
movl $284, %edi # imm = 0x11C
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq -1023(%r15), %rdi
leaq -512(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $512, 72(%rsp) # imm = 0x200
movl $0, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z9InitValueIiEvPT_iS0_, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.10, %esi
movl $287, %edi # imm = 0x11F
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str.11, %esi
movl $289, %edi # imm = 0x121
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.12, %esi
movl $290, %edi # imm = 0x122
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbp
movl $.L.str.14, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
movq 56(%rsp), %rbx # 8-byte Reload
je .LBB0_46
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB0_9
# %bb.8:
movzbl 67(%r13), %eax
jmp .LBB0_10
.LBB0_9:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.9, %esi
movl $295, %edi # imm = 0x127
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $2048, %r8d # imm = 0x800
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movl $512, 148(%rsp) # imm = 0x200
movl $33554432, 144(%rsp) # imm = 0x2000000
movl $0, 140(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 148(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 140(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.10, %esi
movl $298, %edi # imm = 0x12A
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str.11, %esi
movl $300, %edi # imm = 0x12C
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.12, %esi
movl $301, %edi # imm = 0x12D
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.14, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB0_46
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%rbp)
je .LBB0_15
# %bb.14:
movzbl 67(%rbp), %eax
jmp .LBB0_16
.LBB0_15:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.9, %esi
movl $305, %edi # imm = 0x131
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 24(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.16, %esi
movl $306, %edi # imm = 0x132
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.10, %esi
movl $307, %edi # imm = 0x133
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str.11, %esi
movl $309, %edi # imm = 0x135
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.12, %esi
movl $310, %edi # imm = 0x136
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.14, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB0_46
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
cmpb $0, 56(%rbp)
je .LBB0_19
# %bb.18:
movzbl 67(%rbp), %eax
jmp .LBB0_20
.LBB0_19:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit103
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
movl $2048, %edx # imm = 0x800
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r13
movq 48(%rsp), %rdx # 8-byte Reload
.p2align 4, 0x90
.LBB0_21: # =>This Inner Loop Header: Depth=1
movl (%rdx,%r15,4), %eax
movslq (%r14,%r15,4), %rcx
addl %eax, (%r12,%rcx,4)
incq %r15
cmpq $33554432, %r15 # imm = 0x2000000
jne .LBB0_21
# %bb.22:
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_2(%rip), %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.14, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB0_46
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
cmpb $0, 56(%rbp)
je .LBB0_25
# %bb.24:
movzbl 67(%rbp), %eax
jmp .LBB0_26
.LBB0_25:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit108
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_27: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str.20, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r12,%r13,4), %esi
movq %rbp, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB0_46
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110
# in Loop: Header=BB0_27 Depth=1
cmpb $0, 56(%rbp)
je .LBB0_30
# %bb.29: # in Loop: Header=BB0_27 Depth=1
movzbl 67(%rbp), %ecx
jmp .LBB0_31
.p2align 4, 0x90
.LBB0_30: # in Loop: Header=BB0_27 Depth=1
movq %rbp, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
movq 56(%rsp), %rbx # 8-byte Reload
.LBB0_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit113
# in Loop: Header=BB0_27 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl (%rbx,%r13,4), %eax
cmpl (%r12,%r13,4), %eax
jne .LBB0_32
# %bb.37: # in Loop: Header=BB0_27 Depth=1
cmpq $511, %r13 # imm = 0x1FF
leaq 1(%r13), %rax
setae %r15b
movq %rax, %r13
cmpq $512, %rax # imm = 0x200
jne .LBB0_27
# %bb.38:
xorl %eax, %eax
movq 48(%rsp), %rbp # 8-byte Reload
testb $1, %r15b
jne .LBB0_40
jmp .LBB0_45
.LBB0_32:
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB0_46
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i115
cmpb $0, 56(%r13)
movq 48(%rsp), %rbp # 8-byte Reload
je .LBB0_35
# %bb.34:
movzbl 67(%r13), %ecx
jmp .LBB0_36
.LBB0_35:
movq %r13, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
movq 56(%rsp), %rbx # 8-byte Reload
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit118
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
testb $1, %r15b
je .LBB0_45
.LBB0_40:
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB0_46
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i120
cmpb $0, 56(%r13)
je .LBB0_43
# %bb.42:
movzbl 67(%r13), %eax
jmp .LBB0_44
.LBB0_43:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit123
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB0_45:
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_46:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.24, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.25, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.26, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.27, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end1-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__InitValueIiEvPT_iS0_,"axG",@progbits,_Z24__device_stub__InitValueIiEvPT_iS0_,comdat
.weak _Z24__device_stub__InitValueIiEvPT_iS0_ # -- Begin function _Z24__device_stub__InitValueIiEvPT_iS0_
.p2align 4, 0x90
.type _Z24__device_stub__InitValueIiEvPT_iS0_,@function
_Z24__device_stub__InitValueIiEvPT_iS0_: # @_Z24__device_stub__InitValueIiEvPT_iS0_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9InitValueIiEvPT_iS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__InitValueIiEvPT_iS0_, .Lfunc_end2-_Z24__device_stub__InitValueIiEvPT_iS0_
.cfi_endproc
# -- End function
.section .text._Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,"axG",@progbits,_Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,comdat
.weak _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_ # -- Begin function _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.p2align 4, 0x90
.type _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,@function
_Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_: # @_Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, .Lfunc_end3-_Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9InitValueIiEvPT_iS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/zh7i/test/master/Test_Cuda/src/Test_Cuda.hip"
.size .L.str, 102
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void **)&input_data, array_num * sizeof(operand_type))"
.size .L.str.1, 66
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc((void **)&input_segment_id, array_num * sizeof(int))"
.size .L.str.2, 63
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **)&output_segment_result, segment_num * sizeof(operand_type))"
.size .L.str.3, 79
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipEventCreate(&event1)"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipEventCreate(&event2)"
.size .L.str.5, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy(input_data, input_data_cpu, array_num * sizeof(operand_type), hipMemcpyHostToDevice)"
.size .L.str.7, 95
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy(input_segment_id, input_segment_id_cpu, array_num * sizeof(int), hipMemcpyHostToDevice)"
.size .L.str.8, 98
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipEventRecord(event1, 0)"
.size .L.str.9, 26
.type _Z9InitValueIiEvPT_iS0_,@object # @_Z9InitValueIiEvPT_iS0_
.section .rodata._Z9InitValueIiEvPT_iS0_,"aG",@progbits,_Z9InitValueIiEvPT_iS0_,comdat
.weak _Z9InitValueIiEvPT_iS0_
.p2align 3, 0x0
_Z9InitValueIiEvPT_iS0_:
.quad _Z24__device_stub__InitValueIiEvPT_iS0_
.size _Z9InitValueIiEvPT_iS0_, 8
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz "hipEventRecord(event2, 0)"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipEventSynchronize(event2)"
.size .L.str.11, 28
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipEventElapsedTime(&time, event1, event2)"
.size .L.str.12, 43
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Kernel InitValue Execution time "
.size .L.str.13, 33
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " ms"
.size .L.str.14, 4
.type _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,@object # @_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.section .rodata._Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,"aG",@progbits,_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_,comdat
.weak _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.p2align 3, 0x0
_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_:
.quad _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.size _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_, 8
.type .L.str.15,@object # @.str.15
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.15:
.asciz "Kernel Segmentation Reduction time "
.size .L.str.15, 36
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "hipMemcpy(output_segment_result_cpu, output_segment_result, segment_num * sizeof(operand_type), hipMemcpyDeviceToHost)"
.size .L.str.16, 119
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Memory copy time: "
.size .L.str.17, 19
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "CPU reduction time "
.size .L.str.18, 20
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "gpu result: "
.size .L.str.19, 13
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " gold result: "
.size .L.str.20, 15
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Error comparing with Gold! "
.size .L.str.21, 28
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Position "
.size .L.str.22, 10
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Test passed! "
.size .L.str.23, 14
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " returned "
.size .L.str.24, 11
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "("
.size .L.str.25, 2
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz ") at "
.size .L.str.26, 6
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz ":"
.size .L.str.27, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9InitValueIiEvPT_iS0_"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_"
.size .L__unnamed_2, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__InitValueIiEvPT_iS0_
.addrsig_sym _Z27__device_stub__SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z9InitValueIiEvPT_iS0_
.addrsig_sym _Z12SegmentationI5SumOpIiEiEvPT0_PiS3_iiS2_
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} | code for sm_80
Function : _Z14sumArraysOnGPUPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ MUFU.RCP64H R3, 123.0999755859375 ; /* 0x405ec66600037908 */
/* 0x000e220000001800 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x66666666 ; /* 0x66666666ff0a7424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x270 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x405ec666 ; /* 0x405ec666ff0b7424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0110*/ DFMA R4, R2, -R10, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c000000080a */
/*0120*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0130*/ DFMA R2, R2, R4, R2 ; /* 0x000000040202722b */
/* 0x001e0c0000000002 */
/*0140*/ DFMA R10, R2, -R10, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c000000080a */
/*0150*/ DFMA R2, R2, R10, R2 ; /* 0x0000000a0202722b */
/* 0x001fc80000000002 */
/*0160*/ DMUL R4, R8, 4 ; /* 0x4010000008047828 */
/* 0x004e0c0000000000 */
/*0170*/ DMUL R10, R4, R2 ; /* 0x00000002040a7228 */
/* 0x001e080000000000 */
/*0180*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe20003f2e200 */
/*0190*/ DADD R24, R8, R6 ; /* 0x0000000008187229 */
/* 0x008e480000000006 */
/*01a0*/ DFMA R12, R10, c[0x2][0x0], R4 ; /* 0x008000000a0c7a2b */
/* 0x001e080000000004 */
/*01b0*/ DFMA R24, R6, 7, R24 ; /* 0x401c00000618782b */
/* 0x002fc80000000018 */
/*01c0*/ DFMA R2, R2, R12, R10 ; /* 0x0000000c0202722b */
/* 0x001e14000000000a */
/*01d0*/ FFMA R10, RZ, 3.4808592796325683594, R3 ; /* 0x405ec666ff0a7823 */
/* 0x001fca0000000003 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA P1, 0x260 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, 0x66666666 ; /* 0x66666666ff0c7424 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R2, 0x240 ; /* 0x0000024000027802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R13, RZ, RZ, 0x405ec666 ; /* 0x405ec666ff0d7424 */
/* 0x000fe400078e00ff */
/*0230*/ CALL.REL.NOINC 0x640 ; /* 0x0000040000007944 */
/* 0x000fea0003c00000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ MUFU.RCP64H R11, 0.39999985694885253906 ; /* 0x3fd99999000b7908 */
/* 0x000e220000001800 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, -0x66666666 ; /* 0x9999999aff0e7424 */
/* 0x000fe200078e00ff */
/*0290*/ DADD R24, R24, R2 ; /* 0x0000000018187229 */
/* 0x000ea20000000002 */
/*02a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd99999 ; /* 0x3fd99999ff0f7424 */
/* 0x000fe200078e00ff */
/*02b0*/ BSSY B0, 0x430 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fc600078e00ff */
/*02d0*/ DFMA R24, -R8, R6, R24 ; /* 0x000000060818722b */
/* 0x004e8c0000000118 */
/*02e0*/ DFMA R24, R8, R8, R24 ; /* 0x000000080818722b */
/* 0x004fc80000000018 */
/*02f0*/ DFMA R4, R10, -R14, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c000000080e */
/*0300*/ DFMA R12, R4, R4, R4 ; /* 0x00000004040c722b */
/* 0x001e080000000004 */
/*0310*/ DMUL R4, R8, -9 ; /* 0xc022000008047828 */
/* 0x000e880000000000 */
/*0320*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e08000000000a */
/*0330*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x004e880000000000 */
/*0340*/ DFMA R10, R12, -R14, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e08000000080e */
/*0350*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x004fc80000000000 */
/*0360*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0370*/ DMUL R12, R4, R10 ; /* 0x0000000a040c7228 */
/* 0x001e220000000000 */
/*0380*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0390*/ DFMA R14, R12, c[0x2][0x8], R4 ; /* 0x008002000c0e7a2b */
/* 0x001e0c0000000004 */
/*03a0*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001e14000000000c */
/*03b0*/ FFMA R2, RZ, 1.6999999284744262695, R11 ; /* 0x3fd99999ff027823 */
/* 0x001fca000000000b */
/*03c0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*03d0*/ @P0 BRA P1, 0x420 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03e0*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe200078e00ff */
/*03f0*/ MOV R2, 0x420 ; /* 0x0000042000027802 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd99999 ; /* 0x3fd99999ff0d7424 */
/* 0x000fe400078e00ff */
/*0410*/ CALL.REL.NOINC 0x640 ; /* 0x0000022000007944 */
/* 0x002fea0003c00000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ MUFU.RCP64H R3, 0.19999992847442626953 ; /* 0x3fc9999900037908 */
/* 0x000e220000001800 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe200078e00ff */
/*0450*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fc99999 ; /* 0x3fc99999ff0d7424 */
/* 0x000fe200078e00ff */
/*0470*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe20003f2e200 */
/*0480*/ BSSY B0, 0x5e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0490*/ DADD R24, R24, R10 ; /* 0x0000000018187229 */
/* 0x000fc8000000000a */
/*04a0*/ DFMA R4, R2, -R12, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c000000080c */
/*04b0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*04c0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*04d0*/ DFMA R2, R4, -R12, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c000000080c */
/*04e0*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*04f0*/ DMUL R4, R6, R2 ; /* 0x0000000206047228 */
/* 0x001e0c0000000000 */
/*0500*/ DFMA R12, R4, c[0x2][0x10], R6 ; /* 0x00800400040c7a2b */
/* 0x001e0c0000000006 */
/*0510*/ DFMA R2, R2, R12, R4 ; /* 0x0000000c0202722b */
/* 0x001e140000000004 */
/*0520*/ FFMA R4, RZ, 1.5749999284744262695, R3 ; /* 0x3fc99999ff047823 */
/* 0x001fca0000000003 */
/*0530*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0540*/ @P0 BRA P1, 0x5d0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0560*/ MOV R2, 0x5b0 ; /* 0x000005b000027802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fc99999 ; /* 0x3fc99999ff0d7424 */
/* 0x000fe400078e00ff */
/*05a0*/ CALL.REL.NOINC 0x640 ; /* 0x0000009000007944 */
/* 0x002fea0003c00000 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ DADD R24, R24, R2 ; /* 0x0000000018187229 */
/* 0x0000a40000000002 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x001fc800078e00ff */
/*0600*/ DFMA R24, R8, R8, R24 ; /* 0x000000080818722b */
/* 0x004e220000000018 */
/*0610*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0620*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x001fe2000c101b04 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f0e200 */
/*0650*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0005 */
/*0660*/ LOP3.LUT R10, R13.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0d0a7812 */
/* 0x040fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0680*/ LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d1a7812 */
/* 0x000fe200078ec0ff */
/*0690*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*06a0*/ FSETP.GEU.AND P2, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f4e200 */
/*06b0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*06c0*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*06d0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*06e0*/ LOP3.LUT R3, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f037812 */
/* 0x000fe200078ec0ff */
/*06f0*/ BSSY B1, 0xbf0 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*0700*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0710*/ ISETP.GE.U32.AND P1, PT, R3, R26, PT ; /* 0x0000001a0300720c */
/* 0x000fca0003f26070 */
/*0720*/ @!P2 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d04a812 */
/* 0x000fe200078ec0ff */
/*0730*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e260000001800 */
/*0740*/ @!P2 ISETP.GE.U32.AND P3, PT, R3, R4, PT ; /* 0x000000040300a20c */
/* 0x000fe40003f66070 */
/*0750*/ MOV R4, 0x1ca00000 ; /* 0x1ca0000000047802 */
/* 0x000fe40000000f00 */
/*0760*/ @!P0 LOP3.LUT R26, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1a8812 */
/* 0x000fe400078ec0ff */
/*0770*/ @!P2 SEL R5, R4, 0x63400000, !P3 ; /* 0x634000000405a807 */
/* 0x000fc40005800000 */
/*0780*/ SEL R17, R4, 0x63400000, !P1 ; /* 0x6340000004117807 */
/* 0x000fe40004800000 */
/*0790*/ @!P2 LOP3.LUT R18, R5, 0x80000000, R15, 0xf8, !PT ; /* 0x800000000512a812 */
/* 0x000fe200078ef80f */
/*07a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*07b0*/ LOP3.LUT R17, R17, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x000fe200078ef80f */
/*07c0*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x001e22000000080a */
/*07d0*/ @!P2 LOP3.LUT R19, R18, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001213a812 */
/* 0x000fe200078efcff */
/*07e0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*07f0*/ IADD3 R27, R26, -0x1, RZ ; /* 0xffffffff1a1b7810 */
/* 0x000fc60007ffe0ff */
/*0800*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0810*/ @!P2 DFMA R16, R16, 2, -R18 ; /* 0x400000001010a82b */
/* 0x000e480000000812 */
/*0820*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*0830*/ @!P2 LOP3.LUT R5, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001105a812 */
/* 0x002fe200078ec0ff */
/*0840*/ DFMA R18, R20, -R10, 1 ; /* 0x3ff000001412742b */
/* 0x001e06000000080a */
/*0850*/ IADD3 R22, R5, -0x1, RZ ; /* 0xffffffff05167810 */
/* 0x000fc60007ffe0ff */
/*0860*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x001e220000000014 */
/*0870*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc80003f04070 */
/*0880*/ ISETP.GT.U32.OR P0, PT, R27, 0x7feffffe, P0 ; /* 0x7feffffe1b00780c */
/* 0x000fe20000704470 */
/*0890*/ DMUL R20, R18, R16 ; /* 0x0000001012147228 */
/* 0x001e0c0000000000 */
/*08a0*/ DFMA R22, R20, -R10, R16 ; /* 0x8000000a1416722b */
/* 0x001e0c0000000010 */
/*08b0*/ DFMA R22, R18, R22, R20 ; /* 0x000000161216722b */
/* 0x0010620000000014 */
/*08c0*/ @P0 BRA 0xa90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT R14, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0e7812 */
/* 0x000fc800078ec0ff */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, R14, PT ; /* 0x0000000e0300720c */
/* 0x040fe20003f06070 */
/*08f0*/ IMAD.IADD R5, R3, 0x1, -R14 ; /* 0x0000000103057824 */
/* 0x000fc600078e0a0e */
/*0900*/ SEL R4, R4, 0x63400000, !P0 ; /* 0x6340000004047807 */
/* 0x000fe40004000000 */
/*0910*/ IMNMX R5, R5, -0x46a00000, !PT ; /* 0xb960000005057817 */
/* 0x000fc80007800200 */
/*0920*/ IMNMX R3, R5, 0x46a00000, PT ; /* 0x46a0000005037817 */
/* 0x000fca0003800200 */
/*0930*/ IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a04 */
/*0940*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0950*/ IADD3 R5, R3, 0x7fe00000, RZ ; /* 0x7fe0000003057810 */
/* 0x000fcc0007ffe0ff */
/*0960*/ DMUL R18, R22, R4 ; /* 0x0000000416127228 */
/* 0x003e140000000000 */
/*0970*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0980*/ @P0 BRA 0xbe0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0990*/ DFMA R10, R22, -R10, R16 ; /* 0x8000000a160a722b */
/* 0x000e0c0000000010 */
/*09a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fc800078e00ff */
/*09b0*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x040fe40003f0d000 */
/*09c0*/ LOP3.LUT R13, R11, 0x80000000, R13, 0x48, !PT ; /* 0x800000000b0d7812 */
/* 0x000fc800078e480d */
/*09d0*/ LOP3.LUT R11, R13, R5, RZ, 0xfc, !PT ; /* 0x000000050d0b7212 */
/* 0x000fce00078efcff */
/*09e0*/ @!P0 BRA 0xbe0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0a00*/ DMUL.RP R10, R22, R10 ; /* 0x0000000a160a7228 */
/* 0x000e220000008000 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0a20*/ IADD3 R3, -R3, -0x43300000, RZ ; /* 0xbcd0000003037810 */
/* 0x000fca0007ffe1ff */
/*0a30*/ DFMA R4, R18, -R4, R22 ; /* 0x800000041204722b */
/* 0x000e460000000016 */
/*0a40*/ LOP3.LUT R13, R11, R13, RZ, 0x3c, !PT ; /* 0x0000000d0b0d7212 */
/* 0x001fce00078e3cff */
/*0a50*/ FSETP.NEU.AND P0, PT, |R5|, R3, PT ; /* 0x000000030500720b */
/* 0x002fc80003f0d200 */
/*0a60*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0a70*/ FSEL R19, R13, R19, !P0 ; /* 0x000000130d137208 */
/* 0x000fe20004000000 */
/*0a80*/ BRA 0xbe0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a90*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0aa0*/ @P0 BRA 0xbc0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0ab0*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0ac0*/ @P0 BRA 0xb90 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, R26, PT ; /* 0x0000001a0500720c */
/* 0x000fe20003f05270 */
/*0ae0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x001fe200078e00ff */
/*0af0*/ MOV R18, 0x0 ; /* 0x0000000000127802 */
/* 0x000fd60000000f00 */
/*0b00*/ @!P0 BRA 0xbe0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ; /* 0x7ff000000500780c */
/* 0x000fe40003f05270 */
/*0b20*/ LOP3.LUT R19, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f137812 */
/* 0x000fe400078e480d */
/*0b30*/ ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; /* 0x000000ff1a00720c */
/* 0x000fda0004702670 */
/*0b40*/ @P0 LOP3.LUT R3, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013030812 */
/* 0x000fe200078efcff */
/*0b50*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0b60*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0b70*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0003 */
/*0b80*/ BRA 0xbe0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R19, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d137812 */
/* 0x001fe200078efcff */
/*0ba0*/ IMAD.MOV.U32 R18, RZ, RZ, R12 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000c */
/*0bb0*/ BRA 0xbe0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bc0*/ LOP3.LUT R19, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f137812 */
/* 0x001fe200078efcff */
/*0bd0*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000e */
/*0be0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e0012 */
/*0c10*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*0c20*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff3d002007950 */
/* 0x000fec0003c3ffff */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} | .file "tmpxft_000e740a_00000000-6_sumArraysOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
.type _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i, @function
_Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumArraysOnGPUPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i, .-_Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
.globl _Z14sumArraysOnGPUPdS_S_i
.type _Z14sumArraysOnGPUPdS_S_i, @function
_Z14sumArraysOnGPUPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumArraysOnGPUPdS_S_i, .-_Z14sumArraysOnGPUPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumArraysOnGPUPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumArraysOnGPUPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumArraysOnGPUPdS_S_i
.globl _Z14sumArraysOnGPUPdS_S_i
.p2align 8
.type _Z14sumArraysOnGPUPdS_S_i,@function
_Z14sumArraysOnGPUPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0x3fd99999
s_mov_b32 s8, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s7, 0x405ec666
s_mov_b32 s6, 0x66666666
v_add_co_u32 v12, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[2:3], 0xc0220000
v_mul_f64 v[6:7], v[2:3], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[2:3], v[4:5]
v_div_scale_f64 v[8:9], null, s[6:7], s[6:7], v[6:7]
v_div_scale_f64 v[22:23], vcc_lo, v[6:7], s[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[4:5], v[2:3], v[4:5]
v_rcp_f64_e32 v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_div_scale_f64 v[10:11], null, s[8:9], s[8:9], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
v_rcp_f64_e32 v[16:17], v[10:11]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s0, v[4:5], s[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], -v[8:9], v[20:21], v[22:23]
v_fma_f64 v[10:11], -v[10:11], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[8:9], s[6:7], v[6:7]
v_div_fixup_f64 v[4:5], v[10:11], s[8:9], v[4:5]
s_mov_b32 s9, 0x3fc99999
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, s[8:9], s[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_add_f64 v[16:17], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[16:17], v[12:13], 0x401c0000, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[14:15], vcc_lo, v[12:13], s[8:9], v[12:13]
v_add_f64 v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[14:15], v[8:9]
v_fma_f64 v[6:7], -v[12:13], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_fma_f64 v[6:7], v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[10:11], v[8:9], v[16:17]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_f64 v[4:5], v[6:7], v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], s[8:9], v[12:13]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumArraysOnGPUPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumArraysOnGPUPdS_S_i, .Lfunc_end0-_Z14sumArraysOnGPUPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumArraysOnGPUPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sumArraysOnGPUPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(double *A, double *B, double *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) C[i] = A[i] + B[i] + 7*A[i] + 4*B[i]/123.1 - B[i]*A[i] + B[i]*B[i] - 9*B[i]*B[i]*B[i]/0.4 + A[i]/0.2 + B[i]*B[i];
} | .text
.file "sumArraysOnGPU.hip"
.globl _Z29__device_stub__sumArraysOnGPUPdS_S_i # -- Begin function _Z29__device_stub__sumArraysOnGPUPdS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__sumArraysOnGPUPdS_S_i,@function
_Z29__device_stub__sumArraysOnGPUPdS_S_i: # @_Z29__device_stub__sumArraysOnGPUPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumArraysOnGPUPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sumArraysOnGPUPdS_S_i, .Lfunc_end0-_Z29__device_stub__sumArraysOnGPUPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumArraysOnGPUPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumArraysOnGPUPdS_S_i,@object # @_Z14sumArraysOnGPUPdS_S_i
.section .rodata,"a",@progbits
.globl _Z14sumArraysOnGPUPdS_S_i
.p2align 3, 0x0
_Z14sumArraysOnGPUPdS_S_i:
.quad _Z29__device_stub__sumArraysOnGPUPdS_S_i
.size _Z14sumArraysOnGPUPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumArraysOnGPUPdS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumArraysOnGPUPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumArraysOnGPUPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sumArraysOnGPUPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ MUFU.RCP64H R3, 123.0999755859375 ; /* 0x405ec66600037908 */
/* 0x000e220000001800 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x66666666 ; /* 0x66666666ff0a7424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x270 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x405ec666 ; /* 0x405ec666ff0b7424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0110*/ DFMA R4, R2, -R10, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c000000080a */
/*0120*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0130*/ DFMA R2, R2, R4, R2 ; /* 0x000000040202722b */
/* 0x001e0c0000000002 */
/*0140*/ DFMA R10, R2, -R10, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c000000080a */
/*0150*/ DFMA R2, R2, R10, R2 ; /* 0x0000000a0202722b */
/* 0x001fc80000000002 */
/*0160*/ DMUL R4, R8, 4 ; /* 0x4010000008047828 */
/* 0x004e0c0000000000 */
/*0170*/ DMUL R10, R4, R2 ; /* 0x00000002040a7228 */
/* 0x001e080000000000 */
/*0180*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe20003f2e200 */
/*0190*/ DADD R24, R8, R6 ; /* 0x0000000008187229 */
/* 0x008e480000000006 */
/*01a0*/ DFMA R12, R10, c[0x2][0x0], R4 ; /* 0x008000000a0c7a2b */
/* 0x001e080000000004 */
/*01b0*/ DFMA R24, R6, 7, R24 ; /* 0x401c00000618782b */
/* 0x002fc80000000018 */
/*01c0*/ DFMA R2, R2, R12, R10 ; /* 0x0000000c0202722b */
/* 0x001e14000000000a */
/*01d0*/ FFMA R10, RZ, 3.4808592796325683594, R3 ; /* 0x405ec666ff0a7823 */
/* 0x001fca0000000003 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA P1, 0x260 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, 0x66666666 ; /* 0x66666666ff0c7424 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R2, 0x240 ; /* 0x0000024000027802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R13, RZ, RZ, 0x405ec666 ; /* 0x405ec666ff0d7424 */
/* 0x000fe400078e00ff */
/*0230*/ CALL.REL.NOINC 0x640 ; /* 0x0000040000007944 */
/* 0x000fea0003c00000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ MUFU.RCP64H R11, 0.39999985694885253906 ; /* 0x3fd99999000b7908 */
/* 0x000e220000001800 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, -0x66666666 ; /* 0x9999999aff0e7424 */
/* 0x000fe200078e00ff */
/*0290*/ DADD R24, R24, R2 ; /* 0x0000000018187229 */
/* 0x000ea20000000002 */
/*02a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd99999 ; /* 0x3fd99999ff0f7424 */
/* 0x000fe200078e00ff */
/*02b0*/ BSSY B0, 0x430 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fc600078e00ff */
/*02d0*/ DFMA R24, -R8, R6, R24 ; /* 0x000000060818722b */
/* 0x004e8c0000000118 */
/*02e0*/ DFMA R24, R8, R8, R24 ; /* 0x000000080818722b */
/* 0x004fc80000000018 */
/*02f0*/ DFMA R4, R10, -R14, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c000000080e */
/*0300*/ DFMA R12, R4, R4, R4 ; /* 0x00000004040c722b */
/* 0x001e080000000004 */
/*0310*/ DMUL R4, R8, -9 ; /* 0xc022000008047828 */
/* 0x000e880000000000 */
/*0320*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e08000000000a */
/*0330*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x004e880000000000 */
/*0340*/ DFMA R10, R12, -R14, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e08000000080e */
/*0350*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x004fc80000000000 */
/*0360*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0370*/ DMUL R12, R4, R10 ; /* 0x0000000a040c7228 */
/* 0x001e220000000000 */
/*0380*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0390*/ DFMA R14, R12, c[0x2][0x8], R4 ; /* 0x008002000c0e7a2b */
/* 0x001e0c0000000004 */
/*03a0*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001e14000000000c */
/*03b0*/ FFMA R2, RZ, 1.6999999284744262695, R11 ; /* 0x3fd99999ff027823 */
/* 0x001fca000000000b */
/*03c0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*03d0*/ @P0 BRA P1, 0x420 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03e0*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe200078e00ff */
/*03f0*/ MOV R2, 0x420 ; /* 0x0000042000027802 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd99999 ; /* 0x3fd99999ff0d7424 */
/* 0x000fe400078e00ff */
/*0410*/ CALL.REL.NOINC 0x640 ; /* 0x0000022000007944 */
/* 0x002fea0003c00000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ MUFU.RCP64H R3, 0.19999992847442626953 ; /* 0x3fc9999900037908 */
/* 0x000e220000001800 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe200078e00ff */
/*0450*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fc99999 ; /* 0x3fc99999ff0d7424 */
/* 0x000fe200078e00ff */
/*0470*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe20003f2e200 */
/*0480*/ BSSY B0, 0x5e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0490*/ DADD R24, R24, R10 ; /* 0x0000000018187229 */
/* 0x000fc8000000000a */
/*04a0*/ DFMA R4, R2, -R12, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c000000080c */
/*04b0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*04c0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*04d0*/ DFMA R2, R4, -R12, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c000000080c */
/*04e0*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*04f0*/ DMUL R4, R6, R2 ; /* 0x0000000206047228 */
/* 0x001e0c0000000000 */
/*0500*/ DFMA R12, R4, c[0x2][0x10], R6 ; /* 0x00800400040c7a2b */
/* 0x001e0c0000000006 */
/*0510*/ DFMA R2, R2, R12, R4 ; /* 0x0000000c0202722b */
/* 0x001e140000000004 */
/*0520*/ FFMA R4, RZ, 1.5749999284744262695, R3 ; /* 0x3fc99999ff047823 */
/* 0x001fca0000000003 */
/*0530*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0540*/ @P0 BRA P1, 0x5d0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0560*/ MOV R2, 0x5b0 ; /* 0x000005b000027802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, -0x66666666 ; /* 0x9999999aff0c7424 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fc99999 ; /* 0x3fc99999ff0d7424 */
/* 0x000fe400078e00ff */
/*05a0*/ CALL.REL.NOINC 0x640 ; /* 0x0000009000007944 */
/* 0x002fea0003c00000 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ DADD R24, R24, R2 ; /* 0x0000000018187229 */
/* 0x0000a40000000002 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x001fc800078e00ff */
/*0600*/ DFMA R24, R8, R8, R24 ; /* 0x000000080818722b */
/* 0x004e220000000018 */
/*0610*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0620*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x001fe2000c101b04 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f0e200 */
/*0650*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0005 */
/*0660*/ LOP3.LUT R10, R13.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0d0a7812 */
/* 0x040fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0680*/ LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d1a7812 */
/* 0x000fe200078ec0ff */
/*0690*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*06a0*/ FSETP.GEU.AND P2, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f4e200 */
/*06b0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*06c0*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*06d0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*06e0*/ LOP3.LUT R3, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f037812 */
/* 0x000fe200078ec0ff */
/*06f0*/ BSSY B1, 0xbf0 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*0700*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0710*/ ISETP.GE.U32.AND P1, PT, R3, R26, PT ; /* 0x0000001a0300720c */
/* 0x000fca0003f26070 */
/*0720*/ @!P2 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d04a812 */
/* 0x000fe200078ec0ff */
/*0730*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e260000001800 */
/*0740*/ @!P2 ISETP.GE.U32.AND P3, PT, R3, R4, PT ; /* 0x000000040300a20c */
/* 0x000fe40003f66070 */
/*0750*/ MOV R4, 0x1ca00000 ; /* 0x1ca0000000047802 */
/* 0x000fe40000000f00 */
/*0760*/ @!P0 LOP3.LUT R26, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1a8812 */
/* 0x000fe400078ec0ff */
/*0770*/ @!P2 SEL R5, R4, 0x63400000, !P3 ; /* 0x634000000405a807 */
/* 0x000fc40005800000 */
/*0780*/ SEL R17, R4, 0x63400000, !P1 ; /* 0x6340000004117807 */
/* 0x000fe40004800000 */
/*0790*/ @!P2 LOP3.LUT R18, R5, 0x80000000, R15, 0xf8, !PT ; /* 0x800000000512a812 */
/* 0x000fe200078ef80f */
/*07a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*07b0*/ LOP3.LUT R17, R17, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x000fe200078ef80f */
/*07c0*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x001e22000000080a */
/*07d0*/ @!P2 LOP3.LUT R19, R18, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001213a812 */
/* 0x000fe200078efcff */
/*07e0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*07f0*/ IADD3 R27, R26, -0x1, RZ ; /* 0xffffffff1a1b7810 */
/* 0x000fc60007ffe0ff */
/*0800*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0810*/ @!P2 DFMA R16, R16, 2, -R18 ; /* 0x400000001010a82b */
/* 0x000e480000000812 */
/*0820*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*0830*/ @!P2 LOP3.LUT R5, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001105a812 */
/* 0x002fe200078ec0ff */
/*0840*/ DFMA R18, R20, -R10, 1 ; /* 0x3ff000001412742b */
/* 0x001e06000000080a */
/*0850*/ IADD3 R22, R5, -0x1, RZ ; /* 0xffffffff05167810 */
/* 0x000fc60007ffe0ff */
/*0860*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x001e220000000014 */
/*0870*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc80003f04070 */
/*0880*/ ISETP.GT.U32.OR P0, PT, R27, 0x7feffffe, P0 ; /* 0x7feffffe1b00780c */
/* 0x000fe20000704470 */
/*0890*/ DMUL R20, R18, R16 ; /* 0x0000001012147228 */
/* 0x001e0c0000000000 */
/*08a0*/ DFMA R22, R20, -R10, R16 ; /* 0x8000000a1416722b */
/* 0x001e0c0000000010 */
/*08b0*/ DFMA R22, R18, R22, R20 ; /* 0x000000161216722b */
/* 0x0010620000000014 */
/*08c0*/ @P0 BRA 0xa90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT R14, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0e7812 */
/* 0x000fc800078ec0ff */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, R14, PT ; /* 0x0000000e0300720c */
/* 0x040fe20003f06070 */
/*08f0*/ IMAD.IADD R5, R3, 0x1, -R14 ; /* 0x0000000103057824 */
/* 0x000fc600078e0a0e */
/*0900*/ SEL R4, R4, 0x63400000, !P0 ; /* 0x6340000004047807 */
/* 0x000fe40004000000 */
/*0910*/ IMNMX R5, R5, -0x46a00000, !PT ; /* 0xb960000005057817 */
/* 0x000fc80007800200 */
/*0920*/ IMNMX R3, R5, 0x46a00000, PT ; /* 0x46a0000005037817 */
/* 0x000fca0003800200 */
/*0930*/ IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a04 */
/*0940*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0950*/ IADD3 R5, R3, 0x7fe00000, RZ ; /* 0x7fe0000003057810 */
/* 0x000fcc0007ffe0ff */
/*0960*/ DMUL R18, R22, R4 ; /* 0x0000000416127228 */
/* 0x003e140000000000 */
/*0970*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0980*/ @P0 BRA 0xbe0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0990*/ DFMA R10, R22, -R10, R16 ; /* 0x8000000a160a722b */
/* 0x000e0c0000000010 */
/*09a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fc800078e00ff */
/*09b0*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x040fe40003f0d000 */
/*09c0*/ LOP3.LUT R13, R11, 0x80000000, R13, 0x48, !PT ; /* 0x800000000b0d7812 */
/* 0x000fc800078e480d */
/*09d0*/ LOP3.LUT R11, R13, R5, RZ, 0xfc, !PT ; /* 0x000000050d0b7212 */
/* 0x000fce00078efcff */
/*09e0*/ @!P0 BRA 0xbe0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0a00*/ DMUL.RP R10, R22, R10 ; /* 0x0000000a160a7228 */
/* 0x000e220000008000 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0a20*/ IADD3 R3, -R3, -0x43300000, RZ ; /* 0xbcd0000003037810 */
/* 0x000fca0007ffe1ff */
/*0a30*/ DFMA R4, R18, -R4, R22 ; /* 0x800000041204722b */
/* 0x000e460000000016 */
/*0a40*/ LOP3.LUT R13, R11, R13, RZ, 0x3c, !PT ; /* 0x0000000d0b0d7212 */
/* 0x001fce00078e3cff */
/*0a50*/ FSETP.NEU.AND P0, PT, |R5|, R3, PT ; /* 0x000000030500720b */
/* 0x002fc80003f0d200 */
/*0a60*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0a70*/ FSEL R19, R13, R19, !P0 ; /* 0x000000130d137208 */
/* 0x000fe20004000000 */
/*0a80*/ BRA 0xbe0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a90*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0aa0*/ @P0 BRA 0xbc0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0ab0*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0ac0*/ @P0 BRA 0xb90 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, R26, PT ; /* 0x0000001a0500720c */
/* 0x000fe20003f05270 */
/*0ae0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x001fe200078e00ff */
/*0af0*/ MOV R18, 0x0 ; /* 0x0000000000127802 */
/* 0x000fd60000000f00 */
/*0b00*/ @!P0 BRA 0xbe0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ; /* 0x7ff000000500780c */
/* 0x000fe40003f05270 */
/*0b20*/ LOP3.LUT R19, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f137812 */
/* 0x000fe400078e480d */
/*0b30*/ ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; /* 0x000000ff1a00720c */
/* 0x000fda0004702670 */
/*0b40*/ @P0 LOP3.LUT R3, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013030812 */
/* 0x000fe200078efcff */
/*0b50*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0b60*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0b70*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0003 */
/*0b80*/ BRA 0xbe0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R19, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d137812 */
/* 0x001fe200078efcff */
/*0ba0*/ IMAD.MOV.U32 R18, RZ, RZ, R12 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000c */
/*0bb0*/ BRA 0xbe0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bc0*/ LOP3.LUT R19, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f137812 */
/* 0x001fe200078efcff */
/*0bd0*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000e */
/*0be0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e0012 */
/*0c10*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*0c20*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff3d002007950 */
/* 0x000fec0003c3ffff */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumArraysOnGPUPdS_S_i
.globl _Z14sumArraysOnGPUPdS_S_i
.p2align 8
.type _Z14sumArraysOnGPUPdS_S_i,@function
_Z14sumArraysOnGPUPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0x3fd99999
s_mov_b32 s8, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s7, 0x405ec666
s_mov_b32 s6, 0x66666666
v_add_co_u32 v12, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[2:3], 0xc0220000
v_mul_f64 v[6:7], v[2:3], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[2:3], v[4:5]
v_div_scale_f64 v[8:9], null, s[6:7], s[6:7], v[6:7]
v_div_scale_f64 v[22:23], vcc_lo, v[6:7], s[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[4:5], v[2:3], v[4:5]
v_rcp_f64_e32 v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_div_scale_f64 v[10:11], null, s[8:9], s[8:9], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
v_rcp_f64_e32 v[16:17], v[10:11]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s0, v[4:5], s[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], -v[8:9], v[20:21], v[22:23]
v_fma_f64 v[10:11], -v[10:11], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[8:9], s[6:7], v[6:7]
v_div_fixup_f64 v[4:5], v[10:11], s[8:9], v[4:5]
s_mov_b32 s9, 0x3fc99999
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, s[8:9], s[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_add_f64 v[16:17], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[16:17], v[12:13], 0x401c0000, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[14:15], vcc_lo, v[12:13], s[8:9], v[12:13]
v_add_f64 v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[14:15], v[8:9]
v_fma_f64 v[6:7], -v[12:13], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_fma_f64 v[6:7], v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[10:11], v[8:9], v[16:17]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_f64 v[4:5], v[6:7], v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], s[8:9], v[12:13]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumArraysOnGPUPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumArraysOnGPUPdS_S_i, .Lfunc_end0-_Z14sumArraysOnGPUPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumArraysOnGPUPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sumArraysOnGPUPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e740a_00000000-6_sumArraysOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
.type _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i, @function
_Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumArraysOnGPUPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i, .-_Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
.globl _Z14sumArraysOnGPUPdS_S_i
.type _Z14sumArraysOnGPUPdS_S_i, @function
_Z14sumArraysOnGPUPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14sumArraysOnGPUPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumArraysOnGPUPdS_S_i, .-_Z14sumArraysOnGPUPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumArraysOnGPUPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumArraysOnGPUPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumArraysOnGPU.hip"
.globl _Z29__device_stub__sumArraysOnGPUPdS_S_i # -- Begin function _Z29__device_stub__sumArraysOnGPUPdS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__sumArraysOnGPUPdS_S_i,@function
_Z29__device_stub__sumArraysOnGPUPdS_S_i: # @_Z29__device_stub__sumArraysOnGPUPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumArraysOnGPUPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sumArraysOnGPUPdS_S_i, .Lfunc_end0-_Z29__device_stub__sumArraysOnGPUPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumArraysOnGPUPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumArraysOnGPUPdS_S_i,@object # @_Z14sumArraysOnGPUPdS_S_i
.section .rodata,"a",@progbits
.globl _Z14sumArraysOnGPUPdS_S_i
.p2align 3, 0x0
_Z14sumArraysOnGPUPdS_S_i:
.quad _Z29__device_stub__sumArraysOnGPUPdS_S_i
.size _Z14sumArraysOnGPUPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumArraysOnGPUPdS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumArraysOnGPUPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumArraysOnGPUPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} | code for sm_80
Function : _Z22kernel_pow_grad_devicePiiS_S_bj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*00a0*/ I2F R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000e240008201400 */
/*00b0*/ FMUL R3, R2, 0.5 ; /* 0x3f00000002037820 */
/* 0x001fcc0000400000 */
/*00c0*/ FRND.TRUNC R3, R3 ; /* 0x0000000300037307 */
/* 0x000e24000020d000 */
/*00d0*/ FADD R5, R3, R3 ; /* 0x0000000303057221 */
/* 0x001fe20000000000 */
/*00e0*/ @!P0 BRA 0x7f0 ; /* 0x0000070000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000200 */
/*0100*/ FADD R3, R2, -R5 ; /* 0x8000000502037221 */
/* 0x000fe20000000000 */
/*0110*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf25270 */
/*0120*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*0130*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e0009 */
/*0140*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x001ea2000c1e1900 */
/*0150*/ SEL R4, R0, RZ, !P1 ; /* 0x000000ff00047207 */
/* 0x000fc80004800000 */
/*0160*/ LEA R10, P0, R4, c[0x0][0x170], 0x2 ; /* 0x00005c00040a7a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R11, R4, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d00040b7a11 */
/* 0x000fca00000f14ff */
/*0180*/ LDG.E R4, [R10.64] ; /* 0x000000060a047981 */
/* 0x000162000c1e1900 */
/*0190*/ MOV R15, 0x3a2c32e4 ; /* 0x3a2c32e4000f7802 */
/* 0x000fe20000000f00 */
/*01a0*/ BSSY B0, 0x740 ; /* 0x0000059000007945 */
/* 0x000fe20003800000 */
/*01b0*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x004e620000201400 */
/*01c0*/ ISETP.NE.AND P3, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f65270 */
/*01d0*/ FMUL R6, |R7|.reuse, 16777216 ; /* 0x4b80000007067820 */
/* 0x042fe20000400200 */
/*01e0*/ FSETP.GEU.AND P0, PT, |R7|, 1.175494350822287508e-38, PT ; /* 0x008000000700780b */
/* 0x000fc80003f0e200 */
/*01f0*/ FSEL R6, R6, |R7|, !P0 ; /* 0x4000000706067208 */
/* 0x000fc80004000000 */
/*0200*/ IADD3 R12, R6, -0x3f3504f3, RZ ; /* 0xc0cafb0d060c7810 */
/* 0x000fc80007ffe0ff */
/*0210*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fc800078ec0ff */
/*0220*/ IADD3 R6, R6, -R13, RZ ; /* 0x8000000d06067210 */
/* 0x000fe40007ffe0ff */
/*0230*/ I2F R13, R13 ; /* 0x0000000d000d7306 */
/* 0x000fe60000201400 */
/*0240*/ FADD R12, R6.reuse, 1 ; /* 0x3f800000060c7421 */
/* 0x040fe40000000000 */
/*0250*/ FADD R8, R6, -1 ; /* 0xbf80000006087421 */
/* 0x000fe20000000000 */
/*0260*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */
/* 0x000fc60000000000 */
/*0270*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000001000 */
/*0280*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */
/* 0x000fc80000000000 */
/*0290*/ FMUL R11, R12, R9 ; /* 0x000000090c0b7220 */
/* 0x001fe40000400000 */
/*02a0*/ FFMA R9, R13, 1.1920928955078125e-07, R6 ; /* 0x340000000d097823 */
/* 0x000fe40000000006 */
/*02b0*/ FADD R6, R8, -R11 ; /* 0x8000000b08067221 */
/* 0x000fe40000000000 */
/*02c0*/ FMUL R10, R11.reuse, R11 ; /* 0x0000000b0b0a7220 */
/* 0x040fe40000400000 */
/*02d0*/ FADD R14, R6, R6 ; /* 0x00000006060e7221 */
/* 0x000fe40000000000 */
/*02e0*/ FFMA R6, R11, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b0b067823 */
/* 0x000fc40000000009 */
/*02f0*/ FFMA R15, R10, R15, 0.0032181653659790754318 ; /* 0x3b52e7db0a0f7423 */
/* 0x000fe4000000000f */
/*0300*/ FFMA R13, R8, -R11, R14 ; /* 0x8000000b080d7223 */
/* 0x000fe4000000000e */
/*0310*/ FADD R8, R9, -R6 ; /* 0x8000000609087221 */
/* 0x000fe40000000000 */
/*0320*/ FFMA R15, R10, R15, 0.018033718690276145935 ; /* 0x3c93bb730a0f7423 */
/* 0x000fe4000000000f */
/*0330*/ FMUL R13, R12, R13 ; /* 0x0000000d0c0d7220 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R8, R11, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b0b087823 */
/* 0x000fc40000000008 */
/*0350*/ FFMA R15, R10.reuse, R15, 0.12022458761930465698 ; /* 0x3df6384f0a0f7423 */
/* 0x040fe4000000000f */
/*0360*/ FFMA R8, R13, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b0d087823 */
/* 0x000fe40000000008 */
/*0370*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fe40000400000 */
/*0380*/ FFMA R8, R11, 1.9251366722983220825e-08, R8 ; /* 0x32a55e340b087823 */
/* 0x000fe40000000008 */
/*0390*/ FMUL R9, R10, 3 ; /* 0x404000000a097820 */
/* 0x000fc80000400000 */
/*03a0*/ FFMA R8, R13, R9, R8 ; /* 0x000000090d087223 */
/* 0x000fc80000000008 */
/*03b0*/ FFMA R11, R11, R10, R8 ; /* 0x0000000a0b0b7223 */
/* 0x000fc80000000008 */
/*03c0*/ FADD R9, R6, R11 ; /* 0x0000000b06097221 */
/* 0x000fc80000000000 */
/*03d0*/ FMUL R8, R2, R9.reuse ; /* 0x0000000902087220 */
/* 0x080fe40000400000 */
/*03e0*/ FADD R6, -R6, R9 ; /* 0x0000000906067221 */
/* 0x000fe40000000100 */
/*03f0*/ FRND R13, R8 ; /* 0x00000008000d7307 */
/* 0x000e220000201000 */
/*0400*/ FFMA R9, R2, R9, -R8 ; /* 0x0000000902097223 */
/* 0x000fe20000000808 */
/*0410*/ FSETP.GEU.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe20003f4e000 */
/*0420*/ FADD R11, R11, -R6 ; /* 0x800000060b0b7221 */
/* 0x000fc80000000000 */
/*0430*/ FFMA R9, R2, R11, R9 ; /* 0x0000000b02097223 */
/* 0x000fe20000000009 */
/*0440*/ HFMA2.MMA R11, -RZ, RZ, 0.64013671875, -15.109375 ; /* 0x391fcb8eff0b7435 */
/* 0x000fe200000001ff */
/*0450*/ F2I.NTZ R10, R8 ; /* 0x00000008000a7305 */
/* 0x0002a20000203100 */
/*0460*/ FADD R6, R8, -R13 ; /* 0x8000000d08067221 */
/* 0x001fe20000000000 */
/*0470*/ FSETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x000fc60003f04000 */
/*0480*/ FADD R6, R9, R6 ; /* 0x0000000609067221 */
/* 0x000fc80000000000 */
/*0490*/ FFMA R9, R6, R11, 0.0013391353422775864601 ; /* 0x3aaf85ed06097423 */
/* 0x000fe2000000000b */
/*04a0*/ SEL R11, RZ, 0x83000000, P0 ; /* 0x83000000ff0b7807 */
/* 0x000fe40000000000 */
/*04b0*/ FSETP.GT.AND P0, PT, |R8|, 152, PT ; /* 0x431800000800780b */
/* 0x000fe20003f04200 */
/*04c0*/ FFMA R9, R6, R9, 0.0096188392490148544312 ; /* 0x3c1d985606097423 */
/* 0x000fe20000000009 */
/*04d0*/ MOV R8, 0x3f800000 ; /* 0x3f80000000087802 */
/* 0x002fc60000000f00 */
/*04e0*/ FFMA R9, R6, R9, 0.055503588169813156128 ; /* 0x3d6357bb06097423 */
/* 0x000fc80000000009 */
/*04f0*/ FFMA R9, R6, R9, 0.24022644758224487305 ; /* 0x3e75fdec06097423 */
/* 0x000fc80000000009 */
/*0500*/ FFMA R9, R6, R9, 0.69314718246459960938 ; /* 0x3f31721806097423 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R6, R9, 1 ; /* 0x3f80000006097423 */
/* 0x000fe20000000009 */
/*0520*/ IADD3 R6, R11, 0x7f000000, RZ ; /* 0x7f0000000b067810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R11, R10, -R11, 0x17 ; /* 0x8000000b0a0b7211 */
/* 0x004fc600078eb8ff */
/*0540*/ FMUL R6, R9, R6 ; /* 0x0000000609067220 */
/* 0x000fc80000400000 */
/*0550*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x000fe20000400000 */
/*0560*/ @P0 FSEL R6, RZ, +INF , !P2 ; /* 0x7f800000ff060808 */
/* 0x000fe20005000000 */
/*0570*/ @!P3 BRA 0x730 ; /* 0x000001b00000b947 */
/* 0x000fea0003800000 */
/*0580*/ FSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f0c200 */
/*0590*/ FSETP.GTU.OR P0, PT, |R7|, +INF , P0 ; /* 0x7f8000000700780b */
/* 0x000fda000070c600 */
/*05a0*/ @P0 BRA 0x720 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f0d200 */
/*05c0*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fda0004702670 */
/*05d0*/ @P0 BRA 0x6a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f0d200 */
/*05f0*/ ISETP.EQ.AND P2, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fda0003f42270 */
/*0600*/ @!P0 BRA P2, 0x730 ; /* 0x0000012000008947 */
/* 0x000fea0001000000 */
/*0610*/ ISETP.GT.AND P0, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fe40003f04270 */
/*0620*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fd60000000f00 */
/*0630*/ @P0 BRA 0x730 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0640*/ FRND.FLOOR R5, R2 ; /* 0x0000000200057307 */
/* 0x000e220000205000 */
/*0650*/ FSETP.NEU.AND P2, PT, |R3|, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fc80003f4d200 */
/*0660*/ FSEL R8, -R6, R6, !P2 ; /* 0x0000000606087208 */
/* 0x000fe40005000100 */
/*0670*/ FSETP.NEU.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x001fc80003f0d000 */
/*0680*/ FSEL R8, R8, +QNAN , !P0 ; /* 0x7fffffff08087808 */
/* 0x000fe20004000000 */
/*0690*/ BRA 0x730 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*06a0*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*06b0*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe20000000000 */
/*06c0*/ FSETP.NEU.AND P2, PT, |R3|, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fe40003f4d200 */
/*06d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*06e0*/ @!P0 LOP3.LUT R7, R7, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000007078812 */
/* 0x000fc800078e3cff */
/*06f0*/ @P2 LOP3.LUT R7, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07072812 */
/* 0x000fc800078ec0ff */
/*0700*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0710*/ BRA 0x730 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0720*/ FADD R8, R2, R7 ; /* 0x0000000702087221 */
/* 0x000fe40000000000 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*0750*/ LEA R6, P0, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000067a11 */
/* 0x000fe200078010ff */
/*0760*/ IMAD R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a24 */
/* 0x020fe200078e02ff */
/*0770*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe40000000f00 */
/*0780*/ LEA.HI.X R7, R0, c[0x0][0x17c], RZ, 0x2, P0 ; /* 0x00005f0000077a11 */
/* 0x000fc600000f14ff */
/*0790*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*07a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06070 */
/*07b0*/ IMAD R5, R8, R5, RZ ; /* 0x0000000508057224 */
/* 0x001fca00078e02ff */
/*07c0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001ee000c101906 */
/*07d0*/ @!P0 BRA 0x120 ; /* 0xfffff94000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000200 */
/*0800*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc8000bf25270 */
/*0810*/ SEL R2, R0, RZ, !P1 ; /* 0x000000ff00027207 */
/* 0x001fc80004800000 */
/*0820*/ LEA R4, P0, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x000fc800078010ff */
/*0830*/ LEA.HI.X R5, R2, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f14ff */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0850*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0860*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fd20000000f00 */
/*0870*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fc800078e0000 */
/*0880*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0890*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06070 */
/*08a0*/ IMAD R7, R4, c[0x0][0x168], RZ ; /* 0x00005a0004077a24 */
/* 0x004fca00078e02ff */
/*08b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101906 */
/*08c0*/ @!P0 BRA 0x810 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} | .file "tmpxft_00112c11_00000000-6_kernel_pow_grad_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3493:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3493:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
.type _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj, @function
_Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj:
.LFB3515:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r9d, 12(%rsp)
movb %r8b, 32(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kernel_pow_grad_devicePiiS_S_bj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3515:
.size _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj, .-_Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.type _Z22kernel_pow_grad_devicePiiS_S_bj, @function
_Z22kernel_pow_grad_devicePiiS_S_bj:
.LFB3516:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3516:
.size _Z22kernel_pow_grad_devicePiiS_S_bj, .-_Z22kernel_pow_grad_devicePiiS_S_bj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22kernel_pow_grad_devicePiiS_S_bj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3518:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kernel_pow_grad_devicePiiS_S_bj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3518:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22kernel_pow_grad_devicePiiS_S_bj
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.p2align 8
.type _Z22kernel_pow_grad_devicePiiS_S_bj,@function
_Z22kernel_pow_grad_devicePiiS_S_bj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x24
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s13, s[0:1], 0x20
s_load_b32 s11, s[0:1], 0x8
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s14, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s13, 0
s_mov_b32 s13, 0
s_cselect_b32 s3, -1, 0
s_add_i32 s0, s11, -1
s_mul_i32 s12, s2, s12
v_cvt_f32_i32_e32 v0, s0
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v7, v[5:6], off
v_mov_b32_e32 v6, 0
v_cndmask_b32_e64 v5, v1, 0, s3
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 1, v7
v_cvt_f32_i32_e32 v7, v7
v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e32 vcc_lo, 0, v6
v_trunc_f32_e32 v8, v6
v_mul_f32_e32 v9, 0.5, v6
v_cndmask_b32_e32 v7, 1.0, v7, vcc_lo
v_cmp_eq_f32_e64 s0, v8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v8, v9
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v5, s11
v_frexp_mant_f32_e64 v10, |v7|
v_cmp_neq_f32_e64 s2, v8, v9
v_frexp_exp_i32_f32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v10
v_cndmask_b32_e64 v12, 0, 1, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e64 v9, s1, 0, v11, s1
s_and_b32 s1, s0, s2
v_ldexp_f32 v8, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v9, v9
v_cndmask_b32_e64 v10, 1.0, v7, s1
v_cndmask_b32_e64 v11, 0, v7, s1
v_add_f32_e32 v12, 1.0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v13, -1.0, v8 :: v_dual_mul_f32 v16, 0x3f317218, v9
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v17, v13, v14
v_add_f32_e32 v15, -1.0, v12
v_cmp_gt_f32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v15
v_fma_f32 v15, v9, 0x3f317218, -v16
v_fmac_f32_e32 v15, 0xb102e308, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v18, v16, v15
v_dual_mul_f32 v9, v12, v17 :: v_dual_sub_f32 v16, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v17, v12, -v9
v_fmac_f32_e32 v12, v17, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v15, v16
v_add_f32_e32 v15, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v13, v15 :: v_dual_sub_f32 v9, v15, v9
v_sub_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v12
v_sub_f32_e32 v12, v13, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v12
v_add_f32_e32 v9, v16, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v14, v9
v_add_f32_e32 v12, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v13, v12, v17
v_mul_f32_e32 v14, v12, v12
v_ldexp_f32 v15, v12, 1
v_sub_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v12, v12, -v14
v_add_f32_e32 v16, v9, v9
v_ldexp_f32 v17, v9, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v12, v16
v_add_f32_e32 v16, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v14, v16, v14
v_mul_f32_e32 v20, v12, v16
v_fmaak_f32 v19, s14, v16, 0x3e91f4c4
v_sub_f32_e32 v13, v13, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, v16, v12, -v20
v_fmac_f32_e32 v14, v16, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v19, v16, v19, 0x3ecccdef :: v_dual_fmac_f32 v14, v13, v12
v_mul_f32_e32 v21, v16, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v20, v14
v_fma_f32 v9, v16, v19, -v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v12, v20 :: v_dual_fmac_f32 v9, v13, v19
v_dual_sub_f32 v14, v14, v16 :: v_dual_add_f32 v13, v21, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v20, 0x3f2aaaaa, v13
v_dual_sub_f32 v19, v13, v21 :: v_dual_add_f32 v16, 0xbf2aaaaa, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v19
v_sub_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, 0x31739010, v9
v_add_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v20, v9
v_sub_f32_e32 v16, v20, v13
v_mul_f32_e32 v19, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v16
v_fma_f32 v16, v12, v13, -v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v12, v9
v_fmac_f32_e32 v16, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v19, v16
v_dual_add_f32 v12, v15, v9 :: v_dual_sub_f32 v13, v9, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v14, v12, v15
v_sub_f32_e32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v14
v_add_f32_e32 v13, v17, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v13, v9
v_add_f32_e32 v13, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v18, v13
v_dual_sub_f32 v12, v13, v12 :: v_dual_sub_f32 v15, v14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v12 :: v_dual_sub_f32 v12, v14, v15
v_dual_add_f32 v16, v8, v9 :: v_dual_sub_f32 v13, v13, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v18, v12
v_sub_f32_e32 v15, v16, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v12, v13, v12 :: v_dual_sub_f32 v13, v16, v15
v_add_f32_e32 v12, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v8, v8, v13 :: v_dual_sub_f32 v9, v9, v15
v_add_f32_e32 v13, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v9, v8
v_sub_f32_e32 v9, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v12, v9
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v13, v8
v_sub_f32_e32 v12, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v6, v9 :: v_dual_sub_f32 v8, v8, v12
v_fma_f32 v9, v6, v9, -v13
v_cmp_class_f32_e64 s1, v13, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v6, v8
v_add_f32_e32 v6, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v6, v13, s1
v_sub_f32_e32 v6, v6, v13
v_cmp_eq_f32_e64 s1, 0x42b17218, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v9, v6
v_cndmask_b32_e64 v12, 0, 0x37000000, s1
v_cmp_neq_f32_e64 s1, 0x7f800000, |v8|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v12
v_cndmask_b32_e64 v6, 0, v6, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v9, 0x3fb8aa3b, v8 :: v_dual_add_f32 v6, v12, v6
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v8
v_fma_f32 v12, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v12, 0x32a5705f, v8 :: v_dual_sub_f32 v9, v9, v13
v_add_f32_e32 v9, v9, v12
v_cvt_i32_f32_e32 v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v9, v12
v_cndmask_b32_e64 v9, 0, v9, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0x7f800000, v9, s1
v_fma_f32 v6, v8, v6, v8
v_cmp_eq_f32_e64 s1, 0x7f800000, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v6, v8, s1
v_bfi_b32 v6, 0x7fffffff, v6, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0x7fc00000, v6, s0
v_cmp_gt_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v6, v6, v8, s0
v_cmp_eq_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s1, vcc_lo, s0
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_cndmask_b32_e64 v7, 0x7f800000, 0, s1
s_or_b32 s13, vcc_lo, s13
v_bfi_b32 v7, 0x7fffffff, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v6, v7, s0
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
v_mul_lo_u32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22kernel_pow_grad_devicePiiS_S_bj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22kernel_pow_grad_devicePiiS_S_bj, .Lfunc_end0-_Z22kernel_pow_grad_devicePiiS_S_bj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 1
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22kernel_pow_grad_devicePiiS_S_bj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22kernel_pow_grad_devicePiiS_S_bj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_pow_grad_device(int *x, int power, int *grad, int *out, bool grad_is_scalar, unsigned int size) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
out[i] = grad[(grad_is_scalar) ? 0 : i] * ((int) power) * ((int) powf((float) x[i], power - 1));
}
} | .text
.file "kernel_pow_grad_device.hip"
.globl _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj # -- Begin function _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.p2align 4, 0x90
.type _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj,@function
_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj: # @_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movb %r8b, 15(%rsp)
movl %r9d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 15(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22kernel_pow_grad_devicePiiS_S_bj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj, .Lfunc_end0-_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22kernel_pow_grad_devicePiiS_S_bj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22kernel_pow_grad_devicePiiS_S_bj,@object # @_Z22kernel_pow_grad_devicePiiS_S_bj
.section .rodata,"a",@progbits
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.p2align 3, 0x0
_Z22kernel_pow_grad_devicePiiS_S_bj:
.quad _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.size _Z22kernel_pow_grad_devicePiiS_S_bj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22kernel_pow_grad_devicePiiS_S_bj"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22kernel_pow_grad_devicePiiS_S_bj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22kernel_pow_grad_devicePiiS_S_bj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*00a0*/ I2F R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000e240008201400 */
/*00b0*/ FMUL R3, R2, 0.5 ; /* 0x3f00000002037820 */
/* 0x001fcc0000400000 */
/*00c0*/ FRND.TRUNC R3, R3 ; /* 0x0000000300037307 */
/* 0x000e24000020d000 */
/*00d0*/ FADD R5, R3, R3 ; /* 0x0000000303057221 */
/* 0x001fe20000000000 */
/*00e0*/ @!P0 BRA 0x7f0 ; /* 0x0000070000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000200 */
/*0100*/ FADD R3, R2, -R5 ; /* 0x8000000502037221 */
/* 0x000fe20000000000 */
/*0110*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf25270 */
/*0120*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*0130*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e0009 */
/*0140*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x001ea2000c1e1900 */
/*0150*/ SEL R4, R0, RZ, !P1 ; /* 0x000000ff00047207 */
/* 0x000fc80004800000 */
/*0160*/ LEA R10, P0, R4, c[0x0][0x170], 0x2 ; /* 0x00005c00040a7a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R11, R4, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d00040b7a11 */
/* 0x000fca00000f14ff */
/*0180*/ LDG.E R4, [R10.64] ; /* 0x000000060a047981 */
/* 0x000162000c1e1900 */
/*0190*/ MOV R15, 0x3a2c32e4 ; /* 0x3a2c32e4000f7802 */
/* 0x000fe20000000f00 */
/*01a0*/ BSSY B0, 0x740 ; /* 0x0000059000007945 */
/* 0x000fe20003800000 */
/*01b0*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x004e620000201400 */
/*01c0*/ ISETP.NE.AND P3, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f65270 */
/*01d0*/ FMUL R6, |R7|.reuse, 16777216 ; /* 0x4b80000007067820 */
/* 0x042fe20000400200 */
/*01e0*/ FSETP.GEU.AND P0, PT, |R7|, 1.175494350822287508e-38, PT ; /* 0x008000000700780b */
/* 0x000fc80003f0e200 */
/*01f0*/ FSEL R6, R6, |R7|, !P0 ; /* 0x4000000706067208 */
/* 0x000fc80004000000 */
/*0200*/ IADD3 R12, R6, -0x3f3504f3, RZ ; /* 0xc0cafb0d060c7810 */
/* 0x000fc80007ffe0ff */
/*0210*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fc800078ec0ff */
/*0220*/ IADD3 R6, R6, -R13, RZ ; /* 0x8000000d06067210 */
/* 0x000fe40007ffe0ff */
/*0230*/ I2F R13, R13 ; /* 0x0000000d000d7306 */
/* 0x000fe60000201400 */
/*0240*/ FADD R12, R6.reuse, 1 ; /* 0x3f800000060c7421 */
/* 0x040fe40000000000 */
/*0250*/ FADD R8, R6, -1 ; /* 0xbf80000006087421 */
/* 0x000fe20000000000 */
/*0260*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */
/* 0x000fc60000000000 */
/*0270*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000001000 */
/*0280*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */
/* 0x000fc80000000000 */
/*0290*/ FMUL R11, R12, R9 ; /* 0x000000090c0b7220 */
/* 0x001fe40000400000 */
/*02a0*/ FFMA R9, R13, 1.1920928955078125e-07, R6 ; /* 0x340000000d097823 */
/* 0x000fe40000000006 */
/*02b0*/ FADD R6, R8, -R11 ; /* 0x8000000b08067221 */
/* 0x000fe40000000000 */
/*02c0*/ FMUL R10, R11.reuse, R11 ; /* 0x0000000b0b0a7220 */
/* 0x040fe40000400000 */
/*02d0*/ FADD R14, R6, R6 ; /* 0x00000006060e7221 */
/* 0x000fe40000000000 */
/*02e0*/ FFMA R6, R11, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b0b067823 */
/* 0x000fc40000000009 */
/*02f0*/ FFMA R15, R10, R15, 0.0032181653659790754318 ; /* 0x3b52e7db0a0f7423 */
/* 0x000fe4000000000f */
/*0300*/ FFMA R13, R8, -R11, R14 ; /* 0x8000000b080d7223 */
/* 0x000fe4000000000e */
/*0310*/ FADD R8, R9, -R6 ; /* 0x8000000609087221 */
/* 0x000fe40000000000 */
/*0320*/ FFMA R15, R10, R15, 0.018033718690276145935 ; /* 0x3c93bb730a0f7423 */
/* 0x000fe4000000000f */
/*0330*/ FMUL R13, R12, R13 ; /* 0x0000000d0c0d7220 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R8, R11, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b0b087823 */
/* 0x000fc40000000008 */
/*0350*/ FFMA R15, R10.reuse, R15, 0.12022458761930465698 ; /* 0x3df6384f0a0f7423 */
/* 0x040fe4000000000f */
/*0360*/ FFMA R8, R13, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b0d087823 */
/* 0x000fe40000000008 */
/*0370*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fe40000400000 */
/*0380*/ FFMA R8, R11, 1.9251366722983220825e-08, R8 ; /* 0x32a55e340b087823 */
/* 0x000fe40000000008 */
/*0390*/ FMUL R9, R10, 3 ; /* 0x404000000a097820 */
/* 0x000fc80000400000 */
/*03a0*/ FFMA R8, R13, R9, R8 ; /* 0x000000090d087223 */
/* 0x000fc80000000008 */
/*03b0*/ FFMA R11, R11, R10, R8 ; /* 0x0000000a0b0b7223 */
/* 0x000fc80000000008 */
/*03c0*/ FADD R9, R6, R11 ; /* 0x0000000b06097221 */
/* 0x000fc80000000000 */
/*03d0*/ FMUL R8, R2, R9.reuse ; /* 0x0000000902087220 */
/* 0x080fe40000400000 */
/*03e0*/ FADD R6, -R6, R9 ; /* 0x0000000906067221 */
/* 0x000fe40000000100 */
/*03f0*/ FRND R13, R8 ; /* 0x00000008000d7307 */
/* 0x000e220000201000 */
/*0400*/ FFMA R9, R2, R9, -R8 ; /* 0x0000000902097223 */
/* 0x000fe20000000808 */
/*0410*/ FSETP.GEU.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe20003f4e000 */
/*0420*/ FADD R11, R11, -R6 ; /* 0x800000060b0b7221 */
/* 0x000fc80000000000 */
/*0430*/ FFMA R9, R2, R11, R9 ; /* 0x0000000b02097223 */
/* 0x000fe20000000009 */
/*0440*/ HFMA2.MMA R11, -RZ, RZ, 0.64013671875, -15.109375 ; /* 0x391fcb8eff0b7435 */
/* 0x000fe200000001ff */
/*0450*/ F2I.NTZ R10, R8 ; /* 0x00000008000a7305 */
/* 0x0002a20000203100 */
/*0460*/ FADD R6, R8, -R13 ; /* 0x8000000d08067221 */
/* 0x001fe20000000000 */
/*0470*/ FSETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x000fc60003f04000 */
/*0480*/ FADD R6, R9, R6 ; /* 0x0000000609067221 */
/* 0x000fc80000000000 */
/*0490*/ FFMA R9, R6, R11, 0.0013391353422775864601 ; /* 0x3aaf85ed06097423 */
/* 0x000fe2000000000b */
/*04a0*/ SEL R11, RZ, 0x83000000, P0 ; /* 0x83000000ff0b7807 */
/* 0x000fe40000000000 */
/*04b0*/ FSETP.GT.AND P0, PT, |R8|, 152, PT ; /* 0x431800000800780b */
/* 0x000fe20003f04200 */
/*04c0*/ FFMA R9, R6, R9, 0.0096188392490148544312 ; /* 0x3c1d985606097423 */
/* 0x000fe20000000009 */
/*04d0*/ MOV R8, 0x3f800000 ; /* 0x3f80000000087802 */
/* 0x002fc60000000f00 */
/*04e0*/ FFMA R9, R6, R9, 0.055503588169813156128 ; /* 0x3d6357bb06097423 */
/* 0x000fc80000000009 */
/*04f0*/ FFMA R9, R6, R9, 0.24022644758224487305 ; /* 0x3e75fdec06097423 */
/* 0x000fc80000000009 */
/*0500*/ FFMA R9, R6, R9, 0.69314718246459960938 ; /* 0x3f31721806097423 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R6, R9, 1 ; /* 0x3f80000006097423 */
/* 0x000fe20000000009 */
/*0520*/ IADD3 R6, R11, 0x7f000000, RZ ; /* 0x7f0000000b067810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R11, R10, -R11, 0x17 ; /* 0x8000000b0a0b7211 */
/* 0x004fc600078eb8ff */
/*0540*/ FMUL R6, R9, R6 ; /* 0x0000000609067220 */
/* 0x000fc80000400000 */
/*0550*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x000fe20000400000 */
/*0560*/ @P0 FSEL R6, RZ, +INF , !P2 ; /* 0x7f800000ff060808 */
/* 0x000fe20005000000 */
/*0570*/ @!P3 BRA 0x730 ; /* 0x000001b00000b947 */
/* 0x000fea0003800000 */
/*0580*/ FSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f0c200 */
/*0590*/ FSETP.GTU.OR P0, PT, |R7|, +INF , P0 ; /* 0x7f8000000700780b */
/* 0x000fda000070c600 */
/*05a0*/ @P0 BRA 0x720 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f0d200 */
/*05c0*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fda0004702670 */
/*05d0*/ @P0 BRA 0x6a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f0d200 */
/*05f0*/ ISETP.EQ.AND P2, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fda0003f42270 */
/*0600*/ @!P0 BRA P2, 0x730 ; /* 0x0000012000008947 */
/* 0x000fea0001000000 */
/*0610*/ ISETP.GT.AND P0, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fe40003f04270 */
/*0620*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fd60000000f00 */
/*0630*/ @P0 BRA 0x730 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0640*/ FRND.FLOOR R5, R2 ; /* 0x0000000200057307 */
/* 0x000e220000205000 */
/*0650*/ FSETP.NEU.AND P2, PT, |R3|, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fc80003f4d200 */
/*0660*/ FSEL R8, -R6, R6, !P2 ; /* 0x0000000606087208 */
/* 0x000fe40005000100 */
/*0670*/ FSETP.NEU.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x001fc80003f0d000 */
/*0680*/ FSEL R8, R8, +QNAN , !P0 ; /* 0x7fffffff08087808 */
/* 0x000fe20004000000 */
/*0690*/ BRA 0x730 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*06a0*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*06b0*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe20000000000 */
/*06c0*/ FSETP.NEU.AND P2, PT, |R3|, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fe40003f4d200 */
/*06d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*06e0*/ @!P0 LOP3.LUT R7, R7, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000007078812 */
/* 0x000fc800078e3cff */
/*06f0*/ @P2 LOP3.LUT R7, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07072812 */
/* 0x000fc800078ec0ff */
/*0700*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0710*/ BRA 0x730 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0720*/ FADD R8, R2, R7 ; /* 0x0000000702087221 */
/* 0x000fe40000000000 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*0750*/ LEA R6, P0, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000067a11 */
/* 0x000fe200078010ff */
/*0760*/ IMAD R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a24 */
/* 0x020fe200078e02ff */
/*0770*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe40000000f00 */
/*0780*/ LEA.HI.X R7, R0, c[0x0][0x17c], RZ, 0x2, P0 ; /* 0x00005f0000077a11 */
/* 0x000fc600000f14ff */
/*0790*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*07a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06070 */
/*07b0*/ IMAD R5, R8, R5, RZ ; /* 0x0000000508057224 */
/* 0x001fca00078e02ff */
/*07c0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001ee000c101906 */
/*07d0*/ @!P0 BRA 0x120 ; /* 0xfffff94000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000200 */
/*0800*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc8000bf25270 */
/*0810*/ SEL R2, R0, RZ, !P1 ; /* 0x000000ff00027207 */
/* 0x001fc80004800000 */
/*0820*/ LEA R4, P0, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x000fc800078010ff */
/*0830*/ LEA.HI.X R5, R2, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f14ff */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0850*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0860*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fd20000000f00 */
/*0870*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fc800078e0000 */
/*0880*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0890*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06070 */
/*08a0*/ IMAD R7, R4, c[0x0][0x168], RZ ; /* 0x00005a0004077a24 */
/* 0x004fca00078e02ff */
/*08b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101906 */
/*08c0*/ @!P0 BRA 0x810 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22kernel_pow_grad_devicePiiS_S_bj
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.p2align 8
.type _Z22kernel_pow_grad_devicePiiS_S_bj,@function
_Z22kernel_pow_grad_devicePiiS_S_bj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x24
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s13, s[0:1], 0x20
s_load_b32 s11, s[0:1], 0x8
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s14, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s13, 0
s_mov_b32 s13, 0
s_cselect_b32 s3, -1, 0
s_add_i32 s0, s11, -1
s_mul_i32 s12, s2, s12
v_cvt_f32_i32_e32 v0, s0
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v7, v[5:6], off
v_mov_b32_e32 v6, 0
v_cndmask_b32_e64 v5, v1, 0, s3
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 1, v7
v_cvt_f32_i32_e32 v7, v7
v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e32 vcc_lo, 0, v6
v_trunc_f32_e32 v8, v6
v_mul_f32_e32 v9, 0.5, v6
v_cndmask_b32_e32 v7, 1.0, v7, vcc_lo
v_cmp_eq_f32_e64 s0, v8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v8, v9
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v5, s11
v_frexp_mant_f32_e64 v10, |v7|
v_cmp_neq_f32_e64 s2, v8, v9
v_frexp_exp_i32_f32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v10
v_cndmask_b32_e64 v12, 0, 1, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e64 v9, s1, 0, v11, s1
s_and_b32 s1, s0, s2
v_ldexp_f32 v8, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v9, v9
v_cndmask_b32_e64 v10, 1.0, v7, s1
v_cndmask_b32_e64 v11, 0, v7, s1
v_add_f32_e32 v12, 1.0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v13, -1.0, v8 :: v_dual_mul_f32 v16, 0x3f317218, v9
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v17, v13, v14
v_add_f32_e32 v15, -1.0, v12
v_cmp_gt_f32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v15
v_fma_f32 v15, v9, 0x3f317218, -v16
v_fmac_f32_e32 v15, 0xb102e308, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v18, v16, v15
v_dual_mul_f32 v9, v12, v17 :: v_dual_sub_f32 v16, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v17, v12, -v9
v_fmac_f32_e32 v12, v17, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v15, v16
v_add_f32_e32 v15, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v13, v15 :: v_dual_sub_f32 v9, v15, v9
v_sub_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v12
v_sub_f32_e32 v12, v13, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v12
v_add_f32_e32 v9, v16, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v14, v9
v_add_f32_e32 v12, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v13, v12, v17
v_mul_f32_e32 v14, v12, v12
v_ldexp_f32 v15, v12, 1
v_sub_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v12, v12, -v14
v_add_f32_e32 v16, v9, v9
v_ldexp_f32 v17, v9, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v12, v16
v_add_f32_e32 v16, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v14, v16, v14
v_mul_f32_e32 v20, v12, v16
v_fmaak_f32 v19, s14, v16, 0x3e91f4c4
v_sub_f32_e32 v13, v13, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, v16, v12, -v20
v_fmac_f32_e32 v14, v16, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v19, v16, v19, 0x3ecccdef :: v_dual_fmac_f32 v14, v13, v12
v_mul_f32_e32 v21, v16, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v20, v14
v_fma_f32 v9, v16, v19, -v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v12, v20 :: v_dual_fmac_f32 v9, v13, v19
v_dual_sub_f32 v14, v14, v16 :: v_dual_add_f32 v13, v21, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v20, 0x3f2aaaaa, v13
v_dual_sub_f32 v19, v13, v21 :: v_dual_add_f32 v16, 0xbf2aaaaa, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v19
v_sub_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, 0x31739010, v9
v_add_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v20, v9
v_sub_f32_e32 v16, v20, v13
v_mul_f32_e32 v19, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v16
v_fma_f32 v16, v12, v13, -v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v12, v9
v_fmac_f32_e32 v16, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v19, v16
v_dual_add_f32 v12, v15, v9 :: v_dual_sub_f32 v13, v9, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v14, v12, v15
v_sub_f32_e32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v14
v_add_f32_e32 v13, v17, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v13, v9
v_add_f32_e32 v13, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v18, v13
v_dual_sub_f32 v12, v13, v12 :: v_dual_sub_f32 v15, v14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v12 :: v_dual_sub_f32 v12, v14, v15
v_dual_add_f32 v16, v8, v9 :: v_dual_sub_f32 v13, v13, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v18, v12
v_sub_f32_e32 v15, v16, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v12, v13, v12 :: v_dual_sub_f32 v13, v16, v15
v_add_f32_e32 v12, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v8, v8, v13 :: v_dual_sub_f32 v9, v9, v15
v_add_f32_e32 v13, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v9, v8
v_sub_f32_e32 v9, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v12, v9
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v13, v8
v_sub_f32_e32 v12, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v6, v9 :: v_dual_sub_f32 v8, v8, v12
v_fma_f32 v9, v6, v9, -v13
v_cmp_class_f32_e64 s1, v13, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v6, v8
v_add_f32_e32 v6, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v6, v13, s1
v_sub_f32_e32 v6, v6, v13
v_cmp_eq_f32_e64 s1, 0x42b17218, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v9, v6
v_cndmask_b32_e64 v12, 0, 0x37000000, s1
v_cmp_neq_f32_e64 s1, 0x7f800000, |v8|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v12
v_cndmask_b32_e64 v6, 0, v6, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v9, 0x3fb8aa3b, v8 :: v_dual_add_f32 v6, v12, v6
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v8
v_fma_f32 v12, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v12, 0x32a5705f, v8 :: v_dual_sub_f32 v9, v9, v13
v_add_f32_e32 v9, v9, v12
v_cvt_i32_f32_e32 v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v9, v12
v_cndmask_b32_e64 v9, 0, v9, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0x7f800000, v9, s1
v_fma_f32 v6, v8, v6, v8
v_cmp_eq_f32_e64 s1, 0x7f800000, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v6, v8, s1
v_bfi_b32 v6, 0x7fffffff, v6, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0x7fc00000, v6, s0
v_cmp_gt_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v6, v6, v8, s0
v_cmp_eq_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s1, vcc_lo, s0
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_cndmask_b32_e64 v7, 0x7f800000, 0, s1
s_or_b32 s13, vcc_lo, s13
v_bfi_b32 v7, 0x7fffffff, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v6, v7, s0
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
v_mul_lo_u32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22kernel_pow_grad_devicePiiS_S_bj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22kernel_pow_grad_devicePiiS_S_bj, .Lfunc_end0-_Z22kernel_pow_grad_devicePiiS_S_bj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 1
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22kernel_pow_grad_devicePiiS_S_bj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22kernel_pow_grad_devicePiiS_S_bj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112c11_00000000-6_kernel_pow_grad_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3493:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3493:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
.type _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj, @function
_Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj:
.LFB3515:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r9d, 12(%rsp)
movb %r8b, 32(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kernel_pow_grad_devicePiiS_S_bj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3515:
.size _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj, .-_Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.type _Z22kernel_pow_grad_devicePiiS_S_bj, @function
_Z22kernel_pow_grad_devicePiiS_S_bj:
.LFB3516:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z49__device_stub__Z22kernel_pow_grad_devicePiiS_S_bjPiiS_S_bj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3516:
.size _Z22kernel_pow_grad_devicePiiS_S_bj, .-_Z22kernel_pow_grad_devicePiiS_S_bj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22kernel_pow_grad_devicePiiS_S_bj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3518:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kernel_pow_grad_devicePiiS_S_bj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3518:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_pow_grad_device.hip"
.globl _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj # -- Begin function _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.p2align 4, 0x90
.type _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj,@function
_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj: # @_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movb %r8b, 15(%rsp)
movl %r9d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 15(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22kernel_pow_grad_devicePiiS_S_bj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj, .Lfunc_end0-_Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22kernel_pow_grad_devicePiiS_S_bj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22kernel_pow_grad_devicePiiS_S_bj,@object # @_Z22kernel_pow_grad_devicePiiS_S_bj
.section .rodata,"a",@progbits
.globl _Z22kernel_pow_grad_devicePiiS_S_bj
.p2align 3, 0x0
_Z22kernel_pow_grad_devicePiiS_S_bj:
.quad _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.size _Z22kernel_pow_grad_devicePiiS_S_bj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22kernel_pow_grad_devicePiiS_S_bj"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__kernel_pow_grad_devicePiiS_S_bj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22kernel_pow_grad_devicePiiS_S_bj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
cudaMalloc((void **)&device_world, worldSize);
cudaMalloc((void **)&device_buffer_world, worldSize);
cudaMemcpy(device_world, host_world, worldSize, cudaMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
cudaMemcpy(host_world, device_world, worldSize, cudaMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
cudaFree(device_world);
cudaFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} | code for sm_80
Function : _Z17game_of_life_turnPhS_s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ LDC.U16 R0, c[0x0][0x170] ; /* 0x00005c00ff007b82 */
/* 0x000e220000000400 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea80000002500 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000ea20000002100 */
/*0070*/ PRMT R0, R0, 0x9910, RZ ; /* 0x0000991000007816 */
/* 0x001fc800000000ff */
/*0080*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*0090*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a00 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R8 ; /* 0x0000010003037a24 */
/* 0x002fe400078e0208 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x004fca00078e0204 */
/*00c0*/ IADD3 R11, R5.reuse, -0x1, R0 ; /* 0xffffffff050b7810 */
/* 0x040fe20007ffe000 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e220000001000 */
/*00e0*/ IADD3 R13, R5, 0x1, RZ ; /* 0x00000001050d7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x001fca0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD R9, R9, R7, RZ ; /* 0x0000000709097224 */
/* 0x002fc800078e02ff */
/*0130*/ IMAD.HI.U32 R2, R7, R9, R6 ; /* 0x0000000907027227 */
/* 0x000fe200078e0006 */
/*0140*/ IADD3 R7, R3.reuse, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x040fe40007ffe0ff */
/*0150*/ IADD3 R9, R3, -0x1, R0 ; /* 0xffffffff03097810 */
/* 0x000fc60007ffe000 */
/*0160*/ IMAD.HI.U32 R4, R2, R7, RZ ; /* 0x0000000702047227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.HI.U32 R6, R2, R11, RZ ; /* 0x0000000b02067227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a04 */
/*0190*/ IADD3 R6, -R6, RZ, RZ ; /* 0x000000ff06067210 */
/* 0x000fc60007ffe1ff */
/*01a0*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fe400078e0207 */
/*01b0*/ IMAD.HI.U32 R4, R2, R13, RZ ; /* 0x0000000d02047227 */
/* 0x000fc600078e00ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f06070 */
/*01d0*/ IMAD R11, R0, R6, R11 ; /* 0x00000006000b7224 */
/* 0x000fe400078e020b */
/*01e0*/ IMAD.HI.U32 R2, R2, R9, RZ ; /* 0x0000000902027227 */
/* 0x000fc600078e00ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fe20003f26070 */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a04 */
/*0210*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a02 */
/*0220*/ IMAD R13, R0.reuse, R4, R13 ; /* 0x00000004000d7224 */
/* 0x040fe400078e020d */
/*0230*/ IMAD R9, R0, R2, R9 ; /* 0x0000000200097224 */
/* 0x000fe200078e0209 */
/*0240*/ LOP3.LUT R2, RZ, R0.reuse, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x080fe200078e33ff */
/*0250*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*0260*/ ISETP.GE.U32.AND P3, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fc40003f66070 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R9, R0.reuse, PT ; /* 0x000000000900720c */
/* 0x080fe40003f06070 */
/*0280*/ @P1 IADD3 R11, -R0, R11, RZ ; /* 0x0000000b000b1210 */
/* 0x000fe40007ffe1ff */
/*0290*/ ISETP.GE.U32.AND P1, PT, R7, R0.reuse, PT ; /* 0x000000000700720c */
/* 0x080fe40003f26070 */
/*02a0*/ ISETP.GE.U32.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fca0003f46070 */
/*02b0*/ @P3 IMAD.IADD R13, R13, 0x1, -R0.reuse ; /* 0x000000010d0d3824 */
/* 0x100fe200078e0a00 */
/*02c0*/ ISETP.NE.U32.AND P3, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f65070 */
/*02d0*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fc600078e0a00 */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R13, R0.reuse, PT ; /* 0x000000000d00720c */
/* 0x080fe20003f06070 */
/*02f0*/ @P1 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107071824 */
/* 0x000fe200078e0a00 */
/*0300*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f26070 */
/*0310*/ @P2 IADD3 R11, -R0, R11, RZ ; /* 0x0000000b000b2210 */
/* 0x000fe40007ffe1ff */
/*0320*/ SEL R7, R2.reuse, R7, !P3 ; /* 0x0000000702077207 */
/* 0x040fe40005800000 */
/*0330*/ SEL R4, R2, R11, !P3 ; /* 0x0000000b02047207 */
/* 0x000fc60005800000 */
/*0340*/ IMAD R12, R0.reuse, R7.reuse, R5 ; /* 0x00000007000c7224 */
/* 0x0c0fe400078e0205 */
/*0350*/ @P0 IMAD.IADD R13, R13, 0x1, -R0 ; /* 0x000000010d0d0824 */
/* 0x000fe400078e0a00 */
/*0360*/ IMAD R14, R0, R7, R4 ; /* 0x00000007000e7224 */
/* 0x000fe400078e0204 */
/*0370*/ @P1 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109091824 */
/* 0x000fe200078e0a00 */
/*0380*/ SEL R10, R2, R13, !P3 ; /* 0x0000000d020a7207 */
/* 0x000fe40005800000 */
/*0390*/ IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e7a10 */
/* 0x000fe40007f1e0ff */
/*03a0*/ SEL R11, R2, R9, !P3 ; /* 0x00000009020b7207 */
/* 0x000fe20005800000 */
/*03b0*/ IMAD R7, R0, R7, R10 ; /* 0x0000000700077224 */
/* 0x000fe200078e020a */
/*03c0*/ IADD3 R12, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe20007f3e0ff */
/*03d0*/ IMAD R6, R0, R3, R4 ; /* 0x0000000300067224 */
/* 0x000fc400078e0204 */
/*03e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f7624 */
/* 0x000fe200000e06ff */
/*03f0*/ IADD3 R8, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007087a10 */
/* 0x000fe20007f1e0ff */
/*0400*/ IMAD R16, R0.reuse, R11, R4 ; /* 0x0000000b00107224 */
/* 0x040fe200078e0204 */
/*0410*/ IADD3.X R13, RZ, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900ff0d7a10 */
/* 0x000fe20000ffe4ff */
/*0420*/ IMAD R4, R0, R3, R10.reuse ; /* 0x0000000300047224 */
/* 0x100fe200078e020a */
/*0430*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe20007f3e0ff */
/*0440*/ IMAD R18, R0, R11.reuse, R10 ; /* 0x0000000b00127224 */
/* 0x080fe200078e020a */
/*0450*/ LDG.E.U8 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x0000a2000c1e1100 */
/*0460*/ IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff097624 */
/* 0x000fe200000e06ff */
/*0470*/ IADD3 R10, P0, R4, c[0x0][0x160], RZ ; /* 0x00005800040a7a10 */
/* 0x000fe20007f1e0ff */
/*0480*/ IMAD R11, R0, R11, R5 ; /* 0x0000000b000b7224 */
/* 0x000fe200078e0205 */
/*0490*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1100 */
/*04a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fc600008e06ff */
/*04b0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*04c0*/ IADD3 R14, P1, R16, c[0x0][0x160], RZ ; /* 0x00005800100e7a10 */
/* 0x001fe40007f3e0ff */
/*04d0*/ IADD3 R16, P2, R11, c[0x0][0x160], RZ ; /* 0x000058000b107a10 */
/* 0x000fe20007f5e0ff */
/*04e0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0b7624 */
/* 0x000fe200000e06ff */
/*04f0*/ IADD3.X R15, RZ, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900ff0f7a10 */
/* 0x000fe20000ffe4ff */
/*0500*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1100 */
/*0510*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe20007f1e0ff */
/*0520*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0530*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1100 */
/*0540*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x000fc400000e06ff */
/*0550*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f28000c1e1100 */
/*0560*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1100 */
/*0570*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f62000c1e1100 */
/*0580*/ BSSY B0, 0x6b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0590*/ HFMA2.MMA R4, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff047435 */
/* 0x000fe200000001ff */
/*05a0*/ IMAD R0, R0, R3, R5 ; /* 0x0000000300007224 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R2, R8, R13, R2 ; /* 0x0000000d08027210 */
/* 0x004fc80007ffe002 */
/*05c0*/ IADD3 R2, R10, R2, R7 ; /* 0x000000020a027210 */
/* 0x008fc80007ffe007 */
/*05d0*/ IADD3 R2, R16, R2, R15 ; /* 0x0000000210027210 */
/* 0x010fca0007ffe00f */
/*05e0*/ IMAD.IADD R2, R2, 0x1, R19 ; /* 0x0000000102027824 */
/* 0x020fca00078e0213 */
/*05f0*/ ISETP.NE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f05270 */
/*0600*/ @!P0 BRA 0x6a0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f05270 */
/*0620*/ @P0 BRA 0x690 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0630*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fca0007f1e0ff */
/*0640*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0650*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0660*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0670*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe20004000000 */
/*0680*/ BRA 0x6a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0690*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x000fe40000000004 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fca0007f1e0ff */
/*06c0*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*06d0*/ STG.E.U8 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101104 */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
cudaMalloc((void **)&device_world, worldSize);
cudaMalloc((void **)&device_buffer_world, worldSize);
cudaMemcpy(device_world, host_world, worldSize, cudaMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
cudaMemcpy(host_world, device_world, worldSize, cudaMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
cudaFree(device_world);
cudaFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} | .file "tmpxft_00093d42_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2358:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2358:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4copyPhiS_j
.type _Z4copyPhiS_j, @function
_Z4copyPhiS_j:
.LFB2353:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r9
movl %esi, %edi
movq %rdx, %r8
movl %ecx, %r11d
movl $0, %r10d
movl $0, %esi
movl $0, %ebx
testl %edi, %edi
jle .L3
.L4:
imull %edi, %esi
movzbl %r10b, %ebp
imull %r11d, %ebp
movl $0, %edx
movl %ebx, %eax
.L6:
addl %esi, %eax
cltq
movzbl (%r9,%rax), %ecx
movzbl %dl, %eax
leal (%rax,%rbp), %eax
movb %cl, (%r8,%rax)
addl $1, %edx
movzbl %dl, %eax
cmpl %edi, %eax
jl .L6
addl $1, %r10d
movzbl %r10b, %esi
cmpl %edi, %esi
jl .L4
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2353:
.size _Z4copyPhiS_j, .-_Z4copyPhiS_j
.globl _Z9zeroWorldPhj
.type _Z9zeroWorldPhj, @function
_Z9zeroWorldPhj:
.LFB2354:
.cfi_startproc
endbr64
testl %esi, %esi
je .L11
movl %esi, %ecx
movl $0, %r9d
movl $0, %r8d
.L13:
movl %r9d, %eax
.L14:
movl %eax, %edx
movb $0, (%rdi,%rdx)
addl $1, %eax
cmpl %ecx, %eax
jne .L14
addl $1, %r8d
addl %esi, %r9d
addl %esi, %ecx
cmpl %esi, %r8d
jne .L13
.L11:
ret
.cfi_endproc
.LFE2354:
.size _Z9zeroWorldPhj, .-_Z9zeroWorldPhj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " ------ \n"
.LC1:
.string "%d"
.LC2:
.string "\n"
.LC3:
.string " ------ \n\n"
.text
.globl _Z10printWorldPhj
.type _Z10printWorldPhj, @function
_Z10printWorldPhj:
.LFB2355:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r14d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
je .L17
movl %r14d, %ebp
movl $0, %r15d
leaq .LC1(%rip), %r13
.L18:
movl %ebp, %ebx
subl %r14d, %ebx
.L19:
movl %ebx, %eax
movzbl (%r12,%rax), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L19
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addl %r14d, %ebp
cmpl %r14d, %r15d
jne .L18
.L17:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2355:
.size _Z10printWorldPhj, .-_Z10printWorldPhj
.globl _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
.type _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s, @function
_Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s:
.LFB2380:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movw %dx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17game_of_life_turnPhS_s(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2380:
.size _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s, .-_Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
.globl _Z17game_of_life_turnPhS_s
.type _Z17game_of_life_turnPhS_s, @function
_Z17game_of_life_turnPhS_s:
.LFB2381:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movswl %dx, %edx
call _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2381:
.size _Z17game_of_life_turnPhS_s, .-_Z17game_of_life_turnPhS_s
.section .rodata.str1.1
.LC6:
.string "CUDA: %d, %f MMCps in %f\n"
.text
.globl main
.type main, @function
main:
.LFB2350:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $8, 36(%rsp)
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %esi
movq %rax, %rdi
call _Z9zeroWorldPhj
movl $16777216, 80(%rsp)
movb $0, 84(%rsp)
movl $16777472, 85(%rsp)
movb $0, 89(%rsp)
movl $16842752, 90(%rsp)
movb $0, 94(%rsp)
movl $0, 95(%rsp)
movb $0, 99(%rsp)
movl $0, 100(%rsp)
movb $0, 104(%rsp)
leaq 80(%rsp), %rdi
movl $256, %ecx
movq %rbp, %rdx
movl $5, %esi
call _Z4copyPhiS_j
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10000, %ebx
jmp .L32
.L31:
movq 8(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 8(%rsp)
movq %rax, 16(%rsp)
subl $1, %ebx
je .L36
.L32:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
jmp .L31
.L36:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC4(%rip), %xmm1
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss .LC5(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2350:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z17game_of_life_turnPhS_s"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2383:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z17game_of_life_turnPhS_s(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2383:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1143199498
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
cudaMalloc((void **)&device_world, worldSize);
cudaMalloc((void **)&device_buffer_world, worldSize);
cudaMemcpy(device_world, host_world, worldSize, cudaMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
cudaMemcpy(host_world, device_world, worldSize, cudaMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
cudaFree(device_world);
cudaFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
hipMalloc((void **)&device_world, worldSize);
hipMalloc((void **)&device_buffer_world, worldSize);
hipMemcpy(device_world, host_world, worldSize, hipMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
hipMemcpy(host_world, device_world, worldSize, hipMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
hipFree(device_world);
hipFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
hipMalloc((void **)&device_world, worldSize);
hipMalloc((void **)&device_buffer_world, worldSize);
hipMemcpy(device_world, host_world, worldSize, hipMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
hipMemcpy(host_world, device_world, worldSize, hipMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
hipFree(device_world);
hipFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17game_of_life_turnPhS_s
.globl _Z17game_of_life_turnPhS_s
.p2align 8
.type _Z17game_of_life_turnPhS_s,@function
_Z17game_of_life_turnPhS_s:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x24
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s4, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_sext_i32_i16 s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s2, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v5, v1
v_bfe_u32 v1, v0, 10, 10
v_mul_lo_u32 v6, s2, v5
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_mul_hi_u32 v3, v5, v6
s_add_i32 s2, s5, -1
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s2, v2
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v9, s2, v0
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v11, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v1, v11, 0
v_mad_u64_u32 v[5:6], null, v8, v11, 0
v_mad_u64_u32 v[4:5], null, v9, v11, 0
v_mul_lo_u32 v6, v6, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v5, s5
v_sub_nc_u32_e32 v6, v8, v6
v_add_nc_u32_e32 v10, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v9, v5
v_mad_u64_u32 v[3:4], null, v10, v11, 0
v_mul_lo_u32 v3, v7, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s5, v5
v_mul_lo_u32 v4, v4, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_subrev_nc_u32_e32 v3, s5, v1
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s5, v6
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_subrev_nc_u32_e32 v9, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v6, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v5
v_sub_nc_u32_e32 v4, v10, v4
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v1
v_subrev_nc_u32_e32 v8, s5, v4
v_subrev_nc_u32_e32 v7, s5, v3
v_cndmask_b32_e32 v6, v1, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_mul_lo_u32 v1, v2, s5
v_subrev_nc_u32_e32 v2, s5, v5
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v8, s5, v4
v_cndmask_b32_e32 v2, v5, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_mul_lo_u32 v6, v6, s5
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v3, v3, s5
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_add_nc_u32_e32 v8, v1, v2
v_add_nc_u32_e32 v5, v2, v6
v_add_nc_u32_e32 v7, v0, v6
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v5, v5, s[2:3]
global_load_u8 v7, v7, s[2:3]
v_add_nc_u32_e32 v6, v4, v6
s_clause 0x1
global_load_u8 v6, v6, s[2:3]
global_load_u8 v8, v8, s[2:3]
v_add_nc_u32_e32 v9, v4, v1
v_add_nc_u32_e32 v2, v2, v3
v_add_nc_u32_e32 v10, v3, v0
v_add_nc_u32_e32 v3, v4, v3
s_clause 0x3
global_load_u8 v4, v9, s[2:3]
global_load_u8 v2, v2, s[2:3]
global_load_u8 v9, v10, s[2:3]
global_load_u8 v3, v3, s[2:3]
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v5, v7, v5
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v5, v5, v6, v8
s_waitcnt vmcnt(2)
v_add3_u32 v2, v5, v4, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v9, v3
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s6, exec_lo, s6
v_cmp_ne_u32_e32 vcc_lo, 3, v2
s_mov_b32 s5, -1
s_and_b32 s4, vcc_lo, exec_lo
s_or_saveexec_b32 s7, s6
s_mov_b32 s6, 0
s_xor_b32 exec_lo, exec_lo, s7
v_cmp_ne_u32_e32 vcc_lo, 2, v2
s_and_not1_b32 s4, s4, exec_lo
s_mov_b32 s6, exec_lo
s_and_b32 s8, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s4, s8
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s7
s_and_not1_b32 s5, s5, exec_lo
s_and_not1_b32 s6, s6, exec_lo
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v0, v1, v0
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_8
global_load_u8 v1, v0, s[2:3]
s_and_not1_b32 s2, s5, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v1
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s2, s3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_cndmask_b32_e64 v1, 0, 1, s5
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17game_of_life_turnPhS_s
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17game_of_life_turnPhS_s, .Lfunc_end0-_Z17game_of_life_turnPhS_s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 2
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17game_of_life_turnPhS_s
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17game_of_life_turnPhS_s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <algorithm>
#include <unistd.h>
#define max(a, b) (a > b ? a : b)
#define min(a, b) (a < b ? a : b)
// Max threadsize is 1024 32*32
typedef unsigned char ubyte;
void printWorld(ubyte *world, uint size);
void zeroWorld(ubyte *world, uint size);
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size);
int coords(int x, int y, int size);
__global__ void game_of_life_turn(ubyte *world, ubyte *buffer_world, short size)
{
// We need to find the x,y of the cell we are looking at
// Because this is a 1d array we have to do some maths.
uint x = threadIdx.x + (blockDim.x * blockIdx.x);
uint y = threadIdx.y + (blockDim.y * blockIdx.y);
// Find the y rows
uint y_up = (y + 1) % size;
uint y_down = (y + size - 1) % size;
// Find the y offsets
uint y_offset = y * size;
uint y_up_offset = y_up * size;
uint y_down_offset = y_down * size;
//printf("(%d,%d) (%d %d) (%d %d) (%d, %d) (%d, %d)\n", x, y, threadIdx.x, threadIdx.y, blockDim.x, blockDim.y, blockIdx.x, blockIdx.y, gridDim.x, gridDim.y);
uint x_left = (x - 1 + size) % size;
uint x_right = (x + 1) % size;
uint offset = x + y_offset;
uint aliveCells = world[x_left + y_up_offset] +
world[x + y_up_offset] +
world[x_right + y_up_offset] +
world[x_left + y_offset] +
world[x_right + y_offset] +
world[x_left + y_down_offset] +
world[x + y_down_offset] +
world[x_right + y_down_offset];
//Any live cell with two or three live neighbours survives.
//Any dead cell with three live neighbours becomes a live cell.
//All other live cells die in the next generation. Similarly, all other dead cells stay dead.
buffer_world[offset] = aliveCells == 3 || (aliveCells == 2 && world[offset]) ? 1 : 0;
}
int main()
{
// To keep the math easy the size of the world must be a square of a square, i.e. X^2^2
// This is so we can easily divide up the world into square blocks for processing
// To make it even easier size should be a poer of 2, i.e. 2^X
uint size = 256;
int turns = 10000;
uint ncells = size * size;
// With the max number of threads being 1024
// The number of threads here will describe the number of blocks
uint threadsCount = min(ncells, 1024);
uint threadDimSize = sqrt(threadsCount);
// Threads create a block of sqrt(threadCount)^2
dim3 threadsPerBlock(threadDimSize, threadDimSize);
// Now we need to find the number of blocks this is the size/ThreadDimSize
uint blockDimSize = size / threadDimSize;
dim3 numBlocks(blockDimSize, blockDimSize);
// Lets make sure our math is correct
// The number of cells is a multiple of threadcount
assert(ncells % threadsCount == 0);
// the number of blocks * num of threads = size
assert(blockDimSize * threadDimSize == size);
//printf("Size %d, ncells %d, Threads: %d, ThreadDimSize %d, BlockDimSize %d\n", size, ncells, threadsCount, threadDimSize, blockDimSize);
// We make a 1d array of bytes, ehere each byte is a cell, to describe the world
ubyte *host_world;
int worldSize = sizeof(ubyte) * ncells;
host_world = (ubyte *)malloc(worldSize);
// We setup the world by first zeroing it out, then copying a pattern (this is the glider)
zeroWorld(host_world, size);
ubyte pattern[5][5] = {
{0, 0, 0, 1, 0},
{0, 1, 0, 1, 0},
{0, 0, 1, 1, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
};
copy((ubyte *)pattern, 5, host_world, size);
// printWorld(host_world, size);
// Set up the Device Memory by create the world and a buffer
// Then by Mallocing on the device, then copying the world over to the device
ubyte *device_world, *device_buffer_world;
hipMalloc((void **)&device_world, worldSize);
hipMalloc((void **)&device_buffer_world, worldSize);
hipMemcpy(device_world, host_world, worldSize, hipMemcpyHostToDevice);
// Time some stuff
struct timeval t0, t1;
gettimeofday(&t0, NULL);
// Run the world
int turn;
for (turn = 0; turn < turns; turn++)
{
game_of_life_turn<<<numBlocks, threadsPerBlock>>>(device_world, device_buffer_world, size);
std::swap(device_world, device_buffer_world);
}
// Finish timing
gettimeofday(&t1, NULL);
// Copy the value of the world back to host memory
hipMemcpy(host_world, device_world, worldSize, hipMemcpyDeviceToHost);
// system("clear");
// printWorld(host_world, size);
// How many seconds it took to execute
float seconds = t1.tv_sec - t0.tv_sec + 1E-6 * (t1.tv_usec - t0.tv_usec);
// How many total calculations
float MMcellCalculations = (1.0 * turns * ncells) / 1000000;
// Millions of Calculations per second
float MMcellsCalculatedperSecond = MMcellCalculations / seconds;
printf("CUDA: %d, %f MMCps in %f\n", size, MMcellsCalculatedperSecond, seconds);
// Free all the Device and host memory
hipFree(device_world);
hipFree(device_buffer_world);
free(host_world);
return 0;
}
void copy(ubyte *pattern, int patternsize, ubyte *world, uint size)
{
ubyte x, y;
for (y = 0; y < patternsize; y++)
{
for (x = 0; x < patternsize; x++)
{
world[x + (size * y)] = pattern[x + (y * patternsize)];
}
}
}
void zeroWorld(ubyte *world, uint size)
{
int x, y;
for (y = 0; y < size; ++y)
{
for (x = 0; x < size; ++x)
{
world[x + (y * size)] = 0;
}
}
}
void printWorld(ubyte *world, uint size)
{
int x, y;
printf(" ------ \n");
for (y = 0; y < size; y++)
{
for (x = 0; x < size; x++)
{
printf("%d", world[x + (y * size)]);
}
printf("\n");
}
printf(" ------ \n\n");
} | .text
.file "main.hip"
.globl _Z32__device_stub__game_of_life_turnPhS_s # -- Begin function _Z32__device_stub__game_of_life_turnPhS_s
.p2align 4, 0x90
.type _Z32__device_stub__game_of_life_turnPhS_s,@function
_Z32__device_stub__game_of_life_turnPhS_s: # @_Z32__device_stub__game_of_life_turnPhS_s
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movw %dx, 14(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 14(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17game_of_life_turnPhS_s, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__game_of_life_turnPhS_s, .Lfunc_end0-_Z32__device_stub__game_of_life_turnPhS_s
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x4423d70a # float 655.359985
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z9zeroWorldPhj.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
movl $65536, %edx # imm = 0x10000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $281474993487872, %rax # imm = 0x1000001000000
movq %rax, 64(%rsp)
movl $1, 72(%rsp)
movw $257, 76(%rsp) # imm = 0x101
movq $0, 78(%rsp)
movl $0, 85(%rsp)
movq %r14, %rax
.p2align 4, 0x90
.LBB1_1: # %.preheader.i40
# =>This Inner Loop Header: Depth=1
movzbl 68(%rsp,%rbx), %ecx
movb %cl, 4(%rax)
movl 64(%rsp,%rbx), %ecx
movl %ecx, (%rax)
addq $5, %rbx
addq $256, %rax # imm = 0x100
cmpq $25, %rbx
jne .LBB1_1
# %bb.2: # %_Z4copyPhiS_j.exit
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 16(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r14, 96(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $10000, %r13d # imm = 0x2710
movabsq $34359738376, %r14 # imm = 0x800000008
movabsq $137438953504, %r15 # imm = 0x2000000020
leaq 112(%rsp), %rbp
leaq 104(%rsp), %rbx
leaq 32(%rsp), %r12
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rcx, 16(%rsp)
movq %rax, 24(%rsp)
decl %r13d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movw $256, 14(%rsp) # imm = 0x100
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
leaq 14(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z17game_of_life_turnPhS_s, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 168(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 176(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl $256, %esi # imm = 0x100
movb $2, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z9zeroWorldPhj # -- Begin function _Z9zeroWorldPhj
.p2align 4, 0x90
.type _Z9zeroWorldPhj,@function
_Z9zeroWorldPhj: # @_Z9zeroWorldPhj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_5
# %bb.1: # %.preheader.preheader
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rsi), %r8d
movb $0, (%rdi,%r8)
incq %rsi
cmpq %rsi, %rax
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incl %edx
addq %rax, %rcx
cmpl %eax, %edx
jne .LBB2_2
.LBB2_5: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9zeroWorldPhj, .Lfunc_end2-_Z9zeroWorldPhj
.cfi_endproc
# -- End function
.globl _Z4copyPhiS_j # -- Begin function _Z4copyPhiS_j
.p2align 4, 0x90
.type _Z4copyPhiS_j,@function
_Z4copyPhiS_j: # @_Z4copyPhiS_j
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %ecx, %eax
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ecx, %r10d
addq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r10,%r11), %ebx
leal (%r8,%r11), %r14d
movb %bl, (%rdx,%r14)
incq %r11
movzbl %r11b, %ebx
cmpl %esi, %ebx
jl .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incl %r9d
movzbl %r9b, %r10d
addq %rax, %r8
addl %esi, %ecx
cmpl %esi, %r10d
jl .LBB3_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_6: # %._crit_edge19
retq
.Lfunc_end3:
.size _Z4copyPhiS_j, .Lfunc_end3-_Z4copyPhiS_j
.cfi_endproc
# -- End function
.globl _Z10printWorldPhj # -- Begin function _Z10printWorldPhj
.p2align 4, 0x90
.type _Z10printWorldPhj,@function
_Z10printWorldPhj: # @_Z10printWorldPhj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
testl %ebp, %ebp
je .LBB4_5
# %bb.1: # %.preheader.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r15,%r12), %eax
movzbl (%rbx,%rax), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
addq %r14, %r15
cmpl %r14d, %ebp
jne .LBB4_2
.LBB4_5: # %._crit_edge
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z10printWorldPhj, .Lfunc_end4-_Z10printWorldPhj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17game_of_life_turnPhS_s, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17game_of_life_turnPhS_s,@object # @_Z17game_of_life_turnPhS_s
.section .rodata,"a",@progbits
.globl _Z17game_of_life_turnPhS_s
.p2align 3, 0x0
_Z17game_of_life_turnPhS_s:
.quad _Z32__device_stub__game_of_life_turnPhS_s
.size _Z17game_of_life_turnPhS_s, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA: %d, %f MMCps in %f\n"
.size .L.str, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17game_of_life_turnPhS_s"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " ------ "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " ------ \n"
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__game_of_life_turnPhS_s
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17game_of_life_turnPhS_s
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17game_of_life_turnPhS_s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ LDC.U16 R0, c[0x0][0x170] ; /* 0x00005c00ff007b82 */
/* 0x000e220000000400 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea80000002500 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000ea20000002100 */
/*0070*/ PRMT R0, R0, 0x9910, RZ ; /* 0x0000991000007816 */
/* 0x001fc800000000ff */
/*0080*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*0090*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a00 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R8 ; /* 0x0000010003037a24 */
/* 0x002fe400078e0208 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x004fca00078e0204 */
/*00c0*/ IADD3 R11, R5.reuse, -0x1, R0 ; /* 0xffffffff050b7810 */
/* 0x040fe20007ffe000 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e220000001000 */
/*00e0*/ IADD3 R13, R5, 0x1, RZ ; /* 0x00000001050d7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x001fca0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD R9, R9, R7, RZ ; /* 0x0000000709097224 */
/* 0x002fc800078e02ff */
/*0130*/ IMAD.HI.U32 R2, R7, R9, R6 ; /* 0x0000000907027227 */
/* 0x000fe200078e0006 */
/*0140*/ IADD3 R7, R3.reuse, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x040fe40007ffe0ff */
/*0150*/ IADD3 R9, R3, -0x1, R0 ; /* 0xffffffff03097810 */
/* 0x000fc60007ffe000 */
/*0160*/ IMAD.HI.U32 R4, R2, R7, RZ ; /* 0x0000000702047227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.HI.U32 R6, R2, R11, RZ ; /* 0x0000000b02067227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a04 */
/*0190*/ IADD3 R6, -R6, RZ, RZ ; /* 0x000000ff06067210 */
/* 0x000fc60007ffe1ff */
/*01a0*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fe400078e0207 */
/*01b0*/ IMAD.HI.U32 R4, R2, R13, RZ ; /* 0x0000000d02047227 */
/* 0x000fc600078e00ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f06070 */
/*01d0*/ IMAD R11, R0, R6, R11 ; /* 0x00000006000b7224 */
/* 0x000fe400078e020b */
/*01e0*/ IMAD.HI.U32 R2, R2, R9, RZ ; /* 0x0000000902027227 */
/* 0x000fc600078e00ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fe20003f26070 */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a04 */
/*0210*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a02 */
/*0220*/ IMAD R13, R0.reuse, R4, R13 ; /* 0x00000004000d7224 */
/* 0x040fe400078e020d */
/*0230*/ IMAD R9, R0, R2, R9 ; /* 0x0000000200097224 */
/* 0x000fe200078e0209 */
/*0240*/ LOP3.LUT R2, RZ, R0.reuse, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x080fe200078e33ff */
/*0250*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*0260*/ ISETP.GE.U32.AND P3, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fc40003f66070 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R9, R0.reuse, PT ; /* 0x000000000900720c */
/* 0x080fe40003f06070 */
/*0280*/ @P1 IADD3 R11, -R0, R11, RZ ; /* 0x0000000b000b1210 */
/* 0x000fe40007ffe1ff */
/*0290*/ ISETP.GE.U32.AND P1, PT, R7, R0.reuse, PT ; /* 0x000000000700720c */
/* 0x080fe40003f26070 */
/*02a0*/ ISETP.GE.U32.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fca0003f46070 */
/*02b0*/ @P3 IMAD.IADD R13, R13, 0x1, -R0.reuse ; /* 0x000000010d0d3824 */
/* 0x100fe200078e0a00 */
/*02c0*/ ISETP.NE.U32.AND P3, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f65070 */
/*02d0*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fc600078e0a00 */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R13, R0.reuse, PT ; /* 0x000000000d00720c */
/* 0x080fe20003f06070 */
/*02f0*/ @P1 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107071824 */
/* 0x000fe200078e0a00 */
/*0300*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f26070 */
/*0310*/ @P2 IADD3 R11, -R0, R11, RZ ; /* 0x0000000b000b2210 */
/* 0x000fe40007ffe1ff */
/*0320*/ SEL R7, R2.reuse, R7, !P3 ; /* 0x0000000702077207 */
/* 0x040fe40005800000 */
/*0330*/ SEL R4, R2, R11, !P3 ; /* 0x0000000b02047207 */
/* 0x000fc60005800000 */
/*0340*/ IMAD R12, R0.reuse, R7.reuse, R5 ; /* 0x00000007000c7224 */
/* 0x0c0fe400078e0205 */
/*0350*/ @P0 IMAD.IADD R13, R13, 0x1, -R0 ; /* 0x000000010d0d0824 */
/* 0x000fe400078e0a00 */
/*0360*/ IMAD R14, R0, R7, R4 ; /* 0x00000007000e7224 */
/* 0x000fe400078e0204 */
/*0370*/ @P1 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109091824 */
/* 0x000fe200078e0a00 */
/*0380*/ SEL R10, R2, R13, !P3 ; /* 0x0000000d020a7207 */
/* 0x000fe40005800000 */
/*0390*/ IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e7a10 */
/* 0x000fe40007f1e0ff */
/*03a0*/ SEL R11, R2, R9, !P3 ; /* 0x00000009020b7207 */
/* 0x000fe20005800000 */
/*03b0*/ IMAD R7, R0, R7, R10 ; /* 0x0000000700077224 */
/* 0x000fe200078e020a */
/*03c0*/ IADD3 R12, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe20007f3e0ff */
/*03d0*/ IMAD R6, R0, R3, R4 ; /* 0x0000000300067224 */
/* 0x000fc400078e0204 */
/*03e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f7624 */
/* 0x000fe200000e06ff */
/*03f0*/ IADD3 R8, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007087a10 */
/* 0x000fe20007f1e0ff */
/*0400*/ IMAD R16, R0.reuse, R11, R4 ; /* 0x0000000b00107224 */
/* 0x040fe200078e0204 */
/*0410*/ IADD3.X R13, RZ, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900ff0d7a10 */
/* 0x000fe20000ffe4ff */
/*0420*/ IMAD R4, R0, R3, R10.reuse ; /* 0x0000000300047224 */
/* 0x100fe200078e020a */
/*0430*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe20007f3e0ff */
/*0440*/ IMAD R18, R0, R11.reuse, R10 ; /* 0x0000000b00127224 */
/* 0x080fe200078e020a */
/*0450*/ LDG.E.U8 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x0000a2000c1e1100 */
/*0460*/ IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff097624 */
/* 0x000fe200000e06ff */
/*0470*/ IADD3 R10, P0, R4, c[0x0][0x160], RZ ; /* 0x00005800040a7a10 */
/* 0x000fe20007f1e0ff */
/*0480*/ IMAD R11, R0, R11, R5 ; /* 0x0000000b000b7224 */
/* 0x000fe200078e0205 */
/*0490*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1100 */
/*04a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fc600008e06ff */
/*04b0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*04c0*/ IADD3 R14, P1, R16, c[0x0][0x160], RZ ; /* 0x00005800100e7a10 */
/* 0x001fe40007f3e0ff */
/*04d0*/ IADD3 R16, P2, R11, c[0x0][0x160], RZ ; /* 0x000058000b107a10 */
/* 0x000fe20007f5e0ff */
/*04e0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0b7624 */
/* 0x000fe200000e06ff */
/*04f0*/ IADD3.X R15, RZ, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900ff0f7a10 */
/* 0x000fe20000ffe4ff */
/*0500*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1100 */
/*0510*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe20007f1e0ff */
/*0520*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0530*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1100 */
/*0540*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x000fc400000e06ff */
/*0550*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f28000c1e1100 */
/*0560*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1100 */
/*0570*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f62000c1e1100 */
/*0580*/ BSSY B0, 0x6b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0590*/ HFMA2.MMA R4, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff047435 */
/* 0x000fe200000001ff */
/*05a0*/ IMAD R0, R0, R3, R5 ; /* 0x0000000300007224 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R2, R8, R13, R2 ; /* 0x0000000d08027210 */
/* 0x004fc80007ffe002 */
/*05c0*/ IADD3 R2, R10, R2, R7 ; /* 0x000000020a027210 */
/* 0x008fc80007ffe007 */
/*05d0*/ IADD3 R2, R16, R2, R15 ; /* 0x0000000210027210 */
/* 0x010fca0007ffe00f */
/*05e0*/ IMAD.IADD R2, R2, 0x1, R19 ; /* 0x0000000102027824 */
/* 0x020fca00078e0213 */
/*05f0*/ ISETP.NE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f05270 */
/*0600*/ @!P0 BRA 0x6a0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f05270 */
/*0620*/ @P0 BRA 0x690 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0630*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fca0007f1e0ff */
/*0640*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0650*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0660*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0670*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe20004000000 */
/*0680*/ BRA 0x6a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0690*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x000fe40000000004 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fca0007f1e0ff */
/*06c0*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*06d0*/ STG.E.U8 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101104 */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17game_of_life_turnPhS_s
.globl _Z17game_of_life_turnPhS_s
.p2align 8
.type _Z17game_of_life_turnPhS_s,@function
_Z17game_of_life_turnPhS_s:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x24
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s4, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_sext_i32_i16 s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s2, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v5, v1
v_bfe_u32 v1, v0, 10, 10
v_mul_lo_u32 v6, s2, v5
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_mul_hi_u32 v3, v5, v6
s_add_i32 s2, s5, -1
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s2, v2
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v9, s2, v0
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v11, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v1, v11, 0
v_mad_u64_u32 v[5:6], null, v8, v11, 0
v_mad_u64_u32 v[4:5], null, v9, v11, 0
v_mul_lo_u32 v6, v6, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v5, s5
v_sub_nc_u32_e32 v6, v8, v6
v_add_nc_u32_e32 v10, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v9, v5
v_mad_u64_u32 v[3:4], null, v10, v11, 0
v_mul_lo_u32 v3, v7, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s5, v5
v_mul_lo_u32 v4, v4, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_subrev_nc_u32_e32 v3, s5, v1
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s5, v6
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_subrev_nc_u32_e32 v9, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v6, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v5
v_sub_nc_u32_e32 v4, v10, v4
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v1
v_subrev_nc_u32_e32 v8, s5, v4
v_subrev_nc_u32_e32 v7, s5, v3
v_cndmask_b32_e32 v6, v1, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_mul_lo_u32 v1, v2, s5
v_subrev_nc_u32_e32 v2, s5, v5
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v8, s5, v4
v_cndmask_b32_e32 v2, v5, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_mul_lo_u32 v6, v6, s5
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v3, v3, s5
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_add_nc_u32_e32 v8, v1, v2
v_add_nc_u32_e32 v5, v2, v6
v_add_nc_u32_e32 v7, v0, v6
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v5, v5, s[2:3]
global_load_u8 v7, v7, s[2:3]
v_add_nc_u32_e32 v6, v4, v6
s_clause 0x1
global_load_u8 v6, v6, s[2:3]
global_load_u8 v8, v8, s[2:3]
v_add_nc_u32_e32 v9, v4, v1
v_add_nc_u32_e32 v2, v2, v3
v_add_nc_u32_e32 v10, v3, v0
v_add_nc_u32_e32 v3, v4, v3
s_clause 0x3
global_load_u8 v4, v9, s[2:3]
global_load_u8 v2, v2, s[2:3]
global_load_u8 v9, v10, s[2:3]
global_load_u8 v3, v3, s[2:3]
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v5, v7, v5
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v5, v5, v6, v8
s_waitcnt vmcnt(2)
v_add3_u32 v2, v5, v4, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v9, v3
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s6, exec_lo, s6
v_cmp_ne_u32_e32 vcc_lo, 3, v2
s_mov_b32 s5, -1
s_and_b32 s4, vcc_lo, exec_lo
s_or_saveexec_b32 s7, s6
s_mov_b32 s6, 0
s_xor_b32 exec_lo, exec_lo, s7
v_cmp_ne_u32_e32 vcc_lo, 2, v2
s_and_not1_b32 s4, s4, exec_lo
s_mov_b32 s6, exec_lo
s_and_b32 s8, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s4, s8
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s7
s_and_not1_b32 s5, s5, exec_lo
s_and_not1_b32 s6, s6, exec_lo
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v0, v1, v0
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_8
global_load_u8 v1, v0, s[2:3]
s_and_not1_b32 s2, s5, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v1
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s2, s3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_cndmask_b32_e64 v1, 0, 1, s5
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17game_of_life_turnPhS_s
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17game_of_life_turnPhS_s, .Lfunc_end0-_Z17game_of_life_turnPhS_s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 2
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17game_of_life_turnPhS_s
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17game_of_life_turnPhS_s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00093d42_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2358:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2358:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4copyPhiS_j
.type _Z4copyPhiS_j, @function
_Z4copyPhiS_j:
.LFB2353:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r9
movl %esi, %edi
movq %rdx, %r8
movl %ecx, %r11d
movl $0, %r10d
movl $0, %esi
movl $0, %ebx
testl %edi, %edi
jle .L3
.L4:
imull %edi, %esi
movzbl %r10b, %ebp
imull %r11d, %ebp
movl $0, %edx
movl %ebx, %eax
.L6:
addl %esi, %eax
cltq
movzbl (%r9,%rax), %ecx
movzbl %dl, %eax
leal (%rax,%rbp), %eax
movb %cl, (%r8,%rax)
addl $1, %edx
movzbl %dl, %eax
cmpl %edi, %eax
jl .L6
addl $1, %r10d
movzbl %r10b, %esi
cmpl %edi, %esi
jl .L4
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2353:
.size _Z4copyPhiS_j, .-_Z4copyPhiS_j
.globl _Z9zeroWorldPhj
.type _Z9zeroWorldPhj, @function
_Z9zeroWorldPhj:
.LFB2354:
.cfi_startproc
endbr64
testl %esi, %esi
je .L11
movl %esi, %ecx
movl $0, %r9d
movl $0, %r8d
.L13:
movl %r9d, %eax
.L14:
movl %eax, %edx
movb $0, (%rdi,%rdx)
addl $1, %eax
cmpl %ecx, %eax
jne .L14
addl $1, %r8d
addl %esi, %r9d
addl %esi, %ecx
cmpl %esi, %r8d
jne .L13
.L11:
ret
.cfi_endproc
.LFE2354:
.size _Z9zeroWorldPhj, .-_Z9zeroWorldPhj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " ------ \n"
.LC1:
.string "%d"
.LC2:
.string "\n"
.LC3:
.string " ------ \n\n"
.text
.globl _Z10printWorldPhj
.type _Z10printWorldPhj, @function
_Z10printWorldPhj:
.LFB2355:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r14d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
je .L17
movl %r14d, %ebp
movl $0, %r15d
leaq .LC1(%rip), %r13
.L18:
movl %ebp, %ebx
subl %r14d, %ebx
.L19:
movl %ebx, %eax
movzbl (%r12,%rax), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L19
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addl %r14d, %ebp
cmpl %r14d, %r15d
jne .L18
.L17:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2355:
.size _Z10printWorldPhj, .-_Z10printWorldPhj
.globl _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
.type _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s, @function
_Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s:
.LFB2380:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movw %dx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17game_of_life_turnPhS_s(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2380:
.size _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s, .-_Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
.globl _Z17game_of_life_turnPhS_s
.type _Z17game_of_life_turnPhS_s, @function
_Z17game_of_life_turnPhS_s:
.LFB2381:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movswl %dx, %edx
call _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2381:
.size _Z17game_of_life_turnPhS_s, .-_Z17game_of_life_turnPhS_s
.section .rodata.str1.1
.LC6:
.string "CUDA: %d, %f MMCps in %f\n"
.text
.globl main
.type main, @function
main:
.LFB2350:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $8, 36(%rsp)
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %esi
movq %rax, %rdi
call _Z9zeroWorldPhj
movl $16777216, 80(%rsp)
movb $0, 84(%rsp)
movl $16777472, 85(%rsp)
movb $0, 89(%rsp)
movl $16842752, 90(%rsp)
movb $0, 94(%rsp)
movl $0, 95(%rsp)
movb $0, 99(%rsp)
movl $0, 100(%rsp)
movb $0, 104(%rsp)
leaq 80(%rsp), %rdi
movl $256, %ecx
movq %rbp, %rdx
movl $5, %esi
call _Z4copyPhiS_j
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10000, %ebx
jmp .L32
.L31:
movq 8(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 8(%rsp)
movq %rax, 16(%rsp)
subl $1, %ebx
je .L36
.L32:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z17game_of_life_turnPhS_sPhS_s
jmp .L31
.L36:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC4(%rip), %xmm1
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss .LC5(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2350:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z17game_of_life_turnPhS_s"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2383:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z17game_of_life_turnPhS_s(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2383:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1143199498
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z32__device_stub__game_of_life_turnPhS_s # -- Begin function _Z32__device_stub__game_of_life_turnPhS_s
.p2align 4, 0x90
.type _Z32__device_stub__game_of_life_turnPhS_s,@function
_Z32__device_stub__game_of_life_turnPhS_s: # @_Z32__device_stub__game_of_life_turnPhS_s
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movw %dx, 14(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 14(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17game_of_life_turnPhS_s, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__game_of_life_turnPhS_s, .Lfunc_end0-_Z32__device_stub__game_of_life_turnPhS_s
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x4423d70a # float 655.359985
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z9zeroWorldPhj.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
movl $65536, %edx # imm = 0x10000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $281474993487872, %rax # imm = 0x1000001000000
movq %rax, 64(%rsp)
movl $1, 72(%rsp)
movw $257, 76(%rsp) # imm = 0x101
movq $0, 78(%rsp)
movl $0, 85(%rsp)
movq %r14, %rax
.p2align 4, 0x90
.LBB1_1: # %.preheader.i40
# =>This Inner Loop Header: Depth=1
movzbl 68(%rsp,%rbx), %ecx
movb %cl, 4(%rax)
movl 64(%rsp,%rbx), %ecx
movl %ecx, (%rax)
addq $5, %rbx
addq $256, %rax # imm = 0x100
cmpq $25, %rbx
jne .LBB1_1
# %bb.2: # %_Z4copyPhiS_j.exit
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 16(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r14, 96(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $10000, %r13d # imm = 0x2710
movabsq $34359738376, %r14 # imm = 0x800000008
movabsq $137438953504, %r15 # imm = 0x2000000020
leaq 112(%rsp), %rbp
leaq 104(%rsp), %rbx
leaq 32(%rsp), %r12
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rcx, 16(%rsp)
movq %rax, 24(%rsp)
decl %r13d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movw $256, 14(%rsp) # imm = 0x100
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
leaq 14(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z17game_of_life_turnPhS_s, %edi
movq %r12, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 168(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 176(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl $256, %esi # imm = 0x100
movb $2, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z9zeroWorldPhj # -- Begin function _Z9zeroWorldPhj
.p2align 4, 0x90
.type _Z9zeroWorldPhj,@function
_Z9zeroWorldPhj: # @_Z9zeroWorldPhj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_5
# %bb.1: # %.preheader.preheader
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rsi), %r8d
movb $0, (%rdi,%r8)
incq %rsi
cmpq %rsi, %rax
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incl %edx
addq %rax, %rcx
cmpl %eax, %edx
jne .LBB2_2
.LBB2_5: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9zeroWorldPhj, .Lfunc_end2-_Z9zeroWorldPhj
.cfi_endproc
# -- End function
.globl _Z4copyPhiS_j # -- Begin function _Z4copyPhiS_j
.p2align 4, 0x90
.type _Z4copyPhiS_j,@function
_Z4copyPhiS_j: # @_Z4copyPhiS_j
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %ecx, %eax
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ecx, %r10d
addq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r10,%r11), %ebx
leal (%r8,%r11), %r14d
movb %bl, (%rdx,%r14)
incq %r11
movzbl %r11b, %ebx
cmpl %esi, %ebx
jl .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incl %r9d
movzbl %r9b, %r10d
addq %rax, %r8
addl %esi, %ecx
cmpl %esi, %r10d
jl .LBB3_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_6: # %._crit_edge19
retq
.Lfunc_end3:
.size _Z4copyPhiS_j, .Lfunc_end3-_Z4copyPhiS_j
.cfi_endproc
# -- End function
.globl _Z10printWorldPhj # -- Begin function _Z10printWorldPhj
.p2align 4, 0x90
.type _Z10printWorldPhj,@function
_Z10printWorldPhj: # @_Z10printWorldPhj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
testl %ebp, %ebp
je .LBB4_5
# %bb.1: # %.preheader.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r15,%r12), %eax
movzbl (%rbx,%rax), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
addq %r14, %r15
cmpl %r14d, %ebp
jne .LBB4_2
.LBB4_5: # %._crit_edge
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z10printWorldPhj, .Lfunc_end4-_Z10printWorldPhj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17game_of_life_turnPhS_s, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17game_of_life_turnPhS_s,@object # @_Z17game_of_life_turnPhS_s
.section .rodata,"a",@progbits
.globl _Z17game_of_life_turnPhS_s
.p2align 3, 0x0
_Z17game_of_life_turnPhS_s:
.quad _Z32__device_stub__game_of_life_turnPhS_s
.size _Z17game_of_life_turnPhS_s, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA: %d, %f MMCps in %f\n"
.size .L.str, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17game_of_life_turnPhS_s"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " ------ "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " ------ \n"
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__game_of_life_turnPhS_s
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17game_of_life_turnPhS_s
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <cuda_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
cudaMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_A, h_A, bytes, cudaMemcpyHostToDevice ) ;
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
cudaDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
cudaMemcpy( h_dC, d_C, bytes, cudaMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
cudaFree( d_A ) ; cudaFree( d_B ) ; cudaFree( d_C ) ;
cudaDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} | code for sm_80
Function : _Z8f_addmatPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <cuda_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
cudaMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_A, h_A, bytes, cudaMemcpyHostToDevice ) ;
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
cudaDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
cudaMemcpy( h_dC, d_C, bytes, cudaMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
cudaFree( d_A ) ; cudaFree( d_B ) ; cudaFree( d_C ) ;
cudaDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} | .file "tmpxft_000e6367_00000000-6_main_v1_sqr_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12getTimeStampv
.type _Z12getTimeStampv, @function
_Z12getTimeStampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12getTimeStampv, .-_Z12getTimeStampv
.globl _Z9initDataAPfii
.type _Z9initDataAPfii, @function
_Z9initDataAPfii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movl %edx, %r8d
movl $0, %r10d
movl $0, %r9d
movss .LC1(%rip), %xmm1
jmp .L9
.L11:
movl %r9d, %eax
movslq %r10d, %rcx
leaq (%rdi,%rcx,4), %rcx
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addq $4, %rcx
cmpl %r8d, %eax
jne .L10
.L12:
addl $1, %r9d
addl %edx, %r10d
addl $1, %r8d
cmpl %r9d, %esi
je .L7
.L9:
testl %edx, %edx
jg .L11
jmp .L12
.L7:
ret
.cfi_endproc
.LFE2058:
.size _Z9initDataAPfii, .-_Z9initDataAPfii
.globl _Z9initDataBPfii
.type _Z9initDataBPfii, @function
_Z9initDataBPfii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
movl %edx, %r8d
movl $0, %r10d
movl $0, %r9d
movss .LC2(%rip), %xmm1
jmp .L16
.L18:
movl %r9d, %eax
movslq %r10d, %rcx
leaq (%rdi,%rcx,4), %rcx
.L17:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addq $4, %rcx
cmpl %r8d, %eax
jne .L17
.L19:
addl $1, %r9d
addl %edx, %r10d
addl $1, %r8d
cmpl %r9d, %esi
je .L14
.L16:
testl %edx, %edx
jg .L18
jmp .L19
.L14:
ret
.cfi_endproc
.LFE2059:
.size _Z9initDataBPfii, .-_Z9initDataBPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f "
.LC4:
.string "\n"
.text
.globl _Z10debugPrintPfii
.type _Z10debugPrintPfii, @function
_Z10debugPrintPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L22
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
jmp .L23
.L25:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L26:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L22
.L23:
testl %r15d, %r15d
jg .L25
jmp .L26
.L22:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10debugPrintPfii, .-_Z10debugPrintPfii
.globl _Z8h_addmatPfS_S_ii
.type _Z8h_addmatPfS_S_ii, @function
_Z8h_addmatPfS_S_ii:
.LFB2061:
.cfi_startproc
endbr64
imull %r8d, %ecx
testl %ecx, %ecx
jle .L29
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L31:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L31
.L29:
ret
.cfi_endproc
.LFE2061:
.size _Z8h_addmatPfS_S_ii, .-_Z8h_addmatPfS_S_ii
.globl _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
.type _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii, @function
_Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8f_addmatPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii, .-_Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
.globl _Z8f_addmatPfS_S_ii
.type _Z8f_addmatPfS_S_ii, @function
_Z8f_addmatPfS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8f_addmatPfS_S_ii, .-_Z8f_addmatPfS_S_ii
.section .rodata.str1.1
.LC5:
.string "Error: wrong number of args\n"
.LC7:
.string "noelems is %d\n"
.LC8:
.string "a"
.LC9:
.string "time.log"
.LC10:
.string "%dX%d %.6f %.6f %.6f %.6f\n"
.LC11:
.string "%.6f %.6f %.6f %.6f\n"
.LC12:
.string "Error: function failed.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L54
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, (%rsp)
imull %eax, %ebp
movslq %ebp, %rax
movq %rax, 8(%rsp)
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movl (%rsp), %edx
movl %r15d, %esi
movq %r13, %rdi
call _Z9initDataAPfii
movl (%rsp), %edx
movl %r15d, %esi
movq %r14, %rdi
call _Z9initDataBPfii
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 88(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L52
sqrtsd %xmm0, %xmm0
.L45:
cvttsd2sil %xmm0, %ecx
leal -1(%rcx,%rbp), %eax
cltd
idivl %ecx
movl %eax, %esi
cmpl $65535, %ecx
jle .L46
imull %eax, %ecx
leal 65534(%rcx), %eax
movl $65535, %ecx
cltd
idivl %ecx
movl %eax, %esi
.L46:
addl $31, %esi
shrl $5, %esi
movl %esi, 92(%rsp)
addl $31, %ecx
shrl $5, %ecx
movl %ecx, 96(%rsp)
movl $1, 100(%rsp)
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z12getTimeStampv
movsd %xmm0, (%rsp)
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call _Z12getTimeStampv
movsd %xmm0, 32(%rsp)
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L47:
call cudaDeviceSynchronize@PLT
call _Z12getTimeStampv
movsd %xmm0, 40(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z12getTimeStampv
movsd %xmm0, 24(%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movl %r12d, %r8d
movl %r15d, %ecx
movq 16(%rsp), %rbx
movq %rbx, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z8h_addmatPfS_S_ii
movq 8(%rsp), %rax
salq $2, %rax
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L48
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movsd 24(%rsp), %xmm4
movapd %xmm4, %xmm5
movsd 40(%rsp), %xmm6
subsd %xmm6, %xmm5
movq %xmm5, %r14
movsd 32(%rsp), %xmm7
subsd %xmm7, %xmm6
movq %xmm6, %r13
movsd (%rsp), %xmm2
subsd %xmm2, %xmm7
movq %xmm7, %rbp
subsd %xmm2, %xmm4
movsd %xmm4, (%rsp)
movapd %xmm5, %xmm3
movapd %xmm6, %xmm2
movapd %xmm7, %xmm1
movapd %xmm4, %xmm0
movl %r12d, %r8d
movl %r15d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $4, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, %xmm3
movq %r13, %xmm2
movq %rbp, %xmm1
movsd (%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
call sqrt@PLT
jmp .L45
.L55:
movl %r12d, %r8d
movl %r15d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
jmp .L47
.L48:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8f_addmatPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8f_addmatPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1077936128
.align 4
.LC2:
.long 1078523331
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <cuda_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
cudaMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_A, h_A, bytes, cudaMemcpyHostToDevice ) ;
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
cudaDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
cudaMemcpy( h_dC, d_C, bytes, cudaMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
cudaFree( d_A ) ; cudaFree( d_B ) ; cudaFree( d_C ) ;
cudaDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <hip/hip_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
hipMalloc( (void **) &d_A, bytes ) ;
hipMalloc( (void **) &d_B, bytes ) ;
hipMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
hipMemcpy( d_A, h_A, bytes, hipMemcpyHostToDevice ) ;
hipMemcpy( d_B, h_B, bytes, hipMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
hipDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
hipMemcpy( h_dC, d_C, bytes, hipMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
hipFree( d_A ) ; hipFree( d_B ) ; hipFree( d_C ) ;
hipDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <hip/hip_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
hipMalloc( (void **) &d_A, bytes ) ;
hipMalloc( (void **) &d_B, bytes ) ;
hipMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
hipMemcpy( d_A, h_A, bytes, hipMemcpyHostToDevice ) ;
hipMemcpy( d_B, h_B, bytes, hipMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
hipDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
hipMemcpy( h_dC, d_C, bytes, hipMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
hipFree( d_A ) ; hipFree( d_B ) ; hipFree( d_C ) ;
hipDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8f_addmatPfS_S_ii
.globl _Z8f_addmatPfS_S_ii
.p2align 8
.type _Z8f_addmatPfS_S_ii,@function
_Z8f_addmatPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x18
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8f_addmatPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8f_addmatPfS_S_ii, .Lfunc_end0-_Z8f_addmatPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8f_addmatPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8f_addmatPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <sys/time.h>
#include <stdio.h>
#include <math.h>
//TODO for writing to file, will be deleted
#include <stdlib.h>
//TODO: could include later
//#include <device_launch_parameters.h>
#include <hip/hip_runtime.h>
//#include "../inc/helper_cuda.h"
#define GRID_YDIM 65535
// time stamp function in seconds
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000000 + tv.tv_sec ;
}
void initDataA(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float) (i+j)/3.0;
}
}
}
void initDataB(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
data[i*ny + j] = (float)3.14*(i+j);
}
}
}
void debugPrint(float* data, int nx, int ny){
int i,j;
for(i = 0; i < nx; i++){
for(j = 0; j < ny; j++){
printf("%f ",data[i*ny + j]);
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_addmat(float *A, float *B, float *C, int nx, int ny){
int i;
for(i = 0; i < nx*ny; i++){
C[i] = A[i] + B[i];
}
}
// device-side matrix addition
//__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// // kernel code might look something like this
// // but you may want to pad the matrices and index into them accordingly
// int ix = threadIdx.x + blockIdx.x*blockDim.x ;
// int iy = threadIdx.y + blockIdx.y*blockDim.y ;
// int idx = iy*nx + ix ;
// if( (ix<nx) && (iy<ny) )
// C[idx] = A[idx] + B[idx] ;
//}
__global__ void f_addmat( float *A, float *B, float *C, int nx, int ny ){
// kernel code might look something like this
// but you may want to pad the matrices and index into them accordingly
int ix = threadIdx.x + blockIdx.x*blockDim.x ;
int iy = threadIdx.y + blockIdx.y*blockDim.y ;
int idx = iy*blockDim.x*gridDim.x + ix ;
if(idx<nx*ny)
C[idx] = A[idx] + B[idx] ;
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 3) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int nx = atoi( argv[1] ) ; // should check validity
int ny = atoi( argv[2] ) ; // should check validity
int noElems = nx*ny ;
int bytes = noElems * sizeof(float) ;
// but you may want to pad the matrices…
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
float *h_B = (float *) malloc( bytes ) ;
float *h_hC = (float *) malloc( bytes ) ; // host result
float *h_dC = (float *) malloc( bytes ) ; // gpu result
// init matrices with random data
//initData( h_A, noElems ) ; initData( h_B, noElems ) ;
initDataA(h_A, nx, ny);
initDataB(h_B, nx, ny);
// alloc memory dev-side
float *d_A, *d_B, *d_C ;
hipMalloc( (void **) &d_A, bytes ) ;
hipMalloc( (void **) &d_B, bytes ) ;
hipMalloc( (void **) &d_C, bytes ) ;
// invoke Kernel
dim3 block( 32, 32 ) ; // you will want to configure this
//int block = 64;
//int grid = (noElems + block-1)/block;
int gy = (int)sqrt(noElems);
int gx = (noElems+gy-1)/gy;
//printf("prev gx %d and gy %d\n",gx,gy);
if(gy > GRID_YDIM){
gx = (gx*gy+GRID_YDIM-1)/GRID_YDIM;
gy = GRID_YDIM;
}
//printf("gx %d and gy %d\n",gx,gy);
gx = (gx+block.x-1)/block.x;
gy = (gy+block.y-1)/block.y;
dim3 grid( gx, gy ) ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
printf("noelems is %d\n",noElems);
//printf("gridx is %d\n",grid);
//printf("gridx is %d and grid y is %d\n",grid.x,grid.y);
double timeStampA = getTimeStamp() ;
//transfer data to dev
hipMemcpy( d_A, h_A, bytes, hipMemcpyHostToDevice ) ;
hipMemcpy( d_B, h_B, bytes, hipMemcpyHostToDevice ) ;
// note that the transfers would be twice as fast if h_A and h_B
// matrices are pinned
double timeStampB = getTimeStamp() ;
f_addmat<<<grid, block>>>( d_A, d_B, d_C, nx, ny ) ;
hipDeviceSynchronize() ;
double timeStampC = getTimeStamp() ;
//copy data back
hipMemcpy( h_dC, d_C, bytes, hipMemcpyDeviceToHost ) ;
double timeStampD = getTimeStamp() ;
// free GPU resources
hipFree( d_A ) ; hipFree( d_B ) ; hipFree( d_C ) ;
hipDeviceReset() ;
// check result
h_addmat( h_A, h_B, h_hC, nx, ny ) ;
// print out results
if(!memcmp(h_hC,h_dC,nx*ny*sizeof(float))){
//debugPrint(h_hC, nx, ny);
//debugPrint(h_dC, nx, ny);
FILE* fptr;
fptr = fopen("time.log","a");
fprintf(fptr,"%dX%d %.6f %.6f %.6f %.6f\n", nx, ny, timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
fclose(fptr);
printf("%.6f %.6f %.6f %.6f\n", timeStampD-timeStampA, timeStampB-timeStampA, timeStampC-timeStampB, timeStampD-timeStampC);
}else{
printf("Error: function failed.\n");
}
} | .text
.file "main_v1_sqr_grid.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12getTimeStampv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12getTimeStampv
.p2align 4, 0x90
.type _Z12getTimeStampv,@function
_Z12getTimeStampv: # @_Z12getTimeStampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI0_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12getTimeStampv, .Lfunc_end0-_Z12getTimeStampv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initDataAPfii
.LCPI1_0:
.long 0x40400000 # float 3
.text
.globl _Z9initDataAPfii
.p2align 4, 0x90
.type _Z9initDataAPfii,@function
_Z9initDataAPfii: # @_Z9initDataAPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %r11d
xorps %xmm1, %xmm1
cvtsi2ss %r11d, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z9initDataAPfii, .Lfunc_end1-_Z9initDataAPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initDataBPfii
.LCPI2_0:
.long 0x4048f5c3 # float 3.1400001
.text
.globl _Z9initDataBPfii
.p2align 4, 0x90
.type _Z9initDataBPfii,@function
_Z9initDataBPfii: # @_Z9initDataBPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %r11d
xorps %xmm1, %xmm1
cvtsi2ss %r11d, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge15
retq
.Lfunc_end2:
.size _Z9initDataBPfii, .Lfunc_end2-_Z9initDataBPfii
.cfi_endproc
# -- End function
.globl _Z10debugPrintPfii # -- Begin function _Z10debugPrintPfii
.p2align 4, 0x90
.type _Z10debugPrintPfii,@function
_Z10debugPrintPfii: # @_Z10debugPrintPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z10debugPrintPfii, .Lfunc_end3-_Z10debugPrintPfii
.cfi_endproc
# -- End function
.globl _Z8h_addmatPfS_S_ii # -- Begin function _Z8h_addmatPfS_S_ii
.p2align 4, 0x90
.type _Z8h_addmatPfS_S_ii,@function
_Z8h_addmatPfS_S_ii: # @_Z8h_addmatPfS_S_ii
.cfi_startproc
# %bb.0:
imull %r8d, %ecx
testl %ecx, %ecx
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z8h_addmatPfS_S_ii, .Lfunc_end4-_Z8h_addmatPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__f_addmatPfS_S_ii # -- Begin function _Z23__device_stub__f_addmatPfS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__f_addmatPfS_S_ii,@function
_Z23__device_stub__f_addmatPfS_S_ii: # @_Z23__device_stub__f_addmatPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8f_addmatPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z23__device_stub__f_addmatPfS_S_ii, .Lfunc_end5-_Z23__device_stub__f_addmatPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x40400000 # float 3
.LCPI6_1:
.long 0x4048f5c3 # float 3.1400001
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB6_27
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %rax, 40(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r15d, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movslq %eax, %r15
movq %r15, 128(%rsp) # 8-byte Spill
shlq $34, %r15
sarq $32, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, (%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq 40(%rsp), %r9 # 8-byte Reload
movq %rax, 168(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB6_13
# %bb.2: # %.preheader.lr.ph.i
movl %r9d, %eax
movl %r14d, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %r14d, %ebp
cmpq %rax, %rdx
je .LBB6_7
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %r14d, %r14d
jle .LBB6_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %ebp, %esi
leaq (%r12,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rdi), %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
jne .LBB6_5
jmp .LBB6_6
.LBB6_7: # %_Z9initDataAPfii.exit
testl %r9d, %r9d
jle .LBB6_13
# %bb.8: # %.preheader.lr.ph.i79
movl %r9d, %eax
movl %r14d, %ecx
xorl %edx, %edx
movss .LCPI6_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i83
# in Loop: Header=BB6_9 Depth=1
incq %rsi
addl %r14d, %edx
cmpq %rax, %rsi
je .LBB6_13
.LBB6_9: # %.preheader.i81
# =>This Loop Header: Depth=1
# Child Loop BB6_11 Depth 2
testl %r14d, %r14d
jle .LBB6_12
# %bb.10: # %.lr.ph.i86
# in Loop: Header=BB6_9 Depth=1
movl %edx, %edi
leaq (,%rdi,4), %rdi
addq %r13, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_11: # Parent Loop BB6_9 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rsi,%r8), %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB6_11
jmp .LBB6_12
.LBB6_13: # %_Z9initDataBPfii.exit
leaq 64(%rsp), %rdi
movq (%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %r15 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB6_15
# %bb.14:
sqrtsd %xmm0, %xmm0
jmp .LBB6_16
.LBB6_15: # %call.sqrt
callq sqrt
movq 24(%rsp), %r15 # 8-byte Reload
.LBB6_16: # %_Z9initDataBPfii.exit.split
cvttsd2si %xmm0, %ebp
leal (%r15,%rbp), %eax
decl %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
cmpl $65536, %ebp # imm = 0x10000
jl .LBB6_18
# %bb.17:
imull %ebp, %eax
movl %eax, %ecx
addl $65534, %ecx # imm = 0xFFFE
movslq %ecx, %rcx
imulq $-2147450879, %rcx, %rcx # imm = 0x80008001
shrq $32, %rcx
addl %ecx, %eax
addl $65534, %eax # imm = 0xFFFE
movl %eax, %ecx
shrl $31, %ecx
sarl $15, %eax
addl %ecx, %eax
movl $65535, %ebp # imm = 0xFFFF
.LBB6_18:
addl $31, %eax
shrl $5, %eax
addl $31, %ebp
shrl $5, %ebp
shlq $32, %rbp
orq %rax, %rbp
movl $.L.str.3, %edi
movq %r15, %rsi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %r12, %rsi
movq (%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_20
# %bb.19:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
movl %r14d, 72(%rsp)
leaq 240(%rsp), %rax
movq %rax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 88(%rsp)
leaq 224(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8f_addmatPfS_S_ii, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_20:
shlq $2, 128(%rsp) # 8-byte Folded Spill
callq hipDeviceSynchronize
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 48(%rsp), %rsi
movq 168(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movq 24(%rsp), %r15 # 8-byte Reload
testl %r15d, %r15d
jle .LBB6_23
# %bb.21: # %.lr.ph.preheader.i
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_22: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%r12,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r13,%rcx,4), %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_22
.LBB6_23: # %_Z8h_addmatPfS_S_ii.exit
movq %rbx, %rdi
movq %rbp, %rsi
movq 128(%rsp), %rdx # 8-byte Reload
callq bcmp@PLT
testl %eax, %eax
je .LBB6_24
# %bb.25:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB6_26
.LBB6_24:
movsd .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 160(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 152(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 144(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 136(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
movsd (%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movapd %xmm3, %xmm1
movsd 32(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
subsd %xmm5, %xmm1
movapd %xmm1, %xmm0
movsd %xmm1, 24(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm1, %xmm3
movsd %xmm3, (%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
subsd %xmm4, %xmm1
movapd %xmm1, %xmm2
movsd %xmm1, 8(%rsp) # 8-byte Spill
subsd %xmm5, %xmm4
movapd %xmm4, %xmm1
movsd %xmm4, 16(%rsp) # 8-byte Spill
movl $.L.str.6, %esi
movq %rax, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %r14d, %ecx
movb $4, %al
callq fprintf
movq %rbx, %rdi
callq fclose
movl $.L.str.7, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd (%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movb $4, %al
callq printf
.LBB6_26:
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_27:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8f_addmatPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type _Z8f_addmatPfS_S_ii,@object # @_Z8f_addmatPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z8f_addmatPfS_S_ii
.p2align 3, 0x0
_Z8f_addmatPfS_S_ii:
.quad _Z23__device_stub__f_addmatPfS_S_ii
.size _Z8f_addmatPfS_S_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "noelems is %d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time.log"
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "a"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%dX%d %.6f %.6f %.6f %.6f\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%.6f %.6f %.6f %.6f\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8f_addmatPfS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: function failed."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error: wrong number of args"
.size .Lstr.1, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__f_addmatPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8f_addmatPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8f_addmatPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8f_addmatPfS_S_ii
.globl _Z8f_addmatPfS_S_ii
.p2align 8
.type _Z8f_addmatPfS_S_ii,@function
_Z8f_addmatPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x18
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8f_addmatPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8f_addmatPfS_S_ii, .Lfunc_end0-_Z8f_addmatPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8f_addmatPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8f_addmatPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e6367_00000000-6_main_v1_sqr_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12getTimeStampv
.type _Z12getTimeStampv, @function
_Z12getTimeStampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12getTimeStampv, .-_Z12getTimeStampv
.globl _Z9initDataAPfii
.type _Z9initDataAPfii, @function
_Z9initDataAPfii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movl %edx, %r8d
movl $0, %r10d
movl $0, %r9d
movss .LC1(%rip), %xmm1
jmp .L9
.L11:
movl %r9d, %eax
movslq %r10d, %rcx
leaq (%rdi,%rcx,4), %rcx
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addq $4, %rcx
cmpl %r8d, %eax
jne .L10
.L12:
addl $1, %r9d
addl %edx, %r10d
addl $1, %r8d
cmpl %r9d, %esi
je .L7
.L9:
testl %edx, %edx
jg .L11
jmp .L12
.L7:
ret
.cfi_endproc
.LFE2058:
.size _Z9initDataAPfii, .-_Z9initDataAPfii
.globl _Z9initDataBPfii
.type _Z9initDataBPfii, @function
_Z9initDataBPfii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
movl %edx, %r8d
movl $0, %r10d
movl $0, %r9d
movss .LC2(%rip), %xmm1
jmp .L16
.L18:
movl %r9d, %eax
movslq %r10d, %rcx
leaq (%rdi,%rcx,4), %rcx
.L17:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addq $4, %rcx
cmpl %r8d, %eax
jne .L17
.L19:
addl $1, %r9d
addl %edx, %r10d
addl $1, %r8d
cmpl %r9d, %esi
je .L14
.L16:
testl %edx, %edx
jg .L18
jmp .L19
.L14:
ret
.cfi_endproc
.LFE2059:
.size _Z9initDataBPfii, .-_Z9initDataBPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f "
.LC4:
.string "\n"
.text
.globl _Z10debugPrintPfii
.type _Z10debugPrintPfii, @function
_Z10debugPrintPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L22
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
jmp .L23
.L25:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L26:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L22
.L23:
testl %r15d, %r15d
jg .L25
jmp .L26
.L22:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10debugPrintPfii, .-_Z10debugPrintPfii
.globl _Z8h_addmatPfS_S_ii
.type _Z8h_addmatPfS_S_ii, @function
_Z8h_addmatPfS_S_ii:
.LFB2061:
.cfi_startproc
endbr64
imull %r8d, %ecx
testl %ecx, %ecx
jle .L29
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L31:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L31
.L29:
ret
.cfi_endproc
.LFE2061:
.size _Z8h_addmatPfS_S_ii, .-_Z8h_addmatPfS_S_ii
.globl _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
.type _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii, @function
_Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8f_addmatPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii, .-_Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
.globl _Z8f_addmatPfS_S_ii
.type _Z8f_addmatPfS_S_ii, @function
_Z8f_addmatPfS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8f_addmatPfS_S_ii, .-_Z8f_addmatPfS_S_ii
.section .rodata.str1.1
.LC5:
.string "Error: wrong number of args\n"
.LC7:
.string "noelems is %d\n"
.LC8:
.string "a"
.LC9:
.string "time.log"
.LC10:
.string "%dX%d %.6f %.6f %.6f %.6f\n"
.LC11:
.string "%.6f %.6f %.6f %.6f\n"
.LC12:
.string "Error: function failed.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L54
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, (%rsp)
imull %eax, %ebp
movslq %ebp, %rax
movq %rax, 8(%rsp)
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movl (%rsp), %edx
movl %r15d, %esi
movq %r13, %rdi
call _Z9initDataAPfii
movl (%rsp), %edx
movl %r15d, %esi
movq %r14, %rdi
call _Z9initDataBPfii
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 88(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L52
sqrtsd %xmm0, %xmm0
.L45:
cvttsd2sil %xmm0, %ecx
leal -1(%rcx,%rbp), %eax
cltd
idivl %ecx
movl %eax, %esi
cmpl $65535, %ecx
jle .L46
imull %eax, %ecx
leal 65534(%rcx), %eax
movl $65535, %ecx
cltd
idivl %ecx
movl %eax, %esi
.L46:
addl $31, %esi
shrl $5, %esi
movl %esi, 92(%rsp)
addl $31, %ecx
shrl $5, %ecx
movl %ecx, 96(%rsp)
movl $1, 100(%rsp)
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z12getTimeStampv
movsd %xmm0, (%rsp)
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call _Z12getTimeStampv
movsd %xmm0, 32(%rsp)
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L47:
call cudaDeviceSynchronize@PLT
call _Z12getTimeStampv
movsd %xmm0, 40(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z12getTimeStampv
movsd %xmm0, 24(%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movl %r12d, %r8d
movl %r15d, %ecx
movq 16(%rsp), %rbx
movq %rbx, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z8h_addmatPfS_S_ii
movq 8(%rsp), %rax
salq $2, %rax
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L48
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movsd 24(%rsp), %xmm4
movapd %xmm4, %xmm5
movsd 40(%rsp), %xmm6
subsd %xmm6, %xmm5
movq %xmm5, %r14
movsd 32(%rsp), %xmm7
subsd %xmm7, %xmm6
movq %xmm6, %r13
movsd (%rsp), %xmm2
subsd %xmm2, %xmm7
movq %xmm7, %rbp
subsd %xmm2, %xmm4
movsd %xmm4, (%rsp)
movapd %xmm5, %xmm3
movapd %xmm6, %xmm2
movapd %xmm7, %xmm1
movapd %xmm4, %xmm0
movl %r12d, %r8d
movl %r15d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $4, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, %xmm3
movq %r13, %xmm2
movq %rbp, %xmm1
movsd (%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
call sqrt@PLT
jmp .L45
.L55:
movl %r12d, %r8d
movl %r15d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z33__device_stub__Z8f_addmatPfS_S_iiPfS_S_ii
jmp .L47
.L48:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8f_addmatPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8f_addmatPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1077936128
.align 4
.LC2:
.long 1078523331
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main_v1_sqr_grid.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12getTimeStampv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12getTimeStampv
.p2align 4, 0x90
.type _Z12getTimeStampv,@function
_Z12getTimeStampv: # @_Z12getTimeStampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI0_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12getTimeStampv, .Lfunc_end0-_Z12getTimeStampv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initDataAPfii
.LCPI1_0:
.long 0x40400000 # float 3
.text
.globl _Z9initDataAPfii
.p2align 4, 0x90
.type _Z9initDataAPfii,@function
_Z9initDataAPfii: # @_Z9initDataAPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %r11d
xorps %xmm1, %xmm1
cvtsi2ss %r11d, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z9initDataAPfii, .Lfunc_end1-_Z9initDataAPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initDataBPfii
.LCPI2_0:
.long 0x4048f5c3 # float 3.1400001
.text
.globl _Z9initDataBPfii
.p2align 4, 0x90
.type _Z9initDataBPfii,@function
_Z9initDataBPfii: # @_Z9initDataBPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %r11d
xorps %xmm1, %xmm1
cvtsi2ss %r11d, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge15
retq
.Lfunc_end2:
.size _Z9initDataBPfii, .Lfunc_end2-_Z9initDataBPfii
.cfi_endproc
# -- End function
.globl _Z10debugPrintPfii # -- Begin function _Z10debugPrintPfii
.p2align 4, 0x90
.type _Z10debugPrintPfii,@function
_Z10debugPrintPfii: # @_Z10debugPrintPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z10debugPrintPfii, .Lfunc_end3-_Z10debugPrintPfii
.cfi_endproc
# -- End function
.globl _Z8h_addmatPfS_S_ii # -- Begin function _Z8h_addmatPfS_S_ii
.p2align 4, 0x90
.type _Z8h_addmatPfS_S_ii,@function
_Z8h_addmatPfS_S_ii: # @_Z8h_addmatPfS_S_ii
.cfi_startproc
# %bb.0:
imull %r8d, %ecx
testl %ecx, %ecx
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z8h_addmatPfS_S_ii, .Lfunc_end4-_Z8h_addmatPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__f_addmatPfS_S_ii # -- Begin function _Z23__device_stub__f_addmatPfS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__f_addmatPfS_S_ii,@function
_Z23__device_stub__f_addmatPfS_S_ii: # @_Z23__device_stub__f_addmatPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8f_addmatPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z23__device_stub__f_addmatPfS_S_ii, .Lfunc_end5-_Z23__device_stub__f_addmatPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x40400000 # float 3
.LCPI6_1:
.long 0x4048f5c3 # float 3.1400001
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB6_27
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %rax, 40(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r15d, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movslq %eax, %r15
movq %r15, 128(%rsp) # 8-byte Spill
shlq $34, %r15
sarq $32, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, (%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq 40(%rsp), %r9 # 8-byte Reload
movq %rax, 168(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB6_13
# %bb.2: # %.preheader.lr.ph.i
movl %r9d, %eax
movl %r14d, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %r14d, %ebp
cmpq %rax, %rdx
je .LBB6_7
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %r14d, %r14d
jle .LBB6_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %ebp, %esi
leaq (%r12,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rdi), %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
jne .LBB6_5
jmp .LBB6_6
.LBB6_7: # %_Z9initDataAPfii.exit
testl %r9d, %r9d
jle .LBB6_13
# %bb.8: # %.preheader.lr.ph.i79
movl %r9d, %eax
movl %r14d, %ecx
xorl %edx, %edx
movss .LCPI6_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i83
# in Loop: Header=BB6_9 Depth=1
incq %rsi
addl %r14d, %edx
cmpq %rax, %rsi
je .LBB6_13
.LBB6_9: # %.preheader.i81
# =>This Loop Header: Depth=1
# Child Loop BB6_11 Depth 2
testl %r14d, %r14d
jle .LBB6_12
# %bb.10: # %.lr.ph.i86
# in Loop: Header=BB6_9 Depth=1
movl %edx, %edi
leaq (,%rdi,4), %rdi
addq %r13, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_11: # Parent Loop BB6_9 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rsi,%r8), %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB6_11
jmp .LBB6_12
.LBB6_13: # %_Z9initDataBPfii.exit
leaq 64(%rsp), %rdi
movq (%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %r15 # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB6_15
# %bb.14:
sqrtsd %xmm0, %xmm0
jmp .LBB6_16
.LBB6_15: # %call.sqrt
callq sqrt
movq 24(%rsp), %r15 # 8-byte Reload
.LBB6_16: # %_Z9initDataBPfii.exit.split
cvttsd2si %xmm0, %ebp
leal (%r15,%rbp), %eax
decl %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
cmpl $65536, %ebp # imm = 0x10000
jl .LBB6_18
# %bb.17:
imull %ebp, %eax
movl %eax, %ecx
addl $65534, %ecx # imm = 0xFFFE
movslq %ecx, %rcx
imulq $-2147450879, %rcx, %rcx # imm = 0x80008001
shrq $32, %rcx
addl %ecx, %eax
addl $65534, %eax # imm = 0xFFFE
movl %eax, %ecx
shrl $31, %ecx
sarl $15, %eax
addl %ecx, %eax
movl $65535, %ebp # imm = 0xFFFF
.LBB6_18:
addl $31, %eax
shrl $5, %eax
addl $31, %ebp
shrl $5, %ebp
shlq $32, %rbp
orq %rax, %rbp
movl $.L.str.3, %edi
movq %r15, %rsi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %r12, %rsi
movq (%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_20
# %bb.19:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
movl %r14d, 72(%rsp)
leaq 240(%rsp), %rax
movq %rax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 88(%rsp)
leaq 224(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8f_addmatPfS_S_ii, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_20:
shlq $2, 128(%rsp) # 8-byte Folded Spill
callq hipDeviceSynchronize
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 48(%rsp), %rsi
movq 168(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movq 24(%rsp), %r15 # 8-byte Reload
testl %r15d, %r15d
jle .LBB6_23
# %bb.21: # %.lr.ph.preheader.i
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_22: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%r12,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r13,%rcx,4), %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_22
.LBB6_23: # %_Z8h_addmatPfS_S_ii.exit
movq %rbx, %rdi
movq %rbp, %rsi
movq 128(%rsp), %rdx # 8-byte Reload
callq bcmp@PLT
testl %eax, %eax
je .LBB6_24
# %bb.25:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB6_26
.LBB6_24:
movsd .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 160(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 152(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 144(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 136(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
movsd (%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movapd %xmm3, %xmm1
movsd 32(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
subsd %xmm5, %xmm1
movapd %xmm1, %xmm0
movsd %xmm1, 24(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm1, %xmm3
movsd %xmm3, (%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
subsd %xmm4, %xmm1
movapd %xmm1, %xmm2
movsd %xmm1, 8(%rsp) # 8-byte Spill
subsd %xmm5, %xmm4
movapd %xmm4, %xmm1
movsd %xmm4, 16(%rsp) # 8-byte Spill
movl $.L.str.6, %esi
movq %rax, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %r14d, %ecx
movb $4, %al
callq fprintf
movq %rbx, %rdi
callq fclose
movl $.L.str.7, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd (%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movb $4, %al
callq printf
.LBB6_26:
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_27:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8f_addmatPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type _Z8f_addmatPfS_S_ii,@object # @_Z8f_addmatPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z8f_addmatPfS_S_ii
.p2align 3, 0x0
_Z8f_addmatPfS_S_ii:
.quad _Z23__device_stub__f_addmatPfS_S_ii
.size _Z8f_addmatPfS_S_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "noelems is %d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time.log"
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "a"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%dX%d %.6f %.6f %.6f %.6f\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%.6f %.6f %.6f %.6f\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8f_addmatPfS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: function failed."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error: wrong number of args"
.size .Lstr.1, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__f_addmatPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8f_addmatPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} | code for sm_80
Function : _Z14dotProductCudaPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ LEA R8, R0, R5, 0xa ; /* 0x0000000500087211 */
/* 0x001fca00078e50ff */
/*0060*/ IMAD.WIDE.U32 R6, R8, R3, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fc800078e0003 */
/*0070*/ IMAD.WIDE.U32 R8, R8, R3, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe400078e0003 */
/*0080*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R5.reuse, 0x1ff, PT ; /* 0x000001ff0500780c */
/* 0x040fe40003f04070 */
/*00b0*/ ISETP.GT.U32.AND P1, PT, R5, 0xff, PT ; /* 0x000000ff0500780c */
/* 0x000fe20003f24070 */
/*00c0*/ FMUL R2, R8, R7 ; /* 0x0000000708027220 */
/* 0x004fca0000400000 */
/*00d0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x000fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 LDS R4, [R5.X4] ; /* 0x0000000005048984 */
/* 0x000fe80000004800 */
/*0100*/ @!P0 LDS R11, [R5.X4+0x800] ; /* 0x00080000050b8984 */
/* 0x000e240000004800 */
/*0110*/ @!P0 FADD R4, R4, R11 ; /* 0x0000000b04048221 */
/* 0x001fca0000000000 */
/*0120*/ @!P0 STS [R5.X4], R4 ; /* 0x0000000405008388 */
/* 0x000fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R5, 0x7f, PT ; /* 0x0000007f0500780c */
/* 0x000fca0003f04070 */
/*0150*/ @!P1 LDS R6, [R5.X4] ; /* 0x0000000005069984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R7, [R5.X4+0x400] ; /* 0x0004000005079984 */
/* 0x000e240000004800 */
/*0170*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R5.X4], R6 ; /* 0x0000000605009388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R5, 0x3f, PT ; /* 0x0000003f0500780c */
/* 0x000fca0003f24070 */
/*01b0*/ @!P0 LDS R2, [R5.X4] ; /* 0x0000000005028984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P0 LDS R7, [R5.X4+0x200] ; /* 0x0002000005078984 */
/* 0x000e240000004800 */
/*01d0*/ @!P0 FADD R2, R2, R7 ; /* 0x0000000702028221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R5, 0x1f, PT ; /* 0x0000001f0500780c */
/* 0x000fca0003f04070 */
/*0210*/ @!P1 LDS R4, [R5.X4] ; /* 0x0000000005049984 */
/* 0x000fe80000004800 */
/*0220*/ @!P1 LDS R7, [R5.X4+0x100] ; /* 0x0001000005079984 */
/* 0x000e240000004800 */
/*0230*/ @!P1 FADD R4, R4, R7 ; /* 0x0000000704049221 */
/* 0x001fca0000000000 */
/*0240*/ @!P1 STS [R5.X4], R4 ; /* 0x0000000405009388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R5, 0xf, PT ; /* 0x0000000f0500780c */
/* 0x000fca0003f24070 */
/*0270*/ @!P0 LDS R6, [R5.X4] ; /* 0x0000000005068984 */
/* 0x000fe80000004800 */
/*0280*/ @!P0 LDS R7, [R5.X4+0x80] ; /* 0x0000800005078984 */
/* 0x000e240000004800 */
/*0290*/ @!P0 FADD R6, R6, R7 ; /* 0x0000000706068221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P0 STS [R5.X4], R6 ; /* 0x0000000605008388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R5, 0x7, PT ; /* 0x000000070500780c */
/* 0x000fca0003f04070 */
/*02d0*/ @!P1 LDS R2, [R5.X4] ; /* 0x0000000005029984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P1 LDS R7, [R5.X4+0x40] ; /* 0x0000400005079984 */
/* 0x000e240000004800 */
/*02f0*/ @!P1 FADD R2, R2, R7 ; /* 0x0000000702029221 */
/* 0x001fca0000000000 */
/*0300*/ @!P1 STS [R5.X4], R2 ; /* 0x0000000205009388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fca0003f24070 */
/*0330*/ @!P0 LDS R4, [R5.X4] ; /* 0x0000000005048984 */
/* 0x000fe80000004800 */
/*0340*/ @!P0 LDS R7, [R5.X4+0x20] ; /* 0x0000200005078984 */
/* 0x000e240000004800 */
/*0350*/ @!P0 FADD R4, R4, R7 ; /* 0x0000000704048221 */
/* 0x001fca0000000000 */
/*0360*/ @!P0 STS [R5.X4], R4 ; /* 0x0000000405008388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fca0003f04070 */
/*0390*/ @!P1 LDS R6, [R5.X4] ; /* 0x0000000005069984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P1 LDS R7, [R5.X4+0x10] ; /* 0x0000100005079984 */
/* 0x000e240000004800 */
/*03b0*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P1 STS [R5.X4], R6 ; /* 0x0000000605009388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fca0003f25270 */
/*03f0*/ @!P0 LDS R2, [R5.X4] ; /* 0x0000000005028984 */
/* 0x000fe80000004800 */
/*0400*/ @!P0 LDS R7, [R5.X4+0x8] ; /* 0x0000080005078984 */
/* 0x000e240000004800 */
/*0410*/ @!P0 FADD R2, R2, R7 ; /* 0x0000000702028221 */
/* 0x001fca0000000000 */
/*0420*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @!P1 LDS R4, [R5.X4] ; /* 0x0000000005049984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R7, [0x4] ; /* 0x00000400ff079984 */
/* 0x000e240000000800 */
/*0460*/ @!P1 FADD R4, R4, R7 ; /* 0x0000000704049221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R5.X4], R4 ; /* 0x0000000405009388 */
/* 0x0001e80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04a0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*04b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*04c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} | .file "tmpxft_000bfa63_00000000-6_dotProductCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
.type _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_, @function
_Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14dotProductCudaPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_, .-_Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
.globl _Z14dotProductCudaPfS_S_
.type _Z14dotProductCudaPfS_S_, @function
_Z14dotProductCudaPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14dotProductCudaPfS_S_, .-_Z14dotProductCudaPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14dotProductCudaPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dotProductCudaPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14dotProductCudaPfS_S_
.globl _Z14dotProductCudaPfS_S_
.p2align 8
.type _Z14dotProductCudaPfS_S_,@function
_Z14dotProductCudaPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v2, 0
v_lshl_or_b32 v1, s2, 10, v0
s_movk_i32 s3, 0x200
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v3, v2 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_4:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dotProductCudaPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14dotProductCudaPfS_S_, .Lfunc_end0-_Z14dotProductCudaPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dotProductCudaPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14dotProductCudaPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define CUDA_THREAD_NUM 1024
// must be a multiply of 2
void dotProductCPU();
__global__ void dotProductCuda(float *a, float *b, float *c) {
__shared__ float se[CUDA_THREAD_NUM];
// Calculate a.*b
se[threadIdx.x]=a[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM]*b[threadIdx.x+blockIdx.x*CUDA_THREAD_NUM];
__syncthreads();
// Sum Reducto
int numActiveThreads=CUDA_THREAD_NUM/2;
while(numActiveThreads>0) {
if(threadIdx.x<numActiveThreads) {
se[threadIdx.x]=se[threadIdx.x]+se[threadIdx.x+numActiveThreads];
}
numActiveThreads=numActiveThreads/2;
__syncthreads();
}
if(threadIdx.x==0) {
c[blockIdx.x]=se[0];
//printf("BlockId: %d, ThreadID: %d, %f \n",blockIdx.x,threadIdx.x,c[blockIdx.x]);
}
return;
} | .text
.file "dotProductCuda.hip"
.globl _Z29__device_stub__dotProductCudaPfS_S_ # -- Begin function _Z29__device_stub__dotProductCudaPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__dotProductCudaPfS_S_,@function
_Z29__device_stub__dotProductCudaPfS_S_: # @_Z29__device_stub__dotProductCudaPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14dotProductCudaPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__dotProductCudaPfS_S_, .Lfunc_end0-_Z29__device_stub__dotProductCudaPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dotProductCudaPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14dotProductCudaPfS_S_,@object # @_Z14dotProductCudaPfS_S_
.section .rodata,"a",@progbits
.globl _Z14dotProductCudaPfS_S_
.p2align 3, 0x0
_Z14dotProductCudaPfS_S_:
.quad _Z29__device_stub__dotProductCudaPfS_S_
.size _Z14dotProductCudaPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14dotProductCudaPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__dotProductCudaPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14dotProductCudaPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14dotProductCudaPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ LEA R8, R0, R5, 0xa ; /* 0x0000000500087211 */
/* 0x001fca00078e50ff */
/*0060*/ IMAD.WIDE.U32 R6, R8, R3, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fc800078e0003 */
/*0070*/ IMAD.WIDE.U32 R8, R8, R3, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe400078e0003 */
/*0080*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R5.reuse, 0x1ff, PT ; /* 0x000001ff0500780c */
/* 0x040fe40003f04070 */
/*00b0*/ ISETP.GT.U32.AND P1, PT, R5, 0xff, PT ; /* 0x000000ff0500780c */
/* 0x000fe20003f24070 */
/*00c0*/ FMUL R2, R8, R7 ; /* 0x0000000708027220 */
/* 0x004fca0000400000 */
/*00d0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x000fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 LDS R4, [R5.X4] ; /* 0x0000000005048984 */
/* 0x000fe80000004800 */
/*0100*/ @!P0 LDS R11, [R5.X4+0x800] ; /* 0x00080000050b8984 */
/* 0x000e240000004800 */
/*0110*/ @!P0 FADD R4, R4, R11 ; /* 0x0000000b04048221 */
/* 0x001fca0000000000 */
/*0120*/ @!P0 STS [R5.X4], R4 ; /* 0x0000000405008388 */
/* 0x000fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R5, 0x7f, PT ; /* 0x0000007f0500780c */
/* 0x000fca0003f04070 */
/*0150*/ @!P1 LDS R6, [R5.X4] ; /* 0x0000000005069984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R7, [R5.X4+0x400] ; /* 0x0004000005079984 */
/* 0x000e240000004800 */
/*0170*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R5.X4], R6 ; /* 0x0000000605009388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R5, 0x3f, PT ; /* 0x0000003f0500780c */
/* 0x000fca0003f24070 */
/*01b0*/ @!P0 LDS R2, [R5.X4] ; /* 0x0000000005028984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P0 LDS R7, [R5.X4+0x200] ; /* 0x0002000005078984 */
/* 0x000e240000004800 */
/*01d0*/ @!P0 FADD R2, R2, R7 ; /* 0x0000000702028221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R5, 0x1f, PT ; /* 0x0000001f0500780c */
/* 0x000fca0003f04070 */
/*0210*/ @!P1 LDS R4, [R5.X4] ; /* 0x0000000005049984 */
/* 0x000fe80000004800 */
/*0220*/ @!P1 LDS R7, [R5.X4+0x100] ; /* 0x0001000005079984 */
/* 0x000e240000004800 */
/*0230*/ @!P1 FADD R4, R4, R7 ; /* 0x0000000704049221 */
/* 0x001fca0000000000 */
/*0240*/ @!P1 STS [R5.X4], R4 ; /* 0x0000000405009388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R5, 0xf, PT ; /* 0x0000000f0500780c */
/* 0x000fca0003f24070 */
/*0270*/ @!P0 LDS R6, [R5.X4] ; /* 0x0000000005068984 */
/* 0x000fe80000004800 */
/*0280*/ @!P0 LDS R7, [R5.X4+0x80] ; /* 0x0000800005078984 */
/* 0x000e240000004800 */
/*0290*/ @!P0 FADD R6, R6, R7 ; /* 0x0000000706068221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P0 STS [R5.X4], R6 ; /* 0x0000000605008388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R5, 0x7, PT ; /* 0x000000070500780c */
/* 0x000fca0003f04070 */
/*02d0*/ @!P1 LDS R2, [R5.X4] ; /* 0x0000000005029984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P1 LDS R7, [R5.X4+0x40] ; /* 0x0000400005079984 */
/* 0x000e240000004800 */
/*02f0*/ @!P1 FADD R2, R2, R7 ; /* 0x0000000702029221 */
/* 0x001fca0000000000 */
/*0300*/ @!P1 STS [R5.X4], R2 ; /* 0x0000000205009388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fca0003f24070 */
/*0330*/ @!P0 LDS R4, [R5.X4] ; /* 0x0000000005048984 */
/* 0x000fe80000004800 */
/*0340*/ @!P0 LDS R7, [R5.X4+0x20] ; /* 0x0000200005078984 */
/* 0x000e240000004800 */
/*0350*/ @!P0 FADD R4, R4, R7 ; /* 0x0000000704048221 */
/* 0x001fca0000000000 */
/*0360*/ @!P0 STS [R5.X4], R4 ; /* 0x0000000405008388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fca0003f04070 */
/*0390*/ @!P1 LDS R6, [R5.X4] ; /* 0x0000000005069984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P1 LDS R7, [R5.X4+0x10] ; /* 0x0000100005079984 */
/* 0x000e240000004800 */
/*03b0*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P1 STS [R5.X4], R6 ; /* 0x0000000605009388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fca0003f25270 */
/*03f0*/ @!P0 LDS R2, [R5.X4] ; /* 0x0000000005028984 */
/* 0x000fe80000004800 */
/*0400*/ @!P0 LDS R7, [R5.X4+0x8] ; /* 0x0000080005078984 */
/* 0x000e240000004800 */
/*0410*/ @!P0 FADD R2, R2, R7 ; /* 0x0000000702028221 */
/* 0x001fca0000000000 */
/*0420*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @!P1 LDS R4, [R5.X4] ; /* 0x0000000005049984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R7, [0x4] ; /* 0x00000400ff079984 */
/* 0x000e240000000800 */
/*0460*/ @!P1 FADD R4, R4, R7 ; /* 0x0000000704049221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R5.X4], R4 ; /* 0x0000000405009388 */
/* 0x0001e80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04a0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*04b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*04c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14dotProductCudaPfS_S_
.globl _Z14dotProductCudaPfS_S_
.p2align 8
.type _Z14dotProductCudaPfS_S_,@function
_Z14dotProductCudaPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v2, 0
v_lshl_or_b32 v1, s2, 10, v0
s_movk_i32 s3, 0x200
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v3, v2 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_4:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dotProductCudaPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14dotProductCudaPfS_S_, .Lfunc_end0-_Z14dotProductCudaPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dotProductCudaPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14dotProductCudaPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bfa63_00000000-6_dotProductCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
.type _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_, @function
_Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14dotProductCudaPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_, .-_Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
.globl _Z14dotProductCudaPfS_S_
.type _Z14dotProductCudaPfS_S_, @function
_Z14dotProductCudaPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14dotProductCudaPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14dotProductCudaPfS_S_, .-_Z14dotProductCudaPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14dotProductCudaPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dotProductCudaPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dotProductCuda.hip"
.globl _Z29__device_stub__dotProductCudaPfS_S_ # -- Begin function _Z29__device_stub__dotProductCudaPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__dotProductCudaPfS_S_,@function
_Z29__device_stub__dotProductCudaPfS_S_: # @_Z29__device_stub__dotProductCudaPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14dotProductCudaPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__dotProductCudaPfS_S_, .Lfunc_end0-_Z29__device_stub__dotProductCudaPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dotProductCudaPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14dotProductCudaPfS_S_,@object # @_Z14dotProductCudaPfS_S_
.section .rodata,"a",@progbits
.globl _Z14dotProductCudaPfS_S_
.p2align 3, 0x0
_Z14dotProductCudaPfS_S_:
.quad _Z29__device_stub__dotProductCudaPfS_S_
.size _Z14dotProductCudaPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14dotProductCudaPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__dotProductCudaPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14dotProductCudaPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
#include<stdio.h>
#include<iostream>
#include<thrust/host_vector.h>
#include<thrust/device_vector.h>
using namespace std;
struct saxpy_functor
{
const float a;
saxpy_functor(float _a): a(_a) {}
__host__ __device__
float operator()(const float& x, const float& b) const
{
return a * x + b;
}
};
void saxpy_fast(float a , thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(a));
}
int main(){
printf("Ready to test thrust\n");
int N = 10;
thrust::host_vector<float> h(N);
for(int i = 0; i < N; i++)
h[i] = i;
thrust::device_vector<float> d = h;
for(int i = 0; i < N / 2; i++)
d[i] = d[i] * -1;
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
saxpy_fast(2.0, d, d);
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagE13saxpy_functorNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R6, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R4, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R7, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R5, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000057a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R9, R6, c[0x0][0x180], R5 ; /* 0x0000600006097a23 */
/* 0x005fca0000000005 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FFMA R11, R0, c[0x0][0x180], R11 ; /* 0x00006000000b7a23 */
/* 0x004fca000000000b */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
#include<stdio.h>
#include<iostream>
#include<thrust/host_vector.h>
#include<thrust/device_vector.h>
using namespace std;
struct saxpy_functor
{
const float a;
saxpy_functor(float _a): a(_a) {}
__host__ __device__
float operator()(const float& x, const float& b) const
{
return a * x + b;
}
};
void saxpy_fast(float a , thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(a));
}
int main(){
printf("Ready to test thrust\n");
int N = 10;
thrust::host_vector<float> h(N);
for(int i = 0; i < N; i++)
h[i] = i;
thrust::device_vector<float> d = h;
for(int i = 0; i < N / 2; i++)
d[i] = d[i] * -1;
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
saxpy_fast(2.0, d, d);
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
return 0;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
#include<thrust/host_vector.h>
#include<thrust/device_vector.h>
using namespace std;
struct saxpy_functor
{
const float a;
saxpy_functor(float _a): a(_a) {}
__host__ __device__
float operator()(const float& x, const float& b) const
{
return a * x + b;
}
};
void saxpy_fast(float a , thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(a));
}
int main(){
printf("Ready to test thrust\n");
int N = 10;
thrust::host_vector<float> h(N);
for(int i = 0; i < N; i++)
h[i] = i;
thrust::device_vector<float> d = h;
for(int i = 0; i < N / 2; i++)
d[i] = d[i] * -1;
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
saxpy_fast(2.0, d, d);
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
#include<thrust/host_vector.h>
#include<thrust/device_vector.h>
using namespace std;
struct saxpy_functor
{
const float a;
saxpy_functor(float _a): a(_a) {}
__host__ __device__
float operator()(const float& x, const float& b) const
{
return a * x + b;
}
};
void saxpy_fast(float a , thrust::device_vector<float>& X, thrust::device_vector<float>& Y)
{
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(a));
}
int main(){
printf("Ready to test thrust\n");
int N = 10;
thrust::host_vector<float> h(N);
for(int i = 0; i < N; i++)
h[i] = i;
thrust::device_vector<float> d = h;
for(int i = 0; i < N / 2; i++)
d[i] = d[i] * -1;
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
saxpy_fast(2.0, d, d);
for(int i = 0; i < N; i++){
std::cout<<d[i]<<' ';
}
std::cout<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s0, v2
flat_store_b32 v[0:1], v3
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagE13saxpy_functorNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R6, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R4, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R7, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R5, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000057a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R9, R6, c[0x0][0x180], R5 ; /* 0x0000600006097a23 */
/* 0x005fca0000000005 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FFMA R9, R0, c[0x0][0x180], R9 ; /* 0x0000600000097a23 */
/* 0x004fca0000000009 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FFMA R11, R0, c[0x0][0x180], R11 ; /* 0x00006000000b7a23 */
/* 0x004fca000000000b */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s0, v2
flat_store_b32 v[0:1], v3
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagE13saxpy_functorNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} | code for sm_80
Function : _Z7takeLogPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.SHL.U32 R6, R0, 0x2, RZ ; /* 0x0000000200067824 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R6, R6, R3, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ BSSY B0, 0x4c0 ; /* 0x0000040000007945 */
/* 0x000fe20003800000 */
/*00c0*/ F2F.F64.F32 R4, R2 ; /* 0x0000000200047310 */
/* 0x0040620000201800 */
/*00d0*/ FSETP.GT.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fe20003f24000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x3ff ; /* 0xfffffc01ff027424 */
/* 0x001fc600078e00ff */
/*00f0*/ FSEL R5, R5, 0.006091669667512178421, P1 ; /* 0x3bc79ca105057808 */
/* 0x002fe40000800000 */
/*0100*/ FSEL R4, R4, 2.2534666340150459063e-31, P1 ; /* 0x0c92422304047808 */
/* 0x000fe40000800000 */
/*0110*/ ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; /* 0x000fffff0500780c */
/* 0x000fe20003f04270 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0130*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd400078e0004 */
/*0140*/ @!P0 DMUL R8, R8, 1.80143985094819840000e+16 ; /* 0x4350000008088828 */
/* 0x000e220000000000 */
/*0150*/ @!P0 MOV R2, 0xfffffbcb ; /* 0xfffffbcb00028802 */
/* 0x000fd20000000f00 */
/*0160*/ @!P0 MOV R5, R9 ; /* 0x0000000900058202 */
/* 0x001fe20000000f00 */
/*0170*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0008 */
/*0180*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P1, PT, R10, 0x7fefffff, PT ; /* 0x7fefffff0a00780c */
/* 0x000fda0003f26070 */
/*01a0*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff061424 */
/* 0x000fe200078e00ff */
/*01b0*/ @P1 FSETP.NEU.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900120b */
/* 0x000fe20003f4d000 */
/*01c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff071424 */
/* 0x000fcc00078e00ff */
/*01d0*/ @P1 DFMA R6, R8, R6, +INF ; /* 0x7ff000000806142b */
/* 0x000e140000000006 */
/*01e0*/ @P1 FSEL R6, R6, RZ, P2 ; /* 0x000000ff06061208 */
/* 0x001fe40001000000 */
/*01f0*/ @P1 FSEL R7, R7, -QNAN , P2 ; /* 0xfff0000007071808 */
/* 0x000fe20001000000 */
/*0200*/ @P1 BRA 0x4b0 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*0210*/ LOP3.LUT R6, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05067812 */
/* 0x040fe200078ec0ff */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0230*/ MOV R16, 0x3ae80f1e ; /* 0x3ae80f1e00107802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff117424 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0270*/ LEA.HI R5, R5, R2, RZ, 0xc ; /* 0x0000000205057211 */
/* 0x000fe400078f60ff */
/*0280*/ ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; /* 0x3ff6a09f0700780c */
/* 0x000fda0003f06270 */
/*0290*/ @P0 IADD3 R9, R7, -0x100000, RZ ; /* 0xfff0000007090810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0009 */
/*02c0*/ LOP3.LUT R4, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005047812 */
/* 0x000fe200078e3cff */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; /* 0x43300000ff057424 */
/* 0x000fc800078e00ff */
/*02e0*/ DADD R14, R6, 1 ; /* 0x3ff00000060e7429 */
/* 0x000e080000000000 */
/*02f0*/ DADD R6, R6, -1 ; /* 0xbff0000006067429 */
/* 0x000fe40000000000 */
/*0300*/ MUFU.RCP64H R9, R15 ; /* 0x0000000f00097308 */
/* 0x001e240000001800 */
/*0310*/ DADD R4, R4, c[0x2][0x38] ; /* 0x00800e0004047629 */
/* 0x000fc80000000000 */
/*0320*/ DFMA R10, -R14, R8, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c0000000108 */
/*0330*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0340*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x001e0c0000000008 */
/*0350*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*0360*/ DFMA R10, R8, R6, R10 ; /* 0x00000006080a722b */
/* 0x001e0c000000000a */
/*0370*/ DMUL R12, R10, R10 ; /* 0x0000000a0a0c7228 */
/* 0x001e080000000000 */
/*0380*/ DADD R14, R6, -R10 ; /* 0x00000000060e7229 */
/* 0x000e48000000080a */
/*0390*/ DFMA R16, R12, R16, c[0x2][0x0] ; /* 0x008000000c10762b */
/* 0x001e080000000010 */
/*03a0*/ DADD R18, R14, R14 ; /* 0x000000000e127229 */
/* 0x002fc8000000000e */
/*03b0*/ DFMA R16, R12, R16, c[0x2][0x8] ; /* 0x008002000c10762b */
/* 0x001e080000000010 */
/*03c0*/ DFMA R14, R4, c[0x2][0x40], R10 ; /* 0x00801000040e7a2b */
/* 0x000fc8000000000a */
/*03d0*/ DFMA R16, R12, R16, c[0x2][0x10] ; /* 0x008004000c10762b */
/* 0x001e080000000010 */
/*03e0*/ DFMA R18, R6, -R10, R18 ; /* 0x8000000a0612722b */
/* 0x000fc80000000012 */
/*03f0*/ DFMA R16, R12, R16, c[0x2][0x18] ; /* 0x008006000c10762b */
/* 0x001e080000000010 */
/*0400*/ DFMA R6, -R4, c[0x2][0x40], R14 ; /* 0x0080100004067a2b */
/* 0x000fc8000000010e */
/*0410*/ DFMA R16, R12, R16, c[0x2][0x20] ; /* 0x008008000c10762b */
/* 0x001e080000000010 */
/*0420*/ DMUL R18, R8, R18 ; /* 0x0000001208127228 */
/* 0x000fc80000000000 */
/*0430*/ DFMA R16, R12, R16, c[0x2][0x28] ; /* 0x00800a000c10762b */
/* 0x001e080000000010 */
/*0440*/ DADD R6, -R10, R6 ; /* 0x000000000a067229 */
/* 0x000fc80000000106 */
/*0450*/ DFMA R16, R12, R16, c[0x2][0x30] ; /* 0x00800c000c10762b */
/* 0x001e0c0000000010 */
/*0460*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x001e0c0000000000 */
/*0470*/ DFMA R16, R10, R16, R18 ; /* 0x000000100a10722b */
/* 0x001e0c0000000012 */
/*0480*/ DADD R6, R16, -R6 ; /* 0x0000000010067229 */
/* 0x001e0c0000000806 */
/*0490*/ DFMA R6, R4, c[0x2][0x48], R6 ; /* 0x0080120004067a2b */
/* 0x001e0c0000000006 */
/*04a0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x00104c0000000006 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x002e620000301000 */
/*04d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*04e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} | .file "tmpxft_001b2b24_00000000-6_takeLog.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7takeLogPfS_iPfS_i
.type _Z29__device_stub__Z7takeLogPfS_iPfS_i, @function
_Z29__device_stub__Z7takeLogPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7takeLogPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7takeLogPfS_iPfS_i, .-_Z29__device_stub__Z7takeLogPfS_iPfS_i
.globl _Z7takeLogPfS_i
.type _Z7takeLogPfS_i, @function
_Z7takeLogPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7takeLogPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7takeLogPfS_i, .-_Z7takeLogPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7takeLogPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7takeLogPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7takeLogPfS_i
.globl _Z7takeLogPfS_i
.p2align 8
.type _Z7takeLogPfS_i,@function
_Z7takeLogPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 1, v1
s_mov_b32 s5, 0x3fc38538
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v0
v_cmp_lt_f32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, 0x3bc79ca1, v3, vcc_lo
v_cndmask_b32_e32 v2, 0xc924223, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[4:5]
s_mov_b32 s0, 0x55555780
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[4:5], v[4:5], v0
v_frexp_exp_i32_f64_e32 v0, v[2:3]
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x204
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_mul_f64 v[16:17], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[16:17], v[4:5]
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[16:17], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[12:13], -v[6:7]
v_add_f64 v[4:5], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[14:15], v[4:5]
v_mul_f64 v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[10:11], v[4:5]
v_mul_f64 v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[14:15], v[6:7], v[8:9]
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[8:9], v[12:13], s[0:1]
v_ldexp_f64 v[12:13], v[6:7], 1
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_mul_f64 v[8:9], v[14:15], v[8:9]
v_cvt_f64_i32_e32 v[14:15], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_add_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[16:17], v[14:15], s[0:1]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[10:11], -v[12:13]
v_fma_f64 v[12:13], v[14:15], s[0:1], -v[16:17]
s_mov_b32 s1, 0x3c7abc9e
s_mov_b32 s0, 0x3b39803f
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[8:9], -v[6:7]
v_fma_f64 v[8:9], v[14:15], s[0:1], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[10:11], v[4:5]
v_add_f64 v[16:17], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[6:7], v[12:13]
v_add_f64 v[10:11], v[12:13], -v[10:11]
v_add_f64 v[8:9], v[8:9], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], -v[6:7]
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[14:15], -v[18:19]
v_add_f64 v[10:11], v[12:13], -v[18:19]
v_add_f64 v[12:13], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[12:13], -v[8:9]
v_add_f64 v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[10:11]
v_add_f64 v[4:5], v[4:5], -v[10:11]
v_add_f64 v[16:17], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[12:13]
v_add_f64 v[10:11], v[16:17], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v4, v2, vcc_lo
v_cndmask_b32_e32 v4, v5, v3, vcc_lo
v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7ff80000, v4, vcc_lo
v_cmp_nge_f64_e32 vcc_lo, 0, v[2:3]
v_cndmask_b32_e32 v4, 0, v0, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cndmask_b32_e32 v5, 0xfff00000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f32_f64_e32 v3, v[4:5]
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7takeLogPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7takeLogPfS_i, .Lfunc_end0-_Z7takeLogPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7takeLogPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7takeLogPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void takeLog(float* input, float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (i < nhalf) {
env[i] = log(input[j] > 0.0 ? input[j] : 1e-20); // take the log of the amplitudes
}
} | .text
.file "takeLog.hip"
.globl _Z22__device_stub__takeLogPfS_i # -- Begin function _Z22__device_stub__takeLogPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__takeLogPfS_i,@function
_Z22__device_stub__takeLogPfS_i: # @_Z22__device_stub__takeLogPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7takeLogPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__takeLogPfS_i, .Lfunc_end0-_Z22__device_stub__takeLogPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7takeLogPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7takeLogPfS_i,@object # @_Z7takeLogPfS_i
.section .rodata,"a",@progbits
.globl _Z7takeLogPfS_i
.p2align 3, 0x0
_Z7takeLogPfS_i:
.quad _Z22__device_stub__takeLogPfS_i
.size _Z7takeLogPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7takeLogPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__takeLogPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7takeLogPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.